Loop Id: 2186 | Module: exec | Source: ams.c:78-79 | Coverage: 1.26% |
---|
Loop Id: 2186 | Module: exec | Source: ams.c:78-79 | Coverage: 1.26% |
---|
0x534a13 VMOVUPD (%R14,%RAX,1),%ZMM7 [2] |
0x534a1a VDIVPD (%R15,%RAX,1),%ZMM7,%ZMM3 [3] |
0x534a21 VADDPD (%R13,%RAX,1),%ZMM3,%ZMM4 [1] |
0x534a29 VMOVUPD %ZMM4,(%R13,%RAX,1) [1] |
0x534a31 VMOVUPD 0x40(%R14,%RAX,1),%ZMM11 [2] |
0x534a39 VDIVPD 0x40(%R15,%RAX,1),%ZMM11,%ZMM9 [3] |
0x534a41 VADDPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM14 [1] |
0x534a49 VMOVUPD %ZMM14,0x40(%R13,%RAX,1) [1] |
0x534a51 VMOVUPD 0x80(%R14,%RAX,1),%ZMM5 [2] |
0x534a59 VDIVPD 0x80(%R15,%RAX,1),%ZMM5,%ZMM0 [3] |
0x534a61 VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM12 [1] |
0x534a69 VMOVUPD %ZMM12,0x80(%R13,%RAX,1) [1] |
0x534a71 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM10 [2] |
0x534a79 VDIVPD 0xc0(%R15,%RAX,1),%ZMM10,%ZMM13 [3] |
0x534a81 VADDPD 0xc0(%R13,%RAX,1),%ZMM13,%ZMM2 [1] |
0x534a89 VMOVUPD %ZMM2,0xc0(%R13,%RAX,1) [1] |
0x534a91 VMOVUPD 0x100(%R14,%RAX,1),%ZMM15 [2] |
0x534a99 VDIVPD 0x100(%R15,%RAX,1),%ZMM15,%ZMM1 [3] |
0x534aa1 VADDPD 0x100(%R13,%RAX,1),%ZMM1,%ZMM6 [1] |
0x534aa9 VMOVUPD %ZMM6,0x100(%R13,%RAX,1) [1] |
0x534ab1 VMOVUPD 0x140(%R14,%RAX,1),%ZMM8 [2] |
0x534ab9 VDIVPD 0x140(%R15,%RAX,1),%ZMM8,%ZMM7 [3] |
0x534ac1 VADDPD 0x140(%R13,%RAX,1),%ZMM7,%ZMM3 [1] |
0x534ac9 VMOVUPD %ZMM3,0x140(%R13,%RAX,1) [1] |
0x534ad1 VMOVUPD 0x180(%R14,%RAX,1),%ZMM4 [2] |
0x534ad9 VDIVPD 0x180(%R15,%RAX,1),%ZMM4,%ZMM11 [3] |
0x534ae1 VADDPD 0x180(%R13,%RAX,1),%ZMM11,%ZMM9 [1] |
0x534ae9 VMOVUPD %ZMM9,0x180(%R13,%RAX,1) [1] |
0x534af1 VMOVUPD 0x1c0(%R14,%RAX,1),%ZMM14 [2] |
0x534af9 VDIVPD 0x1c0(%R15,%RAX,1),%ZMM14,%ZMM5 [3] |
0x534b01 VADDPD 0x1c0(%R13,%RAX,1),%ZMM5,%ZMM0 [1] |
0x534b09 VMOVUPD %ZMM0,0x1c0(%R13,%RAX,1) [1] |
0x534b11 ADD $0x200,%RAX |
0x534b17 CMP %RAX,%R8 |
0x534b1a JNE 534a13 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 78 - 79 |
-------------------------------------------------------------------------------- |
78: for (i = 0; i < num_rows; i++) |
79: u_data[i] += v_data[i] / l1_norms[i]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►95.70+ | hypre_BoomerAMGCycle | par_cycle.c:394 | exec |
○ | hypre_BoomerAMGSolve | par_amg_solve.c:235 | exec |
○ | hypre_PCGSolve | pcg.c:545 | exec |
○ | main | amg.c:419 | exec |
○ | __libc_init_first | libc.so.6 | |
►4.30+ | hypre_BoomerAMGCycle | par_cycle.c:394 | exec |
○ | hypre_BoomerAMGSolve | par_amg_solve.c:235 | exec |
○ | hypre_PCGSolve | pcg.c:424 | exec |
○ | main | amg.c:419 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 7.76 |
Bottlenecks | P0, |
Function | hypre_ParCSRRelax |
Source | ams.c:78-79 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 128.00 |
CQA cycles if no scalar integer | 128.00 |
CQA cycles if FP arith vectorized | 128.00 |
CQA cycles if fully vectorized | 128.00 |
Front-end cycles | 16.50 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 4.00 |
P1 cycles | 12.00 |
P2 cycles | 12.00 |
P3 cycles | 8.00 |
P4 cycles | 16.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 128.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 129.02 |
Stall cycles (UFS) | 112.11 |
Nb insns | 35.00 |
Nb uops | 58.00 |
Nb loads | 24.00 |
Nb stores | 8.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.00 |
Nb FLOP add-sub | 64.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 64.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1536.00 |
Bytes stored | 512.00 |
Stride 0 | 0.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 7.76 |
Bottlenecks | P0, |
Function | hypre_ParCSRRelax |
Source | ams.c:78-79 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 128.00 |
CQA cycles if no scalar integer | 128.00 |
CQA cycles if FP arith vectorized | 128.00 |
CQA cycles if fully vectorized | 128.00 |
Front-end cycles | 16.50 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 4.00 |
P1 cycles | 12.00 |
P2 cycles | 12.00 |
P3 cycles | 8.00 |
P4 cycles | 16.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 128.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 129.02 |
Stall cycles (UFS) | 112.11 |
Nb insns | 35.00 |
Nb uops | 58.00 |
Nb loads | 24.00 |
Nb stores | 8.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.00 |
Nb FLOP add-sub | 64.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 64.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1536.00 |
Bytes stored | 512.00 |
Stride 0 | 0.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | hypre_ParCSRRelax |
Source file and lines | ams.c:78-79 |
Module | exec |
nb instructions | 35 |
nb uops | 58 |
loop length | 269 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 16.50 cycles |
front end | 16.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 16.00 | 1.00 | 12.00 | 12.00 | 8.00 | 16.00 | 1.00 | 8.00 |
cycles | 16.00 | 4.00 | 12.00 | 12.00 | 8.00 | 16.00 | 1.00 | 8.00 |
Cycles executing div or sqrt instructions | 128.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 129.02 |
Stall cycles | 112.11 |
RS full (events) | 128.62 |
Front-end | 16.50 |
Dispatch | 16.00 |
DIV/SQRT | 128.00 |
Data deps. | 1.00 |
Overall L1 | 128.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R14,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD (%R15,%RAX,1),%ZMM7,%ZMM3 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD (%R13,%RAX,1),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM4,(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x40(%R14,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x40(%R15,%RAX,1),%ZMM11,%ZMM9 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM14 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM14,0x40(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x80(%R14,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x80(%R15,%RAX,1),%ZMM5,%ZMM0 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM12 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM12,0x80(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0xc0(%R14,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0xc0(%R15,%RAX,1),%ZMM10,%ZMM13 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0xc0(%R13,%RAX,1),%ZMM13,%ZMM2 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM2,0xc0(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x100(%R14,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x100(%R15,%RAX,1),%ZMM15,%ZMM1 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x100(%R13,%RAX,1),%ZMM1,%ZMM6 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM6,0x100(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x140(%R14,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x140(%R15,%RAX,1),%ZMM8,%ZMM7 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x140(%R13,%RAX,1),%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM3,0x140(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x180(%R14,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x180(%R15,%RAX,1),%ZMM4,%ZMM11 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x180(%R13,%RAX,1),%ZMM11,%ZMM9 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM9,0x180(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x1c0(%R14,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x1c0(%R15,%RAX,1),%ZMM14,%ZMM5 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x1c0(%R13,%RAX,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM0,0x1c0(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RAX,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 534a13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_ParCSRRelax |
Source file and lines | ams.c:78-79 |
Module | exec |
nb instructions | 35 |
nb uops | 58 |
loop length | 269 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 16.50 cycles |
front end | 16.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 16.00 | 1.00 | 12.00 | 12.00 | 8.00 | 16.00 | 1.00 | 8.00 |
cycles | 16.00 | 4.00 | 12.00 | 12.00 | 8.00 | 16.00 | 1.00 | 8.00 |
Cycles executing div or sqrt instructions | 128.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 129.02 |
Stall cycles | 112.11 |
RS full (events) | 128.62 |
Front-end | 16.50 |
Dispatch | 16.00 |
DIV/SQRT | 128.00 |
Data deps. | 1.00 |
Overall L1 | 128.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R14,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD (%R15,%RAX,1),%ZMM7,%ZMM3 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD (%R13,%RAX,1),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM4,(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x40(%R14,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x40(%R15,%RAX,1),%ZMM11,%ZMM9 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM14 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM14,0x40(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x80(%R14,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x80(%R15,%RAX,1),%ZMM5,%ZMM0 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM12 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM12,0x80(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0xc0(%R14,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0xc0(%R15,%RAX,1),%ZMM10,%ZMM13 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0xc0(%R13,%RAX,1),%ZMM13,%ZMM2 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM2,0xc0(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x100(%R14,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x100(%R15,%RAX,1),%ZMM15,%ZMM1 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x100(%R13,%RAX,1),%ZMM1,%ZMM6 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM6,0x100(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x140(%R14,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x140(%R15,%RAX,1),%ZMM8,%ZMM7 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x140(%R13,%RAX,1),%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM3,0x140(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x180(%R14,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x180(%R15,%RAX,1),%ZMM4,%ZMM11 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x180(%R13,%RAX,1),%ZMM11,%ZMM9 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM9,0x180(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD 0x1c0(%R14,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD 0x1c0(%R15,%RAX,1),%ZMM14,%ZMM5 | 4 | 2.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 24 | 16 |
VADDPD 0x1c0(%R13,%RAX,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM0,0x1c0(%R13,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RAX,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 534a13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |