Function: hypre_Rand | Module: exec | Source: random.c:76-115 [...] | Coverage: 0.11% |
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Function: hypre_Rand | Module: exec | Source: random.c:76-115 [...] | Coverage: 0.11% |
---|
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/utilities/random.c: 76 - 115 |
-------------------------------------------------------------------------------- |
76: high = Seed / q; |
77: low = Seed % q; |
78: test = a * low - r * high; |
79: if(test > 0) |
[...] |
99: { |
[...] |
115: return ((HYPRE_Real)(hypre_RandI()) / m); |
0x4df940 PUSH %RBP |
0x4df941 MOV %RSP,%RBP |
0x4df944 MOV 0x4cd1d(%RIP),%RCX |
0x4df94b MOV $0x41a705af1fe3fb79,%RDX |
0x4df955 MOV %RCX,%RAX |
0x4df958 IMUL %RDX |
0x4df95b MOV %RDX,%RAX |
0x4df95e SHR $0x3f,%RAX |
0x4df962 SAR $0xf,%RDX |
0x4df966 ADD %RAX,%RDX |
0x4df969 IMUL $0x1f31d,%RDX,%RAX |
0x4df970 SUB %RAX,%RCX |
0x4df973 IMUL $0x41a7,%RCX,%RAX |
0x4df97a IMUL $-0xb14,%RDX,%RCX |
0x4df981 LEA (%RCX,%RAX,1),%RDX |
0x4df985 TEST %RDX,%RDX |
0x4df988 LEA 0x7fffffff(%RCX,%RAX,1),%RAX |
0x4df990 CMOVG %RDX,%RAX |
0x4df994 MOV %RAX,0x4cccd(%RIP) |
0x4df99b VCVTSI2SD %RAX,%XMM0,%XMM0 |
0x4df9a0 VMULSD 0x2abc0(%RIP),%XMM0,%XMM0 |
0x4df9a8 POP %RBP |
0x4df9a9 RET |
0x4df9aa NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►25.00+ | hypre_BoomerAMGIndepSetInit | par_indepset.c:67 | exec |
○ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 | |
►25.00+ | hypre_BoomerAMGIndepSetInit | par_indepset.c:67 | exec |
○ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 | |
►12.50+ | hypre_BoomerAMGIndepSetInit | par_indepset.c:67 | exec |
○ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 | |
►12.50+ | hypre_BoomerAMGIndepSetInit | par_indepset.c:67 | exec |
○ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:626 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 | |
►12.50+ | hypre_BoomerAMGIndepSetInit | par_indepset.c:67 | exec |
○ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 | |
►12.50+ | hypre_BoomerAMGIndepSetInit | par_indepset.c:67 | exec |
○ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | random.c:76-115 |
Module | exec |
nb instructions | 23 |
nb uops | 25 |
loop length | 106 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.25 cycles |
front end | 6.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 5.00 | 2.17 | 1.83 | 2.00 | 4.25 | 4.25 | 2.00 |
cycles | 4.50 | 6.50 | 2.17 | 1.83 | 2.00 | 4.25 | 4.25 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 16.25 |
Stall cycles | 9.45 |
ROB full (events) | 10.65 |
Front-end | 6.25 |
Dispatch | 6.50 |
Overall L1 | 6.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x4cd1d(%RIP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV $0x41a705af1fe3fb79,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
IMUL %RDX | 2 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3f,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
SAR $0xf,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
ADD %RAX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
IMUL $0x1f31d,%RDX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %RAX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
IMUL $0x41a7,%RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL $-0xb14,%RDX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RCX,%RAX,1),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x7fffffff(%RCX,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVG %RDX,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %RAX,0x4cccd(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VCVTSI2SD %RAX,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMULSD 0x2abc0(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
Source file and lines | random.c:76-115 |
Module | exec |
nb instructions | 23 |
nb uops | 25 |
loop length | 106 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.25 cycles |
front end | 6.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 5.00 | 2.17 | 1.83 | 2.00 | 4.25 | 4.25 | 2.00 |
cycles | 4.50 | 6.50 | 2.17 | 1.83 | 2.00 | 4.25 | 4.25 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 16.25 |
Stall cycles | 9.45 |
ROB full (events) | 10.65 |
Front-end | 6.25 |
Dispatch | 6.50 |
Overall L1 | 6.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x4cd1d(%RIP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV $0x41a705af1fe3fb79,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
IMUL %RDX | 2 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3f,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
SAR $0xf,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
ADD %RAX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
IMUL $0x1f31d,%RDX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %RAX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
IMUL $0x41a7,%RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL $-0xb14,%RDX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RCX,%RAX,1),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x7fffffff(%RCX,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVG %RDX,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %RAX,0x4cccd(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VCVTSI2SD %RAX,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMULSD 0x2abc0(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
Name | Coverage (%) | Time (s) |
---|---|---|
○hypre_Rand | 0.11 | 0.04 |