Loop Id: 759 | Module: exec | Source: par_lr_interp.c:1624-1628 | Coverage: 0.03% |
---|
Loop Id: 759 | Module: exec | Source: par_lr_interp.c:1624-1628 | Coverage: 0.03% |
---|
0x47d0ac VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM14 [6] |
0x47d0b7 KMOVB %K3,%K6 |
0x47d0bb VMOVAPD -0x170(%RBP),%ZMM1 [7] |
0x47d0c5 ADD $0x100,%RCX |
0x47d0cc VPGATHERQQ (%R14,%ZMM14,8),%ZMM2{%K6} [1] |
0x47d0d3 VPCMPEQQ %ZMM12,%ZMM14,%K7 |
0x47d0da KMOVB %K3,%K6 |
0x47d0de VPCMPNLTQ %ZMM11,%ZMM2,%K5 |
0x47d0e5 KORB %K5,%K7,%K1 |
0x47d0e9 VMOVUPD -0x100(%RCX),%ZMM1{%K1} [4] |
0x47d0f0 VMULPD %ZMM10,%ZMM1,%ZMM14 |
0x47d0f6 VCMPPD $0x1,%ZMM13,%ZMM14,%K4{%K1} |
0x47d0fd VMOVAPD %ZMM1,%ZMM2{%K4}{z} |
0x47d103 KMOVB %K3,%K4 |
0x47d107 VADDPD %ZMM2,%ZMM0,%ZMM0 |
0x47d10d VMOVDQU64 -0xc8(%RCX,%R10,1),%ZMM2 [8] |
0x47d118 VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K6} [5] |
0x47d11f VPCMPEQQ %ZMM12,%ZMM2,%K7 |
0x47d126 VPCMPNLTQ %ZMM11,%ZMM14,%K0 |
0x47d12d KORB %K0,%K7,%K5 |
0x47d131 VMOVUPD -0xc0(%RCX),%ZMM1{%K5} [4] |
0x47d138 VMULPD %ZMM10,%ZMM1,%ZMM2 |
0x47d13e VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} |
0x47d145 VMOVDQU64 -0x88(%RCX,%R10,1),%ZMM2 [8] |
0x47d150 VPCMPEQQ %ZMM12,%ZMM2,%K6 |
0x47d157 VMOVAPD %ZMM1,%ZMM14{%K1}{z} |
0x47d15d VADDPD %ZMM14,%ZMM0,%ZMM0 |
0x47d163 VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} [2] |
0x47d16a KMOVB %K3,%K4 |
0x47d16e VPCMPNLTQ %ZMM11,%ZMM14,%K7 |
0x47d175 KORB %K7,%K6,%K5 |
0x47d179 VMOVUPD -0x80(%RCX),%ZMM1{%K5} [4] |
0x47d180 VMULPD %ZMM10,%ZMM1,%ZMM2 |
0x47d186 VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} |
0x47d18d VMOVDQU64 -0x48(%RCX,%R10,1),%ZMM2 [8] |
0x47d198 VPCMPEQQ %ZMM12,%ZMM2,%K6 |
0x47d19f VMOVAPD %ZMM1,%ZMM14{%K1}{z} |
0x47d1a5 VADDPD %ZMM14,%ZMM0,%ZMM0 |
0x47d1ab VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} [3] |
0x47d1b2 VPCMPNLTQ %ZMM11,%ZMM14,%K0 |
0x47d1b9 KORB %K0,%K6,%K7 |
0x47d1bd VBLENDMPD -0x40(%RCX),%ZMM1,%ZMM2{%K7} [4] |
0x47d1c4 VMULPD %ZMM2,%ZMM10,%ZMM1 |
0x47d1ca VMOVAPD %ZMM2,-0x170(%RBP) [7] |
0x47d1d4 VCMPPD $0x1,%ZMM13,%ZMM1,%K5{%K7} |
0x47d1db VMOVAPD %ZMM2,%ZMM14{%K5}{z} |
0x47d1e1 VADDPD %ZMM14,%ZMM0,%ZMM0 |
0x47d1e7 CMP %R8,%RCX |
0x47d1ea JNE 47d0ac |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1624 - 1628 |
-------------------------------------------------------------------------------- |
1624: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1625: { |
1626: i2 = A_diag_j[jj1]; |
1627: if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0) |
1628: sum += A_diag_data[jj1]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.24 |
Bottlenecks | P2, P3, |
Function | hypre_BoomerAMGBuildExtPIInterp._omp_fn.0 |
Source | par_lr_interp.c:1624-1628 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 20.50 |
CQA cycles if no scalar integer | 20.50 |
CQA cycles if FP arith vectorized | 20.50 |
CQA cycles if fully vectorized | 20.50 |
Front-end cycles | 14.00 |
DIV/SQRT cycles | 16.50 |
P0 cycles | 4.00 |
P1 cycles | 20.50 |
P2 cycles | 20.50 |
P3 cycles | 1.00 |
P4 cycles | 16.50 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 16 |
FE+BE cycles (UFS) | 17.03 |
Stall cycles (UFS) | 4.49 |
Nb insns | 49.00 |
Nb uops | 56.00 |
Nb loads | 13.00 |
Nb stores | 1.00 |
Nb stack references | 1.00 |
FLOP/cycle | 3.12 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 32.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 43.71 |
Bytes prefetched | 0.00 |
Bytes loaded | 832.00 |
Bytes stored | 64.00 |
Stride 0 | 1.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 100.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.24 |
Bottlenecks | P2, P3, |
Function | hypre_BoomerAMGBuildExtPIInterp._omp_fn.0 |
Source | par_lr_interp.c:1624-1628 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 20.50 |
CQA cycles if no scalar integer | 20.50 |
CQA cycles if FP arith vectorized | 20.50 |
CQA cycles if fully vectorized | 20.50 |
Front-end cycles | 14.00 |
DIV/SQRT cycles | 16.50 |
P0 cycles | 4.00 |
P1 cycles | 20.50 |
P2 cycles | 20.50 |
P3 cycles | 1.00 |
P4 cycles | 16.50 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 16 |
FE+BE cycles (UFS) | 17.03 |
Stall cycles (UFS) | 4.49 |
Nb insns | 49.00 |
Nb uops | 56.00 |
Nb loads | 13.00 |
Nb stores | 1.00 |
Nb stack references | 1.00 |
FLOP/cycle | 3.12 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 32.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 43.71 |
Bytes prefetched | 0.00 |
Bytes loaded | 832.00 |
Bytes stored | 64.00 |
Stride 0 | 1.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 100.00 |
Path / |
Function | hypre_BoomerAMGBuildExtPIInterp._omp_fn.0 |
Source file and lines | par_lr_interp.c:1624-1628 |
Module | exec |
nb instructions | 49 |
nb uops | 56 |
loop length | 324 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 8 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 14.00 cycles |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 16.50 | 1.00 | 20.50 | 20.50 | 1.00 | 16.50 | 1.00 | 1.00 |
cycles | 16.50 | 4.00 | 20.50 | 20.50 | 1.00 | 16.50 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 16.00 |
FE+BE cycles | 17.03 |
Stall cycles | 4.49 |
PRF full (events) | 6.50 |
Front-end | 14.00 |
Dispatch | 20.50 |
Data deps. | 16.00 |
Overall L1 | 20.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K3,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVAPD -0x170(%RBP),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
ADD $0x100,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VPGATHERQQ (%R14,%ZMM14,8),%ZMM2{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
VPCMPEQQ %ZMM12,%ZMM14,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
KMOVB %K3,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %ZMM11,%ZMM2,%K5 | |||||||||||
KORB %K5,%K7,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD -0x100(%RCX),%ZMM1{%K1} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %ZMM10,%ZMM1,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM13,%ZMM14,%K4{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM1,%ZMM2{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
KMOVB %K3,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VADDPD %ZMM2,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVDQU64 -0xc8(%RCX,%R10,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
VPCMPEQQ %ZMM12,%ZMM2,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %ZMM11,%ZMM14,%K0 | |||||||||||
KORB %K0,%K7,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD -0xc0(%RCX),%ZMM1{%K5} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %ZMM10,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVDQU64 -0x88(%RCX,%R10,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPCMPEQQ %ZMM12,%ZMM2,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM1,%ZMM14{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %ZMM14,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
KMOVB %K3,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %ZMM11,%ZMM14,%K7 | |||||||||||
KORB %K7,%K6,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD -0x80(%RCX),%ZMM1{%K5} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %ZMM10,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVDQU64 -0x48(%RCX,%R10,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPCMPEQQ %ZMM12,%ZMM2,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM1,%ZMM14{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %ZMM14,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
VPCMPNLTQ %ZMM11,%ZMM14,%K0 | |||||||||||
KORB %K0,%K6,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VBLENDMPD -0x40(%RCX),%ZMM1,%ZMM2{%K7} | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULPD %ZMM2,%ZMM10,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVAPD %ZMM2,-0x170(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VCMPPD $0x1,%ZMM13,%ZMM1,%K5{%K7} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM2,%ZMM14{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %ZMM14,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
CMP %R8,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 47d0ac | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_BoomerAMGBuildExtPIInterp._omp_fn.0 |
Source file and lines | par_lr_interp.c:1624-1628 |
Module | exec |
nb instructions | 49 |
nb uops | 56 |
loop length | 324 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 8 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 14.00 cycles |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 16.50 | 1.00 | 20.50 | 20.50 | 1.00 | 16.50 | 1.00 | 1.00 |
cycles | 16.50 | 4.00 | 20.50 | 20.50 | 1.00 | 16.50 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 16.00 |
FE+BE cycles | 17.03 |
Stall cycles | 4.49 |
PRF full (events) | 6.50 |
Front-end | 14.00 |
Dispatch | 20.50 |
Data deps. | 16.00 |
Overall L1 | 20.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU64 -0x8(%RCX,%R10,1),%ZMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K3,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVAPD -0x170(%RBP),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
ADD $0x100,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VPGATHERQQ (%R14,%ZMM14,8),%ZMM2{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
VPCMPEQQ %ZMM12,%ZMM14,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
KMOVB %K3,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %ZMM11,%ZMM2,%K5 | |||||||||||
KORB %K5,%K7,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD -0x100(%RCX),%ZMM1{%K1} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %ZMM10,%ZMM1,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM13,%ZMM14,%K4{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM1,%ZMM2{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
KMOVB %K3,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VADDPD %ZMM2,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVDQU64 -0xc8(%RCX,%R10,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
VPCMPEQQ %ZMM12,%ZMM2,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %ZMM11,%ZMM14,%K0 | |||||||||||
KORB %K0,%K7,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD -0xc0(%RCX),%ZMM1{%K5} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %ZMM10,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVDQU64 -0x88(%RCX,%R10,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPCMPEQQ %ZMM12,%ZMM2,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM1,%ZMM14{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %ZMM14,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
KMOVB %K3,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %ZMM11,%ZMM14,%K7 | |||||||||||
KORB %K7,%K6,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD -0x80(%RCX),%ZMM1{%K5} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %ZMM10,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM13,%ZMM2,%K1{%K5} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVDQU64 -0x48(%RCX,%R10,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPCMPEQQ %ZMM12,%ZMM2,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM1,%ZMM14{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %ZMM14,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VPGATHERQQ (%R14,%ZMM2,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 22 | 5 |
VPCMPNLTQ %ZMM11,%ZMM14,%K0 | |||||||||||
KORB %K0,%K6,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VBLENDMPD -0x40(%RCX),%ZMM1,%ZMM2{%K7} | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULPD %ZMM2,%ZMM10,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVAPD %ZMM2,-0x170(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VCMPPD $0x1,%ZMM13,%ZMM1,%K5{%K7} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM2,%ZMM14{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %ZMM14,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
CMP %R8,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 47d0ac | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |