Loop Id: 2719 | Module: exec | Source: ams.c:569-621 [...] | Coverage: 0.04% |
---|
Loop Id: 2719 | Module: exec | Source: ams.c:569-621 [...] | Coverage: 0.04% |
---|
0x4a7ee0 VMOVSD %XMM2,(%RSI) |
0x4a7ee4 CMP -0x50(%RBP),%R14 |
0x4a7ee8 LEA 0x1(%R14),%R14 |
0x4a7eec JE 4a811f |
0x4a7ef2 MOV %R11,%RDX |
0x4a7ef5 MOV -0x30(%RBP),%RAX |
0x4a7ef9 MOVQ $0,(%RAX,%R14,8) |
0x4a7f01 MOV 0x8(%R8,%R14,8),%R11 |
0x4a7f06 MOV %R11,%R10 |
0x4a7f09 SUB %RDX,%R10 |
0x4a7f0c JLE 4a7ee4 |
0x4a7f0e LEA (%RAX,%R14,8),%RSI |
0x4a7f12 LEA (%RCX,%R11,8),%RAX |
0x4a7f16 ADD $-0x8,%RAX |
0x4a7f1a LEA (%RCX,%RDX,8),%RBX |
0x4a7f1e CMP %RSI,%RAX |
0x4a7f21 JB 4a7f60 |
0x4a7f23 CMP %RBX,%RSI |
0x4a7f26 JB 4a7f60 |
0x4a7f28 VXORPD %XMM2,%XMM2,%XMM2 |
0x4a7f2c NOPL (%RAX) |
(2722) 0x4a7f30 VMOVSD (%RCX,%RDX,8),%XMM3 |
(2722) 0x4a7f35 VANDPD %XMM0,%XMM3,%XMM3 |
(2722) 0x4a7f39 VADDSD %XMM3,%XMM2,%XMM2 |
(2722) 0x4a7f3d VMOVSD %XMM2,(%RSI) |
(2722) 0x4a7f41 INC %RDX |
(2722) 0x4a7f44 CMP %RDX,%R11 |
(2722) 0x4a7f47 JNE 4a7f30 |
0x4a7f49 JMP 4a7ee4 |
0x4a7f60 MOV %R10,%R9 |
0x4a7f63 AND $-0x4,%R9 |
0x4a7f67 JE 4a7fc0 |
0x4a7f69 LEA -0x1(%R9),%RDI |
0x4a7f6d VXORPD %XMM2,%XMM2,%XMM2 |
0x4a7f71 XOR %EAX,%EAX |
0x4a7f73 NOPW %CS:(%RAX,%RAX,1) |
(2721) 0x4a7f80 VANDPD (%RBX,%RAX,8),%YMM1,%YMM3 |
(2721) 0x4a7f85 VADDPD %YMM3,%YMM2,%YMM2 |
(2721) 0x4a7f89 ADD $0x4,%RAX |
(2721) 0x4a7f8d CMP %RDI,%RAX |
(2721) 0x4a7f90 JBE 4a7f80 |
0x4a7f92 VEXTRACTF128 $0x1,%YMM2,%XMM3 |
0x4a7f98 VADDPD %XMM3,%XMM2,%XMM2 |
0x4a7f9c VPERMILPD $0x1,%XMM2,%XMM3 |
0x4a7fa2 VADDSD %XMM3,%XMM2,%XMM2 |
0x4a7fa6 CMP %R9,%R10 |
0x4a7fa9 MOV -0x48(%RBP),%R8 |
0x4a7fad JE 4a7ee0 |
0x4a7fb3 JMP 4a7fc7 |
0x4a7fc0 VXORPD %XMM2,%XMM2,%XMM2 |
0x4a7fc4 XOR %R9D,%R9D |
0x4a7fc7 ADD %R9,%RDX |
0x4a7fca NOPW (%RAX,%RAX,1) |
(2720) 0x4a7fd0 VMOVSD (%RCX,%RDX,8),%XMM3 |
(2720) 0x4a7fd5 VANDPD %XMM0,%XMM3,%XMM3 |
(2720) 0x4a7fd9 VADDSD %XMM3,%XMM2,%XMM2 |
(2720) 0x4a7fdd INC %RDX |
(2720) 0x4a7fe0 CMP %RDX,%R11 |
(2720) 0x4a7fe3 JNE 4a7fd0 |
0x4a7fe5 JMP 4a7ee0 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 569 - 621 |
-------------------------------------------------------------------------------- |
569: if (cf_marker != NULL) |
[...] |
602: for (i = 0; i < num_rows; i++) |
603: { |
604: l1_norm[i] = 0.0; |
605: if (cf_marker == NULL) |
606: { |
607: /* Add the l1 norm of the diag part of the ith row */ |
608: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
609: l1_norm[i] += fabs(A_diag_data[j]); |
[...] |
621: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_BoomerAMGSetup | par_amg_setup.c:1381 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.33 |
CQA speedup if FP arith vectorized | 3.17 |
CQA speedup if fully vectorized | 11.59 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.62 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1Norms |
Source | ams.c:569-621 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.50 |
CQA cycles if no scalar integer | 4.50 |
CQA cycles if FP arith vectorized | 3.31 |
CQA cycles if fully vectorized | 0.91 |
Front-end cycles | 10.50 |
DIV/SQRT cycles | 6.50 |
P0 cycles | 6.50 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 6.50 |
P5 cycles | 6.50 |
P6 cycles | 2.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 12.14 |
Stall cycles (UFS) | 1.08 |
Nb insns | 42.00 |
Nb uops | 42.00 |
Nb loads | 4.00 |
Nb stores | 2.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.29 |
Nb FLOP add-sub | 3.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.57 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 40.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 33.33 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 50.00 |
Vector-efficiency ratio all | 17.08 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 9.38 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 16.67 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 18.75 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.33 |
CQA speedup if FP arith vectorized | 3.17 |
CQA speedup if fully vectorized | 11.59 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.62 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1Norms |
Source | ams.c:569-621 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.50 |
CQA cycles if no scalar integer | 4.50 |
CQA cycles if FP arith vectorized | 3.31 |
CQA cycles if fully vectorized | 0.91 |
Front-end cycles | 10.50 |
DIV/SQRT cycles | 6.50 |
P0 cycles | 6.50 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 6.50 |
P5 cycles | 6.50 |
P6 cycles | 2.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 12.14 |
Stall cycles (UFS) | 1.08 |
Nb insns | 42.00 |
Nb uops | 42.00 |
Nb loads | 4.00 |
Nb stores | 2.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.29 |
Nb FLOP add-sub | 3.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.57 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 40.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 33.33 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 50.00 |
Vector-efficiency ratio all | 17.08 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 9.38 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 16.67 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 18.75 |
Path / |
Function | hypre_ParCSRComputeL1Norms |
Source file and lines | ams.c:569-621 |
Module | exec |
nb instructions | 42 |
nb uops | 42 |
loop length | 170 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 10.50 cycles |
front end | 10.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 6.50 | 6.50 | 2.00 | 2.00 | 2.00 | 6.50 | 6.50 | 2.00 |
cycles | 6.50 | 6.50 | 2.00 | 2.00 | 2.00 | 6.50 | 6.50 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.14 |
Stall cycles | 1.08 |
ROB full (events) | 1.45 |
Front-end | 10.50 |
Dispatch | 6.50 |
Overall L1 | 10.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 75% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 40% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 11% |
load | 12% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 21% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 18% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 17% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM2,(%RSI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP -0x50(%RBP),%R14 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
LEA 0x1(%R14),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4a811f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R11,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVQ $0,(%RAX,%R14,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV 0x8(%R8,%R14,8),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R11,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDX,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4a7ee4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA (%RAX,%R14,8),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RCX,%R11,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $-0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RCX,%RDX,8),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4a7f60 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP %RBX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4a7f60 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4a7ee4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV %R10,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x4,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4a7fc0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x1(%R9),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VEXTRACTF128 $0x1,%YMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPERMILPD $0x1,%XMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VADDSD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 4a7ee0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4a7fc7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD %R9,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4a7ee0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | hypre_ParCSRComputeL1Norms |
Source file and lines | ams.c:569-621 |
Module | exec |
nb instructions | 42 |
nb uops | 42 |
loop length | 170 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 10.50 cycles |
front end | 10.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 6.50 | 6.50 | 2.00 | 2.00 | 2.00 | 6.50 | 6.50 | 2.00 |
cycles | 6.50 | 6.50 | 2.00 | 2.00 | 2.00 | 6.50 | 6.50 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.14 |
Stall cycles | 1.08 |
ROB full (events) | 1.45 |
Front-end | 10.50 |
Dispatch | 6.50 |
Overall L1 | 10.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 75% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 40% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 11% |
load | 12% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 21% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 18% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 17% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 16% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM2,(%RSI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP -0x50(%RBP),%R14 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
LEA 0x1(%R14),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4a811f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R11,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVQ $0,(%RAX,%R14,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV 0x8(%R8,%R14,8),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R11,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDX,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4a7ee4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA (%RAX,%R14,8),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RCX,%R11,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $-0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RCX,%RDX,8),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4a7f60 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP %RBX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4a7f60 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4a7ee4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV %R10,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x4,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4a7fc0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x1(%R9),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VEXTRACTF128 $0x1,%YMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPERMILPD $0x1,%XMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VADDSD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 4a7ee0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4a7fc7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD %R9,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4a7ee0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |