Function: hypre_CSRMatrixSetRownnz | Module: exec | Source: csr_matrix.c:136-168 [...] | Coverage: 0.01% |
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Function: hypre_CSRMatrixSetRownnz | Module: exec | Source: csr_matrix.c:136-168 [...] | Coverage: 0.01% |
---|
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c: 136 - 168 |
-------------------------------------------------------------------------------- |
136: { |
137: HYPRE_Int ierr=0; |
138: HYPRE_Int num_rows = hypre_CSRMatrixNumRows(matrix); |
139: HYPRE_Int *A_i = hypre_CSRMatrixI(matrix); |
[...] |
145: for (i=0; i < num_rows; i++) |
146: { |
147: adiag = (A_i[i+1] - A_i[i]); |
148: if(adiag > 0) irownnz++; |
149: } |
150: |
151: hypre_CSRMatrixNumRownnz(matrix) = irownnz; |
152: |
153: if ((irownnz == 0) || (irownnz == num_rows)) |
154: { |
155: hypre_CSRMatrixRownnz(matrix) = NULL; |
156: } |
157: else |
158: { |
159: Arownnz = hypre_CTAlloc(HYPRE_Int, irownnz); |
160: irownnz = 0; |
161: for (i=0; i < num_rows; i++) |
162: { |
163: adiag = A_i[i+1]-A_i[i]; |
164: if(adiag > 0) Arownnz[irownnz++] = i; |
165: } |
166: hypre_CSRMatrixRownnz(matrix) = Arownnz; |
167: } |
168: return ierr; |
0x4d1520 PUSH %RBP |
0x4d1521 MOV %RSP,%RBP |
0x4d1524 PUSH %R15 |
0x4d1526 PUSH %R14 |
0x4d1528 PUSH %R12 |
0x4d152a PUSH %RBX |
0x4d152b MOV %RDI,%R14 |
0x4d152e MOV 0x10(%RDI),%R15 |
0x4d1532 TEST %R15,%R15 |
0x4d1535 JLE 4d1544 |
0x4d1537 MOV (%R14),%R12 |
0x4d153a CMP $0x8,%R15 |
0x4d153e JAE 4d1551 |
0x4d1540 XOR %EDI,%EDI |
0x4d1542 JMP 4d15be |
0x4d1544 MOVQ $0,0x40(%R14) |
0x4d154c JMP 4d1650 |
0x4d1551 MOV %R15,%RAX |
0x4d1554 SHR $0x3,%RAX |
0x4d1558 MOV (%R12),%RDX |
0x4d155c LEA 0x8(%R12),%RCX |
0x4d1561 XOR %EDI,%EDI |
0x4d1563 VMOVDQU 0x34795(%RIP),%YMM0 |
0x4d156b NOPL (%RAX,%RAX,1) |
(3856) 0x4d1570 VMOVDQU (%RCX),%YMM1 |
(3856) 0x4d1574 VMOVDQU 0x20(%RCX),%YMM2 |
(3856) 0x4d1579 VMOVQ %RDX,%XMM3 |
(3856) 0x4d157e VMOVDQA %YMM1,%YMM4 |
(3856) 0x4d1582 VPERMT2Q %YMM3,%YMM0,%YMM4 |
(3856) 0x4d1588 VALIGNQ $0x3,%YMM1,%YMM2,%YMM3 |
(3856) 0x4d158f VPCMPGTQ %YMM3,%YMM2,%K0 |
(3856) 0x4d1595 KSHIFTLB $0x4,%K0,%K0 |
(3856) 0x4d159b VPCMPGTQ %YMM4,%YMM1,%K1 |
(3856) 0x4d15a1 KORB %K0,%K1,%K0 |
(3856) 0x4d15a5 KMOVB %K0,%EDX |
(3856) 0x4d15a9 POPCNT %RDX,%RDX |
(3856) 0x4d15ae ADD %RDX,%RDI |
(3856) 0x4d15b1 MOV 0x38(%RCX),%RDX |
(3856) 0x4d15b5 ADD $0x40,%RCX |
(3856) 0x4d15b9 DEC %RAX |
(3856) 0x4d15bc JNE 4d1570 |
0x4d15be MOV %R15,%RAX |
0x4d15c1 AND $-0x8,%RAX |
0x4d15c5 CMP %R15,%RAX |
0x4d15c8 JAE 4d15ec |
0x4d15ca MOV (%R12,%RAX,8),%RCX |
0x4d15ce XCHG %AX,%AX |
(3859) 0x4d15d0 MOV 0x8(%R12,%RAX,8),%RDX |
(3859) 0x4d15d5 INC %RAX |
(3859) 0x4d15d8 XOR %ESI,%ESI |
(3859) 0x4d15da CMP %RCX,%RDX |
(3859) 0x4d15dd SETG %SIL |
(3859) 0x4d15e1 ADD %RSI,%RDI |
(3859) 0x4d15e4 MOV %RDX,%RCX |
(3859) 0x4d15e7 CMP %RAX,%R15 |
(3859) 0x4d15ea JNE 4d15d0 |
0x4d15ec MOV %RDI,0x40(%R14) |
0x4d15f0 TEST %RDI,%RDI |
0x4d15f3 JE 4d1650 |
0x4d15f5 CMP %R15,%RDI |
0x4d15f8 JE 4d1650 |
0x4d15fa MOV $0x8,%ESI |
0x4d15ff VZEROUPPER |
0x4d1602 CALL 4dd8f0 <hypre_CAlloc> |
0x4d1607 CMP $0x4,%R15 |
0x4d160b JAE 4d1666 |
0x4d160d XOR %ECX,%ECX |
0x4d160f MOV %R15,%RDX |
0x4d1612 AND $-0x4,%RDX |
0x4d1616 CMP %R15,%RDX |
0x4d1619 JB 4d1638 |
0x4d161b MOV %RAX,0x38(%R14) |
0x4d161f JMP 4d1658 |
0x4d1621 NOPW %CS:(%RAX,%RAX,1) |
(3857) 0x4d1630 MOV %RSI,%RDX |
(3857) 0x4d1633 CMP %RSI,%R15 |
(3857) 0x4d1636 JE 4d161b |
(3857) 0x4d1638 LEA 0x1(%RDX),%RSI |
(3857) 0x4d163c MOV 0x8(%R12,%RDX,8),%RDI |
(3857) 0x4d1641 CMP (%R12,%RDX,8),%RDI |
(3857) 0x4d1645 JLE 4d1630 |
(3857) 0x4d1647 MOV %RDX,(%RAX,%RCX,8) |
(3857) 0x4d164b INC %RCX |
(3857) 0x4d164e JMP 4d1630 |
0x4d1650 MOVQ $0,0x38(%R14) |
0x4d1658 XOR %EAX,%EAX |
0x4d165a POP %RBX |
0x4d165b POP %R12 |
0x4d165d POP %R14 |
0x4d165f POP %R15 |
0x4d1661 POP %RBP |
0x4d1662 VZEROUPPER |
0x4d1665 RET |
0x4d1666 MOV %R15,%RDX |
0x4d1669 SHR $0x2,%RDX |
0x4d166d MOV $0x2,%ESI |
0x4d1672 XOR %ECX,%ECX |
0x4d1674 JMP 4d1689 |
0x4d1676 NOPW %CS:(%RAX,%RAX,1) |
(3858) 0x4d1680 ADD $0x4,%RSI |
(3858) 0x4d1684 DEC %RDX |
(3858) 0x4d1687 JE 4d160f |
(3858) 0x4d1689 MOV -0x8(%R12,%RSI,8),%RDI |
(3858) 0x4d168e CMP -0x10(%R12,%RSI,8),%RDI |
(3858) 0x4d1693 JG 4d16c0 |
(3858) 0x4d1695 MOV (%R12,%RSI,8),%RBX |
(3858) 0x4d1699 CMP %RDI,%RBX |
(3858) 0x4d169c JG 4d16d9 |
(3858) 0x4d169e MOV 0x8(%R12,%RSI,8),%RDI |
(3858) 0x4d16a3 CMP %RBX,%RDI |
(3858) 0x4d16a6 JG 4d16f2 |
(3858) 0x4d16a8 CMP %RDI,0x10(%R12,%RSI,8) |
(3858) 0x4d16ad JLE 4d1680 |
(3858) 0x4d16af JMP 4d1709 |
0x4d16b1 NOPW %CS:(%RAX,%RAX,1) |
(3858) 0x4d16c0 LEA -0x2(%RSI),%RDI |
(3858) 0x4d16c4 MOV %RDI,(%RAX,%RCX,8) |
(3858) 0x4d16c8 INC %RCX |
(3858) 0x4d16cb MOV -0x8(%R12,%RSI,8),%RDI |
(3858) 0x4d16d0 MOV (%R12,%RSI,8),%RBX |
(3858) 0x4d16d4 CMP %RDI,%RBX |
(3858) 0x4d16d7 JLE 4d169e |
(3858) 0x4d16d9 LEA -0x1(%RSI),%RDI |
(3858) 0x4d16dd MOV %RDI,(%RAX,%RCX,8) |
(3858) 0x4d16e1 INC %RCX |
(3858) 0x4d16e4 MOV (%R12,%RSI,8),%RBX |
(3858) 0x4d16e8 MOV 0x8(%R12,%RSI,8),%RDI |
(3858) 0x4d16ed CMP %RBX,%RDI |
(3858) 0x4d16f0 JLE 4d16a8 |
(3858) 0x4d16f2 MOV %RSI,(%RAX,%RCX,8) |
(3858) 0x4d16f6 INC %RCX |
(3858) 0x4d16f9 MOV 0x8(%R12,%RSI,8),%RDI |
(3858) 0x4d16fe CMP %RDI,0x10(%R12,%RSI,8) |
(3858) 0x4d1703 JLE 4d1680 |
(3858) 0x4d1709 LEA 0x1(%RSI),%RDI |
(3858) 0x4d170d MOV %RDI,(%RAX,%RCX,8) |
(3858) 0x4d1711 INC %RCX |
(3858) 0x4d1714 JMP 4d1680 |
0x4d1719 NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_IJMatrixAssembleParCSR | IJMatrix_parcsr.c:2823 | exec |
○ | BuildIJLaplacian27pt | amg.c:2267 | exec |
○ | main | amg.c:274 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | csr_matrix.c:136-168 |
Module | exec |
nb instructions | 65 |
nb uops | 72 |
loop length | 236 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 18.00 cycles |
front end | 18.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 7.50 | 6.00 | 7.00 | 7.00 | 10.00 | 6.00 | 7.50 | 7.00 |
cycles | 7.50 | 6.00 | 7.00 | 7.00 | 10.00 | 6.00 | 7.50 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 16.35 |
Stall cycles | 0.00 |
Front-end | 18.00 |
Dispatch | 10.00 |
Overall L1 | 18.00 |
all | 15% |
load | 50% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 13% |
load | 31% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x10(%RDI),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4d1544 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV (%R14),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP $0x8,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4d1551 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4d15be | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOVQ $0,0x40(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
JMP 4d1650 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV %R15,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV (%R12),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x8(%R12),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDQU 0x34795(%RIP),%YMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R15,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R15,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4d15ec | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV (%R12,%RAX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,0x40(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST %RDI,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4d1650 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP %R15,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4d1650 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV $0x8,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4dd8f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
CMP $0x4,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4d1666 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4d1638 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RAX,0x38(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4d1658 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOVQ $0,0x38(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x2,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV $0x2,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4d1689 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | csr_matrix.c:136-168 |
Module | exec |
nb instructions | 65 |
nb uops | 72 |
loop length | 236 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 18.00 cycles |
front end | 18.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 7.50 | 6.00 | 7.00 | 7.00 | 10.00 | 6.00 | 7.50 | 7.00 |
cycles | 7.50 | 6.00 | 7.00 | 7.00 | 10.00 | 6.00 | 7.50 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 16.35 |
Stall cycles | 0.00 |
Front-end | 18.00 |
Dispatch | 10.00 |
Overall L1 | 18.00 |
all | 15% |
load | 50% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 13% |
load | 31% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x10(%RDI),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4d1544 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV (%R14),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP $0x8,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4d1551 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4d15be | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOVQ $0,0x40(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
JMP 4d1650 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV %R15,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV (%R12),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x8(%R12),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDQU 0x34795(%RIP),%YMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R15,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R15,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4d15ec | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV (%R12,%RAX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,0x40(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST %RDI,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4d1650 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP %R15,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4d1650 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV $0x8,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4dd8f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
CMP $0x4,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4d1666 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4d1638 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RAX,0x38(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4d1658 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOVQ $0,0x38(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x2,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV $0x2,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4d1689 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_CSRMatrixSetRownnz– | 0.01 | 0 |
○Loop 3856 - csr_matrix.c:145-148 - exec | 0.01 | 0 |
○Loop 3858 - csr_matrix.c:161-164 - exec | 0 | 0 |
○Loop 3857 - csr_matrix.c:161-166 - exec | 0 | 0 |
○Loop 3859 - csr_matrix.c:145-148 - exec | 0 | 0 |