Function: hypre_qsort2abs | Module: exec | Source: par_interp.c:3178-3192 | Coverage: 0.03% |
---|
Function: hypre_qsort2abs | Module: exec | Source: par_interp.c:3178-3192 | Coverage: 0.03% |
---|
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3178 - 3192 |
-------------------------------------------------------------------------------- |
3178: { |
3179: HYPRE_Int i, last; |
3180: if (left >= right) |
3181: return; |
3182: hypre_swap2( v, w, left, (left+right)/2); |
3183: last = left; |
3184: for (i = left+1; i <= right; i++) |
3185: if (fabs(w[i]) > fabs(w[left])) |
3186: { |
3187: hypre_swap2(v, w, ++last, i); |
3188: } |
3189: hypre_swap2(v, w, left, last); |
3190: hypre_qsort2abs(v, w, left, last-1); |
3191: hypre_qsort2abs(v, w, last+1, right); |
3192: } |
0x4313d0 PUSH %RBP |
0x4313d1 MOV %RSP,%RBP |
0x4313d4 PUSH %R15 |
0x4313d6 PUSH %R14 |
0x4313d8 PUSH %R13 |
0x4313da PUSH %R12 |
0x4313dc PUSH %RBX |
0x4313dd SUB $0x38,%RSP |
0x4313e1 CMP %RCX,%RDX |
0x4313e4 JGE 43179a |
0x4313ea MOV %RCX,%R14 |
0x4313ed MOV %RDX,%R12 |
0x4313f0 MOV %RSI,%R15 |
0x4313f3 MOV %RDI,%RBX |
0x4313f6 MOV %RCX,%RAX |
0x4313f9 NEG %RAX |
0x4313fc MOV %RAX,-0x48(%RBP) |
0x431400 VMOVDDUP 0xc4b68(%RIP),%XMM0 |
0x431408 VMOVUPD %XMM0,-0x60(%RBP) |
0x43140d MOV %RDX,%R13 |
0x431410 MOV %RCX,-0x38(%RBP) |
0x431414 MOV %RDI,-0x30(%RBP) |
0x431418 JMP 43145a |
0x43141a NOPW (%RAX,%RAX,1) |
(483) 0x431420 MOV -0x38(%RBP),%R14 |
(483) 0x431424 MOV -0x30(%RBP),%RBX |
(483) 0x431428 MOV %RBX,%RDI |
(483) 0x43142b MOV %R15,%RSI |
(483) 0x43142e MOV %R12,%RDX |
(483) 0x431431 MOV %R13,%RCX |
(483) 0x431434 CALL 4ddf60 <hypre_swap2> |
(483) 0x431439 LEA -0x1(%R13),%RCX |
(483) 0x43143d MOV %RBX,%RDI |
(483) 0x431440 MOV %R15,%RSI |
(483) 0x431443 MOV %R12,%RDX |
(483) 0x431446 CALL 4313d0 <hypre_qsort2abs> |
(483) 0x43144b INC %R13 |
(483) 0x43144e MOV %R13,%R12 |
(483) 0x431451 CMP %R14,%R13 |
(483) 0x431454 JGE 43179a |
(483) 0x43145a LEA (%R12,%R14,1),%RAX |
(483) 0x43145e MOV %RAX,%RCX |
(483) 0x431461 SHR $0x3f,%RCX |
(483) 0x431465 ADD %RAX,%RCX |
(483) 0x431468 SAR $0x1,%RCX |
(483) 0x43146b MOV %RBX,%RDI |
(483) 0x43146e MOV %R15,%RSI |
(483) 0x431471 MOV %R12,%RDX |
(483) 0x431474 CALL 4ddf60 <hypre_swap2> |
(483) 0x431479 CMP %R14,%R12 |
(483) 0x43147c JGE 431424 |
(483) 0x43147e SUB %R12,%R14 |
(483) 0x431481 MOV %R12,%R13 |
(483) 0x431484 MOV %R14,-0x40(%RBP) |
(483) 0x431488 CMP $0x8,%R14 |
(483) 0x43148c JAE 431500 |
(483) 0x43148e MOV -0x40(%RBP),%RCX |
(483) 0x431492 MOV %RCX,%RAX |
(483) 0x431495 AND $-0x8,%RAX |
(483) 0x431499 CMP %RCX,%RAX |
(483) 0x43149c JAE 431420 |
(483) 0x43149e LEA (%R12,%RAX,1),%RBX |
(483) 0x4314a2 INC %RBX |
(483) 0x4314a5 MOV -0x38(%RBP),%R14 |
(483) 0x4314a9 JMP 4314c7 |
0x4314ab NOPL (%RAX,%RAX,1) |
(484) 0x4314b0 MOV -0x48(%RBP),%RAX |
(484) 0x4314b4 ADD %RBX,%RAX |
(484) 0x4314b7 INC %RAX |
(484) 0x4314ba INC %RBX |
(484) 0x4314bd CMP $0x1,%RAX |
(484) 0x4314c1 JE 431424 |
(484) 0x4314c7 VMOVSD (%R15,%RBX,8),%XMM0 |
(484) 0x4314cd VMOVUPD -0x60(%RBP),%XMM2 |
(484) 0x4314d2 VANDPD %XMM2,%XMM0,%XMM0 |
(484) 0x4314d6 VMOVSD (%R15,%R12,8),%XMM1 |
(484) 0x4314dc VANDPD %XMM2,%XMM1,%XMM1 |
(484) 0x4314e0 VUCOMISD %XMM1,%XMM0 |
(484) 0x4314e4 JBE 4314b0 |
(484) 0x4314e6 INC %R13 |
(484) 0x4314e9 MOV -0x30(%RBP),%RDI |
(484) 0x4314ed MOV %R15,%RSI |
(484) 0x4314f0 MOV %R13,%RDX |
(484) 0x4314f3 MOV %RBX,%RCX |
(484) 0x4314f6 CALL 4ddf60 <hypre_swap2> |
(484) 0x4314fb JMP 4314b0 |
0x4314fd NOPL (%RAX) |
(483) 0x431500 MOV -0x40(%RBP),%RBX |
(483) 0x431504 SHR $0x3,%RBX |
(483) 0x431508 LEA 0x8(%R12),%R14 |
(483) 0x43150d MOV %R12,%R13 |
(483) 0x431510 JMP 43152d |
0x431512 NOPW %CS:(%RAX,%RAX,1) |
(485) 0x431520 ADD $0x8,%R14 |
(485) 0x431524 DEC %RBX |
(485) 0x431527 JE 43148e |
(485) 0x43152d VMOVSD -0x38(%R15,%R14,8),%XMM0 |
(485) 0x431534 VMOVUPD -0x60(%RBP),%XMM2 |
(485) 0x431539 VANDPD %XMM2,%XMM0,%XMM1 |
(485) 0x43153d VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x431543 VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x431547 VUCOMISD %XMM0,%XMM1 |
(485) 0x43154b JBE 431590 |
(485) 0x43154d LEA -0x7(%R14),%RCX |
(485) 0x431551 INC %R13 |
(485) 0x431554 MOV -0x30(%RBP),%RDI |
(485) 0x431558 MOV %R15,%RSI |
(485) 0x43155b MOV %R13,%RDX |
(485) 0x43155e CALL 4ddf60 <hypre_swap2> |
(485) 0x431563 VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x431569 VMOVDDUP 0xc49ff(%RIP),%XMM2 |
(485) 0x431571 VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x431575 VMOVSD -0x30(%R15,%R14,8),%XMM1 |
(485) 0x43157c VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x431580 VUCOMISD %XMM0,%XMM1 |
(485) 0x431584 JA 4315a9 |
(485) 0x431586 JMP 4315d1 |
0x431588 NOPL (%RAX,%RAX,1) |
(485) 0x431590 VMOVDDUP 0xc49d8(%RIP),%XMM2 |
(485) 0x431598 VMOVSD -0x30(%R15,%R14,8),%XMM1 |
(485) 0x43159f VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x4315a3 VUCOMISD %XMM0,%XMM1 |
(485) 0x4315a7 JBE 4315d1 |
(485) 0x4315a9 LEA -0x6(%R14),%RCX |
(485) 0x4315ad INC %R13 |
(485) 0x4315b0 MOV -0x30(%RBP),%RDI |
(485) 0x4315b4 MOV %R15,%RSI |
(485) 0x4315b7 MOV %R13,%RDX |
(485) 0x4315ba CALL 4ddf60 <hypre_swap2> |
(485) 0x4315bf VMOVDDUP 0xc49a9(%RIP),%XMM2 |
(485) 0x4315c7 VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x4315cd VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x4315d1 VMOVSD -0x28(%R15,%R14,8),%XMM1 |
(485) 0x4315d8 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x4315dc VUCOMISD %XMM0,%XMM1 |
(485) 0x4315e0 JA 431650 |
(485) 0x4315e2 VMOVSD -0x20(%R15,%R14,8),%XMM1 |
(485) 0x4315e9 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x4315ed VUCOMISD %XMM0,%XMM1 |
(485) 0x4315f1 JA 43168d |
(485) 0x4315f7 VMOVSD -0x18(%R15,%R14,8),%XMM1 |
(485) 0x4315fe VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x431602 VUCOMISD %XMM0,%XMM1 |
(485) 0x431606 JA 4316ca |
(485) 0x43160c VMOVSD -0x10(%R15,%R14,8),%XMM1 |
(485) 0x431613 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x431617 VUCOMISD %XMM0,%XMM1 |
(485) 0x43161b JA 431707 |
(485) 0x431621 VMOVSD -0x8(%R15,%R14,8),%XMM1 |
(485) 0x431628 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x43162c VUCOMISD %XMM0,%XMM1 |
(485) 0x431630 JA 431744 |
(485) 0x431636 VMOVSD (%R15,%R14,8),%XMM1 |
(485) 0x43163c VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x431640 VUCOMISD %XMM0,%XMM1 |
(485) 0x431644 JBE 431520 |
(485) 0x43164a JMP 431780 |
0x43164f NOP |
(485) 0x431650 LEA -0x5(%R14),%RCX |
(485) 0x431654 INC %R13 |
(485) 0x431657 MOV -0x30(%RBP),%RDI |
(485) 0x43165b MOV %R15,%RSI |
(485) 0x43165e MOV %R13,%RDX |
(485) 0x431661 CALL 4ddf60 <hypre_swap2> |
(485) 0x431666 VMOVDDUP 0xc4902(%RIP),%XMM2 |
(485) 0x43166e VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x431674 VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x431678 VMOVSD -0x20(%R15,%R14,8),%XMM1 |
(485) 0x43167f VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x431683 VUCOMISD %XMM0,%XMM1 |
(485) 0x431687 JBE 4315f7 |
(485) 0x43168d LEA -0x4(%R14),%RCX |
(485) 0x431691 INC %R13 |
(485) 0x431694 MOV -0x30(%RBP),%RDI |
(485) 0x431698 MOV %R15,%RSI |
(485) 0x43169b MOV %R13,%RDX |
(485) 0x43169e CALL 4ddf60 <hypre_swap2> |
(485) 0x4316a3 VMOVDDUP 0xc48c5(%RIP),%XMM2 |
(485) 0x4316ab VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x4316b1 VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x4316b5 VMOVSD -0x18(%R15,%R14,8),%XMM1 |
(485) 0x4316bc VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x4316c0 VUCOMISD %XMM0,%XMM1 |
(485) 0x4316c4 JBE 43160c |
(485) 0x4316ca LEA -0x3(%R14),%RCX |
(485) 0x4316ce INC %R13 |
(485) 0x4316d1 MOV -0x30(%RBP),%RDI |
(485) 0x4316d5 MOV %R15,%RSI |
(485) 0x4316d8 MOV %R13,%RDX |
(485) 0x4316db CALL 4ddf60 <hypre_swap2> |
(485) 0x4316e0 VMOVDDUP 0xc4888(%RIP),%XMM2 |
(485) 0x4316e8 VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x4316ee VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x4316f2 VMOVSD -0x10(%R15,%R14,8),%XMM1 |
(485) 0x4316f9 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x4316fd VUCOMISD %XMM0,%XMM1 |
(485) 0x431701 JBE 431621 |
(485) 0x431707 LEA -0x2(%R14),%RCX |
(485) 0x43170b INC %R13 |
(485) 0x43170e MOV -0x30(%RBP),%RDI |
(485) 0x431712 MOV %R15,%RSI |
(485) 0x431715 MOV %R13,%RDX |
(485) 0x431718 CALL 4ddf60 <hypre_swap2> |
(485) 0x43171d VMOVDDUP 0xc484b(%RIP),%XMM2 |
(485) 0x431725 VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x43172b VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x43172f VMOVSD -0x8(%R15,%R14,8),%XMM1 |
(485) 0x431736 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x43173a VUCOMISD %XMM0,%XMM1 |
(485) 0x43173e JBE 431636 |
(485) 0x431744 LEA -0x1(%R14),%RCX |
(485) 0x431748 INC %R13 |
(485) 0x43174b MOV -0x30(%RBP),%RDI |
(485) 0x43174f MOV %R15,%RSI |
(485) 0x431752 MOV %R13,%RDX |
(485) 0x431755 CALL 4ddf60 <hypre_swap2> |
(485) 0x43175a VMOVDDUP 0xc480e(%RIP),%XMM2 |
(485) 0x431762 VMOVSD (%R15,%R12,8),%XMM0 |
(485) 0x431768 VANDPD %XMM2,%XMM0,%XMM0 |
(485) 0x43176c VMOVSD (%R15,%R14,8),%XMM1 |
(485) 0x431772 VANDPD %XMM2,%XMM1,%XMM1 |
(485) 0x431776 VUCOMISD %XMM0,%XMM1 |
(485) 0x43177a JBE 431520 |
(485) 0x431780 INC %R13 |
(485) 0x431783 MOV -0x30(%RBP),%RDI |
(485) 0x431787 MOV %R15,%RSI |
(485) 0x43178a MOV %R13,%RDX |
(485) 0x43178d MOV %R14,%RCX |
(485) 0x431790 CALL 4ddf60 <hypre_swap2> |
(485) 0x431795 JMP 431520 |
0x43179a ADD $0x38,%RSP |
0x43179e POP %RBX |
0x43179f POP %R12 |
0x4317a1 POP %R13 |
0x4317a3 POP %R14 |
0x4317a5 POP %R15 |
0x4317a7 POP %RBP |
0x4317a8 RET |
0x4317a9 NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_qsort2abs | par_interp.c:3191 | exec |
○ | hypre_BoomerAMGInterpTruncatio[...] | par_interp.c:2912 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | hypre_BoomerAMGInterpTruncatio[...] | par_interp.c:2726 | exec |
○ | hypre_BoomerAMGBuildExtPIInter[...] | par_lr_interp.c:1799 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:847 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | par_interp.c:3178-3192 |
Module | exec |
nb instructions | 38 |
nb uops | 38 |
loop length | 133 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
micro-operation queue | 9.50 cycles |
front end | 9.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.75 | 1.75 | 6.17 | 5.83 | 10.00 | 1.50 | 2.00 | 6.00 |
cycles | 1.75 | 1.75 | 6.17 | 5.83 | 10.00 | 1.50 | 2.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.11 |
Stall cycles | 0.10 |
SB full (events) | 0.19 |
Front-end | 9.50 |
Dispatch | 10.00 |
Overall L1 | 10.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 50% |
load | 0% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 0% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 12% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 13% |
load | 12% |
store | 15% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SUB $0x38,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RCX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 43179a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RSI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NEG %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVDDUP 0xc4b68(%RIP),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %XMM0,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 43145a | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x38,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | par_interp.c:3178-3192 |
Module | exec |
nb instructions | 38 |
nb uops | 38 |
loop length | 133 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
micro-operation queue | 9.50 cycles |
front end | 9.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.75 | 1.75 | 6.17 | 5.83 | 10.00 | 1.50 | 2.00 | 6.00 |
cycles | 1.75 | 1.75 | 6.17 | 5.83 | 10.00 | 1.50 | 2.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.11 |
Stall cycles | 0.10 |
SB full (events) | 0.19 |
Front-end | 9.50 |
Dispatch | 10.00 |
Overall L1 | 10.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 50% |
load | 0% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 0% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 12% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 13% |
load | 12% |
store | 15% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SUB $0x38,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RCX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 43179a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RSI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NEG %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVDDUP 0xc4b68(%RIP),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %XMM0,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 43145a | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x38,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_qsort2abs– | 0.03 | 0.01 |
▼Loop 483 - par_interp.c:3180-3191 - exec– | 0 | 0 |
○Loop 484 - par_interp.c:3180-3187 - exec | 0.01 | 0 |
○Loop 485 - par_interp.c:3184-3187 - exec | 0 | 0 |