Loop Id: 3353 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.08% |
---|
Loop Id: 3353 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.08% |
---|
0x4c8ec0 MOV %R11,-0x30(%RBP) |
0x4c8ec4 MOV %R15,%R12 |
0x4c8ec7 CMP -0x48(%RBP),%RSI |
0x4c8ecb JGE 4c9240 |
0x4c8ed1 MOV %RSI,%RCX |
0x4c8ed4 CMPQ $0,-0xa0(%RBP) |
0x4c8edc MOV -0x50(%RBP),%RAX |
0x4c8ee0 JE 4c8ef8 |
0x4c8ee2 MOV %R12,(%RDI,%RCX,8) |
0x4c8ee6 MOVQ $0,(%R13,%R12,8) |
0x4c8eef MOV %RCX,(%RAX,%R12,8) |
0x4c8ef3 LEA 0x1(%R12),%R15 |
0x4c8ef8 CMPQ $0,-0x98(%RBP) |
0x4c8f00 JE 4c9080 |
0x4c8f06 MOV -0x60(%RBP),%RAX |
0x4c8f0a MOV (%RAX,%RCX,8),%RDX |
0x4c8f0e LEA 0x1(%RCX),%RSI |
0x4c8f12 CMP 0x8(%RAX,%RCX,8),%RDX |
0x4c8f17 JGE 4c9084 |
0x4c8f1d MOV %RSI,-0x38(%RBP) |
0x4c8f21 MOV -0x30(%RBP),%R11 |
0x4c8f25 MOV %RCX,-0xc8(%RBP) |
0x4c8f2c MOV -0x108(%RBP),%R9 |
0x4c8f33 JMP 4c8f5d |
(3357) 0x4c8f40 MOV -0x40(%RBP),%RDX |
(3357) 0x4c8f44 INC %RDX |
(3357) 0x4c8f47 MOV -0x60(%RBP),%RAX |
(3357) 0x4c8f4b MOV -0xc8(%RBP),%RCX |
(3357) 0x4c8f52 CMP 0x8(%RAX,%RCX,8),%RDX |
(3357) 0x4c8f57 JGE 4c90a0 |
(3357) 0x4c8f5d MOV -0xb8(%RBP),%RAX |
(3357) 0x4c8f64 MOV (%RAX,%RDX,8),%R10 |
(3357) 0x4c8f68 MOV -0xc0(%RBP),%RAX |
(3357) 0x4c8f6f MOV %RDX,-0x40(%RBP) |
(3357) 0x4c8f73 VMOVSD (%RAX,%RDX,8),%XMM0 |
(3357) 0x4c8f78 MOV -0x80(%RBP),%RAX |
(3357) 0x4c8f7c MOV (%RAX,%R10,8),%RSI |
(3357) 0x4c8f80 MOV 0x8(%RAX,%R10,8),%RBX |
(3357) 0x4c8f85 CMP %RBX,%RSI |
(3357) 0x4c8f88 JGE 4c8ff9 |
(3357) 0x4c8f8a MOV -0xb0(%RBP),%RAX |
(3357) 0x4c8f91 JMP 4c8fb4 |
(3359) 0x4c8fa0 VADDSD (%R14,%RDX,8),%XMM1,%XMM1 |
(3359) 0x4c8fa6 VMOVSD %XMM1,(%R14,%RDX,8) |
(3359) 0x4c8fac INC %RSI |
(3359) 0x4c8faf CMP %RBX,%RSI |
(3359) 0x4c8fb2 JGE 4c8ff9 |
(3359) 0x4c8fb4 MOV (%RAX,%RSI,8),%RCX |
(3359) 0x4c8fb8 MOV -0x58(%RBP),%RDX |
(3359) 0x4c8fbc LEA (%RCX,%RDX,1),%R8 |
(3359) 0x4c8fc0 MOV (%RDI,%R8,8),%RDX |
(3359) 0x4c8fc4 VMULSD (%R9,%RSI,8),%XMM0,%XMM1 |
(3359) 0x4c8fca CMP -0x30(%RBP),%RDX |
(3359) 0x4c8fce JGE 4c8fa0 |
(3359) 0x4c8fd0 MOV %R11,(%RDI,%R8,8) |
(3359) 0x4c8fd4 VMOVSD %XMM1,(%R14,%R11,8) |
(3359) 0x4c8fda MOV -0x90(%RBP),%RDX |
(3359) 0x4c8fe1 MOV %RCX,(%RDX,%R11,8) |
(3359) 0x4c8fe5 INC %R11 |
(3359) 0x4c8fe8 MOV -0x80(%RBP),%RCX |
(3359) 0x4c8fec MOV 0x8(%RCX,%R10,8),%RBX |
(3359) 0x4c8ff1 INC %RSI |
(3359) 0x4c8ff4 CMP %RBX,%RSI |
(3359) 0x4c8ff7 JL 4c8fb4 |
(3357) 0x4c8ff9 MOV -0x78(%RBP),%RAX |
(3357) 0x4c8ffd MOV (%RAX,%R10,8),%RSI |
(3357) 0x4c9001 MOV 0x8(%RAX,%R10,8),%RBX |
(3357) 0x4c9006 CMP %RBX,%RSI |
(3357) 0x4c9009 JGE 4c8f40 |
(3357) 0x4c900f MOV -0xa8(%RBP),%R8 |
(3357) 0x4c9016 JMP 4c903a |
(3358) 0x4c9020 VADDSD (%R13,%RDX,8),%XMM1,%XMM1 |
(3358) 0x4c9027 VMOVSD %XMM1,(%R13,%RDX,8) |
(3358) 0x4c902e INC %RSI |
(3358) 0x4c9031 CMP %RBX,%RSI |
(3358) 0x4c9034 JGE 4c8f40 |
(3358) 0x4c903a MOV (%R8,%RSI,8),%RCX |
(3358) 0x4c903e MOV (%RDI,%RCX,8),%RDX |
(3358) 0x4c9042 MOV -0x100(%RBP),%RAX |
(3358) 0x4c9049 VMULSD (%RAX,%RSI,8),%XMM0,%XMM1 |
(3358) 0x4c904e CMP %R12,%RDX |
(3358) 0x4c9051 JGE 4c9020 |
(3358) 0x4c9053 MOV %R15,(%RDI,%RCX,8) |
(3358) 0x4c9057 VMOVSD %XMM1,(%R13,%R15,8) |
(3358) 0x4c905e MOV -0x50(%RBP),%RAX |
(3358) 0x4c9062 MOV %RCX,(%RAX,%R15,8) |
(3358) 0x4c9066 INC %R15 |
(3358) 0x4c9069 MOV -0x78(%RBP),%RCX |
(3358) 0x4c906d MOV 0x8(%RCX,%R10,8),%RBX |
(3358) 0x4c9072 INC %RSI |
(3358) 0x4c9075 CMP %RBX,%RSI |
(3358) 0x4c9078 JL 4c903a |
(3357) 0x4c907a JMP 4c8f40 |
0x4c9080 LEA 0x1(%RCX),%RSI |
0x4c9084 MOV -0x30(%RBP),%R11 |
0x4c9088 MOV -0x68(%RBP),%RAX |
0x4c908c MOV (%RAX,%RCX,8),%R8 |
0x4c9090 CMP (%RAX,%RSI,8),%R8 |
0x4c9094 JGE 4c8ec0 |
0x4c909a JMP 4c90b6 |
0x4c90a0 MOV -0x38(%RBP),%RSI |
0x4c90a4 MOV -0x68(%RBP),%RAX |
0x4c90a8 MOV (%RAX,%RCX,8),%R8 |
0x4c90ac CMP (%RAX,%RSI,8),%R8 |
0x4c90b0 JGE 4c8ec0 |
0x4c90b6 MOV %RSI,-0x38(%RBP) |
0x4c90ba JMP 4c90d5 |
(3354) 0x4c90c0 INC %R8 |
(3354) 0x4c90c3 MOV -0x68(%RBP),%RAX |
(3354) 0x4c90c7 MOV -0x38(%RBP),%RSI |
(3354) 0x4c90cb CMP (%RAX,%RSI,8),%R8 |
(3354) 0x4c90cf JGE 4c8ec0 |
(3354) 0x4c90d5 MOV -0xe0(%RBP),%RAX |
(3354) 0x4c90dc MOV (%RAX,%R8,8),%R9 |
(3354) 0x4c90e0 MOV -0xd8(%RBP),%RAX |
(3354) 0x4c90e7 VMOVSD (%RAX,%R8,8),%XMM0 |
(3354) 0x4c90ed MOV -0x88(%RBP),%RAX |
(3354) 0x4c90f4 MOV (%RAX,%R9,8),%RSI |
(3354) 0x4c90f8 MOV 0x8(%RAX,%R9,8),%RBX |
(3354) 0x4c90fd CMP %RBX,%RSI |
(3354) 0x4c9100 JGE 4c9175 |
(3354) 0x4c9102 MOV -0x50(%RBP),%R10 |
(3354) 0x4c9106 MOV -0x110(%RBP),%RAX |
(3354) 0x4c910d JMP 4c9136 |
(3356) 0x4c9120 VADDSD (%R13,%RDX,8),%XMM1,%XMM1 |
(3356) 0x4c9127 VMOVSD %XMM1,(%R13,%RDX,8) |
(3356) 0x4c912e INC %RSI |
(3356) 0x4c9131 CMP %RBX,%RSI |
(3356) 0x4c9134 JGE 4c9175 |
(3356) 0x4c9136 MOV -0x118(%RBP),%RCX |
(3356) 0x4c913d MOV (%RCX,%RSI,8),%RCX |
(3356) 0x4c9141 MOV (%RDI,%RCX,8),%RDX |
(3356) 0x4c9145 VMULSD (%RAX,%RSI,8),%XMM0,%XMM1 |
(3356) 0x4c914a CMP %R12,%RDX |
(3356) 0x4c914d JGE 4c9120 |
(3356) 0x4c914f MOV %R15,(%RDI,%RCX,8) |
(3356) 0x4c9153 VMOVSD %XMM1,(%R13,%R15,8) |
(3356) 0x4c915a MOV %RCX,(%R10,%R15,8) |
(3356) 0x4c915e INC %R15 |
(3356) 0x4c9161 MOV -0x88(%RBP),%RCX |
(3356) 0x4c9168 MOV 0x8(%RCX,%R9,8),%RBX |
(3356) 0x4c916d INC %RSI |
(3356) 0x4c9170 CMP %RBX,%RSI |
(3356) 0x4c9173 JL 4c9136 |
(3354) 0x4c9175 CMPQ $0,-0xd0(%RBP) |
(3354) 0x4c917d JE 4c90c0 |
(3354) 0x4c9183 MOV -0x70(%RBP),%RAX |
(3354) 0x4c9187 MOV (%RAX,%R9,8),%RSI |
(3354) 0x4c918b MOV 0x8(%RAX,%R9,8),%RBX |
(3354) 0x4c9190 CMP %RBX,%RSI |
(3354) 0x4c9193 JGE 4c90c0 |
(3354) 0x4c9199 MOV -0xe8(%RBP),%R10 |
(3354) 0x4c91a0 JMP 4c91d8 |
(3355) 0x4c91c0 VADDSD (%R14,%RAX,8),%XMM1,%XMM1 |
(3355) 0x4c91c6 VMOVSD %XMM1,(%R14,%RAX,8) |
(3355) 0x4c91cc INC %RSI |
(3355) 0x4c91cf CMP %RBX,%RSI |
(3355) 0x4c91d2 JGE 4c90c0 |
(3355) 0x4c91d8 MOV -0xf0(%RBP),%RAX |
(3355) 0x4c91df MOV (%RAX,%RSI,8),%RAX |
(3355) 0x4c91e3 MOV -0xf8(%RBP),%RCX |
(3355) 0x4c91ea MOV (%RCX,%RAX,8),%RCX |
(3355) 0x4c91ee MOV -0x58(%RBP),%RAX |
(3355) 0x4c91f2 LEA (%RCX,%RAX,1),%RDX |
(3355) 0x4c91f6 MOV (%RDI,%RDX,8),%RAX |
(3355) 0x4c91fa VMULSD (%R10,%RSI,8),%XMM0,%XMM1 |
(3355) 0x4c9200 CMP -0x30(%RBP),%RAX |
(3355) 0x4c9204 JGE 4c91c0 |
(3355) 0x4c9206 MOV %R11,(%RDI,%RDX,8) |
(3355) 0x4c920a VMOVSD %XMM1,(%R14,%R11,8) |
(3355) 0x4c9210 MOV -0x90(%RBP),%RAX |
(3355) 0x4c9217 MOV %RCX,(%RAX,%R11,8) |
(3355) 0x4c921b INC %R11 |
(3355) 0x4c921e MOV -0x70(%RBP),%RAX |
(3355) 0x4c9222 MOV 0x8(%RAX,%R9,8),%RBX |
(3355) 0x4c9227 INC %RSI |
(3355) 0x4c922a CMP %RBX,%RSI |
(3355) 0x4c922d JL 4c91d8 |
(3354) 0x4c922f JMP 4c90c0 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
875: { |
876: B_marker[i1] = jj_count_diag; |
877: C_diag_data[jj_count_diag] = zero; |
878: C_diag_j[jj_count_diag] = i1; |
879: jj_count_diag++; |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | hypre_ParMatmul | par_csr_matop.c:829 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:1226 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 11.47 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-989 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.25 |
CQA cycles if no scalar integer | 10.25 |
CQA cycles if FP arith vectorized | 10.25 |
CQA cycles if fully vectorized | 0.89 |
Front-end cycles | 10.25 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 7.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 7.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.40 |
Stall cycles (UFS) | 0.00 |
Nb insns | 38.00 |
Nb uops | 38.00 |
Nb loads | 17.00 |
Nb stores | 7.00 |
Nb stack references | 10.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.11 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 11.47 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-989 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.25 |
CQA cycles if no scalar integer | 10.25 |
CQA cycles if FP arith vectorized | 10.25 |
CQA cycles if fully vectorized | 0.89 |
Front-end cycles | 10.25 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 7.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 7.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.40 |
Stall cycles (UFS) | 0.00 |
Nb insns | 38.00 |
Nb uops | 38.00 |
Nb loads | 17.00 |
Nb stores | 7.00 |
Nb stack references | 10.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.11 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 38 |
nb uops | 38 |
loop length | 173 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 10.25 cycles |
front end | 10.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
cycles | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.40 |
Stall cycles | 0.00 |
Front-end | 10.25 |
Dispatch | 8.50 |
Overall L1 | 10.25 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R11,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R15,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP -0x48(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c9240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMPQ $0,-0xa0(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 4c8ef8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,(%RDI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,(%R13,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV %RCX,(%RAX,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x1(%R12),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0x98(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 4c9080 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RCX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RCX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x8(%RAX,%RCX,8),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c9084 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RCX,-0xc8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x108(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JMP 4c8f5d | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
LEA 0x1(%RCX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RCX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RSI,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c8ec0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4c90b6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV -0x38(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RCX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RSI,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c8ec0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4c90d5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 38 |
nb uops | 38 |
loop length | 173 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 10.25 cycles |
front end | 10.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
cycles | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.40 |
Stall cycles | 0.00 |
Front-end | 10.25 |
Dispatch | 8.50 |
Overall L1 | 10.25 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R11,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R15,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP -0x48(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c9240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMPQ $0,-0xa0(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 4c8ef8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,(%RDI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,(%R13,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV %RCX,(%RAX,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x1(%R12),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0x98(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 4c9080 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RCX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RCX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x8(%RAX,%RCX,8),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c9084 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RCX,-0xc8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x108(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JMP 4c8f5d | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
LEA 0x1(%RCX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RCX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RSI,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c8ec0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4c90b6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV -0x38(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RCX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RSI,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c8ec0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4c90d5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |