Loop Id: 2820 | Module: exec | Source: IJMatrix_parcsr.c:306-307 | Coverage: 0.03% |
---|
Loop Id: 2820 | Module: exec | Source: IJMatrix_parcsr.c:306-307 | Coverage: 0.03% |
---|
0x57ec1a VMOVDQU64 (%R9,%RBX,1),%ZMM14 [2] |
0x57ec21 VMOVDQU64 %ZMM14,(%R13,%RBX,1) [4] |
0x57ec29 VMOVDQU64 (%R15,%RBX,1),%ZMM15 [3] |
0x57ec30 VMOVDQU64 %ZMM15,(%R10,%RBX,1) [1] |
0x57ec37 VMOVDQU64 0x40(%R9,%RBX,1),%ZMM2 [2] |
0x57ec3f VMOVDQU64 %ZMM2,0x40(%R13,%RBX,1) [4] |
0x57ec47 VMOVDQU64 0x40(%R15,%RBX,1),%ZMM3 [3] |
0x57ec4f VMOVDQU64 %ZMM3,0x40(%R10,%RBX,1) [1] |
0x57ec57 VMOVDQU64 0x80(%R9,%RBX,1),%ZMM0 [2] |
0x57ec5f VMOVDQU64 %ZMM0,0x80(%R13,%RBX,1) [4] |
0x57ec67 VMOVDQU64 0x80(%R15,%RBX,1),%ZMM1 [3] |
0x57ec6f VMOVDQU64 %ZMM1,0x80(%R10,%RBX,1) [1] |
0x57ec77 VMOVDQU64 0xc0(%R9,%RBX,1),%ZMM4 [2] |
0x57ec7f VMOVDQU64 %ZMM4,0xc0(%R13,%RBX,1) [4] |
0x57ec87 VMOVDQU64 0xc0(%R15,%RBX,1),%ZMM5 [3] |
0x57ec8f VMOVDQU64 %ZMM5,0xc0(%R10,%RBX,1) [1] |
0x57ec97 VMOVDQU64 0x100(%R9,%RBX,1),%ZMM6 [2] |
0x57ec9f VMOVDQU64 %ZMM6,0x100(%R13,%RBX,1) [4] |
0x57eca7 VMOVDQU64 0x100(%R15,%RBX,1),%ZMM7 [3] |
0x57ecaf VMOVDQU64 %ZMM7,0x100(%R10,%RBX,1) [1] |
0x57ecb7 VMOVDQU64 0x140(%R9,%RBX,1),%ZMM8 [2] |
0x57ecbf VMOVDQU64 %ZMM8,0x140(%R13,%RBX,1) [4] |
0x57ecc7 VMOVDQU64 0x140(%R15,%RBX,1),%ZMM9 [3] |
0x57eccf VMOVDQU64 %ZMM9,0x140(%R10,%RBX,1) [1] |
0x57ecd7 VMOVDQU64 0x180(%R9,%RBX,1),%ZMM10 [2] |
0x57ecdf VMOVDQU64 %ZMM10,0x180(%R13,%RBX,1) [4] |
0x57ece7 VMOVDQU64 0x180(%R15,%RBX,1),%ZMM11 [3] |
0x57ecef VMOVDQU64 %ZMM11,0x180(%R10,%RBX,1) [1] |
0x57ecf7 VMOVDQU64 0x1c0(%R9,%RBX,1),%ZMM12 [2] |
0x57ecff VMOVDQU64 %ZMM12,0x1c0(%R13,%RBX,1) [4] |
0x57ed07 VMOVDQU64 0x1c0(%R15,%RBX,1),%ZMM13 [3] |
0x57ed0f VMOVDQU64 %ZMM13,0x1c0(%R10,%RBX,1) [1] |
0x57ed17 ADD $0x200,%RBX |
0x57ed1e CMP %RBX,%R14 |
0x57ed21 JNE 57ec1a |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 306 - 307 |
-------------------------------------------------------------------------------- |
306: indx_diag[i] = diag_i[i]; |
307: indx_offd[i] = offd_i[i]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | P4, |
Function | hypre_IJMatrixInitializeParCSR._omp_fn.0 |
Source | IJMatrix_parcsr.c:306-307 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 16.00 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 10.67 |
P2 cycles | 10.67 |
P3 cycles | 16.00 |
P4 cycles | 0.50 |
P5 cycles | 0.50 |
P6 cycles | 10.67 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 16.10 |
Stall cycles (UFS) | 7.31 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 128.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1024.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | P4, |
Function | hypre_IJMatrixInitializeParCSR._omp_fn.0 |
Source | IJMatrix_parcsr.c:306-307 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 16.00 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 10.67 |
P2 cycles | 10.67 |
P3 cycles | 16.00 |
P4 cycles | 0.50 |
P5 cycles | 0.50 |
P6 cycles | 10.67 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 16.10 |
Stall cycles (UFS) | 7.31 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 128.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1024.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | hypre_IJMatrixInitializeParCSR._omp_fn.0 |
Source file and lines | IJMatrix_parcsr.c:306-307 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 269 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 10.67 | 10.67 | 16.00 | 0.50 | 0.50 | 10.67 |
cycles | 0.50 | 0.50 | 10.67 | 10.67 | 16.00 | 0.50 | 0.50 | 10.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 16.10 |
Stall cycles | 7.31 |
RS full (events) | 0.08 |
SB full (events) | 14.58 |
Front-end | 8.50 |
Dispatch | 16.00 |
Data deps. | 1.00 |
Overall L1 | 16.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU64 (%R9,%RBX,1),%ZMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM14,(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 (%R15,%RBX,1),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM15,(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x40(%R9,%RBX,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM2,0x40(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x40(%R15,%RBX,1),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM3,0x40(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x80(%R9,%RBX,1),%ZMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM0,0x80(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x80(%R15,%RBX,1),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM1,0x80(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0xc0(%R9,%RBX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM4,0xc0(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0xc0(%R15,%RBX,1),%ZMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM5,0xc0(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x100(%R9,%RBX,1),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM6,0x100(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x100(%R15,%RBX,1),%ZMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM7,0x100(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x140(%R9,%RBX,1),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM8,0x140(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x140(%R15,%RBX,1),%ZMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM9,0x140(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x180(%R9,%RBX,1),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM10,0x180(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x180(%R15,%RBX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM11,0x180(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x1c0(%R9,%RBX,1),%ZMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM12,0x1c0(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x1c0(%R15,%RBX,1),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM13,0x1c0(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
ADD $0x200,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RBX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 57ec1a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_IJMatrixInitializeParCSR._omp_fn.0 |
Source file and lines | IJMatrix_parcsr.c:306-307 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 269 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 10.67 | 10.67 | 16.00 | 0.50 | 0.50 | 10.67 |
cycles | 0.50 | 0.50 | 10.67 | 10.67 | 16.00 | 0.50 | 0.50 | 10.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 16.10 |
Stall cycles | 7.31 |
RS full (events) | 0.08 |
SB full (events) | 14.58 |
Front-end | 8.50 |
Dispatch | 16.00 |
Data deps. | 1.00 |
Overall L1 | 16.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU64 (%R9,%RBX,1),%ZMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM14,(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 (%R15,%RBX,1),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM15,(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x40(%R9,%RBX,1),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM2,0x40(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x40(%R15,%RBX,1),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM3,0x40(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x80(%R9,%RBX,1),%ZMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM0,0x80(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x80(%R15,%RBX,1),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM1,0x80(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0xc0(%R9,%RBX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM4,0xc0(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0xc0(%R15,%RBX,1),%ZMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM5,0xc0(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x100(%R9,%RBX,1),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM6,0x100(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x100(%R15,%RBX,1),%ZMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM7,0x100(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x140(%R9,%RBX,1),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM8,0x140(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x140(%R15,%RBX,1),%ZMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM9,0x140(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x180(%R9,%RBX,1),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM10,0x180(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x180(%R15,%RBX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM11,0x180(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x1c0(%R9,%RBX,1),%ZMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM12,0x1c0(%R13,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
VMOVDQU64 0x1c0(%R15,%RBX,1),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 %ZMM13,0x1c0(%R10,%RBX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 |
ADD $0x200,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RBX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 57ec1a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |