Loop Id: 2560 | Module: exec | Source: ams.c:78-79 | Coverage: 1.36% |
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Loop Id: 2560 | Module: exec | Source: ams.c:78-79 | Coverage: 1.36% |
---|
0x495b50 VMOVUPD (%RSI,%RDX,8),%YMM0 [2] |
0x495b55 VDIVPD (%RDI,%RDX,8),%YMM0,%YMM0 [3] |
0x495b5a VADDPD (%R12,%RDX,8),%YMM0,%YMM0 [1] |
0x495b60 VMOVUPD %YMM0,(%R12,%RDX,8) [1] |
0x495b66 ADD $0x4,%RDX |
0x495b6a CMP %RCX,%RDX |
0x495b6d JLE 495b50 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 78 - 79 |
-------------------------------------------------------------------------------- |
78: for (i = 0; i < num_rows; i++) |
79: u_data[i] += v_data[i] / l1_norms[i]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►96.00+ | hypre_BoomerAMGCycle | par_cycle.c:322 | exec |
○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
○ | hypre_PCGSolve | pcg.c:545 | exec |
○ | main | amg.c:419 | exec |
○ | __libc_init_first | libc.so.6 | |
►4.00+ | hypre_BoomerAMGCycle | par_cycle.c:322 | exec |
○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
○ | hypre_PCGSolve | pcg.c:424 | exec |
○ | main | amg.c:419 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.00 |
Bottlenecks | P0, |
Function | hypre_ParCSRRelax |
Source | ams.c:78-79 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 2.00 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 1.50 |
P2 cycles | 1.50 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 8.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.22 - 8.23 |
Stall cycles (UFS) | 5.74 - 5.75 |
Nb insns | 7.00 |
Nb uops | 6.00 |
Nb loads | 3.00 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.00 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 4.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 32.00 |
Stride 0 | 0.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.00 |
Bottlenecks | P0, |
Function | hypre_ParCSRRelax |
Source | ams.c:78-79 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 2.00 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 1.50 |
P2 cycles | 1.50 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 8.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.22 - 8.23 |
Stall cycles (UFS) | 5.74 - 5.75 |
Nb insns | 7.00 |
Nb uops | 6.00 |
Nb loads | 3.00 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.00 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 4.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 32.00 |
Stride 0 | 0.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | hypre_ParCSRRelax |
Source file and lines | ams.c:78-79 |
Module | exec |
nb instructions | 7 |
nb uops | 6 |
loop length | 31 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 2.00 cycles |
front end | 2.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 |
cycles | 1.00 | 1.00 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | 8.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.22-8.23 |
Stall cycles | 5.74-5.75 |
LB full (events) | 6.70-6.71 |
Front-end | 2.00 |
Dispatch | 1.50 |
DIV/SQRT | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 50% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%RDX,8),%YMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD (%RDI,%RDX,8),%YMM0,%YMM0 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 8 |
VADDPD (%R12,%RDX,8),%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM0,(%R12,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RCX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 495b50 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_ParCSRRelax |
Source file and lines | ams.c:78-79 |
Module | exec |
nb instructions | 7 |
nb uops | 6 |
loop length | 31 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 2.00 cycles |
front end | 2.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 |
cycles | 1.00 | 1.00 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | 8.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.22-8.23 |
Stall cycles | 5.74-5.75 |
LB full (events) | 6.70-6.71 |
Front-end | 2.00 |
Dispatch | 1.50 |
DIV/SQRT | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 50% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%RDX,8),%YMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VDIVPD (%RDI,%RDX,8),%YMM0,%YMM0 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 8 |
VADDPD (%R12,%RDX,8),%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM0,(%R12,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RCX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 495b50 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |