Loop Id: 3856 | Module: exec | Source: csr_matrix.c:145-148 | Coverage: 0.01% |
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Loop Id: 3856 | Module: exec | Source: csr_matrix.c:145-148 | Coverage: 0.01% |
---|
0x4d1570 VMOVDQU (%RCX),%YMM1 [1] |
0x4d1574 VMOVDQU 0x20(%RCX),%YMM2 [1] |
0x4d1579 VMOVQ %RDX,%XMM3 |
0x4d157e VMOVDQA %YMM1,%YMM4 |
0x4d1582 VPERMT2Q %YMM3,%YMM0,%YMM4 |
0x4d1588 VALIGNQ $0x3,%YMM1,%YMM2,%YMM3 |
0x4d158f VPCMPGTQ %YMM3,%YMM2,%K0 |
0x4d1595 KSHIFTLB $0x4,%K0,%K0 |
0x4d159b VPCMPGTQ %YMM4,%YMM1,%K1 |
0x4d15a1 KORB %K0,%K1,%K0 |
0x4d15a5 KMOVB %K0,%EDX |
0x4d15a9 POPCNT %RDX,%RDX |
0x4d15ae ADD %RDX,%RDI |
0x4d15b1 MOV 0x38(%RCX),%RDX [1] |
0x4d15b5 ADD $0x40,%RCX |
0x4d15b9 DEC %RAX |
0x4d15bc JNE 4d1570 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c: 145 - 148 |
-------------------------------------------------------------------------------- |
145: for (i=0; i < num_rows; i++) |
146: { |
147: adiag = (A_i[i+1] - A_i[i]); |
148: if(adiag > 0) irownnz++; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_IJMatrixAssembleParCSR | IJMatrix_parcsr.c:2823 | exec |
○ | BuildIJLaplacian27pt | amg.c:2267 | exec |
○ | main | amg.c:274 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.20 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.67 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | P5, |
Function | hypre_CSRMatrixSetRownnz |
Source | csr_matrix.c:145-148 |
Source loop unroll info | unrolled by 9 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 9 |
CQA cycles | 6.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 6.00 |
CQA cycles if fully vectorized | 2.25 |
Front-end cycles | 4.00 |
DIV/SQRT cycles | 2.00 |
P0 cycles | 2.00 |
P1 cycles | 1.50 |
P2 cycles | 1.50 |
P3 cycles | 0.00 |
P4 cycles | 6.00 |
P5 cycles | 2.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 6.21 |
Stall cycles (UFS) | 1.78 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 3.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 63.64 |
Vectorization ratio load | 66.67 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 71.43 |
Vector-efficiency ratio all | 36.36 |
Vector-efficiency ratio load | 37.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 39.29 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.20 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.67 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | P5, |
Function | hypre_CSRMatrixSetRownnz |
Source | csr_matrix.c:145-148 |
Source loop unroll info | unrolled by 9 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 9 |
CQA cycles | 6.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 6.00 |
CQA cycles if fully vectorized | 2.25 |
Front-end cycles | 4.00 |
DIV/SQRT cycles | 2.00 |
P0 cycles | 2.00 |
P1 cycles | 1.50 |
P2 cycles | 1.50 |
P3 cycles | 0.00 |
P4 cycles | 6.00 |
P5 cycles | 2.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 6.21 |
Stall cycles (UFS) | 1.78 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 3.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 63.64 |
Vectorization ratio load | 66.67 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 71.43 |
Vector-efficiency ratio all | 36.36 |
Vector-efficiency ratio load | 37.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 39.29 |
Path / |
Function | hypre_CSRMatrixSetRownnz |
Source file and lines | csr_matrix.c:145-148 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 78 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 1.50 | 1.50 | 0.00 | 6.00 | 2.00 | 0.00 |
cycles | 2.00 | 2.00 | 1.50 | 1.50 | 0.00 | 6.00 | 2.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 6.21 |
Stall cycles | 1.78 |
RS full (events) | 3.02 |
PRF full (events) | 0.90 |
Front-end | 4.00 |
Dispatch | 6.00 |
Data deps. | 1.00 |
Overall L1 | 6.00 |
all | 63% |
load | 66% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 71% |
all | 36% |
load | 37% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 39% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RCX),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU 0x20(%RCX),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVQ %RDX,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVDQA %YMM1,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPERMT2Q %YMM3,%YMM0,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VALIGNQ $0x3,%YMM1,%YMM2,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPCMPGTQ %YMM3,%YMM2,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
KSHIFTLB $0x4,%K0,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4 | 1 |
VPCMPGTQ %YMM4,%YMM1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
KORB %K0,%K1,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
KMOVB %K0,%EDX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
POPCNT %RDX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RDX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x38(%RCX),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
DEC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 4d1570 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_CSRMatrixSetRownnz |
Source file and lines | csr_matrix.c:145-148 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 78 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 1.50 | 1.50 | 0.00 | 6.00 | 2.00 | 0.00 |
cycles | 2.00 | 2.00 | 1.50 | 1.50 | 0.00 | 6.00 | 2.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 6.21 |
Stall cycles | 1.78 |
RS full (events) | 3.02 |
PRF full (events) | 0.90 |
Front-end | 4.00 |
Dispatch | 6.00 |
Data deps. | 1.00 |
Overall L1 | 6.00 |
all | 63% |
load | 66% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 71% |
all | 36% |
load | 37% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 39% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RCX),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU 0x20(%RCX),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVQ %RDX,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVDQA %YMM1,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPERMT2Q %YMM3,%YMM0,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VALIGNQ $0x3,%YMM1,%YMM2,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPCMPGTQ %YMM3,%YMM2,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
KSHIFTLB $0x4,%K0,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4 | 1 |
VPCMPGTQ %YMM4,%YMM1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
KORB %K0,%K1,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
KMOVB %K0,%EDX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
POPCNT %RDX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RDX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x38(%RCX),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
DEC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 4d1570 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |