Loop Id: 3964 | Module: exec | Source: csr_matvec.c:485-615 [...] | Coverage: 0.91% |
---|
Loop Id: 3964 | Module: exec | Source: csr_matvec.c:485-615 [...] | Coverage: 0.91% |
---|
0x4e9440 CMP %R8,%RDX |
0x4e9443 LEA 0x1(%RDX),%RDX |
0x4e9447 JE 4e99e0 |
0x4e944d MOV %R11,%RSI |
0x4e9450 MOV -0x48(%RBP),%RAX |
0x4e9454 MOV 0x8(%RAX,%RDX,8),%R11 |
0x4e9459 MOV %R11,%R10 |
0x4e945c SUB %RSI,%R10 |
0x4e945f JLE 4e9440 |
0x4e9461 MOV %R10,%R9 |
0x4e9464 AND $-0x4,%R9 |
0x4e9468 JE 4e94a0 |
0x4e946a LEA -0x1(%R9),%RAX |
0x4e946e XOR %EDI,%EDI |
(3968) 0x4e9470 ADD $0x4,%RDI |
(3968) 0x4e9474 CMP %RAX,%RDI |
(3968) 0x4e9477 JBE 4e9470 |
0x4e9479 MOV %R9,%RDI |
0x4e947c CMP %R9,%R10 |
0x4e947f JNE 4e94a2 |
0x4e9481 JMP 4e94b5 |
0x4e94a0 XOR %EDI,%EDI |
0x4e94a2 MOV %R11,%RAX |
0x4e94a5 SUB %RDI,%RAX |
0x4e94a8 SUB %RSI,%RAX |
0x4e94ab NOPL (%RAX,%RAX,1) |
(3965) 0x4e94b0 DEC %RAX |
(3965) 0x4e94b3 JNE 4e94b0 |
0x4e94b5 CMP $0x4,%R10 |
0x4e94b9 JB 4e954c |
0x4e94bf MOV %R10,%RDI |
0x4e94c2 SHR $0x2,%RDI |
0x4e94c6 LEA 0x18(,%RSI,8),%RAX |
0x4e94ce XCHG %AX,%AX |
(3967) 0x4e94d0 VMOVSD (%R15,%RDX,8),%XMM0 |
(3967) 0x4e94d6 VMOVSD -0x18(%R12,%RAX,1),%XMM1 |
(3967) 0x4e94dd MOV -0x18(%R13,%RAX,1),%RCX |
(3967) 0x4e94e2 VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3967) 0x4e94e8 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3967) 0x4e94ed MOV -0x10(%R13,%RAX,1),%RCX |
(3967) 0x4e94f2 VMOVSD (%R15,%RDX,8),%XMM0 |
(3967) 0x4e94f8 VMOVSD -0x10(%R12,%RAX,1),%XMM1 |
(3967) 0x4e94ff VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3967) 0x4e9505 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3967) 0x4e950a MOV -0x8(%R13,%RAX,1),%RCX |
(3967) 0x4e950f VMOVSD (%R15,%RDX,8),%XMM0 |
(3967) 0x4e9515 VMOVSD -0x8(%R12,%RAX,1),%XMM1 |
(3967) 0x4e951c VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3967) 0x4e9522 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3967) 0x4e9527 MOV (%R13,%RAX,1),%RCX |
(3967) 0x4e952c VMOVSD (%R15,%RDX,8),%XMM0 |
(3967) 0x4e9532 VMOVSD (%R12,%RAX,1),%XMM1 |
(3967) 0x4e9538 VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3967) 0x4e953e VMOVSD %XMM1,(%RBX,%RCX,8) |
(3967) 0x4e9543 ADD $0x20,%RAX |
(3967) 0x4e9547 DEC %RDI |
(3967) 0x4e954a JNE 4e94d0 |
0x4e954c CMP %R10,%R9 |
0x4e954f JAE 4e9440 |
0x4e9555 ADD %R9,%RSI |
0x4e9558 NOPL (%RAX,%RAX,1) |
(3966) 0x4e9560 MOV (%R13,%RSI,8),%RAX |
(3966) 0x4e9565 VMOVSD (%R15,%RDX,8),%XMM0 |
(3966) 0x4e956b VMOVSD (%R12,%RSI,8),%XMM1 |
(3966) 0x4e9571 VFMADD213SD (%RBX,%RAX,8),%XMM0,%XMM1 |
(3966) 0x4e9577 VMOVSD %XMM1,(%RBX,%RAX,8) |
(3966) 0x4e957c INC %RSI |
(3966) 0x4e957f CMP %RSI,%R11 |
(3966) 0x4e9582 JNE 4e9560 |
0x4e9584 JMP 4e9440 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 485 - 615 |
-------------------------------------------------------------------------------- |
485: hypre_assert( num_vectors == hypre_VectorNumVectors(y) ); |
[...] |
608: for (i = 0; i < num_rows; i++) |
609: { |
610: if ( num_vectors==1 ) |
611: { |
612: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
613: { |
614: j = A_j[jj]; |
615: y_data[j] += A_data[jj] * x_data[i]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►98.55+ | hypre_ParCSRMatrixMatvecT | par_csr_matvec.c:432 | exec |
○ | hypre_BoomerAMGCycle | par_cycle.c:431 | exec |
○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
○ | hypre_PCGSolve | pcg.c:545 | exec |
○ | main | amg.c:419 | exec |
○ | __libc_init_first | libc.so.6 | |
►1.45+ | hypre_ParCSRMatrixMatvecT | par_csr_matvec.c:432 | exec |
○ | hypre_BoomerAMGCycle | par_cycle.c:431 | exec |
○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
○ | hypre_PCGSolve | pcg.c:424 | exec |
○ | main | amg.c:419 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 13.27 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.62 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecT |
Source | csr_matvec.c:485-615 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.50 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 8.50 |
CQA cycles if fully vectorized | 0.64 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 5.25 |
P0 cycles | 5.25 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 0.00 |
P4 cycles | 5.25 |
P5 cycles | 5.25 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 8.63 |
Stall cycles (UFS) | 0.00 |
Nb insns | 34.00 |
Nb uops | 34.00 |
Nb loads | 2.00 |
Nb stores | 0.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 1.88 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.46 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.25 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 13.27 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.62 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecT |
Source | csr_matvec.c:485-615 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.50 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 8.50 |
CQA cycles if fully vectorized | 0.64 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 5.25 |
P0 cycles | 5.25 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 0.00 |
P4 cycles | 5.25 |
P5 cycles | 5.25 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 8.63 |
Stall cycles (UFS) | 0.00 |
Nb insns | 34.00 |
Nb uops | 34.00 |
Nb loads | 2.00 |
Nb stores | 0.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 1.88 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.46 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.25 |
Path / |
Function | hypre_CSRMatrixMatvecT |
Source file and lines | csr_matvec.c:485-615 |
Module | exec |
nb instructions | 34 |
nb uops | 34 |
loop length | 126 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 5.25 | 5.25 | 1.00 | 1.00 | 0.00 | 5.25 | 5.25 | 0.00 |
cycles | 5.25 | 5.25 | 1.00 | 1.00 | 0.00 | 5.25 | 5.25 | 0.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 8.63 |
Stall cycles | 0.00 |
Front-end | 8.50 |
Dispatch | 5.25 |
Overall L1 | 8.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x1(%RDX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4e99e0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R11,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x8(%RAX,%RDX,8),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R11,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RSI,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4e9440 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R10,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x4,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4e94a0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x1(%R9),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R9,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP %R9,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 4e94a2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4e94b5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R11,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SUB %RSI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP $0x4,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4e954c | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R10,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA 0x18(,%RSI,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP %R10,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4e9440 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %R9,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4e9440 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | hypre_CSRMatrixMatvecT |
Source file and lines | csr_matvec.c:485-615 |
Module | exec |
nb instructions | 34 |
nb uops | 34 |
loop length | 126 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 5.25 | 5.25 | 1.00 | 1.00 | 0.00 | 5.25 | 5.25 | 0.00 |
cycles | 5.25 | 5.25 | 1.00 | 1.00 | 0.00 | 5.25 | 5.25 | 0.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 8.63 |
Stall cycles | 0.00 |
Front-end | 8.50 |
Dispatch | 5.25 |
Overall L1 | 8.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x1(%RDX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4e99e0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R11,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x8(%RAX,%RDX,8),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R11,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RSI,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4e9440 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R10,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x4,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4e94a0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x1(%R9),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R9,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP %R9,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 4e94a2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4e94b5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R11,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SUB %RSI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP $0x4,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4e954c | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R10,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA 0x18(,%RSI,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP %R10,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4e9440 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %R9,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4e9440 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |