Loop Id: 3331 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.1% |
---|
Loop Id: 3331 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.1% |
---|
0x4b7240 MOV %R11,-0x30(%RBP) |
0x4b7244 MOV %R15,%R12 |
0x4b7247 CMP -0x98(%RBP),%RCX |
0x4b724e JGE 4b7584 |
0x4b7254 MOV %RCX,%RDX |
0x4b7257 CMPQ $0,-0xa8(%RBP) |
0x4b725f MOV -0x50(%RBP),%RAX |
0x4b7263 JE 4b727b |
0x4b7265 MOV %R12,(%RDI,%RDX,8) |
0x4b7269 MOVQ $0,(%R13,%R12,8) |
0x4b7272 MOV %RDX,(%RAX,%R12,8) |
0x4b7276 LEA 0x1(%R12),%R15 |
0x4b727b CMPQ $0,-0xa0(%RBP) |
0x4b7283 JE 4b73f0 |
0x4b7289 MOV -0x60(%RBP),%RAX |
0x4b728d MOV (%RAX,%RDX,8),%RSI |
0x4b7291 LEA 0x1(%RDX),%RCX |
0x4b7295 CMP 0x8(%RAX,%RDX,8),%RSI |
0x4b729a JGE 4b73f4 |
0x4b72a0 MOV %RCX,-0x38(%RBP) |
0x4b72a4 MOV -0x30(%RBP),%R11 |
0x4b72a8 MOV %RDX,-0x48(%RBP) |
0x4b72ac MOV -0x108(%RBP),%R9 |
0x4b72b3 JMP 4b72da |
(3335) 0x4b72c0 MOV -0x40(%RBP),%RSI |
(3335) 0x4b72c4 INC %RSI |
(3335) 0x4b72c7 MOV -0x60(%RBP),%RAX |
(3335) 0x4b72cb MOV -0x48(%RBP),%RDX |
(3335) 0x4b72cf CMP 0x8(%RAX,%RDX,8),%RSI |
(3335) 0x4b72d4 JGE 4b7410 |
(3335) 0x4b72da MOV -0xc0(%RBP),%RAX |
(3335) 0x4b72e1 MOV (%RAX,%RSI,8),%R10 |
(3335) 0x4b72e5 MOV -0xc8(%RBP),%RAX |
(3335) 0x4b72ec MOV %RSI,-0x40(%RBP) |
(3335) 0x4b72f0 VMOVSD (%RAX,%RSI,8),%XMM0 |
(3335) 0x4b72f5 MOV -0x80(%RBP),%RAX |
(3335) 0x4b72f9 MOV (%RAX,%R10,8),%RSI |
(3335) 0x4b72fd MOV 0x8(%RAX,%R10,8),%RBX |
(3335) 0x4b7302 CMP %RBX,%RSI |
(3335) 0x4b7305 JGE 4b7368 |
(3335) 0x4b7307 MOV -0xb8(%RBP),%RAX |
(3335) 0x4b730e JMP 4b7324 |
(3337) 0x4b7310 VADDSD (%R14,%R8,8),%XMM1,%XMM1 |
(3337) 0x4b7316 VMOVSD %XMM1,(%R14,%R8,8) |
(3337) 0x4b731c INC %RSI |
(3337) 0x4b731f CMP %RBX,%RSI |
(3337) 0x4b7322 JGE 4b7368 |
(3337) 0x4b7324 MOV (%RAX,%RSI,8),%RDX |
(3337) 0x4b7328 MOV -0x58(%RBP),%RCX |
(3337) 0x4b732c ADD %RDX,%RCX |
(3337) 0x4b732f MOV (%RDI,%RCX,8),%R8 |
(3337) 0x4b7333 VMULSD (%R9,%RSI,8),%XMM0,%XMM1 |
(3337) 0x4b7339 CMP -0x30(%RBP),%R8 |
(3337) 0x4b733d JGE 4b7310 |
(3337) 0x4b733f MOV %R11,(%RDI,%RCX,8) |
(3337) 0x4b7343 VMOVSD %XMM1,(%R14,%R11,8) |
(3337) 0x4b7349 MOV -0x90(%RBP),%RCX |
(3337) 0x4b7350 MOV %RDX,(%RCX,%R11,8) |
(3337) 0x4b7354 INC %R11 |
(3337) 0x4b7357 MOV -0x80(%RBP),%RCX |
(3337) 0x4b735b MOV 0x8(%RCX,%R10,8),%RBX |
(3337) 0x4b7360 INC %RSI |
(3337) 0x4b7363 CMP %RBX,%RSI |
(3337) 0x4b7366 JL 4b7324 |
(3335) 0x4b7368 MOV -0x78(%RBP),%RAX |
(3335) 0x4b736c MOV (%RAX,%R10,8),%RSI |
(3335) 0x4b7370 MOV 0x8(%RAX,%R10,8),%RBX |
(3335) 0x4b7375 CMP %RBX,%RSI |
(3335) 0x4b7378 JGE 4b72c0 |
(3335) 0x4b737e MOV -0xb0(%RBP),%R8 |
(3335) 0x4b7385 JMP 4b73aa |
(3336) 0x4b7390 VADDSD (%R13,%RCX,8),%XMM1,%XMM1 |
(3336) 0x4b7397 VMOVSD %XMM1,(%R13,%RCX,8) |
(3336) 0x4b739e INC %RSI |
(3336) 0x4b73a1 CMP %RBX,%RSI |
(3336) 0x4b73a4 JGE 4b72c0 |
(3336) 0x4b73aa MOV (%R8,%RSI,8),%RDX |
(3336) 0x4b73ae MOV (%RDI,%RDX,8),%RCX |
(3336) 0x4b73b2 MOV -0x100(%RBP),%RAX |
(3336) 0x4b73b9 VMULSD (%RAX,%RSI,8),%XMM0,%XMM1 |
(3336) 0x4b73be CMP %R12,%RCX |
(3336) 0x4b73c1 JGE 4b7390 |
(3336) 0x4b73c3 MOV %R15,(%RDI,%RDX,8) |
(3336) 0x4b73c7 VMOVSD %XMM1,(%R13,%R15,8) |
(3336) 0x4b73ce MOV -0x50(%RBP),%RAX |
(3336) 0x4b73d2 MOV %RDX,(%RAX,%R15,8) |
(3336) 0x4b73d6 INC %R15 |
(3336) 0x4b73d9 MOV -0x78(%RBP),%RCX |
(3336) 0x4b73dd MOV 0x8(%RCX,%R10,8),%RBX |
(3336) 0x4b73e2 INC %RSI |
(3336) 0x4b73e5 CMP %RBX,%RSI |
(3336) 0x4b73e8 JL 4b73aa |
(3335) 0x4b73ea JMP 4b72c0 |
0x4b73f0 LEA 0x1(%RDX),%RCX |
0x4b73f4 MOV -0x30(%RBP),%R11 |
0x4b73f8 MOV -0x68(%RBP),%RAX |
0x4b73fc MOV (%RAX,%RDX,8),%R8 |
0x4b7400 CMP (%RAX,%RCX,8),%R8 |
0x4b7404 JGE 4b7240 |
0x4b740a JMP 4b7426 |
0x4b7410 MOV -0x38(%RBP),%RCX |
0x4b7414 MOV -0x68(%RBP),%RAX |
0x4b7418 MOV (%RAX,%RDX,8),%R8 |
0x4b741c CMP (%RAX,%RCX,8),%R8 |
0x4b7420 JGE 4b7240 |
0x4b7426 MOV %RCX,-0x38(%RBP) |
0x4b742a JMP 4b7445 |
(3332) 0x4b7430 INC %R8 |
(3332) 0x4b7433 MOV -0x68(%RBP),%RAX |
(3332) 0x4b7437 MOV -0x38(%RBP),%RCX |
(3332) 0x4b743b CMP (%RAX,%RCX,8),%R8 |
(3332) 0x4b743f JGE 4b7240 |
(3332) 0x4b7445 MOV -0xe0(%RBP),%RAX |
(3332) 0x4b744c MOV (%RAX,%R8,8),%R9 |
(3332) 0x4b7450 MOV -0xd8(%RBP),%RAX |
(3332) 0x4b7457 VMOVSD (%RAX,%R8,8),%XMM0 |
(3332) 0x4b745d MOV -0x88(%RBP),%RAX |
(3332) 0x4b7464 MOV (%RAX,%R9,8),%RDX |
(3332) 0x4b7468 MOV 0x8(%RAX,%R9,8),%RBX |
(3332) 0x4b746d CMP %RBX,%RDX |
(3332) 0x4b7470 JGE 4b74d5 |
(3332) 0x4b7472 MOV -0x50(%RBP),%R10 |
(3332) 0x4b7476 MOV -0x110(%RBP),%RAX |
(3332) 0x4b747d JMP 4b7496 |
(3334) 0x4b7480 VADDSD (%R13,%RCX,8),%XMM1,%XMM1 |
(3334) 0x4b7487 VMOVSD %XMM1,(%R13,%RCX,8) |
(3334) 0x4b748e INC %RDX |
(3334) 0x4b7491 CMP %RBX,%RDX |
(3334) 0x4b7494 JGE 4b74d5 |
(3334) 0x4b7496 MOV -0x118(%RBP),%RCX |
(3334) 0x4b749d MOV (%RCX,%RDX,8),%RSI |
(3334) 0x4b74a1 MOV (%RDI,%RSI,8),%RCX |
(3334) 0x4b74a5 VMULSD (%RAX,%RDX,8),%XMM0,%XMM1 |
(3334) 0x4b74aa CMP %R12,%RCX |
(3334) 0x4b74ad JGE 4b7480 |
(3334) 0x4b74af MOV %R15,(%RDI,%RSI,8) |
(3334) 0x4b74b3 VMOVSD %XMM1,(%R13,%R15,8) |
(3334) 0x4b74ba MOV %RSI,(%R10,%R15,8) |
(3334) 0x4b74be INC %R15 |
(3334) 0x4b74c1 MOV -0x88(%RBP),%RCX |
(3334) 0x4b74c8 MOV 0x8(%RCX,%R9,8),%RBX |
(3334) 0x4b74cd INC %RDX |
(3334) 0x4b74d0 CMP %RBX,%RDX |
(3334) 0x4b74d3 JL 4b7496 |
(3332) 0x4b74d5 CMPQ $0,-0xd0(%RBP) |
(3332) 0x4b74dd JE 4b7430 |
(3332) 0x4b74e3 MOV -0x70(%RBP),%RAX |
(3332) 0x4b74e7 MOV (%RAX,%R9,8),%RDX |
(3332) 0x4b74eb MOV 0x8(%RAX,%R9,8),%RBX |
(3332) 0x4b74f0 CMP %RBX,%RDX |
(3332) 0x4b74f3 JGE 4b7430 |
(3332) 0x4b74f9 MOV -0xe8(%RBP),%R10 |
(3332) 0x4b7500 JMP 4b7528 |
(3333) 0x4b7510 VADDSD (%R14,%RAX,8),%XMM1,%XMM1 |
(3333) 0x4b7516 VMOVSD %XMM1,(%R14,%RAX,8) |
(3333) 0x4b751c INC %RDX |
(3333) 0x4b751f CMP %RBX,%RDX |
(3333) 0x4b7522 JGE 4b7430 |
(3333) 0x4b7528 MOV -0xf0(%RBP),%RAX |
(3333) 0x4b752f MOV (%RAX,%RDX,8),%RAX |
(3333) 0x4b7533 MOV -0xf8(%RBP),%RCX |
(3333) 0x4b753a MOV (%RCX,%RAX,8),%RSI |
(3333) 0x4b753e MOV -0x58(%RBP),%RAX |
(3333) 0x4b7542 LEA (%RSI,%RAX,1),%RCX |
(3333) 0x4b7546 MOV (%RDI,%RCX,8),%RAX |
(3333) 0x4b754a VMULSD (%R10,%RDX,8),%XMM0,%XMM1 |
(3333) 0x4b7550 CMP -0x30(%RBP),%RAX |
(3333) 0x4b7554 JGE 4b7510 |
(3333) 0x4b7556 MOV %R11,(%RDI,%RCX,8) |
(3333) 0x4b755a VMOVSD %XMM1,(%R14,%R11,8) |
(3333) 0x4b7560 MOV -0x90(%RBP),%RAX |
(3333) 0x4b7567 MOV %RSI,(%RAX,%R11,8) |
(3333) 0x4b756b INC %R11 |
(3333) 0x4b756e MOV -0x70(%RBP),%RAX |
(3333) 0x4b7572 MOV 0x8(%RAX,%R9,8),%RBX |
(3333) 0x4b7577 INC %RDX |
(3333) 0x4b757a CMP %RBX,%RDX |
(3333) 0x4b757d JL 4b7528 |
(3332) 0x4b757f JMP 4b7430 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
875: { |
876: B_marker[i1] = jj_count_diag; |
877: C_diag_data[jj_count_diag] = zero; |
878: C_diag_j[jj_count_diag] = i1; |
879: jj_count_diag++; |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | hypre_ParMatmul | par_csr_matop.c:829 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:1226 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 11.47 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-989 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.25 |
CQA cycles if no scalar integer | 10.25 |
CQA cycles if FP arith vectorized | 10.25 |
CQA cycles if fully vectorized | 0.89 |
Front-end cycles | 10.25 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 7.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 7.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.40 |
Stall cycles (UFS) | 0.00 |
Nb insns | 38.00 |
Nb uops | 38.00 |
Nb loads | 17.00 |
Nb stores | 7.00 |
Nb stack references | 10.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.11 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 11.47 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-989 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.25 |
CQA cycles if no scalar integer | 10.25 |
CQA cycles if FP arith vectorized | 10.25 |
CQA cycles if fully vectorized | 0.89 |
Front-end cycles | 10.25 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 7.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 7.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.40 |
Stall cycles (UFS) | 0.00 |
Nb insns | 38.00 |
Nb uops | 38.00 |
Nb loads | 17.00 |
Nb stores | 7.00 |
Nb stack references | 10.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.11 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 38 |
nb uops | 38 |
loop length | 173 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 10.25 cycles |
front end | 10.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
cycles | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.40 |
Stall cycles | 0.00 |
Front-end | 10.25 |
Dispatch | 8.50 |
Overall L1 | 10.25 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R11,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R15,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP -0x98(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b7584 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMPQ $0,-0xa8(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 4b727b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,(%RDI,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,(%R13,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV %RDX,(%RAX,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x1(%R12),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0xa0(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 4b73f0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RDX,8),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RDX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x8(%RAX,%RDX,8),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b73f4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x108(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JMP 4b72da | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
LEA 0x1(%RDX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RDX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RCX,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b7240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4b7426 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RDX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RCX,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b7240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4b7445 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 38 |
nb uops | 38 |
loop length | 173 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 10.25 cycles |
front end | 10.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
cycles | 4.50 | 4.50 | 8.50 | 8.50 | 7.00 | 4.50 | 4.50 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.40 |
Stall cycles | 0.00 |
Front-end | 10.25 |
Dispatch | 8.50 |
Overall L1 | 10.25 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R11,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R15,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP -0x98(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b7584 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMPQ $0,-0xa8(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 4b727b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,(%RDI,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,(%R13,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV %RDX,(%RAX,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x1(%R12),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0xa0(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 4b73f0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RDX,8),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RDX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x8(%RAX,%RDX,8),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b73f4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x108(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JMP 4b72da | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
LEA 0x1(%RDX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RDX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RCX,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b7240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4b7426 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RAX,%RDX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RAX,%RCX,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4b7240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4b7445 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |