Loop Id: 1189 | Module: exec | Source: par_lr_interp.c:1221-1627 [...] | Coverage: 0.07% |
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Loop Id: 1189 | Module: exec | Source: par_lr_interp.c:1221-1627 [...] | Coverage: 0.07% |
---|
0x453260 VMOVDQU (%R15,%R12,8),%YMM1 [2] |
0x453266 KXNORW %K0,%K0,%K1 |
0x45326a VPXOR %XMM4,%XMM4,%XMM4 |
0x45326e VPGATHERQQ (%RBX,%YMM1,8),%YMM4{%K1} [1] |
0x453275 VPCMPEQQ %YMM7,%YMM1,%K0 |
0x45327b VPCMPNLTQ %YMM8,%YMM4,%K1 |
0x453282 KORW %K0,%K1,%K1 |
0x453286 VMOVUPD (%R11,%R12,8),%YMM1{%K1}{z} [3] |
0x45328d VMULPD %YMM1,%YMM12,%YMM4 |
0x453291 VCMPPD $0x1,%YMM2,%YMM4,%K1{%K1} |
0x453298 VADDPD %YMM1,%YMM3,%YMM3{%K1} |
0x45329e ADD $0x4,%R12 |
0x4532a2 CMP %RSI,%R12 |
0x4532a5 JBE 453260 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1221 - 1627 |
-------------------------------------------------------------------------------- |
1221: if (n_fine) |
[...] |
1624: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1625: { |
1626: i2 = A_diag_j[jj1]; |
1627: if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | hypre_BoomerAMGBuildExtPIInter[...] | par_lr_interp.c:1196 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:847 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.33 |
CQA speedup if fully vectorized | 2.55 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source | par_lr_interp.c:1221-1627 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.00 |
CQA cycles if no scalar integer | 4.00 |
CQA cycles if FP arith vectorized | 3.00 |
CQA cycles if fully vectorized | 1.57 |
Front-end cycles | 3.75 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 2.00 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 0.00 |
P4 cycles | 3.00 |
P5 cycles | 2.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 4 |
FE+BE cycles (UFS) | 4.12 |
Stall cycles (UFS) | 0.38 |
Nb insns | 14.00 |
Nb uops | 15.00 |
Nb loads | 3.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 4.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 47.22 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 45.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.33 |
CQA speedup if fully vectorized | 2.55 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source | par_lr_interp.c:1221-1627 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.00 |
CQA cycles if no scalar integer | 4.00 |
CQA cycles if FP arith vectorized | 3.00 |
CQA cycles if fully vectorized | 1.57 |
Front-end cycles | 3.75 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 2.00 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 0.00 |
P4 cycles | 3.00 |
P5 cycles | 2.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 4 |
FE+BE cycles (UFS) | 4.12 |
Stall cycles (UFS) | 0.38 |
Nb insns | 14.00 |
Nb uops | 15.00 |
Nb loads | 3.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 4.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 47.22 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 45.00 |
Path / |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source file and lines | par_lr_interp.c:1221-1627 |
Module | exec |
nb instructions | 14 |
nb uops | 15 |
loop length | 71 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 7 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 3.75 cycles |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 3.00 | 3.00 | 0.00 | 3.00 | 2.00 | 0.00 |
cycles | 3.00 | 2.00 | 3.00 | 3.00 | 0.00 | 3.00 | 2.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 4.00 |
FE+BE cycles | 4.12 |
Stall cycles | 0.38 |
PRF full (events) | 0.60 |
Front-end | 3.75 |
Dispatch | 3.00 |
Data deps. | 4.00 |
Overall L1 | 4.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 45% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 43% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 47% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%R15,%R12,8),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPGATHERQQ (%RBX,%YMM1,8),%YMM4{%K1} | 4 | 1 | 0 | 2 | 2 | 0 | 1 | 0 | 0 | 20 | 4 |
VPCMPEQQ %YMM7,%YMM1,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %YMM8,%YMM4,%K1 | |||||||||||
KORW %K0,%K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD (%R11,%R12,8),%YMM1{%K1}{z} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %YMM1,%YMM12,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%YMM2,%YMM4,%K1{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %YMM1,%YMM3,%YMM3{%K1} | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD $0x4,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RSI,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 453260 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source file and lines | par_lr_interp.c:1221-1627 |
Module | exec |
nb instructions | 14 |
nb uops | 15 |
loop length | 71 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 7 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 3.75 cycles |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 3.00 | 3.00 | 0.00 | 3.00 | 2.00 | 0.00 |
cycles | 3.00 | 2.00 | 3.00 | 3.00 | 0.00 | 3.00 | 2.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 4.00 |
FE+BE cycles | 4.12 |
Stall cycles | 0.38 |
PRF full (events) | 0.60 |
Front-end | 3.75 |
Dispatch | 3.00 |
Data deps. | 4.00 |
Overall L1 | 4.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 45% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 43% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 47% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%R15,%R12,8),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPGATHERQQ (%RBX,%YMM1,8),%YMM4{%K1} | 4 | 1 | 0 | 2 | 2 | 0 | 1 | 0 | 0 | 20 | 4 |
VPCMPEQQ %YMM7,%YMM1,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPCMPNLTQ %YMM8,%YMM4,%K1 | |||||||||||
KORW %K0,%K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD (%R11,%R12,8),%YMM1{%K1}{z} | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMULPD %YMM1,%YMM12,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%YMM2,%YMM4,%K1{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %YMM1,%YMM3,%YMM3{%K1} | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD $0x4,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RSI,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 453260 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |