Loop Id: 3031 | Module: exec | Source: csr_matrix.c:145-148 | Coverage: 0.01% |
---|
Loop Id: 3031 | Module: exec | Source: csr_matrix.c:145-148 | Coverage: 0.01% |
---|
0x59a343 VMOVDQU64 0x8(%R8),%ZMM11 [1] |
0x59a34d VMOVDQU64 0x48(%R8),%ZMM15 [1] |
0x59a357 ADD $0x200,%R8 |
0x59a35e VMOVDQU64 -0x178(%R8),%ZMM6 [2] |
0x59a368 VMOVDQU64 -0x138(%R8),%ZMM10 [2] |
0x59a372 VPSUBQ -0x200(%R8),%ZMM11,%ZMM12 [2] |
0x59a379 VPSUBQ -0x1c0(%R8),%ZMM15,%ZMM5 [2] |
0x59a380 VPSUBQ -0x180(%R8),%ZMM6,%ZMM7 [2] |
0x59a387 VPCMPNLEQ %ZMM2,%ZMM12,%K1 |
0x59a38e VPCMPNLEQ %ZMM2,%ZMM5,%K2 |
0x59a395 VPCMPNLEQ %ZMM2,%ZMM7,%K3 |
0x59a39c VMOVDQA64 %ZMM1,%ZMM13{%K1}{z} |
0x59a3a2 VMOVDQA64 %ZMM1,%ZMM3{%K2}{z} |
0x59a3a8 VPSUBQ %ZMM13,%ZMM0,%ZMM14 |
0x59a3ae VPSUBQ -0x140(%R8),%ZMM10,%ZMM0 [2] |
0x59a3b5 VMOVDQU64 -0xf8(%R8),%ZMM13 [2] |
0x59a3bf VMOVDQA64 %ZMM1,%ZMM8{%K3}{z} |
0x59a3c5 VPSUBQ %ZMM3,%ZMM14,%ZMM4 |
0x59a3cb VMOVDQU64 -0xb8(%R8),%ZMM3 [2] |
0x59a3d5 VPSUBQ -0x100(%R8),%ZMM13,%ZMM14 [2] |
0x59a3dc VPCMPNLEQ %ZMM2,%ZMM0,%K4 |
0x59a3e3 VPSUBQ %ZMM8,%ZMM4,%ZMM9 |
0x59a3e9 VMOVDQU64 -0x78(%R8),%ZMM8 [2] |
0x59a3f3 VPSUBQ -0xc0(%R8),%ZMM3,%ZMM4 [2] |
0x59a3fa VPCMPNLEQ %ZMM2,%ZMM14,%K5 |
0x59a401 VMOVDQA64 %ZMM1,%ZMM11{%K4}{z} |
0x59a407 VPCMPNLEQ %ZMM2,%ZMM4,%K6 |
0x59a40e VPSUBQ %ZMM11,%ZMM9,%ZMM12 |
0x59a414 VMOVDQU64 -0x38(%R8),%ZMM11 [2] |
0x59a41e VPSUBQ -0x80(%R8),%ZMM8,%ZMM9 [2] |
0x59a425 VMOVDQA64 %ZMM1,%ZMM15{%K5}{z} |
0x59a42b VPSUBQ %ZMM15,%ZMM12,%ZMM5 |
0x59a431 VPSUBQ -0x40(%R8),%ZMM11,%ZMM12 [2] |
0x59a438 VPCMPNLEQ %ZMM2,%ZMM9,%K7 |
0x59a43f VMOVDQA64 %ZMM1,%ZMM6{%K6}{z} |
0x59a445 VPCMPNLEQ %ZMM2,%ZMM12,%K1 |
0x59a44c VPSUBQ %ZMM6,%ZMM5,%ZMM7 |
0x59a452 VMOVDQA64 %ZMM1,%ZMM10{%K7}{z} |
0x59a458 VPSUBQ %ZMM10,%ZMM7,%ZMM0 |
0x59a45e VMOVDQA64 %ZMM1,%ZMM13{%K1}{z} |
0x59a464 VPSUBQ %ZMM13,%ZMM0,%ZMM0 |
0x59a46a CMP %R8,%RSI |
0x59a46d JNE 59a343 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c: 145 - 148 |
-------------------------------------------------------------------------------- |
145: for (i=0; i < num_rows; i++) |
146: { |
147: adiag = (A_i[i+1] - A_i[i]); |
148: if(adiag > 0) irownnz++; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_IJMatrixAssembleParCSR | IJMatrix_parcsr.c:2826 | exec |
○ | BuildIJLaplacian27pt | amg.c:2272 | exec |
○ | main | amg.c:274 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixSetRownnz |
Source | csr_matrix.c:145-148 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.50 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 8.50 |
CQA cycles if fully vectorized | 8.50 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 1.00 |
P1 cycles | 8.00 |
P2 cycles | 8.00 |
P3 cycles | 0.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 8 |
FE+BE cycles (UFS) | 8.63 |
Stall cycles (UFS) | 0.00 |
Nb insns | 43.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 120.47 |
Bytes prefetched | 0.00 |
Bytes loaded | 1024.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 100.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixSetRownnz |
Source | csr_matrix.c:145-148 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.50 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 8.50 |
CQA cycles if fully vectorized | 8.50 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 1.00 |
P1 cycles | 8.00 |
P2 cycles | 8.00 |
P3 cycles | 0.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 8 |
FE+BE cycles (UFS) | 8.63 |
Stall cycles (UFS) | 0.00 |
Nb insns | 43.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 120.47 |
Bytes prefetched | 0.00 |
Bytes loaded | 1024.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 100.00 |
Path / |
Function | hypre_CSRMatrixSetRownnz |
Source file and lines | csr_matrix.c:145-148 |
Module | exec |
nb instructions | 43 |
nb uops | 34 |
loop length | 304 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 8.00 | 1.00 | 8.00 | 8.00 | 0.00 | 8.00 | 1.00 | 0.00 |
cycles | 8.00 | 1.00 | 8.00 | 8.00 | 0.00 | 8.00 | 1.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 8.00 |
FE+BE cycles | 8.63 |
Stall cycles | 0.00 |
Front-end | 8.50 |
Dispatch | 8.00 |
Data deps. | 8.00 |
Overall L1 | 8.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU64 0x8(%R8),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 0x48(%R8),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
ADD $0x200,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 -0x178(%R8),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 -0x138(%R8),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0x200(%R8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x1c0(%R8),%ZMM15,%ZMM5 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x180(%R8),%ZMM6,%ZMM7 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM12,%K1 | |||||||||||
VPCMPNLEQ %ZMM2,%ZMM5,%K2 | |||||||||||
VPCMPNLEQ %ZMM2,%ZMM7,%K3 | |||||||||||
VMOVDQA64 %ZMM1,%ZMM13{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDQA64 %ZMM1,%ZMM3{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM13,%ZMM0,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x140(%R8),%ZMM10,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0xf8(%R8),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM8{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM3,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0xb8(%R8),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0x100(%R8),%ZMM13,%ZMM14 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM0,%K4 | |||||||||||
VPSUBQ %ZMM8,%ZMM4,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0x78(%R8),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0xc0(%R8),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM14,%K5 | |||||||||||
VMOVDQA64 %ZMM1,%ZMM11{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPCMPNLEQ %ZMM2,%ZMM4,%K6 | |||||||||||
VPSUBQ %ZMM11,%ZMM9,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0x38(%R8),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0x80(%R8),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM15{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM15,%ZMM12,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x40(%R8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM9,%K7 | |||||||||||
VMOVDQA64 %ZMM1,%ZMM6{%K6}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPCMPNLEQ %ZMM2,%ZMM12,%K1 | |||||||||||
VPSUBQ %ZMM6,%ZMM5,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM10{%K7}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM10,%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM13{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM13,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 59a343 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | hypre_CSRMatrixSetRownnz |
Source file and lines | csr_matrix.c:145-148 |
Module | exec |
nb instructions | 43 |
nb uops | 34 |
loop length | 304 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 8.00 | 1.00 | 8.00 | 8.00 | 0.00 | 8.00 | 1.00 | 0.00 |
cycles | 8.00 | 1.00 | 8.00 | 8.00 | 0.00 | 8.00 | 1.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 8.00 |
FE+BE cycles | 8.63 |
Stall cycles | 0.00 |
Front-end | 8.50 |
Dispatch | 8.00 |
Data deps. | 8.00 |
Overall L1 | 8.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU64 0x8(%R8),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 0x48(%R8),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
ADD $0x200,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 -0x178(%R8),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQU64 -0x138(%R8),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0x200(%R8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x1c0(%R8),%ZMM15,%ZMM5 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x180(%R8),%ZMM6,%ZMM7 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM12,%K1 | |||||||||||
VPCMPNLEQ %ZMM2,%ZMM5,%K2 | |||||||||||
VPCMPNLEQ %ZMM2,%ZMM7,%K3 | |||||||||||
VMOVDQA64 %ZMM1,%ZMM13{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDQA64 %ZMM1,%ZMM3{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM13,%ZMM0,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x140(%R8),%ZMM10,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0xf8(%R8),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM8{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM3,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0xb8(%R8),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0x100(%R8),%ZMM13,%ZMM14 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM0,%K4 | |||||||||||
VPSUBQ %ZMM8,%ZMM4,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0x78(%R8),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0xc0(%R8),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM14,%K5 | |||||||||||
VMOVDQA64 %ZMM1,%ZMM11{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPCMPNLEQ %ZMM2,%ZMM4,%K6 | |||||||||||
VPSUBQ %ZMM11,%ZMM9,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQU64 -0x38(%R8),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSUBQ -0x80(%R8),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM15{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM15,%ZMM12,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPSUBQ -0x40(%R8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VPCMPNLEQ %ZMM2,%ZMM9,%K7 | |||||||||||
VMOVDQA64 %ZMM1,%ZMM6{%K6}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPCMPNLEQ %ZMM2,%ZMM12,%K1 | |||||||||||
VPSUBQ %ZMM6,%ZMM5,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM10{%K7}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM10,%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM1,%ZMM13{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPSUBQ %ZMM13,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 59a343 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |