Function: hypre_BoomerAMGIndepSetInit | Module: exec | Source: par_indepset.c:49-70 | Coverage: 0.01% |
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Function: hypre_BoomerAMGIndepSetInit | Module: exec | Source: par_indepset.c:49-70 | Coverage: 0.01% |
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/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_indepset.c: 49 - 70 |
-------------------------------------------------------------------------------- |
49: { |
50: hypre_CSRMatrix *S_diag = hypre_ParCSRMatrixDiag(S); |
51: MPI_Comm comm = hypre_ParCSRMatrixComm(S); |
52: HYPRE_Int S_num_nodes = hypre_CSRMatrixNumRows(S_diag); |
53: HYPRE_Int i, my_id; |
54: HYPRE_Int ierr = 0; |
55: |
56: hypre_MPI_Comm_rank(comm,&my_id); |
57: i = 2747+my_id; |
58: if (seq_rand) i = 2747; |
59: hypre_SeedRand(i); |
60: if (seq_rand) |
61: { |
62: for (i = 0; i < hypre_ParCSRMatrixFirstRowIndex(S); i++) |
63: hypre_Rand(); |
64: } |
65: for (i = 0; i < S_num_nodes; i++) |
66: { |
67: measure_array[i] += hypre_Rand(); |
68: } |
69: |
70: return (ierr); |
0x431140 PUSH %RBP |
0x431141 MOV %RSP,%RBP |
0x431144 PUSH %R15 |
0x431146 PUSH %R14 |
0x431148 PUSH %R13 |
0x43114a PUSH %R12 |
0x43114c PUSH %RBX |
0x43114d SUB $0x48,%RSP |
0x431151 MOV %RDX,%R15 |
0x431154 MOV %RSI,%R13 |
0x431157 MOV %RDI,%R14 |
0x43115a MOV 0x38(%RDI),%RAX |
0x43115e MOV (%RDI),%EDI |
0x431160 MOV 0x10(%RAX),%R12 |
0x431164 LEA -0x68(%RBP),%RSI |
0x431168 CALL 4f57a0 <hypre_MPI_Comm_rank> |
0x43116d MOV $0xabb,%EAX |
0x431172 MOV -0x68(%RBP),%RDI |
0x431176 ADD %RAX,%RDI |
0x431179 TEST %R15,%R15 |
0x43117c CMOVNE %RAX,%RDI |
0x431180 CALL 4f6000 <hypre_SeedRand> |
0x431185 TEST %R15,%R15 |
0x431188 JE 4311ea |
0x43118a MOV 0x18(%R14),%R14 |
0x43118e TEST %R14,%R14 |
0x431191 JLE 4311ea |
0x431193 CMP $0x8,%R14 |
0x431197 JB 4311cd |
0x431199 MOV %R14,%RBX |
0x43119c SHR $0x3,%RBX |
(404) 0x4311a0 CALL 4f6070 <hypre_Rand> |
(404) 0x4311a5 CALL 4f6070 <hypre_Rand> |
(404) 0x4311aa CALL 4f6070 <hypre_Rand> |
(404) 0x4311af CALL 4f6070 <hypre_Rand> |
(404) 0x4311b4 CALL 4f6070 <hypre_Rand> |
(404) 0x4311b9 CALL 4f6070 <hypre_Rand> |
(404) 0x4311be CALL 4f6070 <hypre_Rand> |
(404) 0x4311c3 CALL 4f6070 <hypre_Rand> |
(404) 0x4311c8 DEC %RBX |
(404) 0x4311cb JNE 4311a0 |
0x4311cd MOV %R14,%RAX |
0x4311d0 AND $-0x8,%RAX |
0x4311d4 CMP %R14,%RAX |
0x4311d7 JAE 4311ea |
0x4311d9 SUB %RAX,%R14 |
0x4311dc NOPL (%RAX) |
(403) 0x4311e0 CALL 4f6070 <hypre_Rand> |
(403) 0x4311e5 DEC %R14 |
(403) 0x4311e8 JNE 4311e0 |
0x4311ea TEST %R12,%R12 |
0x4311ed JLE 4312de |
0x4311f3 CMP $0x8,%R12 |
0x4311f7 JB 4312ad |
0x4311fd MOV %R12,%R14 |
0x431200 SHR $0x3,%R14 |
0x431204 LEA 0x20(%R13),%RBX |
0x431208 NOPL (%RAX,%RAX,1) |
(402) 0x431210 VZEROUPPER |
(402) 0x431213 CALL 4f6070 <hypre_Rand> |
(402) 0x431218 VMOVUPD %XMM0,-0x60(%RBP) |
(402) 0x43121d CALL 4f6070 <hypre_Rand> |
(402) 0x431222 VMOVUPD %XMM0,-0x50(%RBP) |
(402) 0x431227 CALL 4f6070 <hypre_Rand> |
(402) 0x43122c VMOVUPD %XMM0,-0x40(%RBP) |
(402) 0x431231 CALL 4f6070 <hypre_Rand> |
(402) 0x431236 VMOVUPD -0x60(%RBP),%XMM1 |
(402) 0x43123b VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 |
(402) 0x431240 VMOVUPD -0x40(%RBP),%XMM2 |
(402) 0x431245 VUNPCKLPD %XMM0,%XMM2,%XMM0 |
(402) 0x431249 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
(402) 0x43124f VADDPD -0x20(%RBX),%YMM0,%YMM0 |
(402) 0x431254 VMOVUPD %YMM0,-0x20(%RBX) |
(402) 0x431259 VZEROUPPER |
(402) 0x43125c CALL 4f6070 <hypre_Rand> |
(402) 0x431261 VMOVUPD %XMM0,-0x60(%RBP) |
(402) 0x431266 CALL 4f6070 <hypre_Rand> |
(402) 0x43126b VMOVUPD %XMM0,-0x50(%RBP) |
(402) 0x431270 CALL 4f6070 <hypre_Rand> |
(402) 0x431275 VMOVUPD %XMM0,-0x40(%RBP) |
(402) 0x43127a CALL 4f6070 <hypre_Rand> |
(402) 0x43127f VMOVUPD -0x60(%RBP),%XMM1 |
(402) 0x431284 VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 |
(402) 0x431289 VMOVUPD -0x40(%RBP),%XMM2 |
(402) 0x43128e VUNPCKLPD %XMM0,%XMM2,%XMM0 |
(402) 0x431292 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
(402) 0x431298 VADDPD (%RBX),%YMM0,%YMM0 |
(402) 0x43129c VMOVUPD %YMM0,(%RBX) |
(402) 0x4312a0 ADD $0x40,%RBX |
(402) 0x4312a4 DEC %R14 |
(402) 0x4312a7 JNE 431210 |
0x4312ad MOV %R12,%RBX |
0x4312b0 AND $-0x8,%RBX |
0x4312b4 CMP %R12,%RBX |
0x4312b7 JAE 4312de |
0x4312b9 NOPL (%RAX) |
(401) 0x4312c0 VZEROUPPER |
(401) 0x4312c3 CALL 4f6070 <hypre_Rand> |
(401) 0x4312c8 VADDSD (%R13,%RBX,8),%XMM0,%XMM0 |
(401) 0x4312cf VMOVSD %XMM0,(%R13,%RBX,8) |
(401) 0x4312d6 INC %RBX |
(401) 0x4312d9 CMP %RBX,%R12 |
(401) 0x4312dc JNE 4312c0 |
0x4312de XOR %EAX,%EAX |
0x4312e0 ADD $0x48,%RSP |
0x4312e4 POP %RBX |
0x4312e5 POP %R12 |
0x4312e7 POP %R13 |
0x4312e9 POP %R14 |
0x4312eb POP %R15 |
0x4312ed POP %RBP |
0x4312ee VZEROUPPER |
0x4312f1 RET |
0x4312f2 NOPW %CS:(%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | par_indepset.c:49-70 |
Module | exec |
nb instructions | 61 |
nb uops | 66 |
loop length | 206 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 16.50 cycles |
front end | 16.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 7.50 | 7.50 | 6.83 | 6.50 | 8.00 | 7.50 | 7.50 | 6.67 |
cycles | 7.50 | 7.50 | 6.83 | 6.50 | 8.00 | 7.50 | 7.50 | 6.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 15.37 |
Stall cycles | 0.00 |
Front-end | 16.50 |
Dispatch | 8.00 |
Overall L1 | 16.50 |
all | 6% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SUB $0x48,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RSI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x38(%RDI),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RDI),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x10(%RAX),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA -0x68(%RBP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4f57a0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV $0xabb,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x68(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD %RAX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMOVNE %RAX,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
CALL 4f6000 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4311ea | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x18(%R14),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4311ea | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x8,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4311cd | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R14,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R14,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4311ea | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
SUB %RAX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
TEST %R12,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4312de | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x8,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4312ad | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA 0x20(%R13),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R12,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R12,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4312de | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x48,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | par_indepset.c:49-70 |
Module | exec |
nb instructions | 61 |
nb uops | 66 |
loop length | 206 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 16.50 cycles |
front end | 16.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 7.50 | 7.50 | 6.83 | 6.50 | 8.00 | 7.50 | 7.50 | 6.67 |
cycles | 7.50 | 7.50 | 6.83 | 6.50 | 8.00 | 7.50 | 7.50 | 6.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 15.37 |
Stall cycles | 0.00 |
Front-end | 16.50 |
Dispatch | 8.00 |
Overall L1 | 16.50 |
all | 6% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SUB $0x48,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RSI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x38(%RDI),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RDI),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x10(%RAX),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA -0x68(%RBP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4f57a0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV $0xabb,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x68(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD %RAX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMOVNE %RAX,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
CALL 4f6000 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4311ea | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x18(%R14),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4311ea | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x8,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4311cd | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R14,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R14,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4311ea | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
SUB %RAX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
TEST %R12,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 4312de | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x8,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 4312ad | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA 0x20(%R13),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R12,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R12,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 4312de | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x48,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGIndepSetInit– | 0.01 | 0 |
○Loop 402 - par_indepset.c:65-67 - exec | 0.01 | 0 |
○Loop 403 - par_indepset.c:62-63 - exec | 0 | 0 |
○Loop 401 - par_indepset.c:65-67 - exec | 0 | 0 |
○Loop 404 - par_indepset.c:62-63 - exec | 0 | 0 |