Loop Id: 3333 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.13% |
---|
Loop Id: 3333 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.13% |
---|
0x4c7ca0 MOV -0x80(%RBP),%RCX |
0x4c7ca4 MOV -0x58(%RBP),%RDX |
0x4c7ca8 MOV %R13,(%RCX,%RDX,8) |
0x4c7cac MOV -0x78(%RBP),%RCX |
0x4c7cb0 MOV %R11,(%RCX,%RDX,8) |
0x4c7cb4 MOV %RSI,%RDX |
0x4c7cb7 MOV %R14,%R11 |
0x4c7cba MOV %RAX,%R13 |
0x4c7cbd CMP -0x38(%RBP),%RSI |
0x4c7cc1 MOV 0x58(%RBP),%RBX |
0x4c7cc5 JGE 4c7f06 |
0x4c7ccb CMPQ $0,0x78(%RBP) |
0x4c7cd0 JE 4c7cda |
0x4c7cd2 MOV %R13,(%R15,%RDX,8) |
0x4c7cd6 LEA 0x1(%R13),%RAX |
0x4c7cda CMPQ $0,0x70(%RBP) |
0x4c7cdf MOV %RDX,-0x58(%RBP) |
0x4c7ce3 JE 4c7e00 |
0x4c7ce9 MOV 0x10(%RBP),%RCX |
0x4c7ced MOV (%RCX,%RDX,8),%R8 |
0x4c7cf1 LEA 0x1(%RDX),%RSI |
0x4c7cf5 CMP 0x8(%RCX,%RDX,8),%R8 |
0x4c7cfa JGE 4c7e04 |
0x4c7d00 MOV %RSI,-0x50(%RBP) |
0x4c7d04 MOV %R11,%R14 |
0x4c7d07 JMP 4c7d36 |
(3337) 0x4c7d20 INC %R8 |
(3337) 0x4c7d23 MOV 0x10(%RBP),%RCX |
(3337) 0x4c7d27 MOV -0x58(%RBP),%RDX |
(3337) 0x4c7d2b CMP 0x8(%RCX,%RDX,8),%R8 |
(3337) 0x4c7d30 JGE 4c7e20 |
(3337) 0x4c7d36 MOV 0x18(%RBP),%RCX |
(3337) 0x4c7d3a MOV (%RCX,%R8,8),%RDI |
(3337) 0x4c7d3e MOV 0x50(%RBP),%RCX |
(3337) 0x4c7d42 MOV (%RCX,%RDI,8),%RDX |
(3337) 0x4c7d46 MOV 0x8(%RCX,%RDI,8),%RCX |
(3337) 0x4c7d4b JMP 4c7d63 |
(3339) 0x4c7d60 INC %RDX |
(3339) 0x4c7d63 CMP %RCX,%RDX |
(3339) 0x4c7d66 JGE 4c7da0 |
(3339) 0x4c7d68 MOV (%RBX,%RDX,8),%RSI |
(3339) 0x4c7d6c ADD %R12,%RSI |
(3339) 0x4c7d6f CMP %R11,(%R15,%RSI,8) |
(3339) 0x4c7d73 JGE 4c7d60 |
(3339) 0x4c7d75 MOV %R14,(%R15,%RSI,8) |
(3339) 0x4c7d79 INC %R14 |
(3339) 0x4c7d7c MOV 0x50(%RBP),%RCX |
(3339) 0x4c7d80 MOV 0x8(%RCX,%RDI,8),%RCX |
(3339) 0x4c7d85 JMP 4c7d60 |
(3337) 0x4c7da0 MOV 0x40(%RBP),%RCX |
(3337) 0x4c7da4 MOV (%RCX,%RDI,8),%RDX |
(3337) 0x4c7da8 MOV 0x8(%RCX,%RDI,8),%RCX |
(3337) 0x4c7dad JMP 4c7dc3 |
(3338) 0x4c7dc0 INC %RDX |
(3338) 0x4c7dc3 CMP %RCX,%RDX |
(3338) 0x4c7dc6 JGE 4c7d20 |
(3338) 0x4c7dcc MOV 0x48(%RBP),%RSI |
(3338) 0x4c7dd0 MOV (%RSI,%RDX,8),%RSI |
(3338) 0x4c7dd4 CMP %R13,(%R15,%RSI,8) |
(3338) 0x4c7dd8 JGE 4c7dc0 |
(3338) 0x4c7dda MOV %RAX,(%R15,%RSI,8) |
(3338) 0x4c7dde INC %RAX |
(3338) 0x4c7de1 MOV 0x40(%RBP),%RCX |
(3338) 0x4c7de5 MOV 0x8(%RCX,%RDI,8),%RCX |
(3338) 0x4c7dea JMP 4c7dc0 |
0x4c7e00 LEA 0x1(%RDX),%RSI |
0x4c7e04 MOV %R11,%R14 |
0x4c7e07 MOV -0x60(%RBP),%RCX |
0x4c7e0b MOV (%RCX,%RDX,8),%RBX |
0x4c7e0f CMP (%RCX,%RSI,8),%RBX |
0x4c7e13 JGE 4c7ca0 |
0x4c7e19 JMP 4c7e36 |
0x4c7e20 MOV -0x50(%RBP),%RSI |
0x4c7e24 MOV -0x60(%RBP),%RCX |
0x4c7e28 MOV (%RCX,%RDX,8),%RBX |
0x4c7e2c CMP (%RCX,%RSI,8),%RBX |
0x4c7e30 JGE 4c7ca0 |
0x4c7e36 MOV %RSI,-0x50(%RBP) |
0x4c7e3a JMP 4c7e55 |
(3334) 0x4c7e40 INC %RBX |
(3334) 0x4c7e43 MOV -0x60(%RBP),%RCX |
(3334) 0x4c7e47 MOV -0x50(%RBP),%RSI |
(3334) 0x4c7e4b CMP (%RCX,%RSI,8),%RBX |
(3334) 0x4c7e4f JGE 4c7ca0 |
(3334) 0x4c7e55 MOV -0x88(%RBP),%RCX |
(3334) 0x4c7e5c MOV (%RCX,%RBX,8),%R8 |
(3334) 0x4c7e60 MOV (%R10,%R8,8),%RDX |
(3334) 0x4c7e64 MOV 0x8(%R10,%R8,8),%RCX |
(3334) 0x4c7e69 JMP 4c7e83 |
(3336) 0x4c7e80 INC %RDX |
(3336) 0x4c7e83 CMP %RCX,%RDX |
(3336) 0x4c7e86 JGE 4c7ea0 |
(3336) 0x4c7e88 MOV (%R9,%RDX,8),%RSI |
(3336) 0x4c7e8c CMP %R13,(%R15,%RSI,8) |
(3336) 0x4c7e90 JGE 4c7e80 |
(3336) 0x4c7e92 MOV %RAX,(%R15,%RSI,8) |
(3336) 0x4c7e96 INC %RAX |
(3336) 0x4c7e99 MOV 0x8(%R10,%R8,8),%RCX |
(3336) 0x4c7e9e JMP 4c7e80 |
(3334) 0x4c7ea0 CMPQ $0,0x88(%RBP) |
(3334) 0x4c7ea8 JE 4c7e40 |
(3334) 0x4c7eaa MOV 0x30(%RBP),%RCX |
(3334) 0x4c7eae MOV (%RCX,%R8,8),%RDI |
(3334) 0x4c7eb2 MOV 0x8(%RCX,%R8,8),%RDX |
(3334) 0x4c7eb7 JMP 4c7ec3 |
(3335) 0x4c7ec0 INC %RDI |
(3335) 0x4c7ec3 CMP %RDX,%RDI |
(3335) 0x4c7ec6 JGE 4c7e40 |
(3335) 0x4c7ecc MOV 0x38(%RBP),%RCX |
(3335) 0x4c7ed0 MOV (%RCX,%RDI,8),%RCX |
(3335) 0x4c7ed4 MOV 0x60(%RBP),%RSI |
(3335) 0x4c7ed8 MOV (%RSI,%RCX,8),%RCX |
(3335) 0x4c7edc ADD %R12,%RCX |
(3335) 0x4c7edf CMP %R11,(%R15,%RCX,8) |
(3335) 0x4c7ee3 JGE 4c7ec0 |
(3335) 0x4c7ee5 MOV %R14,(%R15,%RCX,8) |
(3335) 0x4c7ee9 INC %R14 |
(3335) 0x4c7eec MOV 0x30(%RBP),%RCX |
(3335) 0x4c7ef0 MOV 0x8(%RCX,%R8,8),%RDX |
(3335) 0x4c7ef5 JMP 4c7ec0 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242 |
-------------------------------------------------------------------------------- |
127: for (i1 = ns; i1 < ne; i1++) |
[...] |
135: if ( allsquare ) { |
136: B_marker[i1] = jj_count_diag; |
137: jj_count_diag++; |
[...] |
144: if (num_cols_offd_A) |
145: { |
146: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
147: { |
148: i2 = A_offd_j[jj2]; |
[...] |
154: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
155: { |
156: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
164: if (B_marker[i3] < jj_row_begin_offd) |
165: { |
166: B_marker[i3] = jj_count_offd; |
167: jj_count_offd++; |
168: } |
169: } |
170: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
171: { |
172: i3 = B_ext_diag_j[jj3]; |
173: |
174: if (B_marker[i3] < jj_row_begin_diag) |
175: { |
176: B_marker[i3] = jj_count_diag; |
177: jj_count_diag++; |
[...] |
187: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
188: { |
189: i2 = A_diag_j[jj2]; |
[...] |
195: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
196: { |
197: i3 = B_diag_j[jj3]; |
[...] |
205: if (B_marker[i3] < jj_row_begin_diag) |
206: { |
207: B_marker[i3] = jj_count_diag; |
208: jj_count_diag++; |
[...] |
216: if (num_cols_offd_B) |
217: { |
218: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
219: { |
220: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
228: if (B_marker[i3] < jj_row_begin_offd) |
229: { |
230: B_marker[i3] = jj_count_offd; |
231: jj_count_offd++; |
[...] |
241: (*C_diag_i)[i1] = jj_row_begin_diag; |
242: (*C_offd_i)[i1] = jj_row_begin_offd; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | hypre_ParMatmul | par_csr_matop.c:102 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:1226 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.26 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.75 |
CQA cycles if no scalar integer | 10.75 |
CQA cycles if FP arith vectorized | 10.75 |
CQA cycles if fully vectorized | 1.34 |
Front-end cycles | 10.75 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 6.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 6.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.90 |
Stall cycles (UFS) | 0.00 |
Nb insns | 40.00 |
Nb uops | 40.00 |
Nb loads | 17.00 |
Nb stores | 6.00 |
Nb stack references | 10.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.12 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 48.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.26 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.75 |
CQA cycles if no scalar integer | 10.75 |
CQA cycles if FP arith vectorized | 10.75 |
CQA cycles if fully vectorized | 1.34 |
Front-end cycles | 10.75 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 6.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 6.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.90 |
Stall cycles (UFS) | 0.00 |
Nb insns | 40.00 |
Nb uops | 40.00 |
Nb loads | 17.00 |
Nb stores | 6.00 |
Nb stack references | 10.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.12 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 48.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 40 |
nb uops | 40 |
loop length | 160 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 10.75 cycles |
front end | 10.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 8.50 | 8.50 | 6.00 | 4.50 | 4.50 | 6.00 |
cycles | 4.50 | 4.50 | 8.50 | 8.50 | 6.00 | 4.50 | 4.50 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.90 |
Stall cycles | 0.00 |
Front-end | 10.75 |
Dispatch | 8.50 |
Overall L1 | 10.75 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x80(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x58(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R13,(%RCX,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x78(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R11,(%RCX,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP -0x38(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JGE 4c7f06 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMPQ $0,0x78(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 4c7cda | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R13,(%R15,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x1(%R13),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,0x70(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %RDX,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JE 4c7e00 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RCX,%RDX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RDX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x8(%RCX,%RDX,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c7e04 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R11,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4c7d36 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
LEA 0x1(%RDX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RCX,%RDX,8),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RCX,%RSI,8),%RBX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c7ca0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4c7e36 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RCX,%RDX,8),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RCX,%RSI,8),%RBX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c7ca0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4c7e55 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 40 |
nb uops | 40 |
loop length | 160 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 10.75 cycles |
front end | 10.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 8.50 | 8.50 | 6.00 | 4.50 | 4.50 | 6.00 |
cycles | 4.50 | 4.50 | 8.50 | 8.50 | 6.00 | 4.50 | 4.50 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.90 |
Stall cycles | 0.00 |
Front-end | 10.75 |
Dispatch | 8.50 |
Overall L1 | 10.75 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x80(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x58(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R13,(%RCX,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x78(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R11,(%RCX,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP -0x38(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JGE 4c7f06 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMPQ $0,0x78(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 4c7cda | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R13,(%R15,%RDX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x1(%R13),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,0x70(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %RDX,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JE 4c7e00 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RCX,%RDX,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RDX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x8(%RCX,%RDX,8),%R8 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c7e04 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R11,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4c7d36 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
LEA 0x1(%RDX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RCX,%RDX,8),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RCX,%RSI,8),%RBX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c7ca0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 4c7e36 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%RCX,%RDX,8),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP (%RCX,%RSI,8),%RBX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JGE 4c7ca0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4c7e55 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |