Loop Id: 3120 | Module: exec | Source: csr_matvec.c:307-314 | Coverage: 47.27% |
---|
Loop Id: 3120 | Module: exec | Source: csr_matvec.c:307-314 | Coverage: 47.27% |
---|
0x5a1b30 MOV 0x28(%RSP),%RAX |
0x5a1b35 MOV (%R8,%R12,8),%RDX |
0x5a1b39 MOV 0x8(%R8,%R12,8),%R11 |
0x5a1b3e VMOVSD (%RAX,%R12,8),%XMM5 |
0x5a1b44 CMP %R11,%RDX |
0x5a1b47 JGE 5a1e5b |
0x5a1b4d MOV %R11,%RSI |
0x5a1b50 MOV %RDX,%R15 |
0x5a1b53 SUB %RDX,%RSI |
0x5a1b56 LEA -0x1(%RSI),%RCX |
0x5a1b5a CMP $0x6,%RCX |
0x5a1b5e JBE 5a2c3d |
0x5a1b64 MOV %RSI,%R10 |
0x5a1b67 LEA (,%RDX,8),%RCX |
0x5a1b6f VXORPD %XMM0,%XMM0,%XMM0 |
0x5a1b73 XOR %EAX,%EAX |
0x5a1b75 SHR $0x3,%R10 |
0x5a1b79 LEA (%R14,%RCX,1),%R9 |
0x5a1b7d ADD %R13,%RCX |
0x5a1b80 SAL $0x6,%R10 |
0x5a1b84 LEA -0x40(%R10),%RDI |
0x5a1b88 SHR $0x6,%RDI |
0x5a1b8c INC %RDI |
0x5a1b8f AND $0x7,%EDI |
0x5a1b92 JE 5a1c9b |
0x5a1b98 CMP $0x1,%RDI |
0x5a1b9c JE 5a1c75 |
0x5a1ba2 CMP $0x2,%RDI |
0x5a1ba6 JE 5a1c58 |
0x5a1bac CMP $0x3,%RDI |
0x5a1bb0 JE 5a1c3b |
0x5a1bb6 CMP $0x4,%RDI |
0x5a1bba JE 5a1c1e |
0x5a1bbc CMP $0x5,%RDI |
0x5a1bc0 JE 5a1c01 |
0x5a1bc2 CMP $0x6,%RDI |
0x5a1bc6 JE 5a1be4 |
0x5a1bc8 VMOVDQU64 (%RCX),%ZMM6 |
0x5a1bce KMOVB %K0,%K4 |
0x5a1bd2 MOV $0x40,%EAX |
0x5a1bd7 VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} |
0x5a1bde VFNMADD231PD (%R9),%ZMM14,%ZMM0 |
0x5a1be4 VMOVDQU64 (%RCX,%RAX,1),%ZMM11 |
0x5a1beb KMOVB %K0,%K2 |
0x5a1bef VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} |
0x5a1bf6 VFNMADD231PD (%R9,%RAX,1),%ZMM7,%ZMM0 |
0x5a1bfd ADD $0x40,%RAX |
0x5a1c01 VMOVDQU64 (%RCX,%RAX,1),%ZMM12 |
0x5a1c08 KMOVB %K0,%K1 |
0x5a1c0c VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} |
0x5a1c13 VFNMADD231PD (%R9,%RAX,1),%ZMM2,%ZMM0 |
0x5a1c1a ADD $0x40,%RAX |
0x5a1c1e VMOVDQU64 (%RCX,%RAX,1),%ZMM4 |
0x5a1c25 KMOVB %K0,%K5 |
0x5a1c29 VGATHERQPD (%RBX,%ZMM4,8),%ZMM13{%K5} |
0x5a1c30 VFNMADD231PD (%R9,%RAX,1),%ZMM13,%ZMM0 |
0x5a1c37 ADD $0x40,%RAX |
0x5a1c3b VMOVDQU64 (%RCX,%RAX,1),%ZMM10 |
0x5a1c42 KMOVB %K0,%K6 |
0x5a1c46 VGATHERQPD (%RBX,%ZMM10,8),%ZMM1{%K6} |
0x5a1c4d VFNMADD231PD (%R9,%RAX,1),%ZMM1,%ZMM0 |
0x5a1c54 ADD $0x40,%RAX |
0x5a1c58 VMOVDQU64 (%RCX,%RAX,1),%ZMM9 |
0x5a1c5f KMOVB %K0,%K3 |
0x5a1c63 VGATHERQPD (%RBX,%ZMM9,8),%ZMM3{%K3} |
0x5a1c6a VFNMADD231PD (%R9,%RAX,1),%ZMM3,%ZMM0 |
0x5a1c71 ADD $0x40,%RAX |
0x5a1c75 VMOVDQU64 (%RCX,%RAX,1),%ZMM15 |
0x5a1c7c KMOVB %K0,%K7 |
0x5a1c80 VGATHERQPD (%RBX,%ZMM15,8),%ZMM8{%K7} |
0x5a1c87 VFNMADD231PD (%R9,%RAX,1),%ZMM8,%ZMM0 |
0x5a1c8e ADD $0x40,%RAX |
0x5a1c92 CMP %RAX,%R10 |
0x5a1c95 JE 5a1d80 |
(3121) 0x5a1c9b VMOVDQU64 (%RCX,%RAX,1),%ZMM6 |
(3121) 0x5a1ca2 KMOVB %K0,%K4 |
(3121) 0x5a1ca6 VMOVDQU64 0x40(%RCX,%RAX,1),%ZMM11 |
(3121) 0x5a1cae KMOVB %K0,%K2 |
(3121) 0x5a1cb2 VMOVDQU64 0x80(%RCX,%RAX,1),%ZMM12 |
(3121) 0x5a1cba KMOVB %K0,%K1 |
(3121) 0x5a1cbe VMOVDQU64 0xc0(%RCX,%RAX,1),%ZMM4 |
(3121) 0x5a1cc6 KMOVB %K0,%K5 |
(3121) 0x5a1cca VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} |
(3121) 0x5a1cd1 VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} |
(3121) 0x5a1cd8 VMOVDQU64 0x100(%RCX,%RAX,1),%ZMM13 |
(3121) 0x5a1ce0 KMOVB %K0,%K6 |
(3121) 0x5a1ce4 VFNMADD231PD (%R9,%RAX,1),%ZMM14,%ZMM0 |
(3121) 0x5a1ceb VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} |
(3121) 0x5a1cf2 VMOVDQU64 0x140(%RCX,%RAX,1),%ZMM1 |
(3121) 0x5a1cfa KMOVB %K0,%K3 |
(3121) 0x5a1cfe VGATHERQPD (%RBX,%ZMM13,8),%ZMM10{%K6} |
(3121) 0x5a1d05 VMOVDQU64 0x180(%RCX,%RAX,1),%ZMM3 |
(3121) 0x5a1d0d KMOVB %K0,%K7 |
(3121) 0x5a1d11 VMOVDQU64 0x1c0(%RCX,%RAX,1),%ZMM8 |
(3121) 0x5a1d19 VGATHERQPD (%RBX,%ZMM1,8),%ZMM9{%K3} |
(3121) 0x5a1d20 KMOVB %K0,%K4 |
(3121) 0x5a1d24 VGATHERQPD (%RBX,%ZMM3,8),%ZMM15{%K7} |
(3121) 0x5a1d2b VFNMADD231PD 0x40(%R9,%RAX,1),%ZMM7,%ZMM0 |
(3121) 0x5a1d33 VFNMADD132PD 0x80(%R9,%RAX,1),%ZMM0,%ZMM2 |
(3121) 0x5a1d3b VGATHERQPD (%RBX,%ZMM4,8),%ZMM0{%K5} |
(3121) 0x5a1d42 VFNMADD132PD 0xc0(%R9,%RAX,1),%ZMM2,%ZMM0 |
(3121) 0x5a1d4a VFNMADD132PD 0x100(%R9,%RAX,1),%ZMM0,%ZMM10 |
(3121) 0x5a1d52 VGATHERQPD (%RBX,%ZMM8,8),%ZMM0{%K4} |
(3121) 0x5a1d59 VFNMADD132PD 0x140(%R9,%RAX,1),%ZMM10,%ZMM9 |
(3121) 0x5a1d61 VFNMADD132PD 0x180(%R9,%RAX,1),%ZMM9,%ZMM15 |
(3121) 0x5a1d69 VFNMADD132PD 0x1c0(%R9,%RAX,1),%ZMM15,%ZMM0 |
(3121) 0x5a1d71 ADD $0x200,%RAX |
(3121) 0x5a1d77 CMP %RAX,%R10 |
(3121) 0x5a1d7a JNE 5a1c9b |
0x5a1d80 VEXTRACTF64X4 $0x1,%ZMM0,%YMM6 |
0x5a1d87 MOV %RSI,%R9 |
0x5a1d8a VADDPD %YMM0,%YMM6,%YMM14 |
0x5a1d8e AND $-0x8,%R9 |
0x5a1d92 VADDPD %YMM0,%YMM6,%YMM8 |
0x5a1d96 ADD %R9,%RDX |
0x5a1d99 VEXTRACTF64X2 $0x1,%YMM14,%XMM11 |
0x5a1da0 VADDPD %XMM14,%XMM11,%XMM7 |
0x5a1da5 VUNPCKHPD %XMM7,%XMM7,%XMM12 |
0x5a1da9 VADDPD %XMM7,%XMM12,%XMM2 |
0x5a1dad VADDSD %XMM2,%XMM5,%XMM15 |
0x5a1db1 TEST $0x7,%SIL |
0x5a1db5 JE 5a254c |
0x5a1dbb SUB %R9,%RSI |
0x5a1dbe LEA -0x1(%RSI),%RCX |
0x5a1dc2 CMP $0x2,%RCX |
0x5a1dc6 JBE 5a2c5a |
0x5a1dcc ADD %R15,%R9 |
0x5a1dcf KMOVB %K0,%K2 |
0x5a1dd3 MOV %RSI,%R15 |
0x5a1dd6 VMOVDQU (%R13,%R9,8),%YMM4 |
0x5a1ddd AND $-0x4,%R15 |
0x5a1de1 ADD %R15,%RDX |
0x5a1de4 AND $0x3,%ESI |
0x5a1de7 VGATHERQPD (%RBX,%YMM4,8),%YMM13{%K2} |
0x5a1dee VFNMADD132PD (%R14,%R9,8),%YMM8,%YMM13 |
0x5a1df4 VEXTRACTF64X2 $0x1,%YMM13,%XMM10 |
0x5a1dfb VADDPD %XMM13,%XMM10,%XMM1 |
0x5a1e00 VUNPCKHPD %XMM1,%XMM1,%XMM9 |
0x5a1e04 VADDPD %XMM1,%XMM9,%XMM3 |
0x5a1e08 VADDSD %XMM3,%XMM5,%XMM5 |
0x5a1e0c JE 5a1e5b |
0x5a1e0e MOV (%R13,%RDX,8),%R9 |
0x5a1e13 LEA 0x1(%RDX),%R10 |
0x5a1e17 LEA (,%RDX,8),%RSI |
0x5a1e1f VMOVSD (%RBX,%R9,8),%XMM15 |
0x5a1e25 VFNMADD231SD (%R14,%RDX,8),%XMM15,%XMM5 |
0x5a1e2b CMP %R11,%R10 |
0x5a1e2e JGE 5a1e5b |
0x5a1e30 MOV 0x8(%R13,%RSI,1),%RDI |
0x5a1e35 ADD $0x2,%RDX |
0x5a1e39 VMOVSD (%RBX,%RDI,8),%XMM8 |
0x5a1e3e VFNMADD231SD 0x8(%R14,%RSI,1),%XMM8,%XMM5 |
0x5a1e45 CMP %R11,%RDX |
0x5a1e48 JGE 5a1e5b |
0x5a1e4a MOV 0x10(%R13,%RSI,1),%RDX |
0x5a1e4f VMOVSD (%RBX,%RDX,8),%XMM0 |
0x5a1e54 VFNMADD231SD 0x10(%R14,%RSI,1),%XMM0,%XMM5 |
0x5a1e5b MOV 0x30(%RSP),%R11 |
0x5a1e60 VMOVSD %XMM5,(%R11,%R12,8) |
0x5a1e66 INC %R12 |
0x5a1e69 CMP %R12,0x38(%RSP) |
0x5a1e6e JNE 5a1b30 |
0x5a254c VMOVSD %XMM15,%XMM15,%XMM5 |
0x5a2550 JMP 5a1e5b |
0x5a2c3d VMOVSD %XMM5,%XMM5,%XMM15 |
0x5a2c41 VXORPD %XMM8,%XMM8,%XMM8 |
0x5a2c46 XOR %R9D,%R9D |
0x5a2c49 JMP 5a1dbb |
0x5a2c5a VMOVSD %XMM15,%XMM15,%XMM5 |
0x5a2c5e JMP 5a1e0e |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 307 - 314 |
-------------------------------------------------------------------------------- |
307: for (i = iBegin; i < iEnd; i++) |
308: { |
309: tempx = b_data[i]; |
310: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
311: { |
312: tempx -= A_data[jj] * x_data[A_j[jj]]; |
313: } |
314: y_data[i] = tempx; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.08 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.11 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.08 |
Bottlenecks | P2, P3, |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source | csr_matvec.c:307-314 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 45.50 |
CQA cycles if no scalar integer | 42.00 |
CQA cycles if FP arith vectorized | 45.50 |
CQA cycles if fully vectorized | 40.94 |
Front-end cycles | 42.25 |
DIV/SQRT cycles | 28.50 |
P0 cycles | 28.50 |
P1 cycles | 45.50 |
P2 cycles | 45.50 |
P3 cycles | 1.00 |
P4 cycles | 28.50 |
P5 cycles | 28.50 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 87.65 |
Stall cycles (UFS) | 48.85 |
Nb insns | 135.00 |
Nb uops | 159.00 |
Nb loads | 39.00 |
Nb stores | 1.00 |
Nb stack references | 3.00 |
FLOP/cycle | 3.16 |
Nb FLOP add-sub | 18.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 63.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 34.46 |
Bytes prefetched | 0.00 |
Bytes loaded | 1560.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 53.85 |
Vectorization ratio load | 77.42 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 75.00 |
Vectorization ratio fma | 72.73 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 39.39 |
Vector-efficiency ratio all | 45.77 |
Vector-efficiency ratio load | 75.40 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 28.13 |
Vector-efficiency ratio fma | 71.59 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 34.85 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.08 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.11 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.08 |
Bottlenecks | P2, P3, |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source | csr_matvec.c:307-314 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 45.50 |
CQA cycles if no scalar integer | 42.00 |
CQA cycles if FP arith vectorized | 45.50 |
CQA cycles if fully vectorized | 40.94 |
Front-end cycles | 42.25 |
DIV/SQRT cycles | 28.50 |
P0 cycles | 28.50 |
P1 cycles | 45.50 |
P2 cycles | 45.50 |
P3 cycles | 1.00 |
P4 cycles | 28.50 |
P5 cycles | 28.50 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 87.65 |
Stall cycles (UFS) | 48.85 |
Nb insns | 135.00 |
Nb uops | 159.00 |
Nb loads | 39.00 |
Nb stores | 1.00 |
Nb stack references | 3.00 |
FLOP/cycle | 3.16 |
Nb FLOP add-sub | 18.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 63.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 34.46 |
Bytes prefetched | 0.00 |
Bytes loaded | 1560.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 53.85 |
Vectorization ratio load | 77.42 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 75.00 |
Vectorization ratio fma | 72.73 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 39.39 |
Vector-efficiency ratio all | 45.77 |
Vector-efficiency ratio load | 75.40 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 28.13 |
Vector-efficiency ratio fma | 71.59 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 34.85 |
Path / |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source file and lines | csr_matvec.c:307-314 |
Module | exec |
nb instructions | 135 |
nb uops | 159 |
loop length | 642 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 14 |
used ymm registers | 6 |
used zmm registers | 15 |
nb stack references | 3 |
micro-operation queue | 42.25 cycles |
front end | 42.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 28.50 | 28.50 | 45.50 | 45.50 | 1.00 | 28.50 | 28.50 | 1.00 |
cycles | 28.50 | 28.50 | 45.50 | 45.50 | 1.00 | 28.50 | 28.50 | 1.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 87.65 |
Stall cycles | 48.85 |
ROB full (events) | 57.13 |
Front-end | 42.25 |
Dispatch | 45.50 |
Overall L1 | 45.50 |
all | 34% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 64% |
load | 69% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 75% |
fma | 72% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 72% |
all | 53% |
load | 77% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 75% |
fma | 72% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 39% |
all | 40% |
load | 93% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 48% |
load | 69% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | 71% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 53% |
all | 45% |
load | 75% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | 71% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 34% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x28(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%R8,%R12,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x8(%R8,%R12,8),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RAX,%R12,8),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP %R11,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R11,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x6,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 5a2c3d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA (,%RDX,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA (%R14,%RCX,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R13,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SAL $0x6,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA -0x40(%R10),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x6,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
INC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
AND $0x7,%EDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c9b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x1,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c75 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x2,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c58 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x3,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c3b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x4,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c1e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x5,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c01 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x6,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1be4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMOVDQU64 (%RCX),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV $0x40,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM2,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM4,8),%ZMM13{%K5} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM13,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM10,8),%ZMM1{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM1,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM9,8),%ZMM3{%K3} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM15,8),%ZMM8{%K7} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM8,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RAX,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1d80 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VEXTRACTF64X4 $0x1,%ZMM0,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV %RSI,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %YMM0,%YMM6,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
AND $-0x8,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VADDPD %YMM0,%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R9,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VEXTRACTF64X2 $0x1,%YMM14,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %XMM14,%XMM11,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VUNPCKHPD %XMM7,%XMM7,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VADDPD %XMM7,%XMM12,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM2,%XMM5,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST $0x7,%SIL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a254c | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
SUB %R9,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 5a2c5a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %R15,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %RSI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDQU (%R13,%R9,8),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
AND $-0x4,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
AND $0x3,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VGATHERQPD (%RBX,%YMM4,8),%YMM13{%K2} | 4 | 1 | 0 | 2 | 2 | 0 | 1 | 0 | 0 | 20 | 4 |
VFNMADD132PD (%R14,%R9,8),%YMM8,%YMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF64X2 $0x1,%YMM13,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %XMM13,%XMM10,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VUNPCKHPD %XMM1,%XMM1,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VADDPD %XMM1,%XMM9,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM3,%XMM5,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV (%R13,%RDX,8),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RDX),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDX,8),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RBX,%R9,8),%XMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFNMADD231SD (%R14,%RDX,8),%XMM15,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R11,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x8(%R13,%RSI,1),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x2,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD (%RBX,%RDI,8),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFNMADD231SD 0x8(%R14,%RSI,1),%XMM8,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R11,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%R13,%RSI,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RBX,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFNMADD231SD 0x10(%R14,%RSI,1),%XMM0,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x30(%RSP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM5,(%R11,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
INC %R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R12,0x38(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 5a1b30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMOVSD %XMM15,%XMM15,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
JMP 5a1e5b | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
VMOVSD %XMM5,%XMM5,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 5a1dbb | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
VMOVSD %XMM15,%XMM15,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
JMP 5a1e0e | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source file and lines | csr_matvec.c:307-314 |
Module | exec |
nb instructions | 135 |
nb uops | 159 |
loop length | 642 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 14 |
used ymm registers | 6 |
used zmm registers | 15 |
nb stack references | 3 |
micro-operation queue | 42.25 cycles |
front end | 42.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 28.50 | 28.50 | 45.50 | 45.50 | 1.00 | 28.50 | 28.50 | 1.00 |
cycles | 28.50 | 28.50 | 45.50 | 45.50 | 1.00 | 28.50 | 28.50 | 1.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 87.65 |
Stall cycles | 48.85 |
ROB full (events) | 57.13 |
Front-end | 42.25 |
Dispatch | 45.50 |
Overall L1 | 45.50 |
all | 34% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 64% |
load | 69% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 75% |
fma | 72% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 72% |
all | 53% |
load | 77% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 75% |
fma | 72% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 39% |
all | 40% |
load | 93% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 48% |
load | 69% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | 71% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 53% |
all | 45% |
load | 75% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | 71% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 34% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x28(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV (%R8,%R12,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x8(%R8,%R12,8),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RAX,%R12,8),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP %R11,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R11,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x6,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 5a2c3d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RSI,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA (,%RDX,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x3,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA (%R14,%RCX,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R13,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SAL $0x6,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA -0x40(%R10),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x6,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
INC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
AND $0x7,%EDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c9b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x1,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c75 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x2,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c58 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x3,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c3b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x4,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c1e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x5,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1c01 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x6,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1be4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMOVDQU64 (%RCX),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV $0x40,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM2,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM4,8),%ZMM13{%K5} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM13,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM10,8),%ZMM1{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM1,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM9,8),%ZMM3{%K3} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVDQU64 (%RCX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
KMOVB %K0,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (%RBX,%ZMM15,8),%ZMM8{%K7} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
VFNMADD231PD (%R9,%RAX,1),%ZMM8,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RAX,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a1d80 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VEXTRACTF64X4 $0x1,%ZMM0,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV %RSI,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDPD %YMM0,%YMM6,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
AND $-0x8,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VADDPD %YMM0,%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R9,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VEXTRACTF64X2 $0x1,%YMM14,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %XMM14,%XMM11,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VUNPCKHPD %XMM7,%XMM7,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VADDPD %XMM7,%XMM12,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM2,%XMM5,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST $0x7,%SIL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 5a254c | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
SUB %R9,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 5a2c5a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %R15,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %RSI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDQU (%R13,%R9,8),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
AND $-0x4,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
AND $0x3,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VGATHERQPD (%RBX,%YMM4,8),%YMM13{%K2} | 4 | 1 | 0 | 2 | 2 | 0 | 1 | 0 | 0 | 20 | 4 |
VFNMADD132PD (%R14,%R9,8),%YMM8,%YMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF64X2 $0x1,%YMM13,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VADDPD %XMM13,%XMM10,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VUNPCKHPD %XMM1,%XMM1,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VADDPD %XMM1,%XMM9,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM3,%XMM5,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV (%R13,%RDX,8),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RDX),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDX,8),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RBX,%R9,8),%XMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFNMADD231SD (%R14,%RDX,8),%XMM15,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R11,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x8(%R13,%RSI,1),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x2,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD (%RBX,%RDI,8),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFNMADD231SD 0x8(%R14,%RSI,1),%XMM8,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R11,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 5a1e5b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%R13,%RSI,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RBX,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFNMADD231SD 0x10(%R14,%RSI,1),%XMM0,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x30(%RSP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM5,(%R11,%R12,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
INC %R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R12,0x38(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 5a1b30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMOVSD %XMM15,%XMM15,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
JMP 5a1e5b | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
VMOVSD %XMM5,%XMM5,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 5a1dbb | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
VMOVSD %XMM15,%XMM15,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
JMP 5a1e0e | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |