Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2311 - 2320 |
-------------------------------------------------------------------------------- |
2311: for (i=0; i < num_var; i++) |
2312: { |
2313: if (CF_marker[i] > 0 ) |
2314: { |
2315: if (CF_marker[i] == 1) CF_marker[i] = new_CF_marker[cnt++]; |
2316: else { CF_marker[i] = 1; cnt++;} |
2317: } |
2318: } |
2319: |
2320: return 0; |
0x47f290 TEST %RSI,%RSI |
0x47f293 JLE 47f39d |
0x47f299 CMP $0x4,%RSI |
0x47f29d JAE 47f2a6 |
0x47f29f XOR %EAX,%EAX |
0x47f2a1 JMP 47f391 |
0x47f2a6 PUSH %RBP |
0x47f2a7 MOV %RSP,%RBP |
0x47f2aa MOV %RSI,%RCX |
0x47f2ad SHR $0x2,%RCX |
0x47f2b1 LEA 0x18(%RDI),%R8 |
0x47f2b5 XOR %EAX,%EAX |
0x47f2b7 JMP 47f2d7 |
0x47f2b9 NOPL (%RAX) |
(2158) 0x47f2c0 MOVQ $0x1,(%R8) |
(2158) 0x47f2c7 INC %RAX |
(2158) 0x47f2ca ADD $0x20,%R8 |
(2158) 0x47f2ce DEC %RCX |
(2158) 0x47f2d1 JE 47f390 |
(2158) 0x47f2d7 MOV -0x18(%R8),%R9 |
(2158) 0x47f2db TEST %R9,%R9 |
(2158) 0x47f2de JLE 47f30b |
(2158) 0x47f2e0 CMP $0x1,%R9 |
(2158) 0x47f2e4 JNE 47f300 |
(2158) 0x47f2e6 MOV (%RDX,%RAX,8),%R9 |
(2158) 0x47f2ea INC %RAX |
(2158) 0x47f2ed MOV %R9,-0x18(%R8) |
(2158) 0x47f2f1 JMP 47f30b |
0x47f2f3 NOPW %CS:(%RAX,%RAX,1) |
(2158) 0x47f300 MOVQ $0x1,-0x18(%R8) |
(2158) 0x47f308 INC %RAX |
(2158) 0x47f30b MOV -0x10(%R8),%R9 |
(2158) 0x47f30f TEST %R9,%R9 |
(2158) 0x47f312 JLE 47f33b |
(2158) 0x47f314 CMP $0x1,%R9 |
(2158) 0x47f318 JNE 47f330 |
(2158) 0x47f31a MOV (%RDX,%RAX,8),%R9 |
(2158) 0x47f31e INC %RAX |
(2158) 0x47f321 MOV %R9,-0x10(%R8) |
(2158) 0x47f325 JMP 47f33b |
0x47f327 NOPW (%RAX,%RAX,1) |
(2158) 0x47f330 MOVQ $0x1,-0x10(%R8) |
(2158) 0x47f338 INC %RAX |
(2158) 0x47f33b MOV -0x8(%R8),%R9 |
(2158) 0x47f33f TEST %R9,%R9 |
(2158) 0x47f342 JLE 47f36b |
(2158) 0x47f344 CMP $0x1,%R9 |
(2158) 0x47f348 JNE 47f360 |
(2158) 0x47f34a MOV (%RDX,%RAX,8),%R9 |
(2158) 0x47f34e INC %RAX |
(2158) 0x47f351 MOV %R9,-0x8(%R8) |
(2158) 0x47f355 JMP 47f36b |
0x47f357 NOPW (%RAX,%RAX,1) |
(2158) 0x47f360 MOVQ $0x1,-0x8(%R8) |
(2158) 0x47f368 INC %RAX |
(2158) 0x47f36b MOV (%R8),%R9 |
(2158) 0x47f36e TEST %R9,%R9 |
(2158) 0x47f371 JLE 47f2ca |
(2158) 0x47f377 CMP $0x1,%R9 |
(2158) 0x47f37b JNE 47f2c0 |
(2158) 0x47f381 MOV (%RDX,%RAX,8),%R9 |
(2158) 0x47f385 INC %RAX |
(2158) 0x47f388 MOV %R9,(%R8) |
(2158) 0x47f38b JMP 47f2ca |
0x47f390 POP %RBP |
0x47f391 MOV %RSI,%RCX |
0x47f394 AND $-0x4,%RCX |
0x47f398 CMP %RSI,%RCX |
0x47f39b JB 47f3b3 |
0x47f39d XOR %EAX,%EAX |
0x47f39f RET |
(2157) 0x47f3a0 MOVQ $0x1,(%RDI,%RCX,8) |
(2157) 0x47f3a8 INC %RAX |
(2157) 0x47f3ab INC %RCX |
(2157) 0x47f3ae CMP %RCX,%RSI |
(2157) 0x47f3b1 JE 47f39d |
(2157) 0x47f3b3 MOV (%RDI,%RCX,8),%R8 |
(2157) 0x47f3b7 TEST %R8,%R8 |
(2157) 0x47f3ba JLE 47f3ab |
(2157) 0x47f3bc CMP $0x1,%R8 |
(2157) 0x47f3c0 JNE 47f3a0 |
(2157) 0x47f3c2 MOV (%RDX,%RAX,8),%R8 |
(2157) 0x47f3c6 INC %RAX |
(2157) 0x47f3c9 MOV %R8,(%RDI,%RCX,8) |
(2157) 0x47f3cd JMP 47f3ab |
0x47f3cf NOP |
Path / |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 25 |
nb uops | 25 |
loop length | 96 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.17 cycles |
front end | 4.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
cycles | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.26 |
Stall cycles | 0.00 |
Front-end | 4.17 |
Dispatch | 2.50 |
Overall L1 | 4.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 47f39d <hypre_BoomerAMGCorrectCFMarker+0x10d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 47f2a6 <hypre_BoomerAMGCorrectCFMarker+0x16> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47f391 <hypre_BoomerAMGCorrectCFMarker+0x101> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47f2d7 <hypre_BoomerAMGCorrectCFMarker+0x47> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 47f3b3 <hypre_BoomerAMGCorrectCFMarker+0x123> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 25 |
nb uops | 25 |
loop length | 96 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.17 cycles |
front end | 4.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
cycles | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.26 |
Stall cycles | 0.00 |
Front-end | 4.17 |
Dispatch | 2.50 |
Overall L1 | 4.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 47f39d <hypre_BoomerAMGCorrectCFMarker+0x10d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 47f2a6 <hypre_BoomerAMGCorrectCFMarker+0x16> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47f391 <hypre_BoomerAMGCorrectCFMarker+0x101> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 47f2d7 <hypre_BoomerAMGCorrectCFMarker+0x47> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 47f3b3 <hypre_BoomerAMGCorrectCFMarker+0x123> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGCorrectCFMarker– | 0.01 | 0 |
○Loop 2158 - par_strength.c:2311-2316 - exec | 0.01 | 0.09 |
○Loop 2157 - par_strength.c:2311-2316 - exec | 0 | 0 |