Function: hypre_BoomerAMGBuildMultipass.extracted.28 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.8% |
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Function: hypre_BoomerAMGBuildMultipass.extracted.28 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.8% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881 |
-------------------------------------------------------------------------------- |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1747: if (n_fine) |
1748: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1749: tmp_marker_offd = NULL; |
1750: if (num_cols_offd) |
1751: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1752: tmp_array = NULL; |
1753: if (n_coarse) |
1754: { tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); } |
1755: tmp_array_offd = NULL; |
1756: if (new_num_cols_offd > n_coarse_offd) |
1757: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1758: else |
1759: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);} |
1760: for (i=0; i < n_fine; i++) |
1761: { tmp_marker[i] = -1; } |
1762: for (i=0; i < num_cols_offd; i++) |
1763: { tmp_marker_offd[i] = -1; } |
1764: |
1765: /* Compute this thread's range of pass_length */ |
1766: my_thread_num = hypre_GetThreadNum(); |
1767: num_threads = hypre_NumActiveThreads(); |
1768: thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num; |
1769: if (my_thread_num == num_threads-1) |
1770: { thread_stop = pass_pointer[pass] + pass_length; } |
1771: else |
1772: { thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); } |
1773: |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
1877: } |
1878: hypre_TFree(tmp_marker); |
1879: hypre_TFree(tmp_marker_offd); |
1880: hypre_TFree(tmp_array); |
1881: hypre_TFree(tmp_array_offd); |
0x43f860 PUSH %RBP |
0x43f861 MOV %RSP,%RBP |
0x43f864 PUSH %R15 |
0x43f866 PUSH %R14 |
0x43f868 PUSH %R13 |
0x43f86a PUSH %R12 |
0x43f86c PUSH %RBX |
0x43f86d SUB $0x178,%RSP |
0x43f874 MOV %R9,-0xc8(%RBP) |
0x43f87b MOV %R8,-0xd8(%RBP) |
0x43f882 MOV %RCX,-0xf0(%RBP) |
0x43f889 MOV %RDX,-0x168(%RBP) |
0x43f890 MOV 0x138(%RBP),%RAX |
0x43f897 MOV %RAX,-0x30(%RBP) |
0x43f89b MOV 0x130(%RBP),%R13 |
0x43f8a2 MOV 0x128(%RBP),%RAX |
0x43f8a9 MOV %RAX,-0x40(%RBP) |
0x43f8ad MOV 0x120(%RBP),%RAX |
0x43f8b4 MOV %RAX,-0x1a0(%RBP) |
0x43f8bb MOV 0x118(%RBP),%RAX |
0x43f8c2 MOV %RAX,-0x118(%RBP) |
0x43f8c9 MOV 0x110(%RBP),%R15 |
0x43f8d0 MOV 0x108(%RBP),%R12 |
0x43f8d7 MOV 0x100(%RBP),%R14 |
0x43f8de MOV 0xf8(%RBP),%RAX |
0x43f8e5 MOV %RAX,-0x48(%RBP) |
0x43f8e9 MOV 0xf0(%RBP),%RAX |
0x43f8f0 MOV %RAX,-0x170(%RBP) |
0x43f8f7 MOV 0xe8(%RBP),%RAX |
0x43f8fe MOV %RAX,-0x160(%RBP) |
0x43f905 MOV 0xe0(%RBP),%RAX |
0x43f90c MOV %RAX,-0x158(%RBP) |
0x43f913 MOV 0xd8(%RBP),%RAX |
0x43f91a MOV %RAX,-0x110(%RBP) |
0x43f921 MOV 0xd0(%RBP),%RAX |
0x43f928 MOV %RAX,-0x108(%RBP) |
0x43f92f MOV 0xc8(%RBP),%RAX |
0x43f936 MOV %RAX,-0x60(%RBP) |
0x43f93a MOV 0xc0(%RBP),%RAX |
0x43f941 MOV %RAX,-0x140(%RBP) |
0x43f948 MOV 0xb8(%RBP),%RAX |
0x43f94f MOV %RAX,-0x68(%RBP) |
0x43f953 MOV 0xb0(%RBP),%RAX |
0x43f95a MOV %RAX,-0xc0(%RBP) |
0x43f961 MOV 0xa8(%RBP),%RAX |
0x43f968 MOV %RAX,-0x148(%RBP) |
0x43f96f MOV 0xa0(%RBP),%RAX |
0x43f976 MOV %RAX,-0x178(%RBP) |
0x43f97d MOV 0x98(%RBP),%RAX |
0x43f984 MOV %RAX,-0x150(%RBP) |
0x43f98b MOV 0x90(%RBP),%RAX |
0x43f992 MOV %RAX,-0x38(%RBP) |
0x43f996 MOV 0x88(%RBP),%RAX |
0x43f99d MOV %RAX,-0xa0(%RBP) |
0x43f9a4 MOV 0x80(%RBP),%RAX |
0x43f9ab MOV %RAX,-0x80(%RBP) |
0x43f9af MOV 0x78(%RBP),%RAX |
0x43f9b3 MOV %RAX,-0x50(%RBP) |
0x43f9b7 MOV 0x70(%RBP),%RAX |
0x43f9bb MOV %RAX,-0xb8(%RBP) |
0x43f9c2 MOV 0x68(%RBP),%RAX |
0x43f9c6 MOV %RAX,-0x78(%RBP) |
0x43f9ca MOV 0x60(%RBP),%RBX |
0x43f9ce MOV 0x58(%RBP),%RAX |
0x43f9d2 MOV %RAX,-0x198(%RBP) |
0x43f9d9 MOV 0x50(%RBP),%RAX |
0x43f9dd MOV %RAX,-0xe8(%RBP) |
0x43f9e4 MOV 0x48(%RBP),%RAX |
0x43f9e8 MOV %RAX,-0x190(%RBP) |
0x43f9ef MOV 0x40(%RBP),%RAX |
0x43f9f3 MOV %RAX,-0xe0(%RBP) |
0x43f9fa MOV 0x38(%RBP),%RAX |
0x43f9fe MOV %RAX,-0x188(%RBP) |
0x43fa05 MOV 0x30(%RBP),%RAX |
0x43fa09 MOV %RAX,-0x138(%RBP) |
0x43fa10 MOV 0x28(%RBP),%RAX |
0x43fa14 MOV %RAX,-0x58(%RBP) |
0x43fa18 MOV 0x20(%RBP),%RAX |
0x43fa1c MOV %RAX,-0x180(%RBP) |
0x43fa23 MOV 0x18(%RBP),%RAX |
0x43fa27 MOV %RAX,-0x130(%RBP) |
0x43fa2e MOV 0x10(%RBP),%RAX |
0x43fa32 MOV %RAX,-0x88(%RBP) |
0x43fa39 MOV (%R14),%RDI |
0x43fa3c TEST %RDI,%RDI |
0x43fa3f JE 43fa4d |
0x43fa41 MOV $0x8,%ESI |
0x43fa46 CALL 4cf760 <hypre_CAlloc> |
0x43fa4b JMP 43fa4f |
0x43fa4d XOR %EAX,%EAX |
0x43fa4f MOV %RAX,-0x90(%RBP) |
0x43fa56 MOV (%RBX),%RDI |
0x43fa59 TEST %RDI,%RDI |
0x43fa5c JE 43fa6e |
0x43fa5e MOV $0x8,%ESI |
0x43fa63 CALL 4cf760 <hypre_CAlloc> |
0x43fa68 MOV %RAX,-0x70(%RBP) |
0x43fa6c JMP 43fa76 |
0x43fa6e MOVQ $0,-0x70(%RBP) |
0x43fa76 MOV (%R12),%RDI |
0x43fa7a TEST %RDI,%RDI |
0x43fa7d JE 43fa8e |
0x43fa7f MOV $0x8,%ESI |
0x43fa84 CALL 4cf760 <hypre_CAlloc> |
0x43fa89 MOV %RAX,%R12 |
0x43fa8c JMP 43fa91 |
0x43fa8e XOR %R12D,%R12D |
0x43fa91 CMP %R15,%R13 |
0x43fa94 CMOVG %R13,%R15 |
0x43fa98 MOV $0x8,%ESI |
0x43fa9d MOV %R15,%RDI |
0x43faa0 CALL 4cf760 <hypre_CAlloc> |
0x43faa5 MOV %RAX,%R15 |
0x43faa8 CMPQ $0,(%R14) |
0x43faac MOV -0x90(%RBP),%RCX |
0x43fab3 JLE 43fad0 |
0x43fab5 XOR %EAX,%EAX |
0x43fab7 NOPW (%RAX,%RAX,1) |
(833) 0x43fac0 MOVQ $-0x1,(%RCX,%RAX,8) |
(833) 0x43fac8 INC %RAX |
(833) 0x43facb CMP (%R14),%RAX |
(833) 0x43face JL 43fac0 |
0x43fad0 CMPQ $0,(%RBX) |
0x43fad4 MOV -0x70(%RBP),%RCX |
0x43fad8 JLE 43faf0 |
0x43fada XOR %EAX,%EAX |
0x43fadc NOPL (%RAX) |
(832) 0x43fae0 MOVQ $-0x1,(%RCX,%RAX,8) |
(832) 0x43fae8 INC %RAX |
(832) 0x43faeb CMP (%RBX),%RAX |
(832) 0x43faee JL 43fae0 |
0x43faf0 CALL 4d1410 <hypre_GetThreadNum> |
0x43faf5 MOV %RAX,%RBX |
0x43faf8 CALL 4d1400 <hypre_NumActiveThreads> |
0x43fafd MOV %RAX,%RCX |
0x43fb00 MOV -0x68(%RBP),%RAX |
0x43fb04 MOV (%RAX),%RAX |
0x43fb07 MOV -0x48(%RBP),%R9 |
0x43fb0b MOV (%R9),%RDX |
0x43fb0e MOV (%RAX,%RDX,8),%RDI |
0x43fb12 MOV -0x30(%RBP),%RAX |
0x43fb16 MOV (%RAX),%RSI |
0x43fb19 MOV %RSI,%RAX |
0x43fb1c OR %RCX,%RAX |
0x43fb1f SHR $0x20,%RAX |
0x43fb23 JE 43fb2f |
0x43fb25 MOV %RSI,%RAX |
0x43fb28 CQTO |
0x43fb2a IDIV %RCX |
0x43fb2d JMP 43fb35 |
0x43fb2f MOV %ESI,%EAX |
0x43fb31 XOR %EDX,%EDX |
0x43fb33 DIV %ECX |
0x43fb35 MOV -0x40(%RBP),%R11 |
0x43fb39 MOV -0x38(%RBP),%RDX |
0x43fb3d MOV %RAX,%R8 |
0x43fb40 IMUL %RBX,%R8 |
0x43fb44 DEC %RCX |
0x43fb47 LEA 0x1(%RBX),%R10 |
0x43fb4b IMUL %RAX,%R10 |
0x43fb4f CMP %RCX,%RBX |
0x43fb52 CMOVE %RSI,%R10 |
0x43fb56 MOV %R10,-0xd0(%RBP) |
0x43fb5d CMP %R10,%R8 |
0x43fb60 JGE 4406a7 |
0x43fb66 ADD %RDI,-0xd0(%RBP) |
0x43fb6d ADD %RDI,%R8 |
0x43fb70 MOV -0xc0(%RBP),%RAX |
0x43fb77 MOV (%RAX),%RAX |
0x43fb7a MOV %RAX,-0x128(%RBP) |
0x43fb81 MOV -0xb8(%RBP),%RAX |
0x43fb88 MOV (%RAX),%RAX |
0x43fb8b MOV %RAX,-0x68(%RBP) |
0x43fb8f MOV -0x60(%RBP),%RAX |
0x43fb93 MOV (%RAX),%RAX |
0x43fb96 MOV %RAX,-0xb8(%RBP) |
0x43fb9d MOV -0xa0(%RBP),%RAX |
0x43fba4 MOV (%RAX),%RAX |
0x43fba7 MOV %RAX,-0x60(%RBP) |
0x43fbab MOV -0x88(%RBP),%RAX |
0x43fbb2 MOV (%RAX),%RAX |
0x43fbb5 MOV %RAX,-0x120(%RBP) |
0x43fbbc MOV -0x50(%RBP),%RAX |
0x43fbc0 ADD $0x18,%RAX |
0x43fbc4 MOV %RAX,-0x100(%RBP) |
0x43fbcb LEA 0x18(%RDX),%RAX |
0x43fbcf MOV %RAX,-0xf8(%RBP) |
0x43fbd6 VXORPD %XMM8,%XMM8,%XMM8 |
0x43fbdb JMP 43fbf7 |
0x43fbdd NOPL (%RAX) |
(812) 0x43fbe0 MOV -0xc0(%RBP),%R8 |
(812) 0x43fbe7 INC %R8 |
(812) 0x43fbea CMP -0xd0(%RBP),%R8 |
(812) 0x43fbf1 JGE 4406a7 |
(812) 0x43fbf7 MOV %R8,-0xc0(%RBP) |
(812) 0x43fbfe MOV -0x128(%RBP),%RAX |
(812) 0x43fc05 MOV (%RAX,%R8,8),%RCX |
(812) 0x43fc09 MOV -0x140(%RBP),%RAX |
(812) 0x43fc10 MOV (%RAX,%RCX,8),%R14 |
(812) 0x43fc14 MOV -0x68(%RBP),%RAX |
(812) 0x43fc18 MOV (%RAX,%RCX,8),%R13 |
(812) 0x43fc1c MOV %RCX,-0x30(%RBP) |
(812) 0x43fc20 MOV 0x8(%RAX,%RCX,8),%RSI |
(812) 0x43fc25 LEA (%RSI,%R14,1),%RAX |
(812) 0x43fc29 SUB %R13,%RAX |
(812) 0x43fc2c CMP %RAX,%R14 |
(812) 0x43fc2f JGE 43fdc6 |
(812) 0x43fc35 MOV -0x108(%RBP),%RAX |
(812) 0x43fc3c MOV (%RAX),%RBX |
(812) 0x43fc3f MOV -0x78(%RBP),%RAX |
(812) 0x43fc43 MOV (%RAX),%RAX |
(812) 0x43fc46 MOV %RSI,%RCX |
(812) 0x43fc49 SUB %R13,%RCX |
(812) 0x43fc4c CMP $0xc,%RCX |
(812) 0x43fc50 JBE 43fd90 |
(812) 0x43fc56 MOV %RSI,-0xb0(%RBP) |
(812) 0x43fc5d VMOVUPD %XMM6,-0xa0(%RBP) |
(812) 0x43fc65 LEA (%RAX,%R13,8),%RDI |
(812) 0x43fc69 LEA (,%RCX,8),%RDX |
(812) 0x43fc71 XOR %ESI,%ESI |
(812) 0x43fc73 MOV %RCX,-0xa8(%RBP) |
(812) 0x43fc7a VZEROUPPER |
(812) 0x43fc7d CALL 4d8930 <_intel_fast_memset> |
(812) 0x43fc82 MOV -0xa8(%RBP),%R10 |
(812) 0x43fc89 MOV -0x48(%RBP),%R9 |
(812) 0x43fc8d MOV %R10,%RAX |
(812) 0x43fc90 SHR $0x2,%RAX |
(812) 0x43fc94 LEA (,%R14,8),%RCX |
(812) 0x43fc9c MOV -0x100(%RBP),%RDX |
(812) 0x43fca3 LEA (%RDX,%R13,8),%RDX |
(812) 0x43fca7 XOR %ESI,%ESI |
(812) 0x43fca9 NOPL (%RAX) |
(830) 0x43fcb0 MOV (%R9),%RDI |
(830) 0x43fcb3 MOV (%RBX,%RDI,8),%RDI |
(830) 0x43fcb7 ADD %RCX,%RDI |
(830) 0x43fcba MOV (%RDI,%RSI,8),%RDI |
(830) 0x43fcbe LEA (%RSI,%R13,1),%R8 |
(830) 0x43fcc2 MOV %R8,(%R12,%RDI,8) |
(830) 0x43fcc6 MOV %RDI,-0x18(%RDX,%RSI,8) |
(830) 0x43fccb MOV (%R9),%RDI |
(830) 0x43fcce MOV (%RBX,%RDI,8),%RDI |
(830) 0x43fcd2 ADD %RCX,%RDI |
(830) 0x43fcd5 MOV 0x8(%RDI,%RSI,8),%RDI |
(830) 0x43fcda LEA (%RSI,%R13,1),%R8 |
(830) 0x43fcde INC %R8 |
(830) 0x43fce1 MOV %R8,(%R12,%RDI,8) |
(830) 0x43fce5 MOV %RDI,-0x10(%RDX,%RSI,8) |
(830) 0x43fcea MOV (%R9),%RDI |
(830) 0x43fced MOV (%RBX,%RDI,8),%RDI |
(830) 0x43fcf1 ADD %RCX,%RDI |
(830) 0x43fcf4 MOV 0x10(%RDI,%RSI,8),%RDI |
(830) 0x43fcf9 LEA (%RSI,%R13,1),%R8 |
(830) 0x43fcfd ADD $0x2,%R8 |
(830) 0x43fd01 MOV %R8,(%R12,%RDI,8) |
(830) 0x43fd05 MOV %RDI,-0x8(%RDX,%RSI,8) |
(830) 0x43fd0a MOV (%R9),%RDI |
(830) 0x43fd0d MOV (%RBX,%RDI,8),%RDI |
(830) 0x43fd11 ADD %RCX,%RDI |
(830) 0x43fd14 MOV 0x18(%RDI,%RSI,8),%RDI |
(830) 0x43fd19 LEA (%RSI,%R13,1),%R8 |
(830) 0x43fd1d ADD $0x3,%R8 |
(830) 0x43fd21 MOV %R8,(%R12,%RDI,8) |
(830) 0x43fd25 MOV %RDI,(%RDX,%RSI,8) |
(830) 0x43fd29 ADD $0x4,%RSI |
(830) 0x43fd2d DEC %RAX |
(830) 0x43fd30 JNE 43fcb0 |
(812) 0x43fd36 MOV %R10,%RAX |
(812) 0x43fd39 AND $-0x4,%RAX |
(812) 0x43fd3d CMP %R10,%RAX |
(812) 0x43fd40 MOV -0x40(%RBP),%R11 |
(812) 0x43fd44 MOV -0x50(%RBP),%RCX |
(812) 0x43fd48 VXORPD %XMM8,%XMM8,%XMM8 |
(812) 0x43fd4d VMOVUPD -0xa0(%RBP),%XMM6 |
(812) 0x43fd55 MOV -0xb0(%RBP),%RDX |
(812) 0x43fd5c JAE 43fdc6 |
(812) 0x43fd5e ADD %RAX,%R13 |
(812) 0x43fd61 ADD %RAX,%R14 |
(812) 0x43fd64 NOPW %CS:(%RAX,%RAX,1) |
(831) 0x43fd70 MOV (%R9),%RAX |
(831) 0x43fd73 MOV (%RBX,%RAX,8),%RAX |
(831) 0x43fd77 MOV (%RAX,%R14,8),%RAX |
(831) 0x43fd7b MOV %R13,(%R12,%RAX,8) |
(831) 0x43fd7f MOV %RAX,(%RCX,%R13,8) |
(831) 0x43fd83 INC %R13 |
(831) 0x43fd86 INC %R14 |
(831) 0x43fd89 CMP %R13,%RDX |
(831) 0x43fd8c JNE 43fd70 |
(812) 0x43fd8e JMP 43fdc6 |
(812) 0x43fd90 MOV -0x50(%RBP),%RDX |
(812) 0x43fd94 NOPW %CS:(%RAX,%RAX,1) |
(829) 0x43fda0 MOV (%R9),%RCX |
(829) 0x43fda3 MOV (%RBX,%RCX,8),%RCX |
(829) 0x43fda7 MOV (%RCX,%R14,8),%RCX |
(829) 0x43fdab MOV %R13,(%R12,%RCX,8) |
(829) 0x43fdaf MOVQ $0,(%RAX,%R13,8) |
(829) 0x43fdb7 MOV %RCX,(%RDX,%R13,8) |
(829) 0x43fdbb INC %R13 |
(829) 0x43fdbe INC %R14 |
(829) 0x43fdc1 CMP %R13,%RSI |
(829) 0x43fdc4 JNE 43fda0 |
(812) 0x43fdc6 MOV -0xb8(%RBP),%RAX |
(812) 0x43fdcd MOV -0x30(%RBP),%RCX |
(812) 0x43fdd1 MOV (%RAX,%RCX,8),%R14 |
(812) 0x43fdd5 MOV -0x60(%RBP),%RAX |
(812) 0x43fdd9 MOV (%RAX,%RCX,8),%R13 |
(812) 0x43fddd MOV 0x8(%RAX,%RCX,8),%RSI |
(812) 0x43fde2 LEA (%RSI,%R14,1),%RAX |
(812) 0x43fde6 SUB %R13,%RAX |
(812) 0x43fde9 CMP %RAX,%R14 |
(812) 0x43fdec MOV -0x38(%RBP),%RDX |
(812) 0x43fdf0 JGE 43ff86 |
(812) 0x43fdf6 MOV -0x110(%RBP),%RAX |
(812) 0x43fdfd MOV (%RAX),%RBX |
(812) 0x43fe00 MOV -0x80(%RBP),%RAX |
(812) 0x43fe04 MOV (%RAX),%RAX |
(812) 0x43fe07 MOV %RSI,%RCX |
(812) 0x43fe0a SUB %R13,%RCX |
(812) 0x43fe0d CMP $0xc,%RCX |
(812) 0x43fe11 JBE 43ff50 |
(812) 0x43fe17 MOV %RSI,-0xb0(%RBP) |
(812) 0x43fe1e VMOVUPD %XMM6,-0xa0(%RBP) |
(812) 0x43fe26 LEA (%RAX,%R13,8),%RDI |
(812) 0x43fe2a LEA (,%RCX,8),%RDX |
(812) 0x43fe32 XOR %ESI,%ESI |
(812) 0x43fe34 MOV %RCX,-0xa8(%RBP) |
(812) 0x43fe3b VZEROUPPER |
(812) 0x43fe3e CALL 4d8930 <_intel_fast_memset> |
(812) 0x43fe43 MOV -0xa8(%RBP),%R10 |
(812) 0x43fe4a MOV -0x48(%RBP),%R9 |
(812) 0x43fe4e MOV %R10,%RAX |
(812) 0x43fe51 SHR $0x2,%RAX |
(812) 0x43fe55 LEA (,%R14,8),%RCX |
(812) 0x43fe5d MOV -0xf8(%RBP),%RDX |
(812) 0x43fe64 LEA (%RDX,%R13,8),%RDX |
(812) 0x43fe68 XOR %ESI,%ESI |
(812) 0x43fe6a NOPW (%RAX,%RAX,1) |
(827) 0x43fe70 MOV (%R9),%RDI |
(827) 0x43fe73 MOV (%RBX,%RDI,8),%RDI |
(827) 0x43fe77 ADD %RCX,%RDI |
(827) 0x43fe7a MOV (%RDI,%RSI,8),%RDI |
(827) 0x43fe7e LEA (%RSI,%R13,1),%R8 |
(827) 0x43fe82 MOV %R8,(%R15,%RDI,8) |
(827) 0x43fe86 MOV %RDI,-0x18(%RDX,%RSI,8) |
(827) 0x43fe8b MOV (%R9),%RDI |
(827) 0x43fe8e MOV (%RBX,%RDI,8),%RDI |
(827) 0x43fe92 ADD %RCX,%RDI |
(827) 0x43fe95 MOV 0x8(%RDI,%RSI,8),%RDI |
(827) 0x43fe9a LEA (%RSI,%R13,1),%R8 |
(827) 0x43fe9e INC %R8 |
(827) 0x43fea1 MOV %R8,(%R15,%RDI,8) |
(827) 0x43fea5 MOV %RDI,-0x10(%RDX,%RSI,8) |
(827) 0x43feaa MOV (%R9),%RDI |
(827) 0x43fead MOV (%RBX,%RDI,8),%RDI |
(827) 0x43feb1 ADD %RCX,%RDI |
(827) 0x43feb4 MOV 0x10(%RDI,%RSI,8),%RDI |
(827) 0x43feb9 LEA (%RSI,%R13,1),%R8 |
(827) 0x43febd ADD $0x2,%R8 |
(827) 0x43fec1 MOV %R8,(%R15,%RDI,8) |
(827) 0x43fec5 MOV %RDI,-0x8(%RDX,%RSI,8) |
(827) 0x43feca MOV (%R9),%RDI |
(827) 0x43fecd MOV (%RBX,%RDI,8),%RDI |
(827) 0x43fed1 ADD %RCX,%RDI |
(827) 0x43fed4 MOV 0x18(%RDI,%RSI,8),%RDI |
(827) 0x43fed9 LEA (%RSI,%R13,1),%R8 |
(827) 0x43fedd ADD $0x3,%R8 |
(827) 0x43fee1 MOV %R8,(%R15,%RDI,8) |
(827) 0x43fee5 MOV %RDI,(%RDX,%RSI,8) |
(827) 0x43fee9 ADD $0x4,%RSI |
(827) 0x43feed DEC %RAX |
(827) 0x43fef0 JNE 43fe70 |
(812) 0x43fef6 MOV %R10,%RAX |
(812) 0x43fef9 AND $-0x4,%RAX |
(812) 0x43fefd CMP %R10,%RAX |
(812) 0x43ff00 MOV -0x40(%RBP),%R11 |
(812) 0x43ff04 MOV -0x38(%RBP),%RDX |
(812) 0x43ff08 VXORPD %XMM8,%XMM8,%XMM8 |
(812) 0x43ff0d VMOVUPD -0xa0(%RBP),%XMM6 |
(812) 0x43ff15 MOV -0xb0(%RBP),%RCX |
(812) 0x43ff1c JAE 43ff86 |
(812) 0x43ff1e ADD %RAX,%R13 |
(812) 0x43ff21 ADD %RAX,%R14 |
(812) 0x43ff24 NOPW %CS:(%RAX,%RAX,1) |
(828) 0x43ff30 MOV (%R9),%RAX |
(828) 0x43ff33 MOV (%RBX,%RAX,8),%RAX |
(828) 0x43ff37 MOV (%RAX,%R14,8),%RAX |
(828) 0x43ff3b MOV %R13,(%R15,%RAX,8) |
(828) 0x43ff3f MOV %RAX,(%RDX,%R13,8) |
(828) 0x43ff43 INC %R13 |
(828) 0x43ff46 INC %R14 |
(828) 0x43ff49 CMP %R13,%RCX |
(828) 0x43ff4c JNE 43ff30 |
(812) 0x43ff4e JMP 43ff86 |
(812) 0x43ff50 MOV -0x38(%RBP),%RDX |
(812) 0x43ff54 NOPW %CS:(%RAX,%RAX,1) |
(826) 0x43ff60 MOV (%R9),%RCX |
(826) 0x43ff63 MOV (%RBX,%RCX,8),%RCX |
(826) 0x43ff67 MOV (%RCX,%R14,8),%RCX |
(826) 0x43ff6b MOV %R13,(%R15,%RCX,8) |
(826) 0x43ff6f MOVQ $0,(%RAX,%R13,8) |
(826) 0x43ff77 MOV %RCX,(%RDX,%R13,8) |
(826) 0x43ff7b INC %R13 |
(826) 0x43ff7e INC %R14 |
(826) 0x43ff81 CMP %R13,%RSI |
(826) 0x43ff84 JNE 43ff60 |
(812) 0x43ff86 MOV -0xe0(%RBP),%RCX |
(812) 0x43ff8d MOV -0x30(%RBP),%RSI |
(812) 0x43ff91 MOV (%RCX,%RSI,8),%RAX |
(812) 0x43ff95 MOV 0x8(%RCX,%RSI,8),%RCX |
(812) 0x43ff9a CMP %RCX,%RAX |
(812) 0x43ff9d MOV -0xc8(%RBP),%R13 |
(812) 0x43ffa4 MOV %RDX,%RBX |
(812) 0x43ffa7 MOV -0x58(%RBP),%R14 |
(812) 0x43ffab JGE 440000 |
(812) 0x43ffad MOV -0x118(%RBP),%RDX |
(812) 0x43ffb4 MOV (%RDX),%RDX |
(812) 0x43ffb7 JMP 43ffc8 |
0x43ffb9 NOPL (%RAX) |
(825) 0x43ffc0 INC %RAX |
(825) 0x43ffc3 CMP %RCX,%RAX |
(825) 0x43ffc6 JGE 440000 |
(825) 0x43ffc8 MOV -0x190(%RBP),%RSI |
(825) 0x43ffcf MOV (%RSI,%RAX,8),%RSI |
(825) 0x43ffd3 MOV (%R9),%RDI |
(825) 0x43ffd6 DEC %RDI |
(825) 0x43ffd9 CMP %RDI,(%RDX,%RSI,8) |
(825) 0x43ffdd JNE 43ffc0 |
(825) 0x43ffdf MOV -0x90(%RBP),%RCX |
(825) 0x43ffe6 MOV -0x30(%RBP),%RDI |
(825) 0x43ffea MOV %RDI,(%RCX,%RSI,8) |
(825) 0x43ffee MOV -0xe0(%RBP),%RCX |
(825) 0x43fff5 MOV 0x8(%RCX,%RDI,8),%RCX |
(825) 0x43fffa JMP 43ffc0 |
0x43fffc NOPL (%RAX) |
(812) 0x440000 MOV -0xe8(%RBP),%RCX |
(812) 0x440007 MOV -0x30(%RBP),%RDX |
(812) 0x44000b MOV (%RCX,%RDX,8),%RAX |
(812) 0x44000f MOV 0x8(%RCX,%RDX,8),%RCX |
(812) 0x440014 JMP 440023 |
0x440016 NOPW %CS:(%RAX,%RAX,1) |
(824) 0x440020 INC %RAX |
(824) 0x440023 CMP %RCX,%RAX |
(824) 0x440026 JGE 440060 |
(824) 0x440028 MOV -0x198(%RBP),%RDX |
(824) 0x44002f MOV (%RDX,%RAX,8),%RDX |
(824) 0x440033 MOV (%R9),%RSI |
(824) 0x440036 DEC %RSI |
(824) 0x440039 MOV -0x1a0(%RBP),%RDI |
(824) 0x440040 CMP %RSI,(%RDI,%RDX,8) |
(824) 0x440044 JNE 440020 |
(824) 0x440046 MOV -0x70(%RBP),%RCX |
(824) 0x44004a MOV -0x30(%RBP),%RSI |
(824) 0x44004e MOV %RSI,(%RCX,%RDX,8) |
(824) 0x440052 MOV -0xe8(%RBP),%RCX |
(824) 0x440059 MOV 0x8(%RCX,%RSI,8),%RCX |
(824) 0x44005e JMP 440020 |
(812) 0x440060 MOV -0x130(%RBP),%RAX |
(812) 0x440067 MOV -0x30(%RBP),%RCX |
(812) 0x44006b MOV (%RAX,%RCX,8),%RSI |
(812) 0x44006f MOV 0x8(%RAX,%RCX,8),%RCX |
(812) 0x440074 LEA 0x1(%RSI),%RDX |
(812) 0x440078 VXORPD %XMM1,%XMM1,%XMM1 |
(812) 0x44007c CMP %RCX,%RDX |
(812) 0x44007f MOV %RSI,-0xa0(%RBP) |
(812) 0x440086 VXORPD %XMM0,%XMM0,%XMM0 |
(812) 0x44008a JGE 440410 |
(812) 0x440090 MOV -0x50(%RBP),%RAX |
(812) 0x440094 JMP 4400b4 |
0x440096 NOPW %CS:(%RAX,%RAX,1) |
(819) 0x4400a0 MOV -0x40(%RBP),%R11 |
(819) 0x4400a4 INC %RDX |
(819) 0x4400a7 CMP %RCX,%RDX |
(819) 0x4400aa MOV -0x48(%RBP),%R9 |
(819) 0x4400ae JE 440410 |
(819) 0x4400b4 MOV -0x180(%RBP),%RSI |
(819) 0x4400bb MOV (%RSI,%RDX,8),%RSI |
(819) 0x4400bf MOV -0x90(%RBP),%RDI |
(819) 0x4400c6 MOV -0x30(%RBP),%R8 |
(819) 0x4400ca CMP %R8,(%RDI,%RSI,8) |
(819) 0x4400ce JNE 440110 |
(819) 0x4400d0 MOV -0x68(%RBP),%R8 |
(819) 0x4400d4 MOV (%R8,%RSI,8),%RDI |
(819) 0x4400d8 MOV 0x8(%R8,%RSI,8),%R8 |
(819) 0x4400dd MOV %R8,%R11 |
(819) 0x4400e0 SUB %RDI,%R11 |
(819) 0x4400e3 JLE 440291 |
(819) 0x4400e9 MOV -0x88(%RBP),%R9 |
(819) 0x4400f0 MOV (%R9),%R9 |
(819) 0x4400f3 MOV -0x78(%RBP),%R10 |
(819) 0x4400f7 MOV (%R10),%R10 |
(819) 0x4400fa CMP $0x4,%R11 |
(819) 0x4400fe JAE 440155 |
(819) 0x440100 JMP 440230 |
0x440105 NOPW %CS:(%RAX,%RAX,1) |
(819) 0x440110 MOV -0x168(%RBP),%RDI |
(819) 0x440117 CMPQ $-0x3,(%RDI,%RSI,8) |
(819) 0x44011c JE 4400a4 |
(819) 0x44011e CMPQ $0x1,-0xf0(%RBP) |
(819) 0x440126 JE 440141 |
(819) 0x440128 MOV -0xd8(%RBP),%R8 |
(819) 0x44012f MOV -0x30(%RBP),%RDI |
(819) 0x440133 MOV (%R8,%RDI,8),%RDI |
(819) 0x440137 CMP (%R8,%RSI,8),%RDI |
(819) 0x44013b JNE 4400a4 |
(819) 0x440141 MOV -0x88(%RBP),%RSI |
(819) 0x440148 MOV (%RSI),%RSI |
(819) 0x44014b VADDSD (%RSI,%RDX,8),%XMM0,%XMM0 |
(819) 0x440150 JMP 4400a4 |
(819) 0x440155 MOV %R11,%RBX |
(819) 0x440158 SHR $0x2,%RBX |
(819) 0x44015c LEA 0x18(,%RDI,8),%R14 |
(819) 0x440164 NOPW %CS:(%RAX,%RAX,1) |
(822) 0x440170 MOV -0x18(%RAX,%R14,1),%R13 |
(822) 0x440175 VMOVSD -0x18(%R10,%R14,1),%XMM2 |
(822) 0x44017c VMOVSD (%R9,%RDX,8),%XMM3 |
(822) 0x440182 MOV (%R12,%R13,8),%R13 |
(822) 0x440186 VMOVSD (%R10,%R13,8),%XMM4 |
(822) 0x44018c VFMADD231SD %XMM2,%XMM3,%XMM4 |
(822) 0x440191 VMOVSD %XMM4,(%R10,%R13,8) |
(822) 0x440197 MOV -0x10(%RAX,%R14,1),%R13 |
(822) 0x44019c VMOVSD -0x10(%R10,%R14,1),%XMM4 |
(822) 0x4401a3 VMOVSD (%R9,%RDX,8),%XMM5 |
(822) 0x4401a9 MOV (%R12,%R13,8),%R13 |
(822) 0x4401ad VMOVSD (%R10,%R13,8),%XMM6 |
(822) 0x4401b3 VFMADD231SD %XMM4,%XMM5,%XMM6 |
(822) 0x4401b8 VMOVSD %XMM6,(%R10,%R13,8) |
(822) 0x4401be VMOVSD -0x8(%R10,%R14,1),%XMM6 |
(822) 0x4401c5 VMULSD (%R9,%RDX,8),%XMM6,%XMM6 |
(822) 0x4401cb MOV -0x8(%RAX,%R14,1),%R13 |
(822) 0x4401d0 MOV (%R12,%R13,8),%R13 |
(822) 0x4401d4 VADDSD (%R10,%R13,8),%XMM6,%XMM7 |
(822) 0x4401da VMOVSD %XMM7,(%R10,%R13,8) |
(822) 0x4401e0 VFMADD213SD %XMM6,%XMM5,%XMM4 |
(822) 0x4401e5 MOV (%RAX,%R14,1),%R13 |
(822) 0x4401e9 VMOVSD (%R10,%R14,1),%XMM5 |
(822) 0x4401ef VMULSD (%R9,%RDX,8),%XMM5,%XMM6 |
(822) 0x4401f5 MOV (%R12,%R13,8),%R13 |
(822) 0x4401f9 VADDSD (%R10,%R13,8),%XMM6,%XMM5 |
(822) 0x4401ff VMOVSD %XMM5,(%R10,%R13,8) |
(822) 0x440205 VADDSD %XMM1,%XMM4,%XMM1 |
(822) 0x440209 VMOVAPD %XMM2,%XMM5 |
(822) 0x44020d VFMADD213SD %XMM6,%XMM3,%XMM5 |
(822) 0x440212 VADDSD %XMM1,%XMM5,%XMM1 |
(822) 0x440216 VADDSD %XMM0,%XMM4,%XMM0 |
(822) 0x44021a VFMADD213SD %XMM6,%XMM3,%XMM2 |
(822) 0x44021f VADDSD %XMM0,%XMM2,%XMM0 |
(822) 0x440223 ADD $0x20,%R14 |
(822) 0x440227 DEC %RBX |
(822) 0x44022a JNE 440170 |
(819) 0x440230 MOV %R11,%RBX |
(819) 0x440233 AND $-0x4,%RBX |
(819) 0x440237 CMP %R11,%RBX |
(819) 0x44023a JAE 440282 |
(819) 0x44023c ADD %RBX,%RDI |
(819) 0x44023f MOV -0xc8(%RBP),%R13 |
(819) 0x440246 MOV -0x38(%RBP),%RBX |
(819) 0x44024a MOV -0x58(%RBP),%R14 |
(819) 0x44024e XCHG %AX,%AX |
(823) 0x440250 MOV (%RAX,%RDI,8),%R11 |
(823) 0x440254 VMOVSD (%R10,%RDI,8),%XMM2 |
(823) 0x44025a VMULSD (%R9,%RDX,8),%XMM2,%XMM6 |
(823) 0x440260 MOV (%R12,%R11,8),%R11 |
(823) 0x440264 VADDSD (%R10,%R11,8),%XMM6,%XMM2 |
(823) 0x44026a VMOVSD %XMM2,(%R10,%R11,8) |
(823) 0x440270 VADDSD %XMM1,%XMM6,%XMM1 |
(823) 0x440274 VADDSD %XMM0,%XMM6,%XMM0 |
(823) 0x440278 INC %RDI |
(823) 0x44027b CMP %RDI,%R8 |
(823) 0x44027e JNE 440250 |
(819) 0x440280 JMP 440291 |
(819) 0x440282 MOV -0xc8(%RBP),%R13 |
(819) 0x440289 MOV -0x38(%RBP),%RBX |
(819) 0x44028d MOV -0x58(%RBP),%R14 |
(819) 0x440291 MOV -0x60(%RBP),%R8 |
(819) 0x440295 MOV (%R8,%RSI,8),%RDI |
(819) 0x440299 MOV 0x8(%R8,%RSI,8),%RSI |
(819) 0x44029e MOV %RSI,%R10 |
(819) 0x4402a1 SUB %RDI,%R10 |
(819) 0x4402a4 JLE 4400a0 |
(819) 0x4402aa MOV -0x88(%RBP),%RAX |
(819) 0x4402b1 MOV (%RAX),%R8 |
(819) 0x4402b4 MOV -0x80(%RBP),%RAX |
(819) 0x4402b8 MOV (%RAX),%R9 |
(819) 0x4402bb CMP $0x4,%R10 |
(819) 0x4402bf JAE 4402c6 |
(819) 0x4402c1 JMP 4403a0 |
(819) 0x4402c6 MOV %R10,%R11 |
(819) 0x4402c9 SHR $0x2,%R11 |
(819) 0x4402cd MOV %RBX,%RAX |
(819) 0x4402d0 LEA 0x18(,%RDI,8),%RBX |
(819) 0x4402d8 NOPL (%RAX,%RAX,1) |
(820) 0x4402e0 MOV -0x18(%RAX,%RBX,1),%R14 |
(820) 0x4402e5 VMOVSD -0x18(%R9,%RBX,1),%XMM2 |
(820) 0x4402ec VMOVSD (%R8,%RDX,8),%XMM3 |
(820) 0x4402f2 MOV (%R15,%R14,8),%R14 |
(820) 0x4402f6 VMOVSD (%R9,%R14,8),%XMM4 |
(820) 0x4402fc VFMADD231SD %XMM2,%XMM3,%XMM4 |
(820) 0x440301 VMOVSD %XMM4,(%R9,%R14,8) |
(820) 0x440307 MOV -0x10(%RAX,%RBX,1),%R14 |
(820) 0x44030c VMOVSD -0x10(%R9,%RBX,1),%XMM4 |
(820) 0x440313 VMOVSD (%R8,%RDX,8),%XMM5 |
(820) 0x440319 MOV (%R15,%R14,8),%R14 |
(820) 0x44031d VMOVSD (%R9,%R14,8),%XMM6 |
(820) 0x440323 VFMADD231SD %XMM4,%XMM5,%XMM6 |
(820) 0x440328 VMOVSD %XMM6,(%R9,%R14,8) |
(820) 0x44032e VMOVSD -0x8(%R9,%RBX,1),%XMM6 |
(820) 0x440335 VMULSD (%R8,%RDX,8),%XMM6,%XMM6 |
(820) 0x44033b MOV -0x8(%RAX,%RBX,1),%R14 |
(820) 0x440340 MOV (%R15,%R14,8),%R14 |
(820) 0x440344 VADDSD (%R9,%R14,8),%XMM6,%XMM7 |
(820) 0x44034a VMOVSD %XMM7,(%R9,%R14,8) |
(820) 0x440350 VFMADD213SD %XMM6,%XMM5,%XMM4 |
(820) 0x440355 MOV (%RAX,%RBX,1),%R14 |
(820) 0x440359 VMOVSD (%R9,%RBX,1),%XMM5 |
(820) 0x44035f VMULSD (%R8,%RDX,8),%XMM5,%XMM6 |
(820) 0x440365 MOV (%R15,%R14,8),%R14 |
(820) 0x440369 VADDSD (%R9,%R14,8),%XMM6,%XMM5 |
(820) 0x44036f VMOVSD %XMM5,(%R9,%R14,8) |
(820) 0x440375 VADDSD %XMM1,%XMM4,%XMM1 |
(820) 0x440379 VMOVAPD %XMM2,%XMM5 |
(820) 0x44037d VFMADD213SD %XMM6,%XMM3,%XMM5 |
(820) 0x440382 VADDSD %XMM1,%XMM5,%XMM1 |
(820) 0x440386 VADDSD %XMM0,%XMM4,%XMM0 |
(820) 0x44038a VFMADD213SD %XMM6,%XMM3,%XMM2 |
(820) 0x44038f VADDSD %XMM0,%XMM2,%XMM0 |
(820) 0x440393 ADD $0x20,%RBX |
(820) 0x440397 DEC %R11 |
(820) 0x44039a JNE 4402e0 |
(819) 0x4403a0 MOV %R10,%R11 |
(819) 0x4403a3 AND $-0x4,%R11 |
(819) 0x4403a7 CMP %R10,%R11 |
(819) 0x4403aa JAE 4403f5 |
(819) 0x4403ac ADD %R11,%RDI |
(819) 0x4403af MOV -0x40(%RBP),%R11 |
(819) 0x4403b3 MOV -0x38(%RBP),%RBX |
(819) 0x4403b7 MOV -0x50(%RBP),%RAX |
(819) 0x4403bb MOV -0x58(%RBP),%R14 |
(819) 0x4403bf NOP |
(821) 0x4403c0 MOV (%RBX,%RDI,8),%R10 |
(821) 0x4403c4 VMOVSD (%R9,%RDI,8),%XMM2 |
(821) 0x4403ca VMULSD (%R8,%RDX,8),%XMM2,%XMM6 |
(821) 0x4403d0 MOV (%R15,%R10,8),%R10 |
(821) 0x4403d4 VADDSD (%R9,%R10,8),%XMM6,%XMM2 |
(821) 0x4403da VMOVSD %XMM2,(%R9,%R10,8) |
(821) 0x4403e0 VADDSD %XMM1,%XMM6,%XMM1 |
(821) 0x4403e4 VADDSD %XMM0,%XMM6,%XMM0 |
(821) 0x4403e8 INC %RDI |
(821) 0x4403eb CMP %RDI,%RSI |
(821) 0x4403ee JNE 4403c0 |
(819) 0x4403f0 JMP 4400a4 |
(819) 0x4403f5 MOV -0x40(%RBP),%R11 |
(819) 0x4403f9 MOV -0x38(%RBP),%RBX |
(819) 0x4403fd MOV -0x50(%RBP),%RAX |
(819) 0x440401 MOV -0x58(%RBP),%R14 |
(819) 0x440405 JMP 4400a4 |
0x44040a NOPW (%RAX,%RAX,1) |
(812) 0x440410 MOV -0x138(%RBP),%RAX |
(812) 0x440417 MOV -0x30(%RBP),%RDX |
(812) 0x44041b MOV (%RAX,%RDX,8),%RCX |
(812) 0x44041f MOV 0x8(%RAX,%RDX,8),%RDX |
(812) 0x440424 CMP %RDX,%RCX |
(812) 0x440427 JGE 440570 |
(812) 0x44042d MOV -0x80(%RBP),%RBX |
(812) 0x440431 MOV -0x78(%RBP),%RAX |
(812) 0x440435 JMP 440456 |
0x440437 NOPW (%RAX,%RAX,1) |
(817) 0x440440 VADDSD (%R14,%RCX,8),%XMM0,%XMM0 |
(817) 0x440446 INC %RCX |
(817) 0x440449 CMP %RDX,%RCX |
(817) 0x44044c MOV -0x48(%RBP),%R9 |
(817) 0x440450 JE 440574 |
(817) 0x440456 MOV -0x188(%RBP),%RSI |
(817) 0x44045d LEA (%RSI,%RCX,8),%RSI |
(817) 0x440461 TEST %R13,%R13 |
(817) 0x440464 JE 440474 |
(817) 0x440466 MOV (%RSI),%RSI |
(817) 0x440469 MOV -0x170(%RBP),%RDI |
(817) 0x440470 LEA (%RDI,%RSI,8),%RSI |
(817) 0x440474 MOV (%RSI),%RDI |
(817) 0x440477 TEST %RDI,%RDI |
(817) 0x44047a JS 440520 |
(817) 0x440480 MOV -0x70(%RBP),%RSI |
(817) 0x440484 MOV -0x30(%RBP),%R8 |
(817) 0x440488 CMP %R8,(%RSI,%RDI,8) |
(817) 0x44048c JNE 440520 |
(817) 0x440492 MOV -0x160(%RBP),%RSI |
(817) 0x440499 MOV 0x8(%RSI,%RDI,8),%RSI |
(817) 0x44049e TEST %RSI,%RSI |
(817) 0x4404a1 JLE 440446 |
(817) 0x4404a3 MOV -0x150(%RBP),%R8 |
(817) 0x4404aa MOV (%R8,%RDI,8),%RDI |
(817) 0x4404ae ADD %RDI,%RSI |
(817) 0x4404b1 MOV -0x158(%RBP),%R8 |
(817) 0x4404b8 MOV (%R8),%R8 |
(817) 0x4404bb MOV (%R9),%R9 |
(817) 0x4404be MOV (%R8,%R9,8),%R8 |
(817) 0x4404c2 NOPW %CS:(%RAX,%RAX,1) |
(818) 0x4404d0 MOV (%R8,%RDI,8),%R9 |
(818) 0x4404d4 VMOVSD (%R11,%RDI,8),%XMM2 |
(818) 0x4404da VMULSD (%R14,%RCX,8),%XMM2,%XMM6 |
(818) 0x4404e0 TEST %R9,%R9 |
(818) 0x4404e3 LEA (%R15,%R9,8),%R10 |
(818) 0x4404e7 NOT %R9 |
(818) 0x4404ea LEA (%R12,%R9,8),%R9 |
(818) 0x4404ee CMOVNS %R10,%R9 |
(818) 0x4404f2 MOV %RBX,%R10 |
(818) 0x4404f5 CMOVS %RAX,%R10 |
(818) 0x4404f9 MOV (%R10),%R10 |
(818) 0x4404fc MOV (%R9),%R9 |
(818) 0x4404ff VADDSD (%R10,%R9,8),%XMM6,%XMM2 |
(818) 0x440505 VMOVSD %XMM2,(%R10,%R9,8) |
(818) 0x44050b VADDSD %XMM1,%XMM6,%XMM1 |
(818) 0x44050f VADDSD %XMM0,%XMM6,%XMM0 |
(818) 0x440513 INC %RDI |
(818) 0x440516 CMP %RSI,%RDI |
(818) 0x440519 JL 4404d0 |
(817) 0x44051b JMP 440446 |
(817) 0x440520 MOV -0x178(%RBP),%RSI |
(817) 0x440527 CMPQ $-0x3,(%RSI,%RDI,8) |
(817) 0x44052c JE 440446 |
(817) 0x440532 CMPQ $0x1,-0xf0(%RBP) |
(817) 0x44053a JE 440440 |
(817) 0x440540 MOV -0x148(%RBP),%RSI |
(817) 0x440547 MOV (%RSI,%RDI,8),%RSI |
(817) 0x44054b MOV -0xd8(%RBP),%RDI |
(817) 0x440552 MOV -0x30(%RBP),%R8 |
(817) 0x440556 CMP (%RDI,%R8,8),%RSI |
(817) 0x44055a JE 440440 |
(817) 0x440560 JMP 440446 |
0x440565 NOPW %CS:(%RAX,%RAX,1) |
(812) 0x440570 MOV -0x80(%RBP),%RBX |
(812) 0x440574 MOV -0x120(%RBP),%RAX |
(812) 0x44057b MOV -0xa0(%RBP),%RCX |
(812) 0x440582 VMULSD (%RAX,%RCX,8),%XMM1,%XMM1 |
(812) 0x440587 VUCOMISD %XMM8,%XMM1 |
(812) 0x44058c JE 44059a |
(812) 0x44058e VXORPD 0xa873a(%RIP),%XMM0,%XMM0 |
(812) 0x440596 VDIVSD %XMM1,%XMM0,%XMM6 |
(812) 0x44059a MOV -0x68(%RBP),%RAX |
(812) 0x44059e MOV -0x30(%RBP),%RCX |
(812) 0x4405a2 MOV (%RAX,%RCX,8),%RSI |
(812) 0x4405a6 MOV 0x8(%RAX,%RCX,8),%RAX |
(812) 0x4405ab MOV %RAX,%RDI |
(812) 0x4405ae SUB %RSI,%RDI |
(812) 0x4405b1 JLE 440622 |
(812) 0x4405b3 MOV -0x78(%RBP),%RCX |
(812) 0x4405b7 MOV (%RCX),%RCX |
(812) 0x4405ba MOV %RDI,%RDX |
(812) 0x4405bd AND $-0x4,%RDX |
(812) 0x4405c1 JE 440600 |
(812) 0x4405c3 LEA -0x1(%RDX),%R8 |
(812) 0x4405c7 VBROADCASTSD %XMM6,%YMM0 |
(812) 0x4405cc LEA (%RCX,%RSI,8),%R9 |
(812) 0x4405d0 XOR %R10D,%R10D |
(812) 0x4405d3 NOPW %CS:(%RAX,%RAX,1) |
(816) 0x4405e0 VMULPD (%R9,%R10,8),%YMM0,%YMM1 |
(816) 0x4405e6 VMOVUPD %YMM1,(%R9,%R10,8) |
(816) 0x4405ec ADD $0x4,%R10 |
(816) 0x4405f0 CMP %R8,%R10 |
(816) 0x4405f3 JBE 4405e0 |
(812) 0x4405f5 CMP %RDX,%RDI |
(812) 0x4405f8 MOV -0x48(%RBP),%R9 |
(812) 0x4405fc JNE 440602 |
(812) 0x4405fe JMP 440622 |
(812) 0x440600 XOR %EDX,%EDX |
(812) 0x440602 ADD %RSI,%RDX |
(812) 0x440605 NOPW %CS:(%RAX,%RAX,1) |
(815) 0x440610 VMULSD (%RCX,%RDX,8),%XMM6,%XMM0 |
(815) 0x440615 VMOVSD %XMM0,(%RCX,%RDX,8) |
(815) 0x44061a INC %RDX |
(815) 0x44061d CMP %RDX,%RAX |
(815) 0x440620 JNE 440610 |
(812) 0x440622 MOV -0x60(%RBP),%RAX |
(812) 0x440626 MOV -0x30(%RBP),%RCX |
(812) 0x44062a MOV (%RAX,%RCX,8),%RSI |
(812) 0x44062e MOV 0x8(%RAX,%RCX,8),%RAX |
(812) 0x440633 MOV %RAX,%RDI |
(812) 0x440636 SUB %RSI,%RDI |
(812) 0x440639 JLE 43fbe0 |
(812) 0x44063f MOV (%RBX),%RCX |
(812) 0x440642 MOV %RDI,%RDX |
(812) 0x440645 AND $-0x4,%RDX |
(812) 0x440649 JE 440684 |
(812) 0x44064b LEA -0x1(%RDX),%R8 |
(812) 0x44064f VBROADCASTSD %XMM6,%YMM0 |
(812) 0x440654 LEA (%RCX,%RSI,8),%R9 |
(812) 0x440658 XOR %R10D,%R10D |
(812) 0x44065b NOPL (%RAX,%RAX,1) |
(814) 0x440660 VMULPD (%R9,%R10,8),%YMM0,%YMM1 |
(814) 0x440666 VMOVUPD %YMM1,(%R9,%R10,8) |
(814) 0x44066c ADD $0x4,%R10 |
(814) 0x440670 CMP %R8,%R10 |
(814) 0x440673 JBE 440660 |
(812) 0x440675 CMP %RDX,%RDI |
(812) 0x440678 MOV -0x48(%RBP),%R9 |
(812) 0x44067c JE 43fbe0 |
(812) 0x440682 JMP 440686 |
(812) 0x440684 XOR %EDX,%EDX |
(812) 0x440686 ADD %RSI,%RDX |
(812) 0x440689 NOPL (%RAX) |
(813) 0x440690 VMULSD (%RCX,%RDX,8),%XMM6,%XMM0 |
(813) 0x440695 VMOVSD %XMM0,(%RCX,%RDX,8) |
(813) 0x44069a INC %RDX |
(813) 0x44069d CMP %RDX,%RAX |
(813) 0x4406a0 JNE 440690 |
(812) 0x4406a2 JMP 43fbe0 |
0x4406a7 MOV -0x90(%RBP),%RDI |
0x4406ae VZEROUPPER |
0x4406b1 CALL 4cf830 <hypre_Free> |
0x4406b6 MOV -0x70(%RBP),%RDI |
0x4406ba CALL 4cf830 <hypre_Free> |
0x4406bf MOV %R12,%RDI |
0x4406c2 CALL 4cf830 <hypre_Free> |
0x4406c7 MOV %R15,%RDI |
0x4406ca ADD $0x178,%RSP |
0x4406d1 POP %RBX |
0x4406d2 POP %R12 |
0x4406d4 POP %R13 |
0x4406d6 POP %R14 |
0x4406d8 POP %R15 |
0x4406da POP %RBP |
0x4406db JMP 4cf830 |
Path / |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 206 |
nb uops | 224 |
loop length | 989 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 82 |
micro-operation queue | 37.33 cycles |
front end | 37.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.10 | 8.00 | 24.67 | 24.67 | 32.00 | 7.00 | 6.90 | 32.00 | 32.00 | 32.00 | 7.00 | 24.67 |
cycles | 7.10 | 11.40 | 24.67 | 24.67 | 32.00 | 7.00 | 6.90 | 32.00 | 32.00 | 32.00 | 7.00 | 24.67 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 35.54-35.60 |
Stall cycles | 0.00 |
Front-end | 37.33 |
Dispatch | 32.00 |
DIV/SQRT | 16.00 |
Overall L1 | 37.33 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x168(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x138(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x130(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x1a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x170(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x160(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x158(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x140(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x148(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x150(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x198(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x190(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x188(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x138(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x180(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43fa4d <hypre_BoomerAMGBuildMultipass.extracted.28+0x1ed> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
JMP 43fa4f <hypre_BoomerAMGBuildMultipass.extracted.28+0x1ef> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43fa6e <hypre_BoomerAMGBuildMultipass.extracted.28+0x20e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43fa76 <hypre_BoomerAMGBuildMultipass.extracted.28+0x216> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOVQ $0,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43fa8e <hypre_BoomerAMGBuildMultipass.extracted.28+0x22e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 43fa91 <hypre_BoomerAMGBuildMultipass.extracted.28+0x231> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %R13,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,(%R14) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x90(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 43fad0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%RBX) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 43faf0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x290> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4d1410 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4d1400 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RDX,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 43fb2f <hypre_BoomerAMGBuildMultipass.extracted.28+0x2cf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 43fb35 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2d5> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x40(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RBX,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%RBX),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RSI,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4406a7 <hypre_BoomerAMGBuildMultipass.extracted.28+0xe47> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,-0xd0(%RBP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x18(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fbf7 <hypre_BoomerAMGBuildMultipass.extracted.28+0x397> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x90(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4cf830 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 206 |
nb uops | 224 |
loop length | 989 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 82 |
micro-operation queue | 37.33 cycles |
front end | 37.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.10 | 8.00 | 24.67 | 24.67 | 32.00 | 7.00 | 6.90 | 32.00 | 32.00 | 32.00 | 7.00 | 24.67 |
cycles | 7.10 | 11.40 | 24.67 | 24.67 | 32.00 | 7.00 | 6.90 | 32.00 | 32.00 | 32.00 | 7.00 | 24.67 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 35.54-35.60 |
Stall cycles | 0.00 |
Front-end | 37.33 |
Dispatch | 32.00 |
DIV/SQRT | 16.00 |
Overall L1 | 37.33 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x168(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x138(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x130(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x1a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x170(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x160(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x158(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x140(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x148(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x150(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x198(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x190(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x188(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x138(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x180(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43fa4d <hypre_BoomerAMGBuildMultipass.extracted.28+0x1ed> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
JMP 43fa4f <hypre_BoomerAMGBuildMultipass.extracted.28+0x1ef> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43fa6e <hypre_BoomerAMGBuildMultipass.extracted.28+0x20e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43fa76 <hypre_BoomerAMGBuildMultipass.extracted.28+0x216> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOVQ $0,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43fa8e <hypre_BoomerAMGBuildMultipass.extracted.28+0x22e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 43fa91 <hypre_BoomerAMGBuildMultipass.extracted.28+0x231> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %R13,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,(%R14) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x90(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 43fad0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%RBX) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 43faf0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x290> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4d1410 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4d1400 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RDX,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 43fb2f <hypre_BoomerAMGBuildMultipass.extracted.28+0x2cf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 43fb35 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2d5> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x40(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RBX,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%RBX),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RSI,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4406a7 <hypre_BoomerAMGBuildMultipass.extracted.28+0xe47> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,-0xd0(%RBP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x18(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fbf7 <hypre_BoomerAMGBuildMultipass.extracted.28+0x397> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x90(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x70(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4cf830 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass.extracted.28– | 1.8 | 0.75 |
○Loop 833 - par_multi_interp.c:1760-1761 - exec | 0.19 | 0.07 |
▼Loop 812 - par_multi_interp.c:1747-1876 - exec– | 0.18 | 0.07 |
▼Loop 819 - par_multi_interp.c:1747-1837 - exec– | 0.61 | 0.22 |
○Loop 823 - par_multi_interp.c:1816-1822 - exec | 0.34 | 0.12 |
○Loop 820 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 822 - par_multi_interp.c:1816-1822 - exec | 0 | 0 |
○Loop 821 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 825 - par_multi_interp.c:1799-1803 - exec | 0.42 | 0.15 |
○Loop 829 - par_multi_interp.c:1782-1787 - exec | 0.04 | 0.02 |
○Loop 814 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
○Loop 815 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |
○Loop 816 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |
○Loop 813 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
▼Loop 817 - par_multi_interp.c:1836-1867 - exec– | 0 | 0 |
○Loop 818 - par_multi_interp.c:1851-1860 - exec | 0 | 0 |
○Loop 826 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 830 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |
○Loop 831 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |
○Loop 824 - par_multi_interp.c:1805-1809 - exec | 0 | 0.01 |
○Loop 828 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 827 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 832 - par_multi_interp.c:1762-1763 - exec | 0 | 0 |