Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.5% |
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Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.5% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
[...] |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x43f0a0 PUSH %RBP |
0x43f0a1 MOV %RSP,%RBP |
0x43f0a4 PUSH %R15 |
0x43f0a6 PUSH %R14 |
0x43f0a8 PUSH %R13 |
0x43f0aa PUSH %R12 |
0x43f0ac PUSH %RBX |
0x43f0ad SUB $0xf8,%RSP |
0x43f0b4 MOV %R9,%RBX |
0x43f0b7 MOV %R8,-0x90(%RBP) |
0x43f0be MOV %RCX,-0x98(%RBP) |
0x43f0c5 MOV %RDX,-0xe0(%RBP) |
0x43f0cc MOV 0xe8(%RBP),%RAX |
0x43f0d3 MOV %RAX,-0x38(%RBP) |
0x43f0d7 MOV 0xe0(%RBP),%RAX |
0x43f0de MOV %RAX,-0xd8(%RBP) |
0x43f0e5 MOV 0xd8(%RBP),%RCX |
0x43f0ec MOV 0xd0(%RBP),%RAX |
0x43f0f3 MOV %RAX,-0x118(%RBP) |
0x43f0fa MOV 0xc8(%RBP),%RAX |
0x43f101 MOV %RAX,-0x110(%RBP) |
0x43f108 MOV 0xc0(%RBP),%RAX |
0x43f10f MOV %RAX,-0xd0(%RBP) |
0x43f116 MOV 0xb8(%RBP),%RAX |
0x43f11d MOV %RAX,-0xc8(%RBP) |
0x43f124 MOV 0xb0(%RBP),%RAX |
0x43f12b MOV %RAX,-0xa0(%RBP) |
0x43f132 MOV 0xa8(%RBP),%RAX |
0x43f139 MOV %RAX,-0xf0(%RBP) |
0x43f140 MOV 0xa0(%RBP),%RAX |
0x43f147 MOV %RAX,-0x30(%RBP) |
0x43f14b MOV 0x98(%RBP),%RAX |
0x43f152 MOV %RAX,-0x58(%RBP) |
0x43f156 MOV 0x90(%RBP),%RAX |
0x43f15d MOV %RAX,-0xc0(%RBP) |
0x43f164 MOV 0x88(%RBP),%RAX |
0x43f16b MOV %RAX,-0xb8(%RBP) |
0x43f172 MOV 0x80(%RBP),%RAX |
0x43f179 MOV %RAX,-0xf8(%RBP) |
0x43f180 MOV 0x78(%RBP),%RAX |
0x43f184 MOV %RAX,-0x120(%RBP) |
0x43f18b MOV 0x70(%RBP),%RAX |
0x43f18f MOV %RAX,-0x108(%RBP) |
0x43f196 MOV 0x68(%RBP),%RAX |
0x43f19a MOV %RAX,-0x40(%RBP) |
0x43f19e MOV 0x60(%RBP),%RAX |
0x43f1a2 MOV %RAX,-0x80(%RBP) |
0x43f1a6 MOV 0x58(%RBP),%RAX |
0x43f1aa MOV %RAX,-0x100(%RBP) |
0x43f1b1 MOV 0x50(%RBP),%RAX |
0x43f1b5 MOV %RAX,-0x48(%RBP) |
0x43f1b9 MOV 0x48(%RBP),%RAX |
0x43f1bd MOV %RAX,-0x78(%RBP) |
0x43f1c1 MOV 0x40(%RBP),%RDX |
0x43f1c5 MOV 0x38(%RBP),%RAX |
0x43f1c9 MOV %RAX,-0xb0(%RBP) |
0x43f1d0 MOV 0x30(%RBP),%RAX |
0x43f1d4 MOV %RAX,-0x88(%RBP) |
0x43f1db MOV 0x28(%RBP),%R12 |
0x43f1df MOV 0x20(%RBP),%RAX |
0x43f1e3 MOV %RAX,-0x50(%RBP) |
0x43f1e7 MOV 0x18(%RBP),%RAX |
0x43f1eb MOV %RAX,-0x60(%RBP) |
0x43f1ef MOV 0x10(%RBP),%RAX |
0x43f1f3 MOV %RAX,-0x68(%RBP) |
0x43f1f7 MOV %RCX,%R15 |
0x43f1fa MOV (%RCX),%RDI |
0x43f1fd TEST %RDI,%RDI |
0x43f200 JE 43f217 |
0x43f202 MOV $0x8,%ESI |
0x43f207 MOV %RDX,%R14 |
0x43f20a CALL 4cf760 <hypre_CAlloc> |
0x43f20f MOV %R14,%RDX |
0x43f212 MOV %RAX,%R13 |
0x43f215 JMP 43f21a |
0x43f217 XOR %R13D,%R13D |
0x43f21a MOV (%RDX),%RDI |
0x43f21d TEST %RDI,%RDI |
0x43f220 JE 43f23d |
0x43f222 MOV $0x8,%ESI |
0x43f227 MOV %RDX,%R14 |
0x43f22a CALL 4cf760 <hypre_CAlloc> |
0x43f22f MOV %R14,%RDX |
0x43f232 MOV %RAX,%R14 |
0x43f235 CMPQ $0,(%R15) |
0x43f239 JG 43f246 |
0x43f23b JMP 43f261 |
0x43f23d XOR %R14D,%R14D |
0x43f240 CMPQ $0,(%R15) |
0x43f244 JLE 43f261 |
0x43f246 XOR %EAX,%EAX |
0x43f248 NOPL (%RAX,%RAX,1) |
(811) 0x43f250 MOVQ $-0x1,(%R13,%RAX,8) |
(811) 0x43f259 INC %RAX |
(811) 0x43f25c CMP (%R15),%RAX |
(811) 0x43f25f JL 43f250 |
0x43f261 CMPQ $0,(%RDX) |
0x43f265 JLE 43f280 |
0x43f267 XOR %EAX,%EAX |
0x43f269 NOPL (%RAX) |
(810) 0x43f270 MOVQ $-0x1,(%R14,%RAX,8) |
(810) 0x43f278 INC %RAX |
(810) 0x43f27b CMP (%RDX),%RAX |
(810) 0x43f27e JL 43f270 |
0x43f280 CALL 4d1410 <hypre_GetThreadNum> |
0x43f285 MOV %RAX,%R15 |
0x43f288 CALL 4d1400 <hypre_NumActiveThreads> |
0x43f28d MOV %RAX,%RCX |
0x43f290 MOV -0x30(%RBP),%RAX |
0x43f294 MOV (%RAX),%RAX |
0x43f297 MOV 0x8(%RAX),%RDI |
0x43f29b MOV -0x38(%RBP),%RAX |
0x43f29f MOV (%RAX),%RSI |
0x43f2a2 MOV %RSI,%RAX |
0x43f2a5 OR %RCX,%RAX |
0x43f2a8 SHR $0x20,%RAX |
0x43f2ac JE 43f2b8 |
0x43f2ae MOV %RSI,%RAX |
0x43f2b1 CQTO |
0x43f2b3 IDIV %RCX |
0x43f2b6 JMP 43f2be |
0x43f2b8 MOV %ESI,%EAX |
0x43f2ba XOR %EDX,%EDX |
0x43f2bc DIV %ECX |
0x43f2be MOV -0x50(%RBP),%R8 |
0x43f2c2 MOV %RAX,%R11 |
0x43f2c5 IMUL %R15,%R11 |
0x43f2c9 DEC %RCX |
0x43f2cc LEA 0x1(%R15),%RDX |
0x43f2d0 IMUL %RAX,%RDX |
0x43f2d4 CMP %RCX,%R15 |
0x43f2d7 CMOVE %RSI,%RDX |
0x43f2db MOV %RDX,-0x70(%RBP) |
0x43f2df CMP %RDX,%R11 |
0x43f2e2 JGE 43f837 |
0x43f2e8 ADD %RDI,-0x70(%RBP) |
0x43f2ec ADD %RDI,%R11 |
0x43f2ef MOV -0x58(%RBP),%RAX |
0x43f2f3 MOV (%RAX),%RAX |
0x43f2f6 MOV %RAX,-0xe8(%RBP) |
0x43f2fd MOV -0x48(%RBP),%RAX |
0x43f301 MOV (%RAX),%RAX |
0x43f304 MOV %RAX,-0x38(%RBP) |
0x43f308 MOV -0xa0(%RBP),%RAX |
0x43f30f MOV (%RAX),%RAX |
0x43f312 MOV %RAX,-0x48(%RBP) |
0x43f316 MOV -0x40(%RBP),%RAX |
0x43f31a MOV (%RAX),%RAX |
0x43f31d MOV %RAX,-0x30(%RBP) |
0x43f321 MOV -0x68(%RBP),%RAX |
0x43f325 MOV (%RAX),%RAX |
0x43f328 MOV %RAX,-0x40(%RBP) |
0x43f32c VXORPD %XMM0,%XMM0,%XMM0 |
0x43f330 VMOVDDUP 0xab350(%RIP),%XMM1 |
0x43f338 MOV %RBX,-0xa8(%RBP) |
0x43f33f JMP 43f361 |
0x43f341 NOPW %CS:(%RAX,%RAX,1) |
(799) 0x43f350 INC %R11 |
(799) 0x43f353 CMP -0x70(%RBP),%R11 |
(799) 0x43f357 MOV -0x50(%RBP),%R8 |
(799) 0x43f35b JGE 43f837 |
(799) 0x43f361 MOV %R11,-0x58(%RBP) |
(799) 0x43f365 MOV -0xe8(%RBP),%RAX |
(799) 0x43f36c MOV (%RAX,%R11,8),%R10 |
(799) 0x43f370 MOV -0xf0(%RBP),%RAX |
(799) 0x43f377 MOV (%RAX,%R10,8),%RDI |
(799) 0x43f37b MOV -0x38(%RBP),%RAX |
(799) 0x43f37f MOV (%RAX,%R10,8),%RCX |
(799) 0x43f383 MOV 0x8(%RAX,%R10,8),%RAX |
(799) 0x43f388 LEA (%RAX,%RDI,1),%RDX |
(799) 0x43f38c SUB %RCX,%RDX |
(799) 0x43f38f CMP %RDX,%RDI |
(799) 0x43f392 JGE 43f465 |
(799) 0x43f398 MOV -0xc8(%RBP),%RDX |
(799) 0x43f39f MOV (%RDX),%RDX |
(799) 0x43f3a2 MOV 0x8(%RDX),%R9 |
(799) 0x43f3a6 MOV -0xb8(%RBP),%RDX |
(799) 0x43f3ad MOV (%RDX),%RSI |
(799) 0x43f3b0 SUB %RCX,%RAX |
(799) 0x43f3b3 CMP $0x8,%RAX |
(799) 0x43f3b7 JB 43f440 |
(799) 0x43f3bd MOV %RAX,%R11 |
(799) 0x43f3c0 SHR $0x3,%R11 |
(799) 0x43f3c4 LEA (%R9,%RDI,8),%RCX |
(799) 0x43f3c8 ADD $0x38,%RCX |
(799) 0x43f3cc NOPL (%RAX) |
(809) 0x43f3d0 MOV -0x38(%RCX),%RDX |
(809) 0x43f3d4 MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f3d8 MOV %R10,(%R13,%RDX,8) |
(809) 0x43f3dd MOV -0x30(%RCX),%RDX |
(809) 0x43f3e1 MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f3e5 MOV %R10,(%R13,%RDX,8) |
(809) 0x43f3ea MOV -0x28(%RCX),%RDX |
(809) 0x43f3ee MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f3f2 MOV %R10,(%R13,%RDX,8) |
(809) 0x43f3f7 MOV -0x20(%RCX),%RDX |
(809) 0x43f3fb MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f3ff MOV %R10,(%R13,%RDX,8) |
(809) 0x43f404 MOV -0x18(%RCX),%RDX |
(809) 0x43f408 MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f40c MOV %R10,(%R13,%RDX,8) |
(809) 0x43f411 MOV -0x10(%RCX),%RDX |
(809) 0x43f415 MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f419 MOV %R10,(%R13,%RDX,8) |
(809) 0x43f41e MOV -0x8(%RCX),%RDX |
(809) 0x43f422 MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f426 MOV %R10,(%R13,%RDX,8) |
(809) 0x43f42b MOV (%RCX),%RDX |
(809) 0x43f42e MOV (%RSI,%RDX,8),%RDX |
(809) 0x43f432 MOV %R10,(%R13,%RDX,8) |
(809) 0x43f437 ADD $0x40,%RCX |
(809) 0x43f43b DEC %R11 |
(809) 0x43f43e JNE 43f3d0 |
(799) 0x43f440 MOV %RAX,%RCX |
(799) 0x43f443 AND $-0x8,%RCX |
(799) 0x43f447 CMP %RAX,%RCX |
(799) 0x43f44a JAE 43f465 |
(799) 0x43f44c LEA (%R9,%RDI,8),%RDI |
(808) 0x43f450 MOV (%RDI,%RCX,8),%RDX |
(808) 0x43f454 MOV (%RSI,%RDX,8),%RDX |
(808) 0x43f458 MOV %R10,(%R13,%RDX,8) |
(808) 0x43f45d INC %RCX |
(808) 0x43f460 CMP %RCX,%RAX |
(808) 0x43f463 JNE 43f450 |
(799) 0x43f465 MOV -0x38(%RBP),%RAX |
(799) 0x43f469 MOV (%RAX,%R10,8),%R11 |
(799) 0x43f46d MOV -0x60(%RBP),%RCX |
(799) 0x43f471 MOV (%RCX,%R10,8),%RAX |
(799) 0x43f475 MOV 0x8(%RCX,%R10,8),%RSI |
(799) 0x43f47a INC %RAX |
(799) 0x43f47d VXORPD %XMM4,%XMM4,%XMM4 |
(799) 0x43f481 VXORPD %XMM3,%XMM3,%XMM3 |
(799) 0x43f485 CMP %RSI,%RAX |
(799) 0x43f488 JGE 43f530 |
(799) 0x43f48e MOV -0xe0(%RBP),%RDI |
(799) 0x43f495 MOV -0xd8(%RBP),%R9 |
(799) 0x43f49c JMP 43f4ac |
0x43f49e XCHG %AX,%AX |
(807) 0x43f4a0 INC %RAX |
(807) 0x43f4a3 CMP %RSI,%RAX |
(807) 0x43f4a6 JGE 43f530 |
(807) 0x43f4ac MOV (%R8,%RAX,8),%RCX |
(807) 0x43f4b0 CMPQ $-0x3,(%RDI,%RCX,8) |
(807) 0x43f4b5 JE 43f4de |
(807) 0x43f4b7 CMPQ $0x1,-0x98(%RBP) |
(807) 0x43f4bf JE 43f4d2 |
(807) 0x43f4c1 MOV -0x90(%RBP),%R15 |
(807) 0x43f4c8 MOV (%R15,%R10,8),%RDX |
(807) 0x43f4cc CMP (%R15,%RCX,8),%RDX |
(807) 0x43f4d0 JNE 43f4de |
(807) 0x43f4d2 MOV -0x68(%RBP),%RDX |
(807) 0x43f4d6 MOV (%RDX),%RDX |
(807) 0x43f4d9 VADDSD (%RDX,%RAX,8),%XMM3,%XMM3 |
(807) 0x43f4de CMP $-0x1,%RCX |
(807) 0x43f4e2 JE 43f4a0 |
(807) 0x43f4e4 CMP %R10,(%R13,%RCX,8) |
(807) 0x43f4e9 JNE 43f4a0 |
(807) 0x43f4eb MOV -0x68(%RBP),%RDX |
(807) 0x43f4ef MOV (%RDX),%RDX |
(807) 0x43f4f2 VMOVSD (%RDX,%RAX,8),%XMM5 |
(807) 0x43f4f7 MOV -0x78(%RBP),%RSI |
(807) 0x43f4fb MOV (%RSI),%RSI |
(807) 0x43f4fe VMOVSD %XMM5,(%RSI,%R11,8) |
(807) 0x43f504 MOV (%R9,%RCX,8),%RCX |
(807) 0x43f508 MOV -0x100(%RBP),%RSI |
(807) 0x43f50f MOV %RCX,(%RSI,%R11,8) |
(807) 0x43f513 INC %R11 |
(807) 0x43f516 VADDSD (%RDX,%RAX,8),%XMM4,%XMM4 |
(807) 0x43f51b MOV -0x60(%RBP),%RCX |
(807) 0x43f51f MOV 0x8(%RCX,%R10,8),%RSI |
(807) 0x43f524 JMP 43f4a0 |
0x43f529 NOPL (%RAX) |
(799) 0x43f530 MOV -0x48(%RBP),%RAX |
(799) 0x43f534 MOV (%RAX,%R10,8),%RDI |
(799) 0x43f538 MOV -0x30(%RBP),%RCX |
(799) 0x43f53c MOV (%RCX,%R10,8),%RAX |
(799) 0x43f540 MOV 0x8(%RCX,%R10,8),%RCX |
(799) 0x43f545 LEA (%RCX,%RDI,1),%RDX |
(799) 0x43f549 SUB %RAX,%RDX |
(799) 0x43f54c CMP %RDX,%RDI |
(799) 0x43f54f JGE 43f624 |
(799) 0x43f555 MOV -0xd0(%RBP),%RDX |
(799) 0x43f55c MOV (%RDX),%RDX |
(799) 0x43f55f MOV 0x8(%RDX),%R9 |
(799) 0x43f563 MOV -0xc0(%RBP),%RDX |
(799) 0x43f56a MOV (%RDX),%RSI |
(799) 0x43f56d SUB %RAX,%RCX |
(799) 0x43f570 CMP $0x8,%RCX |
(799) 0x43f574 JB 43f5f8 |
(799) 0x43f57a MOV %RCX,%RAX |
(799) 0x43f57d SHR $0x3,%RAX |
(799) 0x43f581 LEA (%R9,%RDI,8),%R8 |
(799) 0x43f585 ADD $0x38,%R8 |
(799) 0x43f589 NOPL (%RAX) |
(806) 0x43f590 MOV -0x38(%R8),%RDX |
(806) 0x43f594 MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f598 MOV %R10,(%R14,%RDX,8) |
(806) 0x43f59c MOV -0x30(%R8),%RDX |
(806) 0x43f5a0 MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5a4 MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5a8 MOV -0x28(%R8),%RDX |
(806) 0x43f5ac MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5b0 MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5b4 MOV -0x20(%R8),%RDX |
(806) 0x43f5b8 MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5bc MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5c0 MOV -0x18(%R8),%RDX |
(806) 0x43f5c4 MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5c8 MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5cc MOV -0x10(%R8),%RDX |
(806) 0x43f5d0 MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5d4 MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5d8 MOV -0x8(%R8),%RDX |
(806) 0x43f5dc MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5e0 MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5e4 MOV (%R8),%RDX |
(806) 0x43f5e7 MOV (%RSI,%RDX,8),%RDX |
(806) 0x43f5eb MOV %R10,(%R14,%RDX,8) |
(806) 0x43f5ef ADD $0x40,%R8 |
(806) 0x43f5f3 DEC %RAX |
(806) 0x43f5f6 JNE 43f590 |
(799) 0x43f5f8 MOV %RCX,%RAX |
(799) 0x43f5fb AND $-0x8,%RAX |
(799) 0x43f5ff CMP %RCX,%RAX |
(799) 0x43f602 JAE 43f624 |
(799) 0x43f604 LEA (%R9,%RDI,8),%RDI |
(799) 0x43f608 NOPL (%RAX,%RAX,1) |
(805) 0x43f610 MOV (%RDI,%RAX,8),%RDX |
(805) 0x43f614 MOV (%RSI,%RDX,8),%RDX |
(805) 0x43f618 MOV %R10,(%R14,%RDX,8) |
(805) 0x43f61c INC %RAX |
(805) 0x43f61f CMP %RAX,%RCX |
(805) 0x43f622 JNE 43f610 |
(799) 0x43f624 MOV -0x30(%RBP),%RAX |
(799) 0x43f628 MOV (%RAX,%R10,8),%RAX |
(799) 0x43f62c MOV -0x88(%RBP),%RCX |
(799) 0x43f633 MOV (%RCX,%R10,8),%RSI |
(799) 0x43f637 MOV 0x8(%RCX,%R10,8),%RDI |
(799) 0x43f63c CMP %RDI,%RSI |
(799) 0x43f63f JGE 43f720 |
(799) 0x43f645 MOV -0xb0(%RBP),%RCX |
(799) 0x43f64c LEA (%RCX,%RSI,8),%R9 |
(799) 0x43f650 JMP 43f670 |
0x43f652 NOPW %CS:(%RAX,%RAX,1) |
(804) 0x43f660 INC %RSI |
(804) 0x43f663 ADD $0x8,%R9 |
(804) 0x43f667 CMP %RDI,%RSI |
(804) 0x43f66a JGE 43f720 |
(804) 0x43f670 MOV %R9,%RCX |
(804) 0x43f673 TEST %RBX,%RBX |
(804) 0x43f676 JE 43f686 |
(804) 0x43f678 MOV (%R9),%RCX |
(804) 0x43f67b MOV -0x118(%RBP),%RDX |
(804) 0x43f682 LEA (%RDX,%RCX,8),%RCX |
(804) 0x43f686 MOV (%RCX),%RCX |
(804) 0x43f689 MOV -0x120(%RBP),%RDX |
(804) 0x43f690 CMPQ $-0x3,(%RDX,%RCX,8) |
(804) 0x43f695 JE 43f6c8 |
(804) 0x43f697 CMPQ $0x1,-0x98(%RBP) |
(804) 0x43f69f JE 43f6c2 |
(804) 0x43f6a1 MOV -0x90(%RBP),%RDX |
(804) 0x43f6a8 MOV (%RDX,%R10,8),%RDX |
(804) 0x43f6ac MOV %RBX,%R8 |
(804) 0x43f6af MOV %R12,%RBX |
(804) 0x43f6b2 MOV -0xf8(%RBP),%R15 |
(804) 0x43f6b9 CMP (%R15,%RCX,8),%RDX |
(804) 0x43f6bd MOV %R8,%RBX |
(804) 0x43f6c0 JNE 43f6c8 |
(804) 0x43f6c2 VADDSD (%R12,%RSI,8),%XMM3,%XMM3 |
(804) 0x43f6c8 CMP $-0x1,%RCX |
(804) 0x43f6cc JE 43f660 |
(804) 0x43f6ce CMP %R10,(%R14,%RCX,8) |
(804) 0x43f6d2 JNE 43f660 |
(804) 0x43f6d4 VMOVSD (%R12,%RSI,8),%XMM5 |
(804) 0x43f6da MOV -0x80(%RBP),%RDX |
(804) 0x43f6de MOV (%RDX),%RDX |
(804) 0x43f6e1 VMOVSD %XMM5,(%RDX,%RAX,8) |
(804) 0x43f6e6 MOV -0x110(%RBP),%RDX |
(804) 0x43f6ed MOV (%RDX,%RCX,8),%RCX |
(804) 0x43f6f1 MOV -0x108(%RBP),%RDX |
(804) 0x43f6f8 MOV %RCX,(%RDX,%RAX,8) |
(804) 0x43f6fc INC %RAX |
(804) 0x43f6ff VADDSD (%R12,%RSI,8),%XMM4,%XMM4 |
(804) 0x43f705 MOV -0x88(%RBP),%RCX |
(804) 0x43f70c MOV 0x8(%RCX,%R10,8),%RDI |
(804) 0x43f711 JMP 43f660 |
0x43f716 NOPW %CS:(%RAX,%RAX,1) |
(799) 0x43f720 MOV -0x60(%RBP),%RCX |
(799) 0x43f724 MOV (%RCX,%R10,8),%RCX |
(799) 0x43f728 MOV -0x40(%RBP),%RDX |
(799) 0x43f72c VMULSD (%RDX,%RCX,8),%XMM4,%XMM4 |
(799) 0x43f731 VUCOMISD %XMM0,%XMM4 |
(799) 0x43f735 JE 43f73f |
(799) 0x43f737 VXORPD %XMM1,%XMM3,%XMM2 |
(799) 0x43f73b VDIVSD %XMM4,%XMM2,%XMM2 |
(799) 0x43f73f MOV -0x38(%RBP),%RCX |
(799) 0x43f743 MOV (%RCX,%R10,8),%RCX |
(799) 0x43f747 MOV %R11,%R8 |
(799) 0x43f74a SUB %RCX,%R8 |
(799) 0x43f74d JLE 43f7b2 |
(799) 0x43f74f MOV -0x78(%RBP),%RDX |
(799) 0x43f753 MOV (%RDX),%RSI |
(799) 0x43f756 MOV %R8,%RDI |
(799) 0x43f759 AND $-0x4,%RDI |
(799) 0x43f75d JE 43f791 |
(799) 0x43f75f LEA -0x1(%RDI),%R9 |
(799) 0x43f763 VBROADCASTSD %XMM2,%YMM3 |
(799) 0x43f768 LEA (%RSI,%RCX,8),%RDX |
(799) 0x43f76c XOR %EBX,%EBX |
(799) 0x43f76e XCHG %AX,%AX |
(803) 0x43f770 VMULPD (%RDX,%RBX,8),%YMM3,%YMM4 |
(803) 0x43f775 VMOVUPD %YMM4,(%RDX,%RBX,8) |
(803) 0x43f77a ADD $0x4,%RBX |
(803) 0x43f77e CMP %R9,%RBX |
(803) 0x43f781 JBE 43f770 |
(799) 0x43f783 CMP %RDI,%R8 |
(799) 0x43f786 MOV -0xa8(%RBP),%RBX |
(799) 0x43f78d JNE 43f793 |
(799) 0x43f78f JMP 43f7b2 |
(799) 0x43f791 XOR %EDI,%EDI |
(799) 0x43f793 ADD %RCX,%RDI |
(799) 0x43f796 NOPW %CS:(%RAX,%RAX,1) |
(802) 0x43f7a0 VMULSD (%RSI,%RDI,8),%XMM2,%XMM3 |
(802) 0x43f7a5 VMOVSD %XMM3,(%RSI,%RDI,8) |
(802) 0x43f7aa INC %RDI |
(802) 0x43f7ad CMP %RDI,%R11 |
(802) 0x43f7b0 JNE 43f7a0 |
(799) 0x43f7b2 MOV -0x30(%RBP),%RCX |
(799) 0x43f7b6 MOV (%RCX,%R10,8),%RCX |
(799) 0x43f7ba MOV %RAX,%R8 |
(799) 0x43f7bd SUB %RCX,%R8 |
(799) 0x43f7c0 MOV -0x58(%RBP),%R11 |
(799) 0x43f7c4 JLE 43f350 |
(799) 0x43f7ca MOV -0x80(%RBP),%RDX |
(799) 0x43f7ce MOV (%RDX),%RSI |
(799) 0x43f7d1 MOV %R8,%RDI |
(799) 0x43f7d4 AND $-0x4,%RDI |
(799) 0x43f7d8 JE 43f810 |
(799) 0x43f7da LEA -0x1(%RDI),%R9 |
(799) 0x43f7de VBROADCASTSD %XMM2,%YMM3 |
(799) 0x43f7e3 LEA (%RSI,%RCX,8),%RDX |
(799) 0x43f7e7 XOR %R10D,%R10D |
(799) 0x43f7ea NOPW (%RAX,%RAX,1) |
(801) 0x43f7f0 VMULPD (%RDX,%R10,8),%YMM3,%YMM4 |
(801) 0x43f7f6 VMOVUPD %YMM4,(%RDX,%R10,8) |
(801) 0x43f7fc ADD $0x4,%R10 |
(801) 0x43f800 CMP %R9,%R10 |
(801) 0x43f803 JBE 43f7f0 |
(799) 0x43f805 CMP %RDI,%R8 |
(799) 0x43f808 JE 43f350 |
(799) 0x43f80e JMP 43f812 |
(799) 0x43f810 XOR %EDI,%EDI |
(799) 0x43f812 ADD %RCX,%RDI |
(799) 0x43f815 NOPW %CS:(%RAX,%RAX,1) |
(800) 0x43f820 VMULSD (%RSI,%RDI,8),%XMM2,%XMM3 |
(800) 0x43f825 VMOVSD %XMM3,(%RSI,%RDI,8) |
(800) 0x43f82a INC %RDI |
(800) 0x43f82d CMP %RDI,%RAX |
(800) 0x43f830 JNE 43f820 |
(799) 0x43f832 JMP 43f350 |
0x43f837 MOV %R13,%RDI |
0x43f83a VZEROUPPER |
0x43f83d CALL 4cf830 <hypre_Free> |
0x43f842 MOV %R14,%RDI |
0x43f845 ADD $0xf8,%RSP |
0x43f84c POP %RBX |
0x43f84d POP %R12 |
0x43f84f POP %R13 |
0x43f851 POP %R14 |
0x43f853 POP %R15 |
0x43f855 POP %RBP |
0x43f856 JMP 4cf830 |
0x43f85b NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 166 |
nb uops | 180 |
loop length | 729 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 59 |
micro-operation queue | 30.00 cycles |
front end | 30.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.00 | 8.00 | 19.00 | 19.00 | 23.50 | 6.00 | 6.00 | 23.50 | 23.50 | 23.50 | 6.00 | 19.00 |
cycles | 6.00 | 10.80 | 19.00 | 19.00 | 23.50 | 6.00 | 6.00 | 23.50 | 23.50 | 23.50 | 6.00 | 19.00 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 28.88-28.92 |
Stall cycles | 0.00 |
Front-end | 30.00 |
Dispatch | 23.50 |
DIV/SQRT | 16.00 |
Overall L1 | 30.00 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0xf8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%RCX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43f217 <hypre_BoomerAMGBuildMultipass.extracted.27+0x177> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 43f21a <hypre_BoomerAMGBuildMultipass.extracted.27+0x17a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43f23d <hypre_BoomerAMGBuildMultipass.extracted.27+0x19d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,(%R15) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 43f246 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 43f261 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%R15) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 43f261 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%RDX) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 43f280 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4d1410 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4d1400 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 43f2b8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x218> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 43f2be <hypre_BoomerAMGBuildMultipass.extracted.27+0x21e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x50(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R15),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RDX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f837 <hypre_BoomerAMGBuildMultipass.extracted.27+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,-0x70(%RBP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %RDI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0xab350(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43f361 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2c1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0xf8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4cf830 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 166 |
nb uops | 180 |
loop length | 729 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 59 |
micro-operation queue | 30.00 cycles |
front end | 30.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.00 | 8.00 | 19.00 | 19.00 | 23.50 | 6.00 | 6.00 | 23.50 | 23.50 | 23.50 | 6.00 | 19.00 |
cycles | 6.00 | 10.80 | 19.00 | 19.00 | 23.50 | 6.00 | 6.00 | 23.50 | 23.50 | 23.50 | 6.00 | 19.00 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 28.88-28.92 |
Stall cycles | 0.00 |
Front-end | 30.00 |
Dispatch | 23.50 |
DIV/SQRT | 16.00 |
Overall L1 | 30.00 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0xf8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%RCX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43f217 <hypre_BoomerAMGBuildMultipass.extracted.27+0x177> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 43f21a <hypre_BoomerAMGBuildMultipass.extracted.27+0x17a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 43f23d <hypre_BoomerAMGBuildMultipass.extracted.27+0x19d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4cf760 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,(%R15) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 43f246 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 43f261 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%R15) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 43f261 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%RDX) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 43f280 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 4d1410 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4d1400 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 43f2b8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x218> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 43f2be <hypre_BoomerAMGBuildMultipass.extracted.27+0x21e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x50(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R15),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RDX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f837 <hypre_BoomerAMGBuildMultipass.extracted.27+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,-0x70(%RBP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %RDI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0xab350(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43f361 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2c1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4cf830 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0xf8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4cf830 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass.extracted.27– | 0.5 | 0.21 |
○Loop 811 - par_multi_interp.c:1590-1591 - exec | 0.09 | 0.03 |
▼Loop 799 - par_multi_interp.c:1585-1660 - exec– | 0.05 | 0.02 |
○Loop 807 - par_multi_interp.c:1618-1628 - exec | 0.34 | 0.12 |
○Loop 808 - par_multi_interp.c:1612-1615 - exec | 0.01 | 0 |
○Loop 801 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 803 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 802 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 809 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 806 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 805 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 804 - par_multi_interp.c:1622-1652 - exec | 0 | 0 |
○Loop 800 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 810 - par_multi_interp.c:1592-1593 - exec | 0 | 0 |