Loop Id: 2805 | Module: exec | Source: ams.c:3382-3517 [...] | Coverage: 0.01% |
---|
Loop Id: 2805 | Module: exec | Source: ams.c:3382-3517 [...] | Coverage: 0.01% |
---|
0x497d29 VMOVSD %XMM0,(%R10) |
0x497d2e MOV 0x18(%RSP),%R9 |
0x497d33 NOPW %CS:(%RAX,%RAX,1) |
0x497d40 MOV 0x30(%RSP),%RDX |
0x497d45 LEA 0x1(%RDX),%RAX |
0x497d49 CMP 0x80(%RSP),%RDX |
0x497d51 MOV %RAX,%RDX |
0x497d54 JE 498740 |
0x497d5a MOV 0x48(%RSP),%RAX |
0x497d5f MOV %RDX,0x30(%RSP) |
0x497d64 LEA (%RAX,%RDX,1),%R11 |
0x497d68 MOV 0x50(%RSP),%RAX |
0x497d6d LEA (%RAX,%R11,8),%R10 |
0x497d71 MOVQ $0,(%RAX,%R11,8) |
0x497d79 TEST %RBX,%RBX |
0x497d7c JE 497e00 |
0x497d82 MOV (%RBX,%R11,8),%RDX |
0x497d86 MOV (%R9,%R11,8),%RAX |
0x497d8a MOV 0x8(%R9,%R11,8),%R8 |
0x497d8f VXORPD %XMM0,%XMM0,%XMM0 |
0x497d93 MOV %R8,%RSI |
0x497d96 SUB %RAX,%RSI |
0x497d99 JLE 497fa4 |
0x497d9f CMP $0x4,%RSI |
0x497da3 JAE 497ed4 |
0x497da9 MOV %RSI,%RDI |
0x497dac AND $-0x4,%RDI |
0x497db0 CMP %RSI,%RDI |
0x497db3 JAE 497f9a |
0x497db9 ADD %RDI,%RAX |
0x497dbc MOV 0x10(%RSP),%RBX |
0x497dc1 MOV 0x18(%RSP),%R9 |
0x497dc6 JMP 497ddc |
(2814) 0x497dd0 INC %RAX |
(2814) 0x497dd3 CMP %RAX,%R8 |
(2814) 0x497dd6 JE 497fa4 |
(2814) 0x497ddc MOV (%R13,%RAX,8),%RSI |
(2814) 0x497de1 CMP (%RBX,%RSI,8),%RDX |
(2814) 0x497de5 JNE 497dd0 |
(2814) 0x497de7 VMOVSD (%R14,%RAX,8),%XMM1 |
(2814) 0x497ded VANDPD %XMM5,%XMM1,%XMM1 |
(2814) 0x497df1 VADDSD %XMM1,%XMM0,%XMM0 |
(2814) 0x497df5 VMOVSD %XMM0,(%R10) |
(2814) 0x497dfa JMP 497dd0 |
0x497e00 MOV (%R9,%R11,8),%RDX |
0x497e04 MOV 0x8(%R9,%R11,8),%RAX |
0x497e09 VXORPD %XMM0,%XMM0,%XMM0 |
0x497e0d MOV %RAX,%RDI |
0x497e10 SUB %RDX,%RDI |
0x497e13 JLE 497e5b |
0x497e15 LEA (%R14,%RAX,8),%RSI |
0x497e19 ADD $-0x8,%RSI |
0x497e1d LEA (%R14,%RDX,8),%R8 |
0x497e21 CMP %R10,%RSI |
0x497e24 JB 4980cc |
0x497e2a CMP %R8,%R10 |
0x497e2d JB 4980cc |
0x497e33 NOPW %CS:(%RAX,%RAX,1) |
(2811) 0x497e40 VMOVSD (%R14,%RDX,8),%XMM1 |
(2811) 0x497e46 VANDPD %XMM5,%XMM1,%XMM1 |
(2811) 0x497e4a VADDSD %XMM1,%XMM0,%XMM0 |
(2811) 0x497e4e VMOVSD %XMM0,(%R10) |
(2811) 0x497e53 INC %RDX |
(2811) 0x497e56 CMP %RDX,%RAX |
(2811) 0x497e59 JNE 497e40 |
0x497e5b CMPQ $0,0x60(%RSP) |
0x497e61 JE 497d40 |
0x497e67 MOV 0x58(%RSP),%RAX |
0x497e6c MOV (%RAX,%R11,8),%RDX |
0x497e70 MOV 0x8(%RAX,%R11,8),%RAX |
0x497e75 MOV %RAX,%RDI |
0x497e78 SUB %RDX,%RDI |
0x497e7b JLE 497d40 |
0x497e81 MOV 0x8(%RSP),%R9 |
0x497e86 LEA (%R9,%RAX,8),%RSI |
0x497e8a ADD $-0x8,%RSI |
0x497e8e LEA (%R9,%RDX,8),%R8 |
0x497e92 CMP %R10,%RSI |
0x497e95 JB 498127 |
0x497e9b CMP %R8,%R10 |
0x497e9e JB 498127 |
0x497ea4 MOV 0x18(%RSP),%R9 |
0x497ea9 NOPL (%RAX) |
(2808) 0x497eb0 MOV 0x8(%RSP),%RSI |
(2808) 0x497eb5 VMOVSD (%RSI,%RDX,8),%XMM1 |
(2808) 0x497eba VANDPD %XMM5,%XMM1,%XMM1 |
(2808) 0x497ebe VADDSD %XMM1,%XMM0,%XMM0 |
(2808) 0x497ec2 VMOVSD %XMM0,(%R10) |
(2808) 0x497ec7 INC %RDX |
(2808) 0x497eca CMP %RDX,%RAX |
(2808) 0x497ecd JNE 497eb0 |
0x497ecf JMP 497d40 |
0x497ed4 MOV %RSI,%RDI |
0x497ed7 SHR $0x2,%RDI |
0x497edb LEA 0x18(,%RAX,8),%R9 |
0x497ee3 JMP 497f02 |
(2815) 0x497ef0 MOV 0x28(%RSP),%R15 |
(2815) 0x497ef5 ADD $0x20,%R9 |
(2815) 0x497ef9 DEC %RDI |
(2815) 0x497efc JE 497da9 |
(2815) 0x497f02 MOV -0x18(%R13,%R9,1),%RBX |
(2815) 0x497f07 MOV 0x10(%RSP),%R15 |
(2815) 0x497f0c CMP (%R15,%RBX,8),%RDX |
(2815) 0x497f10 JNE 497f26 |
(2815) 0x497f12 VMOVSD -0x18(%R14,%R9,1),%XMM1 |
(2815) 0x497f19 VANDPD %XMM5,%XMM1,%XMM1 |
(2815) 0x497f1d VADDSD %XMM1,%XMM0,%XMM0 |
(2815) 0x497f21 VMOVSD %XMM0,(%R10) |
(2815) 0x497f26 MOV -0x10(%R13,%R9,1),%RBX |
(2815) 0x497f2b MOV 0x10(%RSP),%R15 |
(2815) 0x497f30 CMP (%R15,%RBX,8),%RDX |
(2815) 0x497f34 JNE 497f4a |
(2815) 0x497f36 VMOVSD -0x10(%R14,%R9,1),%XMM1 |
(2815) 0x497f3d VANDPD %XMM5,%XMM1,%XMM1 |
(2815) 0x497f41 VADDSD %XMM1,%XMM0,%XMM0 |
(2815) 0x497f45 VMOVSD %XMM0,(%R10) |
(2815) 0x497f4a MOV -0x8(%R13,%R9,1),%RBX |
(2815) 0x497f4f MOV 0x10(%RSP),%R15 |
(2815) 0x497f54 CMP (%R15,%RBX,8),%RDX |
(2815) 0x497f58 JNE 497f6e |
(2815) 0x497f5a VMOVSD -0x8(%R14,%R9,1),%XMM1 |
(2815) 0x497f61 VANDPD %XMM5,%XMM1,%XMM1 |
(2815) 0x497f65 VADDSD %XMM1,%XMM0,%XMM0 |
(2815) 0x497f69 VMOVSD %XMM0,(%R10) |
(2815) 0x497f6e MOV (%R13,%R9,1),%RBX |
(2815) 0x497f73 MOV 0x10(%RSP),%R15 |
(2815) 0x497f78 CMP (%R15,%RBX,8),%RDX |
(2815) 0x497f7c JNE 497ef0 |
(2815) 0x497f82 VMOVSD (%R14,%R9,1),%XMM1 |
(2815) 0x497f88 VANDPD %XMM5,%XMM1,%XMM1 |
(2815) 0x497f8c VADDSD %XMM1,%XMM0,%XMM0 |
(2815) 0x497f90 VMOVSD %XMM0,(%R10) |
(2815) 0x497f95 JMP 497ef0 |
0x497f9a MOV 0x10(%RSP),%RBX |
0x497f9f MOV 0x18(%RSP),%R9 |
0x497fa4 CMPQ $0,0x60(%RSP) |
0x497faa JE 497d40 |
0x497fb0 MOV 0x58(%RSP),%RSI |
0x497fb5 MOV (%RSI,%R11,8),%RAX |
0x497fb9 MOV 0x8(%RSI,%R11,8),%R8 |
0x497fbe MOV %R8,%RDI |
0x497fc1 SUB %RAX,%RDI |
0x497fc4 JLE 497d40 |
0x497fca CMP $0x4,%RDI |
0x497fce JAE 49801f |
0x497fd0 MOV %RDI,%RSI |
0x497fd3 AND $-0x4,%RSI |
0x497fd7 CMP %RDI,%RSI |
0x497fda MOV 0x10(%RSP),%RBX |
0x497fdf MOV 0x18(%RSP),%R9 |
0x497fe4 JAE 497d40 |
0x497fea ADD %RSI,%RAX |
0x497fed JMP 497ffc |
(2812) 0x497ff0 INC %RAX |
(2812) 0x497ff3 CMP %RAX,%R8 |
(2812) 0x497ff6 JE 497d40 |
(2812) 0x497ffc MOV (%R12,%RAX,8),%RSI |
(2812) 0x498000 CMP (%R15,%RSI,8),%RDX |
(2812) 0x498004 JNE 497ff0 |
(2812) 0x498006 MOV 0x8(%RSP),%RSI |
(2812) 0x49800b VMOVSD (%RSI,%RAX,8),%XMM1 |
(2812) 0x498010 VANDPD %XMM5,%XMM1,%XMM1 |
(2812) 0x498014 VADDSD %XMM1,%XMM0,%XMM0 |
(2812) 0x498018 VMOVSD %XMM0,(%R10) |
(2812) 0x49801d JMP 497ff0 |
0x49801f MOV %RDI,%RSI |
0x498022 SHR $0x2,%RSI |
0x498026 LEA 0x18(,%RAX,8),%R9 |
0x49802e JMP 498039 |
(2813) 0x498030 ADD $0x20,%R9 |
(2813) 0x498034 DEC %RSI |
(2813) 0x498037 JE 497fd0 |
(2813) 0x498039 MOV -0x18(%R12,%R9,1),%R11 |
(2813) 0x49803e CMP (%R15,%R11,8),%RDX |
(2813) 0x498042 JNE 49805d |
(2813) 0x498044 MOV 0x8(%RSP),%R11 |
(2813) 0x498049 VMOVSD -0x18(%R11,%R9,1),%XMM1 |
(2813) 0x498050 VANDPD %XMM5,%XMM1,%XMM1 |
(2813) 0x498054 VADDSD %XMM1,%XMM0,%XMM0 |
(2813) 0x498058 VMOVSD %XMM0,(%R10) |
(2813) 0x49805d MOV -0x10(%R12,%R9,1),%R11 |
(2813) 0x498062 CMP (%R15,%R11,8),%RDX |
(2813) 0x498066 JNE 498081 |
(2813) 0x498068 MOV 0x8(%RSP),%R11 |
(2813) 0x49806d VMOVSD -0x10(%R11,%R9,1),%XMM1 |
(2813) 0x498074 VANDPD %XMM5,%XMM1,%XMM1 |
(2813) 0x498078 VADDSD %XMM1,%XMM0,%XMM0 |
(2813) 0x49807c VMOVSD %XMM0,(%R10) |
(2813) 0x498081 MOV -0x8(%R12,%R9,1),%R11 |
(2813) 0x498086 CMP (%R15,%R11,8),%RDX |
(2813) 0x49808a JNE 4980a5 |
(2813) 0x49808c MOV 0x8(%RSP),%R11 |
(2813) 0x498091 VMOVSD -0x8(%R11,%R9,1),%XMM1 |
(2813) 0x498098 VANDPD %XMM5,%XMM1,%XMM1 |
(2813) 0x49809c VADDSD %XMM1,%XMM0,%XMM0 |
(2813) 0x4980a0 VMOVSD %XMM0,(%R10) |
(2813) 0x4980a5 MOV (%R12,%R9,1),%R11 |
(2813) 0x4980a9 CMP (%R15,%R11,8),%RDX |
(2813) 0x4980ad JNE 498030 |
(2813) 0x4980af MOV 0x8(%RSP),%R11 |
(2813) 0x4980b4 VMOVSD (%R11,%R9,1),%XMM1 |
(2813) 0x4980ba VANDPD %XMM5,%XMM1,%XMM1 |
(2813) 0x4980be VADDSD %XMM1,%XMM0,%XMM0 |
(2813) 0x4980c2 VMOVSD %XMM0,(%R10) |
(2813) 0x4980c7 JMP 498030 |
0x4980cc MOV %RDI,%RSI |
0x4980cf AND $-0x4,%RSI |
0x4980d3 JE 49817f |
0x4980d9 LEA -0x1(%RSI),%R9 |
0x4980dd VXORPD %XMM0,%XMM0,%XMM0 |
0x4980e1 XOR %EBX,%EBX |
0x4980e3 NOPW %CS:(%RAX,%RAX,1) |
(2810) 0x4980f0 VANDPD (%R8,%RBX,8),%YMM6,%YMM1 |
(2810) 0x4980f6 VADDPD %YMM1,%YMM0,%YMM0 |
(2810) 0x4980fa ADD $0x4,%RBX |
(2810) 0x4980fe CMP %R9,%RBX |
(2810) 0x498101 JBE 4980f0 |
0x498103 VEXTRACTF128 $0x1,%YMM0,%XMM1 |
0x498109 VADDPD %XMM1,%XMM0,%XMM0 |
0x49810d VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
0x498112 VADDSD %XMM1,%XMM0,%XMM0 |
0x498116 CMP %RSI,%RDI |
0x498119 MOV 0x10(%RSP),%RBX |
0x49811e MOV 0x18(%RSP),%R9 |
0x498123 JNE 498181 |
0x498125 JMP 4981a6 |
0x498127 MOV %RDI,%RSI |
0x49812a AND $-0x4,%RSI |
0x49812e JE 4981bc |
0x498134 LEA -0x1(%RSI),%R9 |
0x498138 VXORPD %XMM1,%XMM1,%XMM1 |
0x49813c XOR %R11D,%R11D |
0x49813f NOP |
(2807) 0x498140 VANDPD (%R8,%R11,8),%YMM6,%YMM2 |
(2807) 0x498146 VADDPD %YMM2,%YMM1,%YMM1 |
(2807) 0x49814a ADD $0x4,%R11 |
(2807) 0x49814e CMP %R9,%R11 |
(2807) 0x498151 JBE 498140 |
0x498153 VEXTRACTF128 $0x1,%YMM1,%XMM2 |
0x498159 VADDPD %XMM2,%XMM1,%XMM1 |
0x49815d VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 |
0x498162 VADDSD %XMM2,%XMM1,%XMM1 |
0x498166 VADDSD %XMM1,%XMM0,%XMM0 |
0x49816a CMP %RSI,%RDI |
0x49816d MOV 0x10(%RSP),%RBX |
0x498172 MOV 0x8(%RSP),%R9 |
0x498177 JE 497d29 |
0x49817d JMP 4981be |
0x49817f XOR %ESI,%ESI |
0x498181 ADD %RDX,%RSI |
0x498184 NOPW %CS:(%RAX,%RAX,1) |
(2809) 0x498190 VMOVSD (%R14,%RSI,8),%XMM1 |
(2809) 0x498196 VANDPD %XMM5,%XMM1,%XMM1 |
(2809) 0x49819a VADDSD %XMM1,%XMM0,%XMM0 |
(2809) 0x49819e INC %RSI |
(2809) 0x4981a1 CMP %RSI,%RAX |
(2809) 0x4981a4 JNE 498190 |
0x4981a6 VMOVSD %XMM0,(%R10) |
0x4981ab CMPQ $0,0x60(%RSP) |
0x4981b1 JNE 497e67 |
0x4981b7 JMP 497d40 |
0x4981bc XOR %ESI,%ESI |
0x4981be ADD %RDX,%RSI |
0x4981c1 NOPW %CS:(%RAX,%RAX,1) |
(2806) 0x4981d0 VMOVSD (%R9,%RSI,8),%XMM1 |
(2806) 0x4981d6 VANDPD %XMM5,%XMM1,%XMM1 |
(2806) 0x4981da VADDSD %XMM1,%XMM0,%XMM0 |
(2806) 0x4981de INC %RSI |
(2806) 0x4981e1 CMP %RSI,%RAX |
(2806) 0x4981e4 JNE 4981d0 |
0x4981e6 JMP 497d29 |
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3517 |
-------------------------------------------------------------------------------- |
3382: for (i = ns; i < ne; i++) |
3383: { |
3384: l1_norm[i] = 0.0; |
3385: if (cf_marker == NULL) |
3386: { |
3387: /* Add the l1 norm of the diag part of the ith row */ |
3388: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3389: l1_norm[i] += fabs(A_diag_data[j]); |
3390: /* Add the l1 norm of the offd part of the ith row */ |
3391: if (num_cols_offd) |
3392: { |
3393: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
3394: l1_norm[i] += fabs(A_offd_data[j]); |
3395: } |
3396: } |
3397: else |
3398: { |
3399: cf_diag = cf_marker[i]; |
3400: /* Add the CF l1 norm of the diag part of the ith row */ |
3401: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3402: if (cf_diag == cf_marker[A_diag_J[j]]) |
3403: l1_norm[i] += fabs(A_diag_data[j]); |
3404: /* Add the CF l1 norm of the offd part of the ith row */ |
3405: if (num_cols_offd) |
3406: { |
3407: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
3408: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
3409: l1_norm[i] += fabs(A_offd_data[j]); |
[...] |
3473: if (cf_marker == NULL) |
[...] |
3517: if (num_cols_offd) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.09 |
CQA speedup if FP arith vectorized | 3.15 |
CQA speedup if fully vectorized | 12.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.93 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3382-3385,ams.c:3388-3394,ams.c:3399-3407,ams.c:3473-3473,ams.c:3517-3517 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 23.00 |
CQA cycles if no scalar integer | 11.00 |
CQA cycles if FP arith vectorized | 7.29 |
CQA cycles if fully vectorized | 1.92 |
Front-end cycles | 23.00 |
DIV/SQRT cycles | 11.70 |
P0 cycles | 11.90 |
P1 cycles | 10.33 |
P2 cycles | 10.33 |
P3 cycles | 2.00 |
P4 cycles | 11.90 |
P5 cycles | 11.70 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 11.80 |
P10 cycles | 10.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 23.22 - 23.23 |
Stall cycles (UFS) | 0.00 |
Nb insns | 138.00 |
Nb uops | 138.00 |
Nb loads | 31.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.30 |
Nb FLOP add-sub | 7.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 248.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 22.73 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.67 |
Vector-efficiency ratio all | 15.20 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 10.94 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.83 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.09 |
CQA speedup if FP arith vectorized | 3.15 |
CQA speedup if fully vectorized | 12.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.93 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3382-3385,ams.c:3388-3394,ams.c:3399-3407,ams.c:3473-3473,ams.c:3517-3517 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 23.00 |
CQA cycles if no scalar integer | 11.00 |
CQA cycles if FP arith vectorized | 7.29 |
CQA cycles if fully vectorized | 1.92 |
Front-end cycles | 23.00 |
DIV/SQRT cycles | 11.70 |
P0 cycles | 11.90 |
P1 cycles | 10.33 |
P2 cycles | 10.33 |
P3 cycles | 2.00 |
P4 cycles | 11.90 |
P5 cycles | 11.70 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 11.80 |
P10 cycles | 10.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 23.22 - 23.23 |
Stall cycles (UFS) | 0.00 |
Nb insns | 138.00 |
Nb uops | 138.00 |
Nb loads | 31.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.30 |
Nb FLOP add-sub | 7.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 248.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 22.73 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.67 |
Vector-efficiency ratio all | 15.20 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 10.94 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.83 |
Path / |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3382-3517 |
Module | exec |
nb instructions | 138 |
nb uops | 138 |
loop length | 637 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 23.00 cycles |
front end | 23.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.70 | 11.90 | 10.33 | 10.33 | 2.00 | 11.90 | 11.70 | 2.00 | 2.00 | 2.00 | 11.80 | 10.33 |
cycles | 11.70 | 11.90 | 10.33 | 10.33 | 2.00 | 11.90 | 11.70 | 2.00 | 2.00 | 2.00 | 11.80 | 10.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 23.22-23.23 |
Stall cycles | 0.00 |
Front-end | 23.00 |
Dispatch | 11.90 |
Overall L1 | 23.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 40% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 22% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 12% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 20% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 17% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 15% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x80(%RSP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 498740 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1540> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x48(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVQ $0,(%RAX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 497e00 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc00> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RBX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9,%R11,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497fa4 <hypre_ParCSRComputeL1NormsThreads.extracted+0xda4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 497ed4 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 497f9a <hypre_ParCSRComputeL1NormsThreads.extracted+0xd9a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 497ddc <hypre_ParCSRComputeL1NormsThreads.extracted+0xbdc> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV (%R9,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497e5b <hypre_ParCSRComputeL1NormsThreads.extracted+0xc5b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R14,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $-0x8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R14,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4980cc <hypre_ParCSRComputeL1NormsThreads.extracted+0xecc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4980cc <hypre_ParCSRComputeL1NormsThreads.extracted+0xecc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,0x60(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x58(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R9,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $-0x8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 498127 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf27> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 498127 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf27> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 497f02 <hypre_ParCSRComputeL1NormsThreads.extracted+0xd02> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,0x60(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x58(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49801f <hypre_ParCSRComputeL1NormsThreads.extracted+0xe1f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JAE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 497ffc <hypre_ParCSRComputeL1NormsThreads.extracted+0xdfc> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 498039 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe39> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 49817f <hypre_ParCSRComputeL1NormsThreads.extracted+0xf7f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 498181 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf81> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4981a6 <hypre_ParCSRComputeL1NormsThreads.extracted+0xfa6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 4981bc <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 497d29 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb29> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4981be <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,0x60(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 497e67 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc67> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 497d29 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb29> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3382-3517 |
Module | exec |
nb instructions | 138 |
nb uops | 138 |
loop length | 637 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 23.00 cycles |
front end | 23.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.70 | 11.90 | 10.33 | 10.33 | 2.00 | 11.90 | 11.70 | 2.00 | 2.00 | 2.00 | 11.80 | 10.33 |
cycles | 11.70 | 11.90 | 10.33 | 10.33 | 2.00 | 11.90 | 11.70 | 2.00 | 2.00 | 2.00 | 11.80 | 10.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 23.22-23.23 |
Stall cycles | 0.00 |
Front-end | 23.00 |
Dispatch | 11.90 |
Overall L1 | 23.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 40% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 22% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 12% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 20% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 17% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 15% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x80(%RSP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 498740 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1540> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x48(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVQ $0,(%RAX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 497e00 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc00> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RBX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9,%R11,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497fa4 <hypre_ParCSRComputeL1NormsThreads.extracted+0xda4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 497ed4 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcd4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 497f9a <hypre_ParCSRComputeL1NormsThreads.extracted+0xd9a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 497ddc <hypre_ParCSRComputeL1NormsThreads.extracted+0xbdc> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV (%R9,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497e5b <hypre_ParCSRComputeL1NormsThreads.extracted+0xc5b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R14,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $-0x8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R14,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4980cc <hypre_ParCSRComputeL1NormsThreads.extracted+0xecc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4980cc <hypre_ParCSRComputeL1NormsThreads.extracted+0xecc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,0x60(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x58(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R9,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $-0x8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 498127 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf27> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 498127 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf27> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 497f02 <hypre_ParCSRComputeL1NormsThreads.extracted+0xd02> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMPQ $0,0x60(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x58(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49801f <hypre_ParCSRComputeL1NormsThreads.extracted+0xe1f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JAE 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 497ffc <hypre_ParCSRComputeL1NormsThreads.extracted+0xdfc> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 498039 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe39> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 49817f <hypre_ParCSRComputeL1NormsThreads.extracted+0xf7f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 498181 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf81> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4981a6 <hypre_ParCSRComputeL1NormsThreads.extracted+0xfa6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 4981bc <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 497d29 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb29> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4981be <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,0x60(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 497e67 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc67> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 497d40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 497d29 <hypre_ParCSRComputeL1NormsThreads.extracted+0xb29> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |