Loop Id: 1140 | Module: exec | Source: par_lr_interp.c:1221-1627 [...] | Coverage: 0.05% |
---|
Loop Id: 1140 | Module: exec | Source: par_lr_interp.c:1221-1627 [...] | Coverage: 0.05% |
---|
0x44ff00 MOV (%RAX,%R8,8),%R10 [1] |
0x44ff04 MOV 0x8(%RAX,%R8,8),%RBX [1] |
0x44ff09 MOV 0x10(%RAX,%R8,8),%R15 [1] |
0x44ff0e MOV 0x18(%RAX,%R8,8),%R12 [1] |
0x44ff13 VMOVQ (%R13,%R12,8),%XMM14 [5] |
0x44ff1a VMOVQ (%R13,%R15,8),%XMM15 [6] |
0x44ff21 VPUNPCKLQDQ %XMM14,%XMM15,%XMM14 |
0x44ff26 VMOVQ (%R13,%RBX,8),%XMM15 [2] |
0x44ff2d VMOVQ (%R13,%R10,8),%XMM4 [4] |
0x44ff34 VPUNPCKLQDQ %XMM15,%XMM4,%XMM4 |
0x44ff39 VINSERTI128 $0x1,%XMM14,%YMM4,%YMM4 |
0x44ff3f VPCMPGTQ %YMM4,%YMM7,%YMM4 |
0x44ff44 VPXOR %YMM2,%YMM4,%YMM14 |
0x44ff48 VEXTRACTI128 $0x1,%YMM14,%XMM15 |
0x44ff4e VPCMPEQQ (%RAX,%R8,8),%YMM8,%YMM5 [1] |
0x44ff54 VPACKSSDW %XMM15,%XMM14,%XMM14 |
0x44ff59 VEXTRACTI128 $0x1,%YMM5,%XMM15 |
0x44ff5f VPACKSSDW %XMM15,%XMM5,%XMM15 |
0x44ff64 VPAND %YMM4,%YMM5,%YMM4 |
0x44ff68 VEXTRACTI128 $0x1,%YMM4,%XMM5 |
0x44ff6e VPACKSSDW %XMM5,%XMM4,%XMM4 |
0x44ff72 VBLENDVPS %XMM4,%XMM15,%XMM14,%XMM4 |
0x44ff78 VPMOVSXDQ %XMM4,%YMM5 |
0x44ff7d VMASKMOVPD (%R14,%R8,8),%YMM5,%YMM5 [3] |
0x44ff83 VMULPD %YMM5,%YMM10,%YMM14 |
0x44ff87 VCMPPD $0x1,%YMM13,%YMM14,%YMM14 |
0x44ff8d VEXTRACTF128 $0x1,%YMM14,%XMM15 |
0x44ff93 VPACKSSDW %XMM15,%XMM14,%XMM14 |
0x44ff98 VPAND %XMM4,%XMM14,%XMM4 |
0x44ff9c VPMOVSXDQ %XMM4,%YMM4 |
0x44ffa1 VBLENDVPD %YMM4,%YMM5,%YMM3,%YMM4 |
0x44ffa7 VADDPD %YMM4,%YMM12,%YMM12 |
0x44ffab ADD $0x4,%R8 |
0x44ffaf CMP %RDI,%R8 |
0x44ffb2 JBE 44ff00 |
/home/eoseret/qaas_runs_CPU_9468/171-586-9096/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1221 - 1627 |
-------------------------------------------------------------------------------- |
1221: if (n_fine) |
[...] |
1624: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1625: { |
1626: i2 = A_diag_j[jj1]; |
1627: if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.09 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.47 |
Bottlenecks | P5, |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source | par_lr_interp.c:1221-1221,par_lr_interp.c:1624-1627 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 11.00 |
CQA cycles if fully vectorized | 3.00 |
Front-end cycles | 6.67 |
DIV/SQRT cycles | 8.17 |
P0 cycles | 7.83 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 0.00 |
P4 cycles | 12.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 12.54 - 12.61 |
Stall cycles (UFS) | 5.18 - 5.25 |
Nb insns | 35.00 |
Nb uops | 39.00 |
Nb loads | 10.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.67 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 4.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 78.57 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 90.48 |
Vector-efficiency ratio all | 30.36 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 30.95 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.09 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.47 |
Bottlenecks | P5, |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source | par_lr_interp.c:1221-1221,par_lr_interp.c:1624-1627 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 11.00 |
CQA cycles if fully vectorized | 3.00 |
Front-end cycles | 6.67 |
DIV/SQRT cycles | 8.17 |
P0 cycles | 7.83 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 0.00 |
P4 cycles | 12.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 12.54 - 12.61 |
Stall cycles (UFS) | 5.18 - 5.25 |
Nb insns | 35.00 |
Nb uops | 39.00 |
Nb loads | 10.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.67 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 4.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 78.57 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 90.48 |
Vector-efficiency ratio all | 30.36 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 30.95 |
Path / |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source file and lines | par_lr_interp.c:1221-1627 |
Module | exec |
nb instructions | 35 |
nb uops | 39 |
loop length | 184 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.17 | 7.83 | 3.33 | 3.33 | 0.00 | 12.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
cycles | 8.17 | 7.83 | 3.33 | 3.33 | 0.00 | 12.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 12.54-12.61 |
Stall cycles | 5.18-5.25 |
RS full (events) | 4.69-0.67 |
PRF_FLOAT full (events) | 4.05-5.97 |
Front-end | 6.67 |
Dispatch | 12.00 |
Data deps. | 3.00 |
Overall L1 | 12.00 |
all | 71% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 88% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 78% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 90% |
all | 26% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 29% |
all | 42% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 37% |
all | 30% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 30% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RAX,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R8,8),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RAX,%R8,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX,%R8,8),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R12,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R15,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM14,%XMM15,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ (%R13,%RBX,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R10,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM15,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTI128 $0x1,%XMM14,%YMM4,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPGTQ %YMM4,%YMM7,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPXOR %YMM2,%YMM4,%YMM14 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VEXTRACTI128 $0x1,%YMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPEQQ (%RAX,%R8,8),%YMM8,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VPACKSSDW %XMM15,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VEXTRACTI128 $0x1,%YMM5,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPACKSSDW %XMM15,%XMM5,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPAND %YMM4,%YMM5,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VEXTRACTI128 $0x1,%YMM4,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPACKSSDW %XMM5,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDVPS %XMM4,%XMM15,%XMM14,%XMM4 | 3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2-3 | 1 |
VPMOVSXDQ %XMM4,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMASKMOVPD (%R14,%R8,8),%YMM5,%YMM5 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 8-9 | 0.40 |
VMULPD %YMM5,%YMM10,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%YMM13,%YMM14,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF128 $0x1,%YMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPACKSSDW %XMM15,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPAND %XMM4,%XMM14,%XMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMOVSXDQ %XMM4,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDVPD %YMM4,%YMM5,%YMM3,%YMM4 | 3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2-3 | 1 |
VADDPD %YMM4,%YMM12,%YMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 44ff00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x14c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source file and lines | par_lr_interp.c:1221-1627 |
Module | exec |
nb instructions | 35 |
nb uops | 39 |
loop length | 184 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.17 | 7.83 | 3.33 | 3.33 | 0.00 | 12.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
cycles | 8.17 | 7.83 | 3.33 | 3.33 | 0.00 | 12.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 12.54-12.61 |
Stall cycles | 5.18-5.25 |
RS full (events) | 4.69-0.67 |
PRF_FLOAT full (events) | 4.05-5.97 |
Front-end | 6.67 |
Dispatch | 12.00 |
Data deps. | 3.00 |
Overall L1 | 12.00 |
all | 71% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 88% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 78% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 90% |
all | 26% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 29% |
all | 42% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 37% |
all | 30% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 30% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RAX,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R8,8),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RAX,%R8,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX,%R8,8),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R12,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R15,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM14,%XMM15,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ (%R13,%RBX,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R10,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM15,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTI128 $0x1,%XMM14,%YMM4,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPGTQ %YMM4,%YMM7,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPXOR %YMM2,%YMM4,%YMM14 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VEXTRACTI128 $0x1,%YMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPEQQ (%RAX,%R8,8),%YMM8,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VPACKSSDW %XMM15,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VEXTRACTI128 $0x1,%YMM5,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPACKSSDW %XMM15,%XMM5,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPAND %YMM4,%YMM5,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VEXTRACTI128 $0x1,%YMM4,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPACKSSDW %XMM5,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDVPS %XMM4,%XMM15,%XMM14,%XMM4 | 3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2-3 | 1 |
VPMOVSXDQ %XMM4,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMASKMOVPD (%R14,%R8,8),%YMM5,%YMM5 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 8-9 | 0.40 |
VMULPD %YMM5,%YMM10,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%YMM13,%YMM14,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF128 $0x1,%YMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPACKSSDW %XMM15,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPAND %XMM4,%XMM14,%XMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMOVSXDQ %XMM4,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDVPD %YMM4,%YMM5,%YMM3,%YMM4 | 3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2-3 | 1 |
VADDPD %YMM4,%YMM12,%YMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 44ff00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x14c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |