Function: hypre_BoomerAMGBuildMultipass.extracted.28 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.19% |
---|
Function: hypre_BoomerAMGBuildMultipass.extracted.28 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 1.19% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-3872/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881 |
-------------------------------------------------------------------------------- |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1747: if (n_fine) |
1748: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1749: tmp_marker_offd = NULL; |
1750: if (num_cols_offd) |
1751: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1752: tmp_array = NULL; |
1753: if (n_coarse) |
1754: { tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); } |
[...] |
1760: for (i=0; i < n_fine; i++) |
1761: { tmp_marker[i] = -1; } |
1762: for (i=0; i < num_cols_offd; i++) |
1763: { tmp_marker_offd[i] = -1; } |
1764: |
1765: /* Compute this thread's range of pass_length */ |
1766: my_thread_num = hypre_GetThreadNum(); |
1767: num_threads = hypre_NumActiveThreads(); |
1768: thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num; |
1769: if (my_thread_num == num_threads-1) |
1770: { thread_stop = pass_pointer[pass] + pass_length; } |
1771: else |
1772: { thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); } |
1773: |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
1877: } |
1878: hypre_TFree(tmp_marker); |
1879: hypre_TFree(tmp_marker_offd); |
1880: hypre_TFree(tmp_array); |
1881: hypre_TFree(tmp_array_offd); |
0x443120 PUSH %RBP |
0x443121 MOV %RSP,%RBP |
0x443124 PUSH %R15 |
0x443126 PUSH %R14 |
0x443128 PUSH %R13 |
0x44312a PUSH %R12 |
0x44312c PUSH %RBX |
0x44312d SUB $0x178,%RSP |
0x443134 MOV %R9,-0x198(%RBP) |
0x44313b MOV %R8,-0xc8(%RBP) |
0x443142 MOV %RCX,-0xe8(%RBP) |
0x443149 MOV %RDX,-0x150(%RBP) |
0x443150 MOV 0x138(%RBP),%RAX |
0x443157 MOV %RAX,-0x48(%RBP) |
0x44315b MOV 0x130(%RBP),%RAX |
0x443162 MOV %RAX,-0x40(%RBP) |
0x443166 MOV 0x128(%RBP),%RAX |
0x44316d MOV %RAX,-0x140(%RBP) |
0x443174 MOV 0x120(%RBP),%RAX |
0x44317b MOV %RAX,-0x190(%RBP) |
0x443182 MOV 0x118(%RBP),%RAX |
0x443189 MOV %RAX,-0x188(%RBP) |
0x443190 MOV 0x110(%RBP),%R15 |
0x443197 MOV 0x108(%RBP),%RAX |
0x44319e MOV %RAX,-0x58(%RBP) |
0x4431a2 MOV 0x100(%RBP),%RDI |
0x4431a9 MOV 0xf8(%RBP),%RAX |
0x4431b0 MOV %RAX,-0x60(%RBP) |
0x4431b4 MOV 0xf0(%RBP),%RAX |
0x4431bb MOV %RAX,-0x158(%RBP) |
0x4431c2 MOV 0xe8(%RBP),%RAX |
0x4431c9 MOV %RAX,-0x148(%RBP) |
0x4431d0 MOV 0xe0(%RBP),%RAX |
0x4431d7 MOV %RAX,-0x138(%RBP) |
0x4431de MOV 0xd8(%RBP),%RAX |
0x4431e5 MOV %RAX,-0xc0(%RBP) |
0x4431ec MOV 0xd0(%RBP),%RAX |
0x4431f3 MOV %RAX,-0xb8(%RBP) |
0x4431fa MOV 0xc8(%RBP),%RAX |
0x443201 MOV %RAX,-0x120(%RBP) |
0x443208 MOV 0xc0(%RBP),%RAX |
0x44320f MOV %RAX,-0x118(%RBP) |
0x443216 MOV 0xb8(%RBP),%RAX |
0x44321d MOV %RAX,-0x30(%RBP) |
0x443221 MOV 0xb0(%RBP),%RAX |
0x443228 MOV %RAX,-0x110(%RBP) |
0x44322f MOV 0xa8(%RBP),%RAX |
0x443236 MOV %RAX,-0x128(%RBP) |
0x44323d MOV 0xa0(%RBP),%RAX |
0x443244 MOV %RAX,-0x160(%RBP) |
0x44324b MOV 0x98(%RBP),%RAX |
0x443252 MOV %RAX,-0x130(%RBP) |
0x443259 MOV 0x90(%RBP),%RAX |
0x443260 MOV %RAX,-0x38(%RBP) |
0x443264 MOV 0x88(%RBP),%RAX |
0x44326b MOV %RAX,-0xb0(%RBP) |
0x443272 MOV 0x80(%RBP),%R13 |
0x443279 MOV 0x78(%RBP),%RAX |
0x44327d MOV %RAX,-0x50(%RBP) |
0x443281 MOV 0x70(%RBP),%RAX |
0x443285 MOV %RAX,-0xa8(%RBP) |
0x44328c MOV 0x68(%RBP),%R14 |
0x443290 MOV 0x60(%RBP),%R12 |
0x443294 MOV 0x58(%RBP),%RAX |
0x443298 MOV %RAX,-0x180(%RBP) |
0x44329f MOV 0x50(%RBP),%RAX |
0x4432a3 MOV %RAX,-0xe0(%RBP) |
0x4432aa MOV 0x48(%RBP),%RAX |
0x4432ae MOV %RAX,-0x178(%RBP) |
0x4432b5 MOV 0x40(%RBP),%RAX |
0x4432b9 MOV %RAX,-0xd8(%RBP) |
0x4432c0 MOV 0x38(%RBP),%RAX |
0x4432c4 MOV %RAX,-0x170(%RBP) |
0x4432cb MOV 0x30(%RBP),%RAX |
0x4432cf MOV %RAX,-0x108(%RBP) |
0x4432d6 MOV 0x28(%RBP),%RAX |
0x4432da MOV %RAX,-0xd0(%RBP) |
0x4432e1 MOV 0x20(%RBP),%RAX |
0x4432e5 MOV %RAX,-0x168(%RBP) |
0x4432ec MOV 0x18(%RBP),%RAX |
0x4432f0 MOV %RAX,-0x100(%RBP) |
0x4432f7 MOV 0x10(%RBP),%RBX |
0x4432fb TEST %RDI,%RDI |
0x4432fe MOV %RDI,-0x70(%RBP) |
0x443302 JE 443347 |
0x443304 MOV $0x8,%ESI |
0x443309 CALL 4e6980 <hypre_CAlloc> |
0x44330e MOV %RAX,-0x80(%RBP) |
0x443312 TEST %R12,%R12 |
0x443315 MOV %R12,-0xa0(%RBP) |
0x44331c JE 443359 |
0x44331e MOV $0x8,%ESI |
0x443323 MOV %R12,%RDI |
0x443326 CALL 4e6980 <hypre_CAlloc> |
0x44332b MOV %RAX,-0x78(%RBP) |
0x44332f MOV -0x58(%RBP),%RDI |
0x443333 TEST %RDI,%RDI |
0x443336 JE 443368 |
0x443338 MOV $0x8,%ESI |
0x44333d CALL 4e6980 <hypre_CAlloc> |
0x443342 MOV %RAX,%R12 |
0x443345 JMP 44336b |
0x443347 XOR %EAX,%EAX |
0x443349 MOV %RAX,-0x80(%RBP) |
0x44334d TEST %R12,%R12 |
0x443350 MOV %R12,-0xa0(%RBP) |
0x443357 JNE 44331e |
0x443359 XOR %EAX,%EAX |
0x44335b MOV %RAX,-0x78(%RBP) |
0x44335f MOV -0x58(%RBP),%RDI |
0x443363 TEST %RDI,%RDI |
0x443366 JNE 443338 |
0x443368 XOR %R12D,%R12D |
0x44336b MOV -0x40(%RBP),%RAX |
0x44336f CMP %R15,%RAX |
0x443372 CMOVG %RAX,%R15 |
0x443376 MOV $0x8,%ESI |
0x44337b MOV %R15,%RDI |
0x44337e CALL 4e6980 <hypre_CAlloc> |
0x443383 MOV %RAX,%R15 |
0x443386 MOV -0x70(%RBP),%RDX |
0x44338a TEST %RDX,%RDX |
0x44338d JLE 4433a1 |
0x44338f SAL $0x3,%RDX |
0x443393 MOV -0x80(%RBP),%RDI |
0x443397 MOV $0xff,%ESI |
0x44339c CALL 4efbb0 <_intel_fast_memset> |
0x4433a1 MOV -0xa0(%RBP),%RDX |
0x4433a8 TEST %RDX,%RDX |
0x4433ab JLE 4433bf |
0x4433ad SAL $0x3,%RDX |
0x4433b1 MOV -0x78(%RBP),%RDI |
0x4433b5 MOV $0xff,%ESI |
0x4433ba CALL 4efbb0 <_intel_fast_memset> |
0x4433bf CALL 4e86c0 <hypre_GetThreadNum> |
0x4433c4 MOV %RAX,-0x70(%RBP) |
0x4433c8 CALL 4e86b0 <hypre_NumActiveThreads> |
0x4433cd MOV %RAX,%RCX |
0x4433d0 MOV -0x60(%RBP),%RAX |
0x4433d4 MOV (%RAX),%RAX |
0x4433d7 MOV -0x30(%RBP),%RDX |
0x4433db MOV (%RDX,%RAX,8),%RSI |
0x4433df MOV -0x48(%RBP),%R8 |
0x4433e3 MOV %R8,%RAX |
0x4433e6 OR %RCX,%RAX |
0x4433e9 SHR $0x20,%RAX |
0x4433ed JE 4433f9 |
0x4433ef MOV %R8,%RAX |
0x4433f2 CQTO |
0x4433f4 IDIV %RCX |
0x4433f7 JMP 443400 |
0x4433f9 MOV %R8D,%EAX |
0x4433fc XOR %EDX,%EDX |
0x4433fe DIV %ECX |
0x443400 MOV -0x38(%RBP),%R10 |
0x443404 MOV %RAX,%RDX |
0x443407 MOV -0x70(%RBP),%R9 |
0x44340b IMUL %R9,%RDX |
0x44340f DEC %RCX |
0x443412 LEA 0x1(%R9),%RDI |
0x443416 IMUL %RAX,%RDI |
0x44341a CMP %RCX,%R9 |
0x44341d CMOVE %R8,%RDI |
0x443421 MOV %RDI,-0x58(%RBP) |
0x443425 CMP %RDI,%RDX |
0x443428 JGE 443f1b |
0x44342e MOV -0x58(%RBP),%RAX |
0x443432 ADD %RSI,%RAX |
0x443435 MOV %RAX,-0x58(%RBP) |
0x443439 ADD %RSI,%RDX |
0x44343c MOV -0x50(%RBP),%RAX |
0x443440 ADD $0x38,%RAX |
0x443444 MOV %RAX,-0xf8(%RBP) |
0x44344b LEA 0x38(%R10),%RAX |
0x44344f MOV %RAX,-0xf0(%RBP) |
0x443456 VXORPD %XMM9,%XMM9,%XMM9 |
0x44345b MOV %R12,-0x30(%RBP) |
0x44345f JMP 443484 |
0x443461 NOPW %CS:(%RAX,%RAX,1) |
(963) 0x443470 MOV -0xa0(%RBP),%RDX |
(963) 0x443477 INC %RDX |
(963) 0x44347a CMP -0x58(%RBP),%RDX |
(963) 0x44347e JGE 443f1b |
(963) 0x443484 MOV -0x110(%RBP),%RAX |
(963) 0x44348b MOV %RDX,-0xa0(%RBP) |
(963) 0x443492 MOV (%RAX,%RDX,8),%R9 |
(963) 0x443496 MOV -0x118(%RBP),%RAX |
(963) 0x44349d MOV (%RAX,%R9,8),%R8 |
(963) 0x4434a1 MOV -0xa8(%RBP),%RAX |
(963) 0x4434a8 MOV (%RAX,%R9,8),%R12 |
(963) 0x4434ac MOV 0x8(%RAX,%R9,8),%RSI |
(963) 0x4434b1 LEA (%RSI,%R8,1),%RAX |
(963) 0x4434b5 SUB %R12,%RAX |
(963) 0x4434b8 CMP %RAX,%R8 |
(963) 0x4434bb MOV %R9,-0x48(%RBP) |
(963) 0x4434bf JGE 44369f |
(963) 0x4434c5 MOV -0x60(%RBP),%RAX |
(963) 0x4434c9 MOV (%RAX),%RCX |
(963) 0x4434cc MOV %RSI,%RAX |
(963) 0x4434cf SUB %R12,%RAX |
(963) 0x4434d2 CMP $0xd,%RAX |
(963) 0x4434d6 JB 443660 |
(963) 0x4434dc MOV %RSI,-0x98(%RBP) |
(963) 0x4434e3 VMOVUPD %XMM10,-0x70(%RBP) |
(963) 0x4434e8 LEA (%R14,%R12,8),%RDI |
(963) 0x4434ec LEA (,%RAX,8),%RDX |
(963) 0x4434f4 XOR %ESI,%ESI |
(963) 0x4434f6 MOV %R8,-0x40(%RBP) |
(963) 0x4434fa MOV %RAX,-0x88(%RBP) |
(963) 0x443501 MOV %RCX,-0x90(%RBP) |
(963) 0x443508 VZEROUPPER |
(963) 0x44350b CALL 4efbb0 <_intel_fast_memset> |
(963) 0x443510 MOV -0xb8(%RBP),%RAX |
(963) 0x443517 MOV -0x90(%RBP),%RCX |
(963) 0x44351e MOV (%RAX,%RCX,8),%RAX |
(963) 0x443522 MOV -0x88(%RBP),%RCX |
(963) 0x443529 SHR $0x3,%RCX |
(963) 0x44352d MOV -0x40(%RBP),%RDX |
(963) 0x443531 LEA 0x38(%RAX,%RDX,8),%RDX |
(963) 0x443536 MOV -0xf8(%RBP),%RSI |
(963) 0x44353d LEA (%RSI,%R12,8),%RSI |
(963) 0x443541 MOV %RCX,%RDI |
(963) 0x443544 XOR %R8D,%R8D |
(963) 0x443547 MOV -0x30(%RBP),%R11 |
(963) 0x44354b NOPL (%RAX,%RAX,1) |
(981) 0x443550 MOV -0x38(%RDX,%R8,8),%R9 |
(981) 0x443555 LEA (%R12,%R8,1),%R10 |
(981) 0x443559 MOV %R10,(%R11,%R9,8) |
(981) 0x44355d MOV %R9,-0x38(%RSI,%R8,8) |
(981) 0x443562 MOV -0x30(%RDX,%R8,8),%R9 |
(981) 0x443567 LEA 0x1(%R12,%R8,1),%R10 |
(981) 0x44356c MOV %R10,(%R11,%R9,8) |
(981) 0x443570 MOV %R9,-0x30(%RSI,%R8,8) |
(981) 0x443575 MOV -0x28(%RDX,%R8,8),%R9 |
(981) 0x44357a LEA 0x2(%R12,%R8,1),%R10 |
(981) 0x44357f MOV %R10,(%R11,%R9,8) |
(981) 0x443583 MOV %R9,-0x28(%RSI,%R8,8) |
(981) 0x443588 MOV -0x20(%RDX,%R8,8),%R9 |
(981) 0x44358d LEA 0x3(%R12,%R8,1),%R10 |
(981) 0x443592 MOV %R10,(%R11,%R9,8) |
(981) 0x443596 MOV %R9,-0x20(%RSI,%R8,8) |
(981) 0x44359b MOV -0x18(%RDX,%R8,8),%R9 |
(981) 0x4435a0 LEA 0x4(%R12,%R8,1),%R10 |
(981) 0x4435a5 MOV %R10,(%R11,%R9,8) |
(981) 0x4435a9 MOV %R9,-0x18(%RSI,%R8,8) |
(981) 0x4435ae MOV -0x10(%RDX,%R8,8),%R9 |
(981) 0x4435b3 LEA 0x5(%R12,%R8,1),%R10 |
(981) 0x4435b8 MOV %R10,(%R11,%R9,8) |
(981) 0x4435bc MOV %R9,-0x10(%RSI,%R8,8) |
(981) 0x4435c1 MOV -0x8(%RDX,%R8,8),%R9 |
(981) 0x4435c6 LEA 0x6(%R12,%R8,1),%R10 |
(981) 0x4435cb MOV %R10,(%R11,%R9,8) |
(981) 0x4435cf MOV %R9,-0x8(%RSI,%R8,8) |
(981) 0x4435d4 MOV (%RDX,%R8,8),%R9 |
(981) 0x4435d8 LEA 0x7(%R12,%R8,1),%R10 |
(981) 0x4435dd MOV %R10,(%R11,%R9,8) |
(981) 0x4435e1 MOV %R9,(%RSI,%R8,8) |
(981) 0x4435e5 ADD $0x8,%R8 |
(981) 0x4435e9 DEC %RDI |
(981) 0x4435ec JNE 443550 |
(963) 0x4435f2 MOV -0x88(%RBP),%RSI |
(963) 0x4435f9 MOV %RSI,%RDX |
(963) 0x4435fc AND $-0x8,%RDX |
(963) 0x443600 CMP %RSI,%RDX |
(963) 0x443603 MOV -0x38(%RBP),%R10 |
(963) 0x443607 MOV -0x50(%RBP),%RSI |
(963) 0x44360b VXORPD %XMM9,%XMM9,%XMM9 |
(963) 0x443610 MOV -0x48(%RBP),%R9 |
(963) 0x443614 VMOVUPD -0x70(%RBP),%XMM10 |
(963) 0x443619 MOV -0x98(%RBP),%RDI |
(963) 0x443620 MOV -0x40(%RBP),%R8 |
(963) 0x443624 JE 44369f |
(963) 0x443626 ADD %RDX,%R12 |
(963) 0x443629 SAL $0x6,%RCX |
(963) 0x44362d LEA (%RCX,%R8,8),%RCX |
(963) 0x443631 ADD %RCX,%RAX |
(963) 0x443634 NOPW %CS:(%RAX,%RAX,1) |
(982) 0x443640 MOV (%RAX),%RCX |
(982) 0x443643 MOV %R12,(%R11,%RCX,8) |
(982) 0x443647 MOV %RCX,(%RSI,%R12,8) |
(982) 0x44364b INC %R12 |
(982) 0x44364e ADD $0x8,%RAX |
(982) 0x443652 CMP %R12,%RDI |
(982) 0x443655 JNE 443640 |
(963) 0x443657 JMP 44369f |
0x443659 NOPL (%RAX) |
(963) 0x443660 SAL $0x3,%R8 |
(963) 0x443664 MOV -0xb8(%RBP),%RAX |
(963) 0x44366b ADD (%RAX,%RCX,8),%R8 |
(963) 0x44366f MOV -0x50(%RBP),%RCX |
(963) 0x443673 MOV -0x30(%RBP),%RDX |
(963) 0x443677 NOPW (%RAX,%RAX,1) |
(980) 0x443680 MOV (%R8),%RAX |
(980) 0x443683 MOV %R12,(%RDX,%RAX,8) |
(980) 0x443687 MOVQ $0,(%R14,%R12,8) |
(980) 0x44368f MOV %RAX,(%RCX,%R12,8) |
(980) 0x443693 INC %R12 |
(980) 0x443696 ADD $0x8,%R8 |
(980) 0x44369a CMP %R12,%RSI |
(980) 0x44369d JNE 443680 |
(963) 0x44369f MOV -0x120(%RBP),%RAX |
(963) 0x4436a6 MOV (%RAX,%R9,8),%R8 |
(963) 0x4436aa MOV -0xb0(%RBP),%RAX |
(963) 0x4436b1 MOV (%RAX,%R9,8),%R12 |
(963) 0x4436b5 MOV 0x8(%RAX,%R9,8),%RCX |
(963) 0x4436ba LEA (%RCX,%R8,1),%RAX |
(963) 0x4436be SUB %R12,%RAX |
(963) 0x4436c1 CMP %RAX,%R8 |
(963) 0x4436c4 JGE 443880 |
(963) 0x4436ca MOV -0x60(%RBP),%RAX |
(963) 0x4436ce MOV (%RAX),%RDX |
(963) 0x4436d1 MOV %RCX,%RAX |
(963) 0x4436d4 SUB %R12,%RAX |
(963) 0x4436d7 CMP $0xd,%RAX |
(963) 0x4436db JB 443850 |
(963) 0x4436e1 MOV %RCX,-0x88(%RBP) |
(963) 0x4436e8 VMOVUPD %XMM10,-0x70(%RBP) |
(963) 0x4436ed LEA (%R13,%R12,8),%RDI |
(963) 0x4436f2 MOV %RDX,-0x90(%RBP) |
(963) 0x4436f9 LEA (,%RAX,8),%RDX |
(963) 0x443701 XOR %ESI,%ESI |
(963) 0x443703 MOV %R8,-0x98(%RBP) |
(963) 0x44370a MOV %RAX,-0x40(%RBP) |
(963) 0x44370e VZEROUPPER |
(963) 0x443711 CALL 4efbb0 <_intel_fast_memset> |
(963) 0x443716 MOV -0x98(%RBP),%R11 |
(963) 0x44371d MOV -0xc0(%RBP),%RAX |
(963) 0x443724 MOV -0x90(%RBP),%RCX |
(963) 0x44372b MOV (%RAX,%RCX,8),%RAX |
(963) 0x44372f MOV -0x40(%RBP),%RCX |
(963) 0x443733 SHR $0x3,%RCX |
(963) 0x443737 LEA 0x38(%RAX,%R11,8),%RDX |
(963) 0x44373c MOV -0xf0(%RBP),%RSI |
(963) 0x443743 LEA (%RSI,%R12,8),%RSI |
(963) 0x443747 MOV %RCX,%RDI |
(963) 0x44374a XOR %R8D,%R8D |
(963) 0x44374d NOPL (%RAX) |
(978) 0x443750 MOV -0x38(%RDX,%R8,8),%R9 |
(978) 0x443755 LEA (%R12,%R8,1),%R10 |
(978) 0x443759 MOV %R10,(%R15,%R9,8) |
(978) 0x44375d MOV %R9,-0x38(%RSI,%R8,8) |
(978) 0x443762 MOV -0x30(%RDX,%R8,8),%R9 |
(978) 0x443767 LEA 0x1(%R12,%R8,1),%R10 |
(978) 0x44376c MOV %R10,(%R15,%R9,8) |
(978) 0x443770 MOV %R9,-0x30(%RSI,%R8,8) |
(978) 0x443775 MOV -0x28(%RDX,%R8,8),%R9 |
(978) 0x44377a LEA 0x2(%R12,%R8,1),%R10 |
(978) 0x44377f MOV %R10,(%R15,%R9,8) |
(978) 0x443783 MOV %R9,-0x28(%RSI,%R8,8) |
(978) 0x443788 MOV -0x20(%RDX,%R8,8),%R9 |
(978) 0x44378d LEA 0x3(%R12,%R8,1),%R10 |
(978) 0x443792 MOV %R10,(%R15,%R9,8) |
(978) 0x443796 MOV %R9,-0x20(%RSI,%R8,8) |
(978) 0x44379b MOV -0x18(%RDX,%R8,8),%R9 |
(978) 0x4437a0 LEA 0x4(%R12,%R8,1),%R10 |
(978) 0x4437a5 MOV %R10,(%R15,%R9,8) |
(978) 0x4437a9 MOV %R9,-0x18(%RSI,%R8,8) |
(978) 0x4437ae MOV -0x10(%RDX,%R8,8),%R9 |
(978) 0x4437b3 LEA 0x5(%R12,%R8,1),%R10 |
(978) 0x4437b8 MOV %R10,(%R15,%R9,8) |
(978) 0x4437bc MOV %R9,-0x10(%RSI,%R8,8) |
(978) 0x4437c1 MOV -0x8(%RDX,%R8,8),%R9 |
(978) 0x4437c6 LEA 0x6(%R12,%R8,1),%R10 |
(978) 0x4437cb MOV %R10,(%R15,%R9,8) |
(978) 0x4437cf MOV %R9,-0x8(%RSI,%R8,8) |
(978) 0x4437d4 MOV (%RDX,%R8,8),%R9 |
(978) 0x4437d8 LEA 0x7(%R12,%R8,1),%R10 |
(978) 0x4437dd MOV %R10,(%R15,%R9,8) |
(978) 0x4437e1 MOV %R9,(%RSI,%R8,8) |
(978) 0x4437e5 ADD $0x8,%R8 |
(978) 0x4437e9 DEC %RDI |
(978) 0x4437ec JNE 443750 |
(963) 0x4437f2 MOV -0x40(%RBP),%RSI |
(963) 0x4437f6 MOV %RSI,%RDX |
(963) 0x4437f9 AND $-0x8,%RDX |
(963) 0x4437fd CMP %RSI,%RDX |
(963) 0x443800 MOV -0x38(%RBP),%R10 |
(963) 0x443804 VXORPD %XMM9,%XMM9,%XMM9 |
(963) 0x443809 MOV -0x48(%RBP),%R9 |
(963) 0x44380d VMOVUPD -0x70(%RBP),%XMM10 |
(963) 0x443812 MOV -0x88(%RBP),%RSI |
(963) 0x443819 JE 443880 |
(963) 0x44381b ADD %RDX,%R12 |
(963) 0x44381e SAL $0x6,%RCX |
(963) 0x443822 LEA (%RCX,%R11,8),%RCX |
(963) 0x443826 ADD %RCX,%RAX |
(963) 0x443829 NOPL (%RAX) |
(979) 0x443830 MOV (%RAX),%RCX |
(979) 0x443833 MOV %R12,(%R15,%RCX,8) |
(979) 0x443837 MOV %RCX,(%R10,%R12,8) |
(979) 0x44383b INC %R12 |
(979) 0x44383e ADD $0x8,%RAX |
(979) 0x443842 CMP %R12,%RSI |
(979) 0x443845 JNE 443830 |
(963) 0x443847 JMP 443880 |
0x443849 NOPL (%RAX) |
(963) 0x443850 SAL $0x3,%R8 |
(963) 0x443854 MOV -0xc0(%RBP),%RAX |
(963) 0x44385b ADD (%RAX,%RDX,8),%R8 |
(963) 0x44385f NOP |
(977) 0x443860 MOV (%R8),%RAX |
(977) 0x443863 MOV %R12,(%R15,%RAX,8) |
(977) 0x443867 MOVQ $0,(%R13,%R12,8) |
(977) 0x443870 MOV %RAX,(%R10,%R12,8) |
(977) 0x443874 INC %R12 |
(977) 0x443877 ADD $0x8,%R8 |
(977) 0x44387b CMP %R12,%RCX |
(977) 0x44387e JNE 443860 |
(963) 0x443880 MOV -0xd8(%RBP),%RCX |
(963) 0x443887 MOV (%RCX,%R9,8),%RAX |
(963) 0x44388b MOV 0x8(%RCX,%R9,8),%RCX |
(963) 0x443890 CMP %RCX,%RAX |
(963) 0x443893 MOV -0x30(%RBP),%R12 |
(963) 0x443897 JGE 4438e0 |
(963) 0x443899 MOV -0x60(%RBP),%RDX |
(963) 0x44389d MOV (%RDX),%RDX |
(963) 0x4438a0 DEC %RDX |
(963) 0x4438a3 MOV -0x188(%RBP),%RDI |
(963) 0x4438aa JMP 4438b8 |
0x4438ac NOPL (%RAX) |
(976) 0x4438b0 INC %RAX |
(976) 0x4438b3 CMP %RCX,%RAX |
(976) 0x4438b6 JGE 4438e0 |
(976) 0x4438b8 MOV -0x178(%RBP),%RSI |
(976) 0x4438bf MOV (%RSI,%RAX,8),%RSI |
(976) 0x4438c3 CMP %RDX,(%RDI,%RSI,8) |
(976) 0x4438c7 JNE 4438b0 |
(976) 0x4438c9 MOV -0x80(%RBP),%RCX |
(976) 0x4438cd MOV %R9,(%RCX,%RSI,8) |
(976) 0x4438d1 MOV -0xd8(%RBP),%RCX |
(976) 0x4438d8 MOV 0x8(%RCX,%R9,8),%RCX |
(976) 0x4438dd JMP 4438b0 |
0x4438df NOP |
(963) 0x4438e0 MOV -0xe0(%RBP),%RCX |
(963) 0x4438e7 MOV (%RCX,%R9,8),%RAX |
(963) 0x4438eb MOV 0x8(%RCX,%R9,8),%RCX |
(963) 0x4438f0 CMP %RCX,%RAX |
(963) 0x4438f3 JGE 443940 |
(963) 0x4438f5 MOV -0x60(%RBP),%RDX |
(963) 0x4438f9 MOV (%RDX),%RDX |
(963) 0x4438fc DEC %RDX |
(963) 0x4438ff MOV -0x190(%RBP),%RDI |
(963) 0x443906 JMP 443918 |
0x443908 NOPL (%RAX,%RAX,1) |
(975) 0x443910 INC %RAX |
(975) 0x443913 CMP %RCX,%RAX |
(975) 0x443916 JGE 443940 |
(975) 0x443918 MOV -0x180(%RBP),%RSI |
(975) 0x44391f MOV (%RSI,%RAX,8),%RSI |
(975) 0x443923 CMP %RDX,(%RDI,%RSI,8) |
(975) 0x443927 JNE 443910 |
(975) 0x443929 MOV -0x78(%RBP),%RCX |
(975) 0x44392d MOV %R9,(%RCX,%RSI,8) |
(975) 0x443931 MOV -0xe0(%RBP),%RCX |
(975) 0x443938 MOV 0x8(%RCX,%R9,8),%RCX |
(975) 0x44393d JMP 443910 |
0x44393f NOP |
(963) 0x443940 MOV -0x100(%RBP),%RAX |
(963) 0x443947 MOV (%RAX,%R9,8),%RCX |
(963) 0x44394b MOV 0x8(%RAX,%R9,8),%R11 |
(963) 0x443950 MOV %RCX,%RAX |
(963) 0x443953 MOV %RCX,-0x40(%RBP) |
(963) 0x443957 LEA 0x1(%RCX),%RDX |
(963) 0x44395b VXORPD %XMM1,%XMM1,%XMM1 |
(963) 0x44395f VXORPD %XMM0,%XMM0,%XMM0 |
(963) 0x443963 CMP %R11,%RDX |
(963) 0x443966 JGE 443ca0 |
(963) 0x44396c MOV -0x50(%RBP),%RAX |
(963) 0x443970 MOV %R11,-0x70(%RBP) |
(963) 0x443974 MOV -0x30(%RBP),%RCX |
(963) 0x443978 JMP 443994 |
0x44397a NOPW (%RAX,%RAX,1) |
(970) 0x443980 MOV -0x50(%RBP),%RAX |
(970) 0x443984 MOV -0x48(%RBP),%R9 |
(970) 0x443988 INC %RDX |
(970) 0x44398b CMP %R11,%RDX |
(970) 0x44398e JE 443ca0 |
(970) 0x443994 MOV -0x168(%RBP),%RSI |
(970) 0x44399b MOV (%RSI,%RDX,8),%RSI |
(970) 0x44399f MOV -0x80(%RBP),%RDI |
(970) 0x4439a3 CMP %R9,(%RDI,%RSI,8) |
(970) 0x4439a7 JNE 4439d0 |
(970) 0x4439a9 MOV -0xa8(%RBP),%R8 |
(970) 0x4439b0 MOV (%R8,%RSI,8),%RDI |
(970) 0x4439b4 MOV 0x8(%R8,%RSI,8),%R8 |
(970) 0x4439b9 MOV %R8,%R9 |
(970) 0x4439bc SUB %RDI,%R9 |
(970) 0x4439bf JLE 443b1f |
(970) 0x4439c5 CMP $0x4,%R9 |
(970) 0x4439c9 JAE 443a00 |
(970) 0x4439cb JMP 443ac5 |
(970) 0x4439d0 MOV -0x150(%RBP),%RDI |
(970) 0x4439d7 CMPQ $-0x3,(%RDI,%RSI,8) |
(970) 0x4439dc JE 443988 |
(970) 0x4439de CMPQ $0x1,-0xe8(%RBP) |
(970) 0x4439e6 JE 4439f9 |
(970) 0x4439e8 MOV -0xc8(%RBP),%R8 |
(970) 0x4439ef MOV (%R8,%R9,8),%RDI |
(970) 0x4439f3 CMP (%R8,%RSI,8),%RDI |
(970) 0x4439f7 JNE 443988 |
(970) 0x4439f9 VADDSD (%RBX,%RDX,8),%XMM0,%XMM0 |
(970) 0x4439fe JMP 443988 |
(970) 0x443a00 MOV %R9,%R10 |
(970) 0x443a03 SHR $0x2,%R10 |
(970) 0x443a07 LEA 0x18(,%RDI,8),%R11 |
(970) 0x443a0f NOP |
(973) 0x443a10 MOV -0x18(%RAX,%R11,1),%R12 |
(973) 0x443a15 VMOVSD -0x18(%R14,%R11,1),%XMM2 |
(973) 0x443a1c VMOVSD (%RBX,%RDX,8),%XMM3 |
(973) 0x443a21 MOV (%RCX,%R12,8),%R12 |
(973) 0x443a25 VMOVSD (%R14,%R12,8),%XMM4 |
(973) 0x443a2b VFMADD231SD %XMM2,%XMM3,%XMM4 |
(973) 0x443a30 VMOVSD %XMM4,(%R14,%R12,8) |
(973) 0x443a36 MOV -0x10(%RAX,%R11,1),%R12 |
(973) 0x443a3b VMOVSD -0x10(%R14,%R11,1),%XMM4 |
(973) 0x443a42 VMOVSD (%RBX,%RDX,8),%XMM5 |
(973) 0x443a47 MOV (%RCX,%R12,8),%R12 |
(973) 0x443a4b VMOVSD (%R14,%R12,8),%XMM6 |
(973) 0x443a51 VFMADD231SD %XMM4,%XMM5,%XMM6 |
(973) 0x443a56 VMOVSD %XMM6,(%R14,%R12,8) |
(973) 0x443a5c MOV -0x8(%RAX,%R11,1),%R12 |
(973) 0x443a61 VMOVSD -0x8(%R14,%R11,1),%XMM6 |
(973) 0x443a68 VMOVSD (%RBX,%RDX,8),%XMM7 |
(973) 0x443a6d MOV (%RCX,%R12,8),%R12 |
(973) 0x443a71 VMOVSD (%R14,%R12,8),%XMM8 |
(973) 0x443a77 VFMADD231SD %XMM6,%XMM7,%XMM8 |
(973) 0x443a7c VMOVSD %XMM8,(%R14,%R12,8) |
(973) 0x443a82 VMOVSD (%R14,%R11,1),%XMM8 |
(973) 0x443a88 VMULSD (%RBX,%RDX,8),%XMM8,%XMM10 |
(973) 0x443a8d MOV (%RAX,%R11,1),%R12 |
(973) 0x443a91 MOV (%RCX,%R12,8),%R12 |
(973) 0x443a95 VADDSD (%R14,%R12,8),%XMM10,%XMM8 |
(973) 0x443a9b VMOVSD %XMM8,(%R14,%R12,8) |
(973) 0x443aa1 VFMADD213SD %XMM10,%XMM5,%XMM4 |
(973) 0x443aa6 VFMADD231SD %XMM2,%XMM3,%XMM4 |
(973) 0x443aab VFMADD231SD %XMM6,%XMM7,%XMM4 |
(973) 0x443ab0 VADDSD %XMM1,%XMM4,%XMM1 |
(973) 0x443ab4 VADDSD %XMM0,%XMM4,%XMM0 |
(973) 0x443ab8 ADD $0x20,%R11 |
(973) 0x443abc DEC %R10 |
(973) 0x443abf JNE 443a10 |
(970) 0x443ac5 MOV %R9,%R10 |
(970) 0x443ac8 AND $-0x4,%R10 |
(970) 0x443acc CMP %R9,%R10 |
(970) 0x443acf MOV -0x70(%RBP),%R11 |
(970) 0x443ad3 JNE 443adf |
(970) 0x443ad5 MOV -0x38(%RBP),%R10 |
(970) 0x443ad9 MOV -0x30(%RBP),%R12 |
(970) 0x443add JMP 443b1f |
(970) 0x443adf ADD %R10,%RDI |
(970) 0x443ae2 MOV -0x38(%RBP),%R10 |
(970) 0x443ae6 MOV -0x30(%RBP),%R12 |
(970) 0x443aea NOPW (%RAX,%RAX,1) |
(974) 0x443af0 MOV (%RAX,%RDI,8),%R9 |
(974) 0x443af4 VMOVSD (%R14,%RDI,8),%XMM2 |
(974) 0x443afa VMULSD (%RBX,%RDX,8),%XMM2,%XMM10 |
(974) 0x443aff MOV (%R12,%R9,8),%R9 |
(974) 0x443b03 VADDSD (%R14,%R9,8),%XMM10,%XMM2 |
(974) 0x443b09 VMOVSD %XMM2,(%R14,%R9,8) |
(974) 0x443b0f VADDSD %XMM1,%XMM10,%XMM1 |
(974) 0x443b13 VADDSD %XMM0,%XMM10,%XMM0 |
(974) 0x443b17 INC %RDI |
(974) 0x443b1a CMP %RDI,%R8 |
(974) 0x443b1d JNE 443af0 |
(970) 0x443b1f MOV -0xb0(%RBP),%RAX |
(970) 0x443b26 MOV (%RAX,%RSI,8),%RDI |
(970) 0x443b2a MOV 0x8(%RAX,%RSI,8),%RSI |
(970) 0x443b2f MOV %RSI,%R8 |
(970) 0x443b32 SUB %RDI,%R8 |
(970) 0x443b35 JLE 443980 |
(970) 0x443b3b CMP $0x4,%R8 |
(970) 0x443b3f JAE 443b46 |
(970) 0x443b41 JMP 443c1e |
(970) 0x443b46 MOV %R8,%R9 |
(970) 0x443b49 SHR $0x2,%R9 |
(970) 0x443b4d LEA 0x18(,%RDI,8),%R10 |
(970) 0x443b55 MOV -0x38(%RBP),%RAX |
(970) 0x443b59 NOPL (%RAX) |
(971) 0x443b60 MOV -0x18(%RAX,%R10,1),%R11 |
(971) 0x443b65 VMOVSD -0x18(%R13,%R10,1),%XMM2 |
(971) 0x443b6c VMOVSD (%RBX,%RDX,8),%XMM3 |
(971) 0x443b71 MOV (%R15,%R11,8),%R11 |
(971) 0x443b75 VMOVSD (%R13,%R11,8),%XMM4 |
(971) 0x443b7c VFMADD231SD %XMM2,%XMM3,%XMM4 |
(971) 0x443b81 VMOVSD %XMM4,(%R13,%R11,8) |
(971) 0x443b88 MOV -0x10(%RAX,%R10,1),%R11 |
(971) 0x443b8d VMOVSD -0x10(%R13,%R10,1),%XMM4 |
(971) 0x443b94 VMOVSD (%RBX,%RDX,8),%XMM5 |
(971) 0x443b99 MOV (%R15,%R11,8),%R11 |
(971) 0x443b9d VMOVSD (%R13,%R11,8),%XMM6 |
(971) 0x443ba4 VFMADD231SD %XMM4,%XMM5,%XMM6 |
(971) 0x443ba9 VMOVSD %XMM6,(%R13,%R11,8) |
(971) 0x443bb0 MOV -0x8(%RAX,%R10,1),%R11 |
(971) 0x443bb5 VMOVSD -0x8(%R13,%R10,1),%XMM6 |
(971) 0x443bbc VMOVSD (%RBX,%RDX,8),%XMM7 |
(971) 0x443bc1 MOV (%R15,%R11,8),%R11 |
(971) 0x443bc5 VMOVSD (%R13,%R11,8),%XMM8 |
(971) 0x443bcc VFMADD231SD %XMM6,%XMM7,%XMM8 |
(971) 0x443bd1 VMOVSD %XMM8,(%R13,%R11,8) |
(971) 0x443bd8 VMOVSD (%R13,%R10,1),%XMM8 |
(971) 0x443bdf VMULSD (%RBX,%RDX,8),%XMM8,%XMM10 |
(971) 0x443be4 MOV (%RAX,%R10,1),%R11 |
(971) 0x443be8 MOV (%R15,%R11,8),%R11 |
(971) 0x443bec VADDSD (%R13,%R11,8),%XMM10,%XMM8 |
(971) 0x443bf3 VMOVSD %XMM8,(%R13,%R11,8) |
(971) 0x443bfa VFMADD213SD %XMM10,%XMM5,%XMM4 |
(971) 0x443bff VFMADD231SD %XMM2,%XMM3,%XMM4 |
(971) 0x443c04 VFMADD231SD %XMM6,%XMM7,%XMM4 |
(971) 0x443c09 VADDSD %XMM1,%XMM4,%XMM1 |
(971) 0x443c0d VADDSD %XMM0,%XMM4,%XMM0 |
(971) 0x443c11 ADD $0x20,%R10 |
(971) 0x443c15 DEC %R9 |
(971) 0x443c18 JNE 443b60 |
(970) 0x443c1e MOV %R8,%R9 |
(970) 0x443c21 AND $-0x4,%R9 |
(970) 0x443c25 CMP %R8,%R9 |
(970) 0x443c28 JNE 443c3f |
(970) 0x443c2a MOV -0x38(%RBP),%R10 |
(970) 0x443c2e MOV -0x50(%RBP),%RAX |
(970) 0x443c32 MOV -0x48(%RBP),%R9 |
(970) 0x443c36 MOV -0x70(%RBP),%R11 |
(970) 0x443c3a JMP 443988 |
(970) 0x443c3f ADD %R9,%RDI |
(970) 0x443c42 MOV -0x38(%RBP),%R10 |
(970) 0x443c46 MOV -0x50(%RBP),%RAX |
(970) 0x443c4a MOV -0x48(%RBP),%R9 |
(970) 0x443c4e MOV -0x70(%RBP),%R11 |
(970) 0x443c52 NOPW %CS:(%RAX,%RAX,1) |
(972) 0x443c60 MOV (%R10,%RDI,8),%R8 |
(972) 0x443c64 VMOVSD (%R13,%RDI,8),%XMM2 |
(972) 0x443c6b VMULSD (%RBX,%RDX,8),%XMM2,%XMM10 |
(972) 0x443c70 MOV (%R15,%R8,8),%R8 |
(972) 0x443c74 VADDSD (%R13,%R8,8),%XMM10,%XMM2 |
(972) 0x443c7b VMOVSD %XMM2,(%R13,%R8,8) |
(972) 0x443c82 VADDSD %XMM1,%XMM10,%XMM1 |
(972) 0x443c86 VADDSD %XMM0,%XMM10,%XMM0 |
(972) 0x443c8a INC %RDI |
(972) 0x443c8d CMP %RDI,%RSI |
(972) 0x443c90 JNE 443c60 |
(970) 0x443c92 JMP 443988 |
0x443c97 NOPW (%RAX,%RAX,1) |
(963) 0x443ca0 MOV -0x108(%RBP),%RAX |
(963) 0x443ca7 MOV (%RAX,%R9,8),%RCX |
(963) 0x443cab MOV 0x8(%RAX,%R9,8),%RDX |
(963) 0x443cb0 CMP %RDX,%RCX |
(963) 0x443cb3 JL 443d5a |
(963) 0x443cb9 MOV -0x40(%RBP),%RAX |
(963) 0x443cbd VMULSD (%RBX,%RAX,8),%XMM1,%XMM1 |
(963) 0x443cc2 VUCOMISD %XMM9,%XMM1 |
(963) 0x443cc7 JE 443cd7 |
(963) 0x443cc9 VXORPD 0xbb40d(%RIP){1to2},%XMM0,%XMM0 |
(963) 0x443cd3 VDIVSD %XMM1,%XMM0,%XMM10 |
(963) 0x443cd7 MOV -0xa8(%RBP),%RAX |
(963) 0x443cde MOV (%RAX,%R9,8),%RDX |
(963) 0x443ce2 MOV 0x8(%RAX,%R9,8),%RAX |
(963) 0x443ce7 MOV %RAX,%RSI |
(963) 0x443cea SUB %RDX,%RSI |
(963) 0x443ced JLE 443e94 |
(963) 0x443cf3 MOV %RSI,%RCX |
(963) 0x443cf6 AND $-0x4,%RCX |
(963) 0x443cfa JE 443e7a |
(963) 0x443d00 LEA -0x1(%RCX),%RDI |
(963) 0x443d04 VBROADCASTSD %XMM10,%YMM0 |
(963) 0x443d09 LEA (%R14,%RDX,8),%R8 |
(963) 0x443d0d XOR %R9D,%R9D |
(967) 0x443d10 VMULPD (%R8,%R9,8),%YMM0,%YMM1 |
(967) 0x443d16 VMOVUPD %YMM1,(%R8,%R9,8) |
(967) 0x443d1c ADD $0x4,%R9 |
(967) 0x443d20 CMP %RDI,%R9 |
(967) 0x443d23 JBE 443d10 |
(963) 0x443d25 CMP %RCX,%RSI |
(963) 0x443d28 MOV -0x48(%RBP),%R9 |
(963) 0x443d2c JNE 443e7c |
(963) 0x443d32 JMP 443e94 |
0x443d37 NOPW (%RAX,%RAX,1) |
(968) 0x443d40 MOV %R12,%R11 |
(968) 0x443d43 INC %RCX |
(968) 0x443d46 CMP %RDX,%RCX |
(968) 0x443d49 MOV -0x38(%RBP),%R10 |
(968) 0x443d4d MOV %R11,%R12 |
(968) 0x443d50 MOV -0x48(%RBP),%R9 |
(968) 0x443d54 JE 443cb9 |
(968) 0x443d5a MOV -0x170(%RBP),%RAX |
(968) 0x443d61 LEA (%RAX,%RCX,8),%RSI |
(968) 0x443d65 CMPQ $0,-0x198(%RBP) |
(968) 0x443d6d JE 443d7d |
(968) 0x443d6f MOV (%RSI),%RSI |
(968) 0x443d72 MOV -0x158(%RBP),%RDI |
(968) 0x443d79 LEA (%RDI,%RSI,8),%RSI |
(968) 0x443d7d MOV (%RSI),%RDI |
(968) 0x443d80 TEST %RDI,%RDI |
(968) 0x443d83 JS 443e30 |
(968) 0x443d89 MOV -0x78(%RBP),%RSI |
(968) 0x443d8d CMP %R9,(%RSI,%RDI,8) |
(968) 0x443d91 JNE 443e30 |
(968) 0x443d97 MOV -0x148(%RBP),%RSI |
(968) 0x443d9e MOV 0x8(%RSI,%RDI,8),%RSI |
(968) 0x443da3 TEST %RSI,%RSI |
(968) 0x443da6 JLE 443e71 |
(968) 0x443dac MOV -0x130(%RBP),%R8 |
(968) 0x443db3 MOV (%R8,%RDI,8),%RDI |
(968) 0x443db7 ADD %RDI,%RSI |
(968) 0x443dba MOV -0x60(%RBP),%R8 |
(968) 0x443dbe MOV (%R8),%R8 |
(968) 0x443dc1 MOV -0x138(%RBP),%R9 |
(968) 0x443dc8 MOV (%R9,%R8,8),%R8 |
(968) 0x443dcc MOV -0xd0(%RBP),%R12 |
(968) 0x443dd3 MOV -0x30(%RBP),%R11 |
(968) 0x443dd7 MOV -0x140(%RBP),%RAX |
(968) 0x443dde XCHG %AX,%AX |
(969) 0x443de0 MOV (%R8,%RDI,8),%R9 |
(969) 0x443de4 VMOVSD (%RAX,%RDI,8),%XMM2 |
(969) 0x443de9 VMULSD (%R12,%RCX,8),%XMM2,%XMM10 |
(969) 0x443def TEST %R9,%R9 |
(969) 0x443df2 LEA (%R15,%R9,8),%R10 |
(969) 0x443df6 NOT %R9 |
(969) 0x443df9 LEA (%R11,%R9,8),%R9 |
(969) 0x443dfd CMOVNS %R10,%R9 |
(969) 0x443e01 MOV %R13,%R10 |
(969) 0x443e04 CMOVS %R14,%R10 |
(969) 0x443e08 MOV (%R9),%R9 |
(969) 0x443e0b VADDSD (%R10,%R9,8),%XMM10,%XMM2 |
(969) 0x443e11 VMOVSD %XMM2,(%R10,%R9,8) |
(969) 0x443e17 VADDSD %XMM1,%XMM10,%XMM1 |
(969) 0x443e1b VADDSD %XMM0,%XMM10,%XMM0 |
(969) 0x443e1f INC %RDI |
(969) 0x443e22 CMP %RSI,%RDI |
(969) 0x443e25 JL 443de0 |
(968) 0x443e27 JMP 443d43 |
0x443e2c NOPL (%RAX) |
(968) 0x443e30 MOV -0x160(%RBP),%RSI |
(968) 0x443e37 CMPQ $-0x3,(%RSI,%RDI,8) |
(968) 0x443e3c JE 443d40 |
(968) 0x443e42 CMPQ $0x1,-0xe8(%RBP) |
(968) 0x443e4a MOV -0xd0(%RBP),%R8 |
(968) 0x443e51 JE 443e6b |
(968) 0x443e53 MOV -0x128(%RBP),%RSI |
(968) 0x443e5a MOV (%RSI,%RDI,8),%RSI |
(968) 0x443e5e MOV -0xc8(%RBP),%RDI |
(968) 0x443e65 CMP (%RDI,%R9,8),%RSI |
(968) 0x443e69 JNE 443e71 |
(968) 0x443e6b VADDSD (%R8,%RCX,8),%XMM0,%XMM0 |
(968) 0x443e71 MOV -0x30(%RBP),%R11 |
(968) 0x443e75 JMP 443d43 |
(963) 0x443e7a XOR %ECX,%ECX |
(963) 0x443e7c ADD %RDX,%RCX |
(963) 0x443e7f NOP |
(966) 0x443e80 VMULSD (%R14,%RCX,8),%XMM10,%XMM0 |
(966) 0x443e86 VMOVSD %XMM0,(%R14,%RCX,8) |
(966) 0x443e8c INC %RCX |
(966) 0x443e8f CMP %RCX,%RAX |
(966) 0x443e92 JNE 443e80 |
(963) 0x443e94 MOV -0xb0(%RBP),%RAX |
(963) 0x443e9b MOV (%RAX,%R9,8),%RDX |
(963) 0x443e9f MOV 0x8(%RAX,%R9,8),%RAX |
(963) 0x443ea4 MOV %RAX,%RSI |
(963) 0x443ea7 SUB %RDX,%RSI |
(963) 0x443eaa JLE 443470 |
(963) 0x443eb0 MOV %RSI,%RCX |
(963) 0x443eb3 AND $-0x4,%RCX |
(963) 0x443eb7 JE 443ef0 |
(963) 0x443eb9 LEA -0x1(%RCX),%RDI |
(963) 0x443ebd VBROADCASTSD %XMM10,%YMM0 |
(963) 0x443ec2 LEA (%R13,%RDX,8),%R8 |
(963) 0x443ec7 XOR %R9D,%R9D |
(963) 0x443eca NOPW (%RAX,%RAX,1) |
(965) 0x443ed0 VMULPD (%R8,%R9,8),%YMM0,%YMM1 |
(965) 0x443ed6 VMOVUPD %YMM1,(%R8,%R9,8) |
(965) 0x443edc ADD $0x4,%R9 |
(965) 0x443ee0 CMP %RDI,%R9 |
(965) 0x443ee3 JBE 443ed0 |
(963) 0x443ee5 CMP %RCX,%RSI |
(963) 0x443ee8 JE 443470 |
(963) 0x443eee JMP 443ef2 |
(963) 0x443ef0 XOR %ECX,%ECX |
(963) 0x443ef2 ADD %RDX,%RCX |
(963) 0x443ef5 NOPW %CS:(%RAX,%RAX,1) |
(964) 0x443f00 VMULSD (%R13,%RCX,8),%XMM10,%XMM0 |
(964) 0x443f07 VMOVSD %XMM0,(%R13,%RCX,8) |
(964) 0x443f0e INC %RCX |
(964) 0x443f11 CMP %RCX,%RAX |
(964) 0x443f14 JNE 443f00 |
(963) 0x443f16 JMP 443470 |
0x443f1b MOV -0x80(%RBP),%RDI |
0x443f1f VZEROUPPER |
0x443f22 CALL 4e6a60 <hypre_Free> |
0x443f27 MOV -0x78(%RBP),%RDI |
0x443f2b CALL 4e6a60 <hypre_Free> |
0x443f30 MOV %R12,%RDI |
0x443f33 CALL 4e6a60 <hypre_Free> |
0x443f38 MOV %R15,%RDI |
0x443f3b ADD $0x178,%RSP |
0x443f42 POP %RBX |
0x443f43 POP %R12 |
0x443f45 POP %R13 |
0x443f47 POP %R14 |
0x443f49 POP %R15 |
0x443f4b POP %RBP |
0x443f4c JMP 4e6a60 |
0x443f51 NOPW %CS:(%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 206 |
nb uops | 225 |
loop length | 973 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 80 |
micro-operation queue | 37.50 cycles |
front end | 37.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.90 | 8.80 | 20.67 | 20.67 | 33.00 | 8.80 | 8.70 | 33.00 | 33.00 | 33.00 | 8.80 | 20.67 |
cycles | 8.90 | 12.20 | 20.67 | 20.67 | 33.00 | 8.80 | 8.70 | 33.00 | 33.00 | 33.00 | 8.80 | 20.67 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 35.24-35.30 |
Stall cycles | 0.00 |
Front-end | 37.50 |
Dispatch | 33.00 |
DIV/SQRT | 16.00 |
Overall L1 | 37.50 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0x198(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x150(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x138(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x130(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x140(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x190(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x188(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x100(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x158(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x148(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x138(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x160(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x180(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x170(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x168(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %RDI,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 443347 <hypre_BoomerAMGBuildMultipass.extracted.28+0x227> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R12,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 443359 <hypre_BoomerAMGBuildMultipass.extracted.28+0x239> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 443368 <hypre_BoomerAMGBuildMultipass.extracted.28+0x248> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 44336b <hypre_BoomerAMGBuildMultipass.extracted.28+0x24b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R12,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 44331e <hypre_BoomerAMGBuildMultipass.extracted.28+0x1fe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 443338 <hypre_BoomerAMGBuildMultipass.extracted.28+0x218> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RAX,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4433a1 <hypre_BoomerAMGBuildMultipass.extracted.28+0x281> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4433bf <hypre_BoomerAMGBuildMultipass.extracted.28+0x29f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x78(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 4e86c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4e86b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RAX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 4433f9 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 443400 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2e0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x70(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R9,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R9),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %R8,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 443f1b <hypre_BoomerAMGBuildMultipass.extracted.28+0xdfb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x38,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x38(%R10),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM9,%XMM9,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 443484 <hypre_BoomerAMGBuildMultipass.extracted.28+0x364> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x78(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4e6a60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 206 |
nb uops | 225 |
loop length | 973 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 80 |
micro-operation queue | 37.50 cycles |
front end | 37.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.90 | 8.80 | 20.67 | 20.67 | 33.00 | 8.80 | 8.70 | 33.00 | 33.00 | 33.00 | 8.80 | 20.67 |
cycles | 8.90 | 12.20 | 20.67 | 20.67 | 33.00 | 8.80 | 8.70 | 33.00 | 33.00 | 33.00 | 8.80 | 20.67 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 35.24-35.30 |
Stall cycles | 0.00 |
Front-end | 37.50 |
Dispatch | 33.00 |
DIV/SQRT | 16.00 |
Overall L1 | 37.50 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0x198(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x150(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x138(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x130(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x140(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x190(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x188(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x100(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x158(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x148(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x138(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x120(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x118(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x128(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x160(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x130(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x180(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x170(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x168(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %RDI,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 443347 <hypre_BoomerAMGBuildMultipass.extracted.28+0x227> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R12,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 443359 <hypre_BoomerAMGBuildMultipass.extracted.28+0x239> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 443368 <hypre_BoomerAMGBuildMultipass.extracted.28+0x248> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 44336b <hypre_BoomerAMGBuildMultipass.extracted.28+0x24b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R12,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 44331e <hypre_BoomerAMGBuildMultipass.extracted.28+0x1fe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 443338 <hypre_BoomerAMGBuildMultipass.extracted.28+0x218> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RAX,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4433a1 <hypre_BoomerAMGBuildMultipass.extracted.28+0x281> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4433bf <hypre_BoomerAMGBuildMultipass.extracted.28+0x29f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x78(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 4e86c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4e86b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RAX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 4433f9 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 443400 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2e0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x70(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R9,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R9),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %R8,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 443f1b <hypre_BoomerAMGBuildMultipass.extracted.28+0xdfb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x38,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x38(%R10),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM9,%XMM9,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 443484 <hypre_BoomerAMGBuildMultipass.extracted.28+0x364> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x78(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x178,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4e6a60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass.extracted.28– | 1.19 | 0.24 |
▼Loop 963 - par_multi_interp.c:1747-1876 - exec– | 0.13 | 0.02 |
▼Loop 970 - par_multi_interp.c:1747-1837 - exec– | 0.43 | 0.08 |
○Loop 974 - par_multi_interp.c:1816-1822 - exec | 0.24 | 0.05 |
○Loop 973 - par_multi_interp.c:1816-1820 - exec | 0 | 0 |
○Loop 971 - par_multi_interp.c:1824-1828 - exec | 0 | 0 |
○Loop 972 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 976 - par_multi_interp.c:1799-1803 - exec | 0.37 | 0.07 |
○Loop 980 - par_multi_interp.c:1782-1787 - exec | 0.02 | 0 |
▼Loop 968 - par_multi_interp.c:1747-1867 - exec– | 0 | 0 |
○Loop 969 - par_multi_interp.c:1851-1860 - exec | 0 | 0 |
○Loop 967 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |
○Loop 964 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
○Loop 977 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 966 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |
○Loop 981 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |
○Loop 975 - par_multi_interp.c:1805-1809 - exec | 0 | 0 |
○Loop 982 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |
○Loop 978 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 965 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
○Loop 979 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |