Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: libparcsr_ls.so | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.38% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: libparcsr_ls.so | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.38% |
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/scratch_na/users/xoserete/qaas_runs/171-415-3872/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1584: tmp_marker = NULL; |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
1600: { thread_stop = pass_pointer[1] + pass_length; } |
1601: else |
1602: { thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); } |
1603: |
1604: /* determine P for points of pass 1, i.e. neighbors of coarse points */ |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x8c420 PUSH %RBP |
0x8c421 MOV %RSP,%RBP |
0x8c424 PUSH %R15 |
0x8c426 PUSH %R14 |
0x8c428 PUSH %R13 |
0x8c42a PUSH %R12 |
0x8c42c PUSH %RBX |
0x8c42d AND $-0x40,%RSP |
0x8c431 SUB $0x100,%RSP |
0x8c438 MOV 0xf8(%RDI),%RAX |
0x8c43f MOV 0xf0(%RDI),%RDX |
0x8c446 MOV 0xe0(%RDI),%RCX |
0x8c44d MOV 0xd8(%RDI),%RSI |
0x8c454 MOV 0xd0(%RDI),%R8 |
0x8c45b MOV 0xc8(%RDI),%R9 |
0x8c462 MOV %RAX,0xf8(%RSP) |
0x8c46a MOV 0xc0(%RDI),%R10 |
0x8c471 MOV 0xb0(%RDI),%R12 |
0x8c478 MOV %RDX,0x98(%RSP) |
0x8c480 MOV 0xa8(%RDI),%R13 |
0x8c487 MOV 0x90(%RDI),%RAX |
0x8c48e MOV %RCX,0x8(%RSP) |
0x8c493 MOV 0xb8(%RDI),%R11 |
0x8c49a MOV 0xe8(%RDI),%RBX |
0x8c4a1 MOV %RSI,0x90(%RSP) |
0x8c4a9 MOV %R8,0x28(%RSP) |
0x8c4ae MOV 0xa0(%RDI),%R14 |
0x8c4b5 MOV %R9,0x20(%RSP) |
0x8c4ba MOV 0x98(%RDI),%R15 |
0x8c4c1 MOV %R10,0x60(%RSP) |
0x8c4c6 MOV %R12,0xc8(%RSP) |
0x8c4ce MOV %R13,0x70(%RSP) |
0x8c4d3 MOV %RAX,0xb0(%RSP) |
0x8c4db MOV %R11,0x58(%RSP) |
0x8c4e0 MOV 0x88(%RDI),%R11 |
0x8c4e7 MOV 0x80(%RDI),%RDX |
0x8c4ee MOV 0x78(%RDI),%RCX |
0x8c4f2 MOV 0x70(%RDI),%RSI |
0x8c4f6 MOV 0x68(%RDI),%R8 |
0x8c4fa MOV 0x60(%RDI),%R9 |
0x8c4fe MOV 0x58(%RDI),%R10 |
0x8c502 MOV %RDX,0x88(%RSP) |
0x8c50a MOV 0x40(%RDI),%RAX |
0x8c50e MOV 0x38(%RDI),%RDX |
0x8c512 MOV %RCX,0x50(%RSP) |
0x8c517 MOV 0x50(%RDI),%R12 |
0x8c51b MOV 0x28(%RDI),%RCX |
0x8c51f MOV %RSI,0xd8(%RSP) |
0x8c527 MOV 0x48(%RDI),%R13 |
0x8c52b MOV 0x20(%RDI),%RSI |
0x8c52f MOV %R8,0x80(%RSP) |
0x8c537 MOV %R9,0x48(%RSP) |
0x8c53c MOV 0x18(%RDI),%R8 |
0x8c540 MOV 0x10(%RDI),%R9 |
0x8c544 MOV %R10,0xd0(%RSP) |
0x8c54c MOV %RAX,0x40(%RSP) |
0x8c551 MOV 0x30(%RDI),%R10 |
0x8c555 MOV 0x8(%RDI),%RAX |
0x8c559 MOV (%RDI),%RDI |
0x8c55c MOV %RDX,0xe0(%RSP) |
0x8c564 MOV %RCX,0x38(%RSP) |
0x8c569 MOV %RSI,0xf0(%RSP) |
0x8c571 MOV %R8,0x18(%RSP) |
0x8c576 MOV %R9,0xc0(%RSP) |
0x8c57e MOV %RAX,0xe8(%RSP) |
0x8c586 MOV %RDI,0x10(%RSP) |
0x8c58b TEST %RBX,%RBX |
0x8c58e JNE 8d1ef |
0x8c594 TEST %R12,%R12 |
0x8c597 JNE 8d360 |
0x8c59d XOR %EBX,%EBX |
0x8c59f XOR %R12D,%R12D |
0x8c5a2 MOV %R10,0x78(%RSP) |
0x8c5a7 MOV %R11,0xa0(%RSP) |
0x8c5af VMOVSD %XMM1,0xa8(%RSP) |
0x8c5b8 CALL c990 <hypre_GetThreadNum@plt> |
0x8c5bd MOV %RAX,0xb8(%RSP) |
0x8c5c5 CALL cae0 <hypre_NumActiveThreads@plt> |
0x8c5ca MOV 0xb8(%RSP),%R11 |
0x8c5d2 MOV 0xc8(%RSP),%R8 |
0x8c5da MOV %RAX,%RSI |
0x8c5dd MOV 0xf8(%RSP),%RAX |
0x8c5e5 VMOVSD 0xa8(%RSP),%XMM11 |
0x8c5ee MOV %R11,%RCX |
0x8c5f1 MOV 0x8(%R8),%R9 |
0x8c5f5 MOV 0x78(%RSP),%R10 |
0x8c5fa CQTO |
0x8c5fc MOV 0xa0(%RSP),%R8 |
0x8c604 IDIV %RSI |
0x8c607 DEC %RSI |
0x8c60a IMUL %RAX,%RCX |
0x8c60e ADD %RCX,%RAX |
0x8c611 LEA (%R9,%RCX,1),%RDI |
0x8c615 MOV 0xf8(%RSP),%RCX |
0x8c61d ADD %R9,%RAX |
0x8c620 ADD %R9,%RCX |
0x8c623 CMP %RSI,%R11 |
0x8c626 CMOVNE %RAX,%RCX |
0x8c62a CMP %RDI,%RCX |
0x8c62d JLE 8cfe0 |
0x8c633 MOV 0x70(%RSP),%R9 |
0x8c638 VMOVQ 0xab200(%RIP),%XMM5 |
0x8c640 MOV %R10,%R11 |
0x8c643 VXORPD %XMM4,%XMM4,%XMM4 |
0x8c647 MOV %R8,%R10 |
0x8c64a LEA (%R9,%RDI,8),%RSI |
0x8c64e LEA (%R9,%RCX,8),%RAX |
0x8c652 MOV %RSI,0xc8(%RSP) |
0x8c65a MOV %RAX,0x30(%RSP) |
0x8c65f NOP |
(887) 0x8c660 MOV 0xc8(%RSP),%RDX |
(887) 0x8c668 MOV 0x58(%RSP),%RDI |
(887) 0x8c66d MOV (%RDX),%RDX |
(887) 0x8c670 MOV (%RDI,%RDX,8),%RCX |
(887) 0x8c674 MOV 0x48(%RSP),%RDI |
(887) 0x8c679 LEA (,%RDX,8),%R8 |
(887) 0x8c681 LEA 0x8(%R8),%R9 |
(887) 0x8c685 LEA (%RDI,%R8,1),%RSI |
(887) 0x8c689 MOV 0x8(%RDI,%R8,1),%RAX |
(887) 0x8c68e MOV %RSI,0xa8(%RSP) |
(887) 0x8c696 MOV (%RSI),%RSI |
(887) 0x8c699 ADD %RCX,%RAX |
(887) 0x8c69c SUB %RSI,%RAX |
(887) 0x8c69f MOV %RSI,0xf8(%RSP) |
(887) 0x8c6a7 CMP %RAX,%RCX |
(887) 0x8c6aa JGE 8c7e8 |
(887) 0x8c6b0 MOV 0x20(%RSP),%RDI |
(887) 0x8c6b5 MOV 0x8(%RDI),%RSI |
(887) 0x8c6b9 LEA (%RSI,%RAX,8),%RDI |
(887) 0x8c6bd LEA (%RSI,%RCX,8),%RCX |
(887) 0x8c6c1 MOV %RDI,%RAX |
(887) 0x8c6c4 SUB %RCX,%RAX |
(887) 0x8c6c7 SUB $0x8,%RAX |
(887) 0x8c6cb SHR $0x3,%RAX |
(887) 0x8c6cf INC %RAX |
(887) 0x8c6d2 AND $0x7,%EAX |
(887) 0x8c6d5 JE 8c76d |
(887) 0x8c6db CMP $0x1,%RAX |
(887) 0x8c6df JE 8c759 |
(887) 0x8c6e1 CMP $0x2,%RAX |
(887) 0x8c6e5 JE 8c74a |
(887) 0x8c6e7 CMP $0x3,%RAX |
(887) 0x8c6eb JE 8c73b |
(887) 0x8c6ed CMP $0x4,%RAX |
(887) 0x8c6f1 JE 8c72c |
(887) 0x8c6f3 CMP $0x5,%RAX |
(887) 0x8c6f7 JE 8c71d |
(887) 0x8c6f9 CMP $0x6,%RAX |
(887) 0x8c6fd JE 8c70e |
(887) 0x8c6ff MOV (%RCX),%RSI |
(887) 0x8c702 ADD $0x8,%RCX |
(887) 0x8c706 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c70a MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c70e MOV (%RCX),%RSI |
(887) 0x8c711 ADD $0x8,%RCX |
(887) 0x8c715 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c719 MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c71d MOV (%RCX),%RSI |
(887) 0x8c720 ADD $0x8,%RCX |
(887) 0x8c724 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c728 MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c72c MOV (%RCX),%RSI |
(887) 0x8c72f ADD $0x8,%RCX |
(887) 0x8c733 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c737 MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c73b MOV (%RCX),%RSI |
(887) 0x8c73e ADD $0x8,%RCX |
(887) 0x8c742 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c746 MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c74a MOV (%RCX),%RSI |
(887) 0x8c74d ADD $0x8,%RCX |
(887) 0x8c751 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c755 MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c759 MOV (%RCX),%RSI |
(887) 0x8c75c ADD $0x8,%RCX |
(887) 0x8c760 MOV (%R15,%RSI,8),%RAX |
(887) 0x8c764 MOV %RDX,(%R12,%RAX,8) |
(887) 0x8c768 CMP %RDI,%RCX |
(887) 0x8c76b JE 8c7d5 |
(896) 0x8c76d MOV (%RCX),%RSI |
(896) 0x8c770 ADD $0x40,%RCX |
(896) 0x8c774 MOV (%R15,%RSI,8),%RAX |
(896) 0x8c778 MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c77c MOV -0x38(%RCX),%RSI |
(896) 0x8c780 MOV (%R15,%RSI,8),%RAX |
(896) 0x8c784 MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c788 MOV -0x30(%RCX),%RSI |
(896) 0x8c78c MOV (%R15,%RSI,8),%RAX |
(896) 0x8c790 MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c794 MOV -0x28(%RCX),%RSI |
(896) 0x8c798 MOV (%R15,%RSI,8),%RAX |
(896) 0x8c79c MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c7a0 MOV -0x20(%RCX),%RSI |
(896) 0x8c7a4 MOV (%R15,%RSI,8),%RAX |
(896) 0x8c7a8 MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c7ac MOV -0x18(%RCX),%RSI |
(896) 0x8c7b0 MOV (%R15,%RSI,8),%RAX |
(896) 0x8c7b4 MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c7b8 MOV -0x10(%RCX),%RSI |
(896) 0x8c7bc MOV (%R15,%RSI,8),%RAX |
(896) 0x8c7c0 MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c7c4 MOV -0x8(%RCX),%RSI |
(896) 0x8c7c8 MOV (%R15,%RSI,8),%RAX |
(896) 0x8c7cc MOV %RDX,(%R12,%RAX,8) |
(896) 0x8c7d0 CMP %RDI,%RCX |
(896) 0x8c7d3 JNE 8c76d |
(887) 0x8c7d5 MOV 0xa8(%RSP),%RCX |
(887) 0x8c7dd MOV (%RCX),%RDI |
(887) 0x8c7e0 MOV %RDI,0xf8(%RSP) |
(887) 0x8c7e8 MOV 0x38(%RSP),%RSI |
(887) 0x8c7ed VXORPD %XMM0,%XMM0,%XMM0 |
(887) 0x8c7f1 VMOVSD %XMM0,%XMM0,%XMM2 |
(887) 0x8c7f5 LEA (%RSI,%R8,1),%RAX |
(887) 0x8c7f9 LEA (%RSI,%R9,1),%RSI |
(887) 0x8c7fd MOV %RAX,0xa0(%RSP) |
(887) 0x8c805 MOV (%RAX),%RAX |
(887) 0x8c808 MOV %RAX,0xb8(%RSP) |
(887) 0x8c810 INC %RAX |
(887) 0x8c813 CMP (%RSI),%RAX |
(887) 0x8c816 JGE 8c8fc |
(887) 0x8c81c CMPQ $0x1,0xe8(%RSP) |
(887) 0x8c825 JE 8d000 |
(887) 0x8c82b MOV %R13,0x70(%RSP) |
(887) 0x8c830 MOV %RBX,0xb8(%RSP) |
(887) 0x8c838 MOV 0xf8(%RSP),%RBX |
(887) 0x8c840 MOV %R10,0x78(%RSP) |
(887) 0x8c845 MOV 0x10(%RSP),%R10 |
(887) 0x8c84a MOV %R9,0x68(%RSP) |
(887) 0x8c84f MOV 0xc0(%RSP),%R9 |
(887) 0x8c857 NOPW (%RAX,%RAX,1) |
(895) 0x8c860 MOV (%R11,%RAX,8),%RCX |
(895) 0x8c864 CMPQ $-0x3,(%R10,%RCX,8) |
(895) 0x8c869 JE 8c882 |
(895) 0x8c86b MOV (%R9,%RCX,8),%R13 |
(895) 0x8c86f CMP %R13,(%R9,%R8,1) |
(895) 0x8c873 JNE 8c882 |
(895) 0x8c875 MOV 0xf0(%RSP),%RDI |
(895) 0x8c87d VADDSD (%RDI,%RAX,8),%XMM0,%XMM0 |
(895) 0x8c882 CMP $-0x1,%RCX |
(895) 0x8c886 JE 8c8d5 |
(895) 0x8c888 CMP (%R12,%RCX,8),%RDX |
(895) 0x8c88c JNE 8c8d5 |
(895) 0x8c88e MOV 0xf0(%RSP),%R13 |
(895) 0x8c896 LEA (,%RBX,8),%RDI |
(895) 0x8c89e VMOVSD (%R13,%RAX,8),%XMM6 |
(895) 0x8c8a5 MOV 0xd0(%RSP),%R13 |
(895) 0x8c8ad VMOVSD %XMM6,(%R13,%RBX,8) |
(895) 0x8c8b4 MOV 0x98(%RSP),%R13 |
(895) 0x8c8bc VADDSD %XMM6,%XMM2,%XMM2 |
(895) 0x8c8c0 INC %RBX |
(895) 0x8c8c3 MOV (%R13,%RCX,8),%RCX |
(895) 0x8c8c8 MOV 0x80(%RSP),%R13 |
(895) 0x8c8d0 MOV %RCX,(%R13,%RDI,1) |
(895) 0x8c8d5 INC %RAX |
(895) 0x8c8d8 CMP (%RSI),%RAX |
(895) 0x8c8db JL 8c860 |
(887) 0x8c8dd MOV 0x78(%RSP),%R10 |
(887) 0x8c8e2 MOV 0x70(%RSP),%R13 |
(887) 0x8c8e7 MOV %RBX,0xf8(%RSP) |
(887) 0x8c8ef MOV 0x68(%RSP),%R9 |
(887) 0x8c8f4 MOV 0xb8(%RSP),%RBX |
(887) 0x8c8fc MOV 0x60(%RSP),%RAX |
(887) 0x8c901 MOV 0x50(%RSP),%RDI |
(887) 0x8c906 MOV (%RAX,%RDX,8),%RCX |
(887) 0x8c90a LEA (%RDI,%R8,1),%RSI |
(887) 0x8c90e MOV 0x8(%RDI,%R8,1),%RAX |
(887) 0x8c913 MOV %RSI,0xb8(%RSP) |
(887) 0x8c91b MOV (%RSI),%RSI |
(887) 0x8c91e ADD %RCX,%RAX |
(887) 0x8c921 SUB %RSI,%RAX |
(887) 0x8c924 CMP %RAX,%RCX |
(887) 0x8c927 JGE 8ca6d |
(887) 0x8c92d MOV 0x28(%RSP),%RDI |
(887) 0x8c932 MOV 0x8(%RDI),%RSI |
(887) 0x8c936 LEA (%RSI,%RCX,8),%RCX |
(887) 0x8c93a LEA (%RSI,%RAX,8),%RSI |
(887) 0x8c93e MOV %RSI,%RAX |
(887) 0x8c941 SUB %RCX,%RAX |
(887) 0x8c944 SUB $0x8,%RAX |
(887) 0x8c948 SHR $0x3,%RAX |
(887) 0x8c94c INC %RAX |
(887) 0x8c94f AND $0x7,%EAX |
(887) 0x8c952 JE 8c9ea |
(887) 0x8c958 CMP $0x1,%RAX |
(887) 0x8c95c JE 8c9d6 |
(887) 0x8c95e CMP $0x2,%RAX |
(887) 0x8c962 JE 8c9c7 |
(887) 0x8c964 CMP $0x3,%RAX |
(887) 0x8c968 JE 8c9b8 |
(887) 0x8c96a CMP $0x4,%RAX |
(887) 0x8c96e JE 8c9a9 |
(887) 0x8c970 CMP $0x5,%RAX |
(887) 0x8c974 JE 8c99a |
(887) 0x8c976 CMP $0x6,%RAX |
(887) 0x8c97a JE 8c98b |
(887) 0x8c97c MOV (%RCX),%RDI |
(887) 0x8c97f ADD $0x8,%RCX |
(887) 0x8c983 MOV (%R14,%RDI,8),%RAX |
(887) 0x8c987 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c98b MOV (%RCX),%RDI |
(887) 0x8c98e ADD $0x8,%RCX |
(887) 0x8c992 MOV (%R14,%RDI,8),%RAX |
(887) 0x8c996 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c99a MOV (%RCX),%RDI |
(887) 0x8c99d ADD $0x8,%RCX |
(887) 0x8c9a1 MOV (%R14,%RDI,8),%RAX |
(887) 0x8c9a5 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c9a9 MOV (%RCX),%RDI |
(887) 0x8c9ac ADD $0x8,%RCX |
(887) 0x8c9b0 MOV (%R14,%RDI,8),%RAX |
(887) 0x8c9b4 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c9b8 MOV (%RCX),%RDI |
(887) 0x8c9bb ADD $0x8,%RCX |
(887) 0x8c9bf MOV (%R14,%RDI,8),%RAX |
(887) 0x8c9c3 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c9c7 MOV (%RCX),%RDI |
(887) 0x8c9ca ADD $0x8,%RCX |
(887) 0x8c9ce MOV (%R14,%RDI,8),%RAX |
(887) 0x8c9d2 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c9d6 MOV (%RCX),%RDI |
(887) 0x8c9d9 ADD $0x8,%RCX |
(887) 0x8c9dd MOV (%R14,%RDI,8),%RAX |
(887) 0x8c9e1 MOV %RDX,(%RBX,%RAX,8) |
(887) 0x8c9e5 CMP %RCX,%RSI |
(887) 0x8c9e8 JE 8ca62 |
(887) 0x8c9ea MOV 0xb8(%RSP),%RDI |
(893) 0x8c9f2 MOV (%RCX),%RAX |
(893) 0x8c9f5 ADD $0x40,%RCX |
(893) 0x8c9f9 MOV (%R14,%RAX,8),%RAX |
(893) 0x8c9fd MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca01 MOV -0x38(%RCX),%RAX |
(893) 0x8ca05 MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca09 MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca0d MOV -0x30(%RCX),%RAX |
(893) 0x8ca11 MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca15 MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca19 MOV -0x28(%RCX),%RAX |
(893) 0x8ca1d MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca21 MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca25 MOV -0x20(%RCX),%RAX |
(893) 0x8ca29 MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca2d MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca31 MOV -0x18(%RCX),%RAX |
(893) 0x8ca35 MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca39 MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca3d MOV -0x10(%RCX),%RAX |
(893) 0x8ca41 MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca45 MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca49 MOV -0x8(%RCX),%RAX |
(893) 0x8ca4d MOV (%R14,%RAX,8),%RAX |
(893) 0x8ca51 MOV %RDX,(%RBX,%RAX,8) |
(893) 0x8ca55 CMP %RCX,%RSI |
(893) 0x8ca58 JNE 8c9f2 |
(887) 0x8ca5a MOV %RDI,0xb8(%RSP) |
(887) 0x8ca62 MOV 0xb8(%RSP),%RCX |
(887) 0x8ca6a MOV (%RCX),%RSI |
(887) 0x8ca6d MOV 0x40(%RSP),%RDI |
(887) 0x8ca72 MOV (%RDI,%RDX,8),%RAX |
(887) 0x8ca76 ADD %RDI,%R9 |
(887) 0x8ca79 CMP %RAX,(%R9) |
(887) 0x8ca7c JLE 8d1d8 |
(887) 0x8ca82 CMPQ $0,0x18(%RSP) |
(887) 0x8ca88 JE 8d0b0 |
(887) 0x8ca8e MOV %R14,0x78(%RSP) |
(887) 0x8ca93 MOV 0x8(%RSP),%RDI |
(887) 0x8ca98 MOV %R11,0x70(%RSP) |
(887) 0x8ca9d JMP 8cb11 |
0x8ca9f NOP |
(892) 0x8caa0 MOV 0xb0(%RSP),%R11 |
(892) 0x8caa8 MOV 0xc0(%RSP),%R14 |
(892) 0x8cab0 MOV (%R11,%RCX,8),%R11 |
(892) 0x8cab4 CMP %R11,(%R14,%R8,1) |
(892) 0x8cab8 JE 8cb30 |
(892) 0x8caba CMP $-0x1,%RCX |
(892) 0x8cabe JE 8cb09 |
(892) 0x8cac0 CMP (%RBX,%RCX,8),%RDX |
(892) 0x8cac4 JNE 8cb09 |
(892) 0x8cac6 MOV 0xe0(%RSP),%R11 |
(892) 0x8cace LEA (,%RSI,8),%R14 |
(892) 0x8cad6 VMOVSD (%R11,%RAX,8),%XMM7 |
(892) 0x8cadc MOV 0xd8(%RSP),%R11 |
(892) 0x8cae4 VMOVSD %XMM7,(%R11,%RSI,8) |
(892) 0x8caea MOV 0x90(%RSP),%R11 |
(892) 0x8caf2 VADDSD %XMM7,%XMM2,%XMM2 |
(892) 0x8caf6 INC %RSI |
(892) 0x8caf9 MOV (%R11,%RCX,8),%RCX |
(892) 0x8cafd MOV 0x88(%RSP),%R11 |
(892) 0x8cb05 MOV %RCX,(%R11,%R14,1) |
(892) 0x8cb09 INC %RAX |
(892) 0x8cb0c CMP (%R9),%RAX |
(892) 0x8cb0f JGE 8cb48 |
(892) 0x8cb11 MOV (%R13,%RAX,8),%R14 |
(892) 0x8cb16 MOV (%RDI,%R14,8),%RCX |
(892) 0x8cb1a CMPQ $-0x3,(%R10,%RCX,8) |
(892) 0x8cb1f JE 8caba |
(892) 0x8cb21 CMPQ $0x1,0xe8(%RSP) |
(892) 0x8cb2a JNE 8caa0 |
(892) 0x8cb30 MOV 0xe0(%RSP),%R14 |
(892) 0x8cb38 VADDSD (%R14,%RAX,8),%XMM0,%XMM0 |
(892) 0x8cb3e JMP 8caba |
0x8cb43 NOPL (%RAX,%RAX,1) |
(887) 0x8cb48 MOV 0x78(%RSP),%R14 |
(887) 0x8cb4d MOV 0x70(%RSP),%R11 |
(887) 0x8cb52 MOV 0xb8(%RSP),%RDX |
(887) 0x8cb5a MOV (%RDX),%R8 |
(887) 0x8cb5d MOV 0xa0(%RSP),%R9 |
(887) 0x8cb65 MOV 0xf0(%RSP),%RCX |
(887) 0x8cb6d MOV (%R9),%RAX |
(887) 0x8cb70 VMULSD (%RCX,%RAX,8),%XMM2,%XMM10 |
(887) 0x8cb75 VCOMISD %XMM4,%XMM10 |
(887) 0x8cb79 JE 8cb84 |
(887) 0x8cb7b VXORPD %XMM5,%XMM0,%XMM1 |
(887) 0x8cb7f VDIVSD %XMM10,%XMM1,%XMM11 |
(887) 0x8cb84 MOV 0xa8(%RSP),%RDI |
(887) 0x8cb8c MOV 0xf8(%RSP),%RDX |
(887) 0x8cb94 MOV (%RDI),%RCX |
(887) 0x8cb97 CMP %RDX,%RCX |
(887) 0x8cb9a JGE 8cdb6 |
(887) 0x8cba0 MOV %RDX,%R9 |
(887) 0x8cba3 MOV %RCX,0xb8(%RSP) |
(887) 0x8cbab SUB %RCX,%R9 |
(887) 0x8cbae LEA -0x1(%R9),%RAX |
(887) 0x8cbb2 CMP $0x6,%RAX |
(887) 0x8cbb6 JBE 8d1e0 |
(887) 0x8cbbc MOV 0xd0(%RSP),%RDI |
(887) 0x8cbc4 MOV %R9,%RDX |
(887) 0x8cbc7 VBROADCASTSD %XMM11,%ZMM12 |
(887) 0x8cbcd SHR $0x3,%RDX |
(887) 0x8cbd1 SAL $0x6,%RDX |
(887) 0x8cbd5 LEA (%RDI,%RCX,8),%RAX |
(887) 0x8cbd9 LEA (%RDX,%RAX,1),%RDI |
(887) 0x8cbdd SUB $0x40,%RDX |
(887) 0x8cbe1 SHR $0x6,%RDX |
(887) 0x8cbe5 INC %RDX |
(887) 0x8cbe8 AND $0x7,%EDX |
(887) 0x8cbeb JE 8cc95 |
(887) 0x8cbf1 CMP $0x1,%RDX |
(887) 0x8cbf5 JE 8cc7f |
(887) 0x8cbfb CMP $0x2,%RDX |
(887) 0x8cbff JE 8cc6e |
(887) 0x8cc01 CMP $0x3,%RDX |
(887) 0x8cc05 JE 8cc5d |
(887) 0x8cc07 CMP $0x4,%RDX |
(887) 0x8cc0b JE 8cc4c |
(887) 0x8cc0d CMP $0x5,%RDX |
(887) 0x8cc11 JE 8cc3b |
(887) 0x8cc13 CMP $0x6,%RDX |
(887) 0x8cc17 JE 8cc2a |
(887) 0x8cc19 VMULPD (%RAX),%ZMM12,%ZMM13 |
(887) 0x8cc1f ADD $0x40,%RAX |
(887) 0x8cc23 VMOVUPD %ZMM13,-0x40(%RAX) |
(887) 0x8cc2a VMULPD (%RAX),%ZMM12,%ZMM14 |
(887) 0x8cc30 ADD $0x40,%RAX |
(887) 0x8cc34 VMOVUPD %ZMM14,-0x40(%RAX) |
(887) 0x8cc3b VMULPD (%RAX),%ZMM12,%ZMM15 |
(887) 0x8cc41 ADD $0x40,%RAX |
(887) 0x8cc45 VMOVUPD %ZMM15,-0x40(%RAX) |
(887) 0x8cc4c VMULPD (%RAX),%ZMM12,%ZMM0 |
(887) 0x8cc52 ADD $0x40,%RAX |
(887) 0x8cc56 VMOVUPD %ZMM0,-0x40(%RAX) |
(887) 0x8cc5d VMULPD (%RAX),%ZMM12,%ZMM3 |
(887) 0x8cc63 ADD $0x40,%RAX |
(887) 0x8cc67 VMOVUPD %ZMM3,-0x40(%RAX) |
(887) 0x8cc6e VMULPD (%RAX),%ZMM12,%ZMM2 |
(887) 0x8cc74 ADD $0x40,%RAX |
(887) 0x8cc78 VMOVUPD %ZMM2,-0x40(%RAX) |
(887) 0x8cc7f VMULPD (%RAX),%ZMM12,%ZMM6 |
(887) 0x8cc85 ADD $0x40,%RAX |
(887) 0x8cc89 VMOVUPD %ZMM6,-0x40(%RAX) |
(887) 0x8cc90 CMP %RAX,%RDI |
(887) 0x8cc93 JE 8cd0f |
(889) 0x8cc95 VMULPD (%RAX),%ZMM12,%ZMM7 |
(889) 0x8cc9b ADD $0x200,%RAX |
(889) 0x8cca1 VMULPD -0x1c0(%RAX),%ZMM12,%ZMM8 |
(889) 0x8cca8 VMULPD -0x180(%RAX),%ZMM12,%ZMM9 |
(889) 0x8ccaf VMULPD -0x140(%RAX),%ZMM12,%ZMM10 |
(889) 0x8ccb6 VMULPD -0x100(%RAX),%ZMM12,%ZMM1 |
(889) 0x8ccbd VMULPD -0xc0(%RAX),%ZMM12,%ZMM13 |
(889) 0x8ccc4 VMOVUPD %ZMM7,-0x200(%RAX) |
(889) 0x8cccb VMULPD -0x80(%RAX),%ZMM12,%ZMM14 |
(889) 0x8ccd2 VMOVUPD %ZMM8,-0x1c0(%RAX) |
(889) 0x8ccd9 VMULPD -0x40(%RAX),%ZMM12,%ZMM15 |
(889) 0x8cce0 VMOVUPD %ZMM9,-0x180(%RAX) |
(889) 0x8cce7 VMOVUPD %ZMM10,-0x140(%RAX) |
(889) 0x8ccee VMOVUPD %ZMM1,-0x100(%RAX) |
(889) 0x8ccf5 VMOVUPD %ZMM13,-0xc0(%RAX) |
(889) 0x8ccfc VMOVUPD %ZMM14,-0x80(%RAX) |
(889) 0x8cd03 VMOVUPD %ZMM15,-0x40(%RAX) |
(889) 0x8cd0a CMP %RAX,%RDI |
(889) 0x8cd0d JNE 8cc95 |
(887) 0x8cd0f MOV %R9,%RAX |
(887) 0x8cd12 AND $-0x8,%RAX |
(887) 0x8cd16 ADD %RAX,%RCX |
(887) 0x8cd19 TEST $0x7,%R9B |
(887) 0x8cd1d JE 8cdb6 |
(887) 0x8cd23 SUB %RAX,%R9 |
(887) 0x8cd26 LEA -0x1(%R9),%RDX |
(887) 0x8cd2a CMP $0x2,%RDX |
(887) 0x8cd2e JBE 8cd64 |
(887) 0x8cd30 MOV 0xb8(%RSP),%RDI |
(887) 0x8cd38 MOV 0xd0(%RSP),%RDX |
(887) 0x8cd40 VBROADCASTSD %XMM11,%YMM12 |
(887) 0x8cd45 ADD %RAX,%RDI |
(887) 0x8cd48 MOV %R9,%RAX |
(887) 0x8cd4b LEA (%RDX,%RDI,8),%RDI |
(887) 0x8cd4f AND $-0x4,%RAX |
(887) 0x8cd53 VMULPD (%RDI),%YMM12,%YMM0 |
(887) 0x8cd57 ADD %RAX,%RCX |
(887) 0x8cd5a AND $0x3,%R9D |
(887) 0x8cd5e VMOVUPD %YMM0,(%RDI) |
(887) 0x8cd62 JE 8cdb6 |
(887) 0x8cd64 MOV 0xd0(%RSP),%RDI |
(887) 0x8cd6c LEA (,%RCX,8),%RAX |
(887) 0x8cd74 LEA 0x1(%RCX),%RDX |
(887) 0x8cd78 LEA (%RDI,%RAX,1),%R9 |
(887) 0x8cd7c VMULSD (%R9),%XMM11,%XMM3 |
(887) 0x8cd81 VMOVSD %XMM3,(%R9) |
(887) 0x8cd86 MOV 0xf8(%RSP),%R9 |
(887) 0x8cd8e CMP %RDX,%R9 |
(887) 0x8cd91 JLE 8cdb6 |
(887) 0x8cd93 LEA 0x8(%RDI,%RAX,1),%RDX |
(887) 0x8cd98 ADD $0x2,%RCX |
(887) 0x8cd9c VMULSD (%RDX),%XMM11,%XMM2 |
(887) 0x8cda0 VMOVSD %XMM2,(%RDX) |
(887) 0x8cda4 CMP %RCX,%R9 |
(887) 0x8cda7 JLE 8cdb6 |
(887) 0x8cda9 LEA 0x10(%RDI,%RAX,1),%RCX |
(887) 0x8cdae VMULSD (%RCX),%XMM11,%XMM6 |
(887) 0x8cdb2 VMOVSD %XMM6,(%RCX) |
(887) 0x8cdb6 CMP %R8,%RSI |
(887) 0x8cdb9 JLE 8cfbe |
(887) 0x8cdbf MOV %RSI,%RCX |
(887) 0x8cdc2 MOV %R8,%RDI |
(887) 0x8cdc5 SUB %R8,%RCX |
(887) 0x8cdc8 LEA -0x1(%RCX),%RAX |
(887) 0x8cdcc CMP $0x6,%RAX |
(887) 0x8cdd0 JBE 8d1e7 |
(887) 0x8cdd6 MOV 0xd8(%RSP),%RDX |
(887) 0x8cdde VBROADCASTSD %XMM11,%ZMM7 |
(887) 0x8cde4 LEA (%RDX,%R8,8),%RAX |
(887) 0x8cde8 MOV %RCX,%RDX |
(887) 0x8cdeb SHR $0x3,%RDX |
(887) 0x8cdef SAL $0x6,%RDX |
(887) 0x8cdf3 LEA (%RDX,%RAX,1),%R9 |
(887) 0x8cdf7 SUB $0x40,%RDX |
(887) 0x8cdfb SHR $0x6,%RDX |
(887) 0x8cdff INC %RDX |
(887) 0x8ce02 AND $0x7,%EDX |
(887) 0x8ce05 JE 8ceaf |
(887) 0x8ce0b CMP $0x1,%RDX |
(887) 0x8ce0f JE 8ce99 |
(887) 0x8ce15 CMP $0x2,%RDX |
(887) 0x8ce19 JE 8ce88 |
(887) 0x8ce1b CMP $0x3,%RDX |
(887) 0x8ce1f JE 8ce77 |
(887) 0x8ce21 CMP $0x4,%RDX |
(887) 0x8ce25 JE 8ce66 |
(887) 0x8ce27 CMP $0x5,%RDX |
(887) 0x8ce2b JE 8ce55 |
(887) 0x8ce2d CMP $0x6,%RDX |
(887) 0x8ce31 JE 8ce44 |
(887) 0x8ce33 VMULPD (%RAX),%ZMM7,%ZMM8 |
(887) 0x8ce39 ADD $0x40,%RAX |
(887) 0x8ce3d VMOVUPD %ZMM8,-0x40(%RAX) |
(887) 0x8ce44 VMULPD (%RAX),%ZMM7,%ZMM9 |
(887) 0x8ce4a ADD $0x40,%RAX |
(887) 0x8ce4e VMOVUPD %ZMM9,-0x40(%RAX) |
(887) 0x8ce55 VMULPD (%RAX),%ZMM7,%ZMM10 |
(887) 0x8ce5b ADD $0x40,%RAX |
(887) 0x8ce5f VMOVUPD %ZMM10,-0x40(%RAX) |
(887) 0x8ce66 VMULPD (%RAX),%ZMM7,%ZMM1 |
(887) 0x8ce6c ADD $0x40,%RAX |
(887) 0x8ce70 VMOVUPD %ZMM1,-0x40(%RAX) |
(887) 0x8ce77 VMULPD (%RAX),%ZMM7,%ZMM13 |
(887) 0x8ce7d ADD $0x40,%RAX |
(887) 0x8ce81 VMOVUPD %ZMM13,-0x40(%RAX) |
(887) 0x8ce88 VMULPD (%RAX),%ZMM7,%ZMM14 |
(887) 0x8ce8e ADD $0x40,%RAX |
(887) 0x8ce92 VMOVUPD %ZMM14,-0x40(%RAX) |
(887) 0x8ce99 VMULPD (%RAX),%ZMM7,%ZMM15 |
(887) 0x8ce9f ADD $0x40,%RAX |
(887) 0x8cea3 VMOVUPD %ZMM15,-0x40(%RAX) |
(887) 0x8ceaa CMP %R9,%RAX |
(887) 0x8cead JE 8cf29 |
(888) 0x8ceaf VMULPD (%RAX),%ZMM7,%ZMM12 |
(888) 0x8ceb5 ADD $0x200,%RAX |
(888) 0x8cebb VMULPD -0x1c0(%RAX),%ZMM7,%ZMM0 |
(888) 0x8cec2 VMULPD -0x180(%RAX),%ZMM7,%ZMM3 |
(888) 0x8cec9 VMULPD -0x140(%RAX),%ZMM7,%ZMM2 |
(888) 0x8ced0 VMULPD -0x100(%RAX),%ZMM7,%ZMM6 |
(888) 0x8ced7 VMULPD -0xc0(%RAX),%ZMM7,%ZMM8 |
(888) 0x8cede VMOVUPD %ZMM12,-0x200(%RAX) |
(888) 0x8cee5 VMULPD -0x80(%RAX),%ZMM7,%ZMM9 |
(888) 0x8ceec VMOVUPD %ZMM0,-0x1c0(%RAX) |
(888) 0x8cef3 VMULPD -0x40(%RAX),%ZMM7,%ZMM10 |
(888) 0x8cefa VMOVUPD %ZMM3,-0x180(%RAX) |
(888) 0x8cf01 VMOVUPD %ZMM2,-0x140(%RAX) |
(888) 0x8cf08 VMOVUPD %ZMM6,-0x100(%RAX) |
(888) 0x8cf0f VMOVUPD %ZMM8,-0xc0(%RAX) |
(888) 0x8cf16 VMOVUPD %ZMM9,-0x80(%RAX) |
(888) 0x8cf1d VMOVUPD %ZMM10,-0x40(%RAX) |
(888) 0x8cf24 CMP %R9,%RAX |
(888) 0x8cf27 JNE 8ceaf |
(887) 0x8cf29 MOV %RCX,%R9 |
(887) 0x8cf2c AND $-0x8,%R9 |
(887) 0x8cf30 ADD %R9,%R8 |
(887) 0x8cf33 TEST $0x7,%CL |
(887) 0x8cf36 JE 8cfbe |
(887) 0x8cf3c SUB %R9,%RCX |
(887) 0x8cf3f LEA -0x1(%RCX),%RAX |
(887) 0x8cf43 CMP $0x2,%RAX |
(887) 0x8cf47 JBE 8cf74 |
(887) 0x8cf49 ADD %RDI,%R9 |
(887) 0x8cf4c MOV 0xd8(%RSP),%RDI |
(887) 0x8cf54 VBROADCASTSD %XMM11,%YMM7 |
(887) 0x8cf59 LEA (%RDI,%R9,8),%RDX |
(887) 0x8cf5d MOV %RCX,%R9 |
(887) 0x8cf60 VMULPD (%RDX),%YMM7,%YMM1 |
(887) 0x8cf64 AND $-0x4,%R9 |
(887) 0x8cf68 ADD %R9,%R8 |
(887) 0x8cf6b AND $0x3,%ECX |
(887) 0x8cf6e VMOVUPD %YMM1,(%RDX) |
(887) 0x8cf72 JE 8cfbe |
(887) 0x8cf74 MOV 0xd8(%RSP),%RAX |
(887) 0x8cf7c LEA (,%R8,8),%RCX |
(887) 0x8cf84 LEA 0x1(%R8),%RDX |
(887) 0x8cf88 LEA (%RAX,%RCX,1),%RDI |
(887) 0x8cf8c VMULSD (%RDI),%XMM11,%XMM13 |
(887) 0x8cf90 VMOVSD %XMM13,(%RDI) |
(887) 0x8cf94 CMP %RDX,%RSI |
(887) 0x8cf97 JLE 8cfbe |
(887) 0x8cf99 LEA 0x8(%RAX,%RCX,1),%R9 |
(887) 0x8cf9e ADD $0x2,%R8 |
(887) 0x8cfa2 VMULSD (%R9),%XMM11,%XMM14 |
(887) 0x8cfa7 VMOVSD %XMM14,(%R9) |
(887) 0x8cfac CMP %R8,%RSI |
(887) 0x8cfaf JLE 8cfbe |
(887) 0x8cfb1 LEA 0x10(%RAX,%RCX,1),%RSI |
(887) 0x8cfb6 VMULSD (%RSI),%XMM11,%XMM15 |
(887) 0x8cfba VMOVSD %XMM15,(%RSI) |
(887) 0x8cfbe ADDQ $0x8,0xc8(%RSP) |
(887) 0x8cfc7 MOV 0x30(%RSP),%RCX |
(887) 0x8cfcc MOV 0xc8(%RSP),%R8 |
(887) 0x8cfd4 CMP %RCX,%R8 |
(887) 0x8cfd7 JNE 8c660 |
0x8cfdd VZEROUPPER |
0x8cfe0 MOV %R12,%RDI |
0x8cfe3 CALL c840 <hypre_Free@plt> |
0x8cfe8 LEA -0x28(%RBP),%RSP |
0x8cfec MOV %RBX,%RDI |
0x8cfef POP %RBX |
0x8cff0 POP %R12 |
0x8cff2 POP %R13 |
0x8cff4 POP %R14 |
0x8cff6 POP %R15 |
0x8cff8 POP %RBP |
0x8cff9 JMP c840 |
0x8cffe XCHG %AX,%AX |
(887) 0x8d000 MOV %R10,0xb8(%RSP) |
(887) 0x8d008 MOV %R8,0x78(%RSP) |
(887) 0x8d00d MOV 0x10(%RSP),%R8 |
(887) 0x8d012 MOV %R9,0x70(%RSP) |
(887) 0x8d017 MOV 0xf8(%RSP),%R9 |
(887) 0x8d01f NOP |
(894) 0x8d020 MOV (%R11,%RAX,8),%RCX |
(894) 0x8d024 CMPQ $-0x3,(%R8,%RCX,8) |
(894) 0x8d029 JE 8d039 |
(894) 0x8d02b MOV 0xf0(%RSP),%R10 |
(894) 0x8d033 VADDSD (%R10,%RAX,8),%XMM0,%XMM0 |
(894) 0x8d039 CMP $-0x1,%RCX |
(894) 0x8d03d JE 8d088 |
(894) 0x8d03f CMP (%R12,%RCX,8),%RDX |
(894) 0x8d043 JNE 8d088 |
(894) 0x8d045 MOV 0xf0(%RSP),%R10 |
(894) 0x8d04d LEA (,%R9,8),%RDI |
(894) 0x8d055 VMOVSD (%R10,%RAX,8),%XMM3 |
(894) 0x8d05b MOV 0xd0(%RSP),%R10 |
(894) 0x8d063 VMOVSD %XMM3,(%R10,%R9,8) |
(894) 0x8d069 MOV 0x98(%RSP),%R10 |
(894) 0x8d071 VADDSD %XMM3,%XMM2,%XMM2 |
(894) 0x8d075 INC %R9 |
(894) 0x8d078 MOV (%R10,%RCX,8),%RCX |
(894) 0x8d07c MOV 0x80(%RSP),%R10 |
(894) 0x8d084 MOV %RCX,(%R10,%RDI,1) |
(894) 0x8d088 INC %RAX |
(894) 0x8d08b CMP (%RSI),%RAX |
(894) 0x8d08e JL 8d020 |
(887) 0x8d090 MOV 0xb8(%RSP),%R10 |
(887) 0x8d098 MOV 0x78(%RSP),%R8 |
(887) 0x8d09d MOV %R9,0xf8(%RSP) |
(887) 0x8d0a5 MOV 0x70(%RSP),%R9 |
(887) 0x8d0aa JMP 8c8fc |
0x8d0af NOP |
(887) 0x8d0b0 CMPQ $0x1,0xe8(%RSP) |
(887) 0x8d0b9 JE 8d160 |
(887) 0x8d0bf MOV %R14,0x78(%RSP) |
(887) 0x8d0c4 NOPL (%RAX) |
(891) 0x8d0c8 MOV (%R13,%RAX,8),%RCX |
(891) 0x8d0cd CMPQ $-0x3,(%R10,%RCX,8) |
(891) 0x8d0d2 JE 8d0fc |
(891) 0x8d0d4 MOV 0xc0(%RSP),%RDI |
(891) 0x8d0dc MOV 0xb0(%RSP),%R14 |
(891) 0x8d0e4 MOV (%RDI,%R8,1),%RDI |
(891) 0x8d0e8 CMP %RDI,(%R14,%RCX,8) |
(891) 0x8d0ec JNE 8d0fc |
(891) 0x8d0ee MOV 0xe0(%RSP),%R14 |
(891) 0x8d0f6 VADDSD (%R14,%RAX,8),%XMM0,%XMM0 |
(891) 0x8d0fc CMP $-0x1,%RCX |
(891) 0x8d100 JE 8d14a |
(891) 0x8d102 CMP (%RBX,%RCX,8),%RDX |
(891) 0x8d106 JNE 8d14a |
(891) 0x8d108 MOV 0xe0(%RSP),%RDI |
(891) 0x8d110 LEA (,%RSI,8),%R14 |
(891) 0x8d118 VMOVSD (%RDI,%RAX,8),%XMM9 |
(891) 0x8d11d MOV 0xd8(%RSP),%RDI |
(891) 0x8d125 VMOVSD %XMM9,(%RDI,%RSI,8) |
(891) 0x8d12a MOV 0x90(%RSP),%RDI |
(891) 0x8d132 VADDSD %XMM9,%XMM2,%XMM2 |
(891) 0x8d137 INC %RSI |
(891) 0x8d13a MOV (%RDI,%RCX,8),%RCX |
(891) 0x8d13e MOV 0x88(%RSP),%RDI |
(891) 0x8d146 MOV %RCX,(%RDI,%R14,1) |
(891) 0x8d14a INC %RAX |
(891) 0x8d14d CMP %RAX,(%R9) |
(891) 0x8d150 JG 8d0c8 |
(887) 0x8d156 MOV 0x78(%RSP),%R14 |
(887) 0x8d15b JMP 8cb52 |
(890) 0x8d160 MOV (%R13,%RAX,8),%RCX |
(890) 0x8d165 CMPQ $-0x3,(%R10,%RCX,8) |
(890) 0x8d16a JE 8d17a |
(890) 0x8d16c MOV 0xe0(%RSP),%R8 |
(890) 0x8d174 VADDSD (%R8,%RAX,8),%XMM0,%XMM0 |
(890) 0x8d17a CMP $-0x1,%RCX |
(890) 0x8d17e JE 8d1c8 |
(890) 0x8d180 CMP (%RBX,%RCX,8),%RDX |
(890) 0x8d184 JNE 8d1c8 |
(890) 0x8d186 MOV 0xe0(%RSP),%RDI |
(890) 0x8d18e LEA (,%RSI,8),%R8 |
(890) 0x8d196 VMOVSD (%RDI,%RAX,8),%XMM8 |
(890) 0x8d19b MOV 0xd8(%RSP),%RDI |
(890) 0x8d1a3 VMOVSD %XMM8,(%RDI,%RSI,8) |
(890) 0x8d1a8 MOV 0x90(%RSP),%RDI |
(890) 0x8d1b0 VADDSD %XMM8,%XMM2,%XMM2 |
(890) 0x8d1b5 INC %RSI |
(890) 0x8d1b8 MOV (%RDI,%RCX,8),%RCX |
(890) 0x8d1bc MOV 0x88(%RSP),%RDI |
(890) 0x8d1c4 MOV %RCX,(%RDI,%R8,1) |
(890) 0x8d1c8 INC %RAX |
(890) 0x8d1cb CMP %RAX,(%R9) |
(890) 0x8d1ce JG 8d160 |
(887) 0x8d1d0 JMP 8cb52 |
0x8d1d5 NOPL (%RAX) |
(887) 0x8d1d8 MOV %RSI,%R8 |
(887) 0x8d1db JMP 8cb5d |
(887) 0x8d1e0 XOR %EAX,%EAX |
(887) 0x8d1e2 JMP 8cd23 |
(887) 0x8d1e7 XOR %R9D,%R9D |
(887) 0x8d1ea JMP 8cf3c |
0x8d1ef MOV $0x8,%ESI |
0x8d1f4 MOV %RBX,%RDI |
0x8d1f7 MOV %R10,0x68(%RSP) |
0x8d1fc MOV %R12,0x78(%RSP) |
0x8d201 MOV %R11,0xa0(%RSP) |
0x8d209 VMOVSD %XMM1,0xa8(%RSP) |
0x8d212 MOV %RBX,0xb8(%RSP) |
0x8d21a CALL d808 <.plt.got@start+0x18> |
0x8d21f MOV 0x78(%RSP),%RCX |
0x8d224 MOV 0xb8(%RSP),%RDX |
0x8d22c VMOVSD 0xa8(%RSP),%XMM1 |
0x8d235 MOV 0xa0(%RSP),%R11 |
0x8d23d MOV %RAX,%R12 |
0x8d240 TEST %RCX,%RCX |
0x8d243 MOV 0x68(%RSP),%R10 |
0x8d248 JNE 8d2fb |
0x8d24e XOR %EBX,%EBX |
0x8d250 TEST %RDX,%RDX |
0x8d253 JLE 8c5a2 |
0x8d259 SAL $0x3,%RDX |
0x8d25d MOV $0xff,%ESI |
0x8d262 MOV %R12,%RDI |
0x8d265 MOV %R10,0x78(%RSP) |
0x8d26a MOV %RCX,0xa0(%RSP) |
0x8d272 MOV %R11,0xa8(%RSP) |
0x8d27a VMOVSD %XMM1,0xb8(%RSP) |
0x8d283 CALL c0f0 <memset@plt> |
0x8d288 VMOVSD 0xb8(%RSP),%XMM1 |
0x8d291 MOV 0xa8(%RSP),%R11 |
0x8d299 MOV 0xa0(%RSP),%RCX |
0x8d2a1 MOV 0x78(%RSP),%R10 |
0x8d2a6 TEST %RCX,%RCX |
0x8d2a9 JLE 8c5a2 |
0x8d2af LEA (,%RCX,8),%RDX |
0x8d2b7 MOV $0xff,%ESI |
0x8d2bc MOV %RBX,%RDI |
0x8d2bf MOV %R10,0xa0(%RSP) |
0x8d2c7 MOV %R11,0xa8(%RSP) |
0x8d2cf VMOVSD %XMM1,0xb8(%RSP) |
0x8d2d8 CALL c0f0 <memset@plt> |
0x8d2dd VMOVSD 0xb8(%RSP),%XMM1 |
0x8d2e6 MOV 0xa8(%RSP),%R11 |
0x8d2ee MOV 0xa0(%RSP),%R10 |
0x8d2f6 JMP 8c5a2 |
0x8d2fb MOV %RCX,%RDI |
0x8d2fe MOV $0x8,%ESI |
0x8d303 MOV %R10,0x68(%RSP) |
0x8d308 MOV %R11,0x78(%RSP) |
0x8d30d MOV %RDX,0xa0(%RSP) |
0x8d315 MOV %RCX,0xb8(%RSP) |
0x8d31d VMOVSD %XMM1,0xa8(%RSP) |
0x8d326 CALL d808 <.plt.got@start+0x18> |
0x8d32b MOV 0xa0(%RSP),%RDX |
0x8d333 MOV 0xb8(%RSP),%RCX |
0x8d33b VMOVSD 0xa8(%RSP),%XMM1 |
0x8d344 MOV 0x78(%RSP),%R11 |
0x8d349 MOV %RAX,%RBX |
0x8d34c TEST %RDX,%RDX |
0x8d34f MOV 0x68(%RSP),%R10 |
0x8d354 JG 8d259 |
0x8d35a JMP 8d2a6 |
0x8d35f NOP |
0x8d360 MOV %R12,%RDI |
0x8d363 MOV $0x8,%ESI |
0x8d368 MOV %R10,0x78(%RSP) |
0x8d36d MOV %R11,0xa0(%RSP) |
0x8d375 MOV %R12,0xb8(%RSP) |
0x8d37d XOR %R12D,%R12D |
0x8d380 VMOVSD %XMM1,0xa8(%RSP) |
0x8d389 CALL d808 <.plt.got@start+0x18> |
0x8d38e MOV 0xb8(%RSP),%RCX |
0x8d396 VMOVSD 0xa8(%RSP),%XMM1 |
0x8d39f MOV 0xa0(%RSP),%R11 |
0x8d3a7 MOV 0x78(%RSP),%R10 |
0x8d3ac MOV %RAX,%RBX |
0x8d3af JMP 8d2a6 |
0x8d3b4 NOPW %CS:(%RAX,%RAX,1) |
0x8d3bf NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.29 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.71 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | libparcsr_ls.so |
nb instructions | 205 |
nb uops | 218 |
loop length | 1086 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 36.33 cycles |
front end | 36.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.61-34.66 |
Stall cycles | 0.00 |
Front-end | 36.33 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 36.33 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 8d1ef <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdcf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 8d360 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xf40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL c990 <hypre_GetThreadNum@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL cae0 <hypre_NumActiveThreads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
DEC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 8cfe0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0xab200(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RCX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL c840 <hypre_Free@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP c840 <hypre_Free@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL d808 <.plt.got@start+0x18> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 8d2fb <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xedb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 8c5a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL c0f0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 8c5a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL c0f0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 8c5a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL d808 <.plt.got@start+0x18> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xa0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 8d259 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe39> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 8d2a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL d808 <.plt.got@start+0x18> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 8d2a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | libparcsr_ls.so |
nb instructions | 205 |
nb uops | 218 |
loop length | 1086 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 36.33 cycles |
front end | 36.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.61-34.66 |
Stall cycles | 0.00 |
Front-end | 36.33 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 36.33 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 8d1ef <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdcf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 8d360 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xf40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL c990 <hypre_GetThreadNum@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL cae0 <hypre_NumActiveThreads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
DEC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 8cfe0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0xab200(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RCX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL c840 <hypre_Free@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP c840 <hypre_Free@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL d808 <.plt.got@start+0x18> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 8d2fb <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xedb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 8c5a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL c0f0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 8c5a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL c0f0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 8c5a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL d808 <.plt.got@start+0x18> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xa0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 8d259 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe39> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 8d2a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL d808 <.plt.got@start+0x18> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 8d2a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.9– | 0.38 | 0.07 |
▼Loop 887 - par_multi_interp.c:1605-1660 - libparcsr_ls.so– | 0.06 | 0.01 |
○Loop 894 - par_multi_interp.c:1618-1628 - libparcsr_ls.so | 0.31 | 0.05 |
○Loop 896 - par_multi_interp.c:1612-1615 - libparcsr_ls.so | 0 | 0 |
○Loop 891 - par_multi_interp.c:1639-1652 - libparcsr_ls.so | 0 | 0 |
○Loop 893 - par_multi_interp.c:1633-1636 - libparcsr_ls.so | 0 | 0 |
○Loop 889 - par_multi_interp.c:1657-1658 - libparcsr_ls.so | 0 | 0 |
○Loop 888 - par_multi_interp.c:1659-1660 - libparcsr_ls.so | 0 | 0 |
○Loop 892 - par_multi_interp.c:1639-1652 - libparcsr_ls.so | 0 | 0 |
○Loop 895 - par_multi_interp.c:1618-1628 - libparcsr_ls.so | 0 | 0 |
○Loop 890 - par_multi_interp.c:1639-1652 - libparcsr_ls.so | 0 | 0 |