Loop Id: 407 | Module: libparcsr_ls.so | Source: ams.c:3363-3517 [...] | Coverage: 0.01% |
---|
Loop Id: 407 | Module: libparcsr_ls.so | Source: ams.c:3363-3517 [...] | Coverage: 0.01% |
---|
0x1d34d VMOVSD %XMM0,(%R10) |
0x1d352 NOPW %CS:(%RAX,%RAX,1) |
0x1d360 MOV -0x90(%RBP),%RDX |
0x1d367 LEA 0x1(%RDX),%RAX |
0x1d36b CMP -0xa0(%RBP),%RDX |
0x1d372 MOV %RAX,%RDX |
0x1d375 MOV -0x30(%RBP),%R8 |
0x1d379 JE 1dd0b |
0x1d37f MOV -0x70(%RBP),%RAX |
0x1d383 MOV %RDX,-0x90(%RBP) |
0x1d38a LEA (%RAX,%RDX,1),%R11 |
0x1d38e MOV -0x40(%RBP),%RAX |
0x1d392 LEA (%RAX,%R11,8),%R10 |
0x1d396 MOVQ $0,(%RAX,%R11,8) |
0x1d39e TEST %R8,%R8 |
0x1d3a1 JE 1d460 |
0x1d3a7 MOV (%R8,%R11,8),%RDX |
0x1d3ab MOV -0x50(%RBP),%RSI |
0x1d3af MOV (%RSI,%R11,8),%RAX |
0x1d3b3 MOV 0x8(%RSI,%R11,8),%R15 |
0x1d3b8 VXORPD %XMM0,%XMM0,%XMM0 |
0x1d3bc MOV %R15,%RDI |
0x1d3bf SUB %RAX,%RDI |
0x1d3c2 JLE 1d3de |
0x1d3c4 CMP $0x4,%RDI |
0x1d3c8 JAE 1d520 |
0x1d3ce MOV %RDI,%RSI |
0x1d3d1 AND $-0x4,%RSI |
0x1d3d5 CMP %RDI,%RSI |
0x1d3d8 JNE 1d5e1 |
0x1d3de CMPQ $0,-0x80(%RBP) |
0x1d3e3 MOV -0x60(%RBP),%R15 |
0x1d3e7 JE 1d360 |
0x1d3ed MOV -0x78(%RBP),%RSI |
0x1d3f1 MOV (%RSI,%R11,8),%RAX |
0x1d3f5 MOV 0x8(%RSI,%R11,8),%R11 |
0x1d3fa MOV %R11,%R8 |
0x1d3fd SUB %RAX,%R8 |
0x1d400 JLE 1d360 |
0x1d406 CMP $0x4,%R8 |
0x1d40a JAE 1d61b |
0x1d410 MOV %R8,%RSI |
0x1d413 AND $-0x4,%RSI |
0x1d417 CMP %R8,%RSI |
0x1d41a JE 1d360 |
0x1d420 ADD %RSI,%RAX |
0x1d423 JMP 1d43c |
(414) 0x1d430 INC %RAX |
(414) 0x1d433 CMP %RAX,%R11 |
(414) 0x1d436 JE 1d360 |
(414) 0x1d43c MOV (%R12,%RAX,8),%RSI |
(414) 0x1d440 CMP (%R15,%RSI,8),%RDX |
(414) 0x1d444 JNE 1d430 |
(414) 0x1d446 VMOVSD (%R14,%RAX,8),%XMM1 |
(414) 0x1d44c VANDPD %XMM5,%XMM1,%XMM1 |
(414) 0x1d450 VADDSD %XMM1,%XMM0,%XMM0 |
(414) 0x1d454 VMOVSD %XMM0,(%R10) |
(414) 0x1d459 JMP 1d430 |
0x1d460 MOV -0x50(%RBP),%RAX |
0x1d464 MOV (%RAX,%R11,8),%RDX |
0x1d468 MOV 0x8(%RAX,%R11,8),%RAX |
0x1d46d VXORPD %XMM0,%XMM0,%XMM0 |
0x1d471 MOV %RAX,%RDI |
0x1d474 SUB %RDX,%RDI |
0x1d477 JLE 1d4ba |
0x1d479 LEA -0x8(%RBX,%RAX,8),%RSI |
0x1d47e LEA (%RBX,%RDX,8),%R8 |
0x1d482 CMP %R10,%RSI |
0x1d485 JB 1d6bc |
0x1d48b CMP %R8,%R10 |
0x1d48e JB 1d6bc |
0x1d494 NOPW %CS:(%RAX,%RAX,1) |
(413) 0x1d4a0 VMOVSD (%RBX,%RDX,8),%XMM1 |
(413) 0x1d4a5 VANDPD %XMM5,%XMM1,%XMM1 |
(413) 0x1d4a9 VADDSD %XMM1,%XMM0,%XMM0 |
(413) 0x1d4ad VMOVSD %XMM0,(%R10) |
(413) 0x1d4b2 INC %RDX |
(413) 0x1d4b5 CMP %RDX,%RAX |
(413) 0x1d4b8 JNE 1d4a0 |
0x1d4ba CMPQ $0,-0x80(%RBP) |
0x1d4bf JE 1d360 |
0x1d4c5 MOV -0x78(%RBP),%RAX |
0x1d4c9 MOV (%RAX,%R11,8),%RDX |
0x1d4cd MOV 0x8(%RAX,%R11,8),%RAX |
0x1d4d2 MOV %RAX,%RDI |
0x1d4d5 SUB %RDX,%RDI |
0x1d4d8 JLE 1d360 |
0x1d4de LEA -0x8(%R14,%RAX,8),%RSI |
0x1d4e3 LEA (%R14,%RDX,8),%R8 |
0x1d4e7 CMP %R10,%RSI |
0x1d4ea JB 1d711 |
0x1d4f0 CMP %R8,%R10 |
0x1d4f3 JB 1d711 |
0x1d4f9 NOPL (%RAX) |
(410) 0x1d500 VMOVSD (%R14,%RDX,8),%XMM1 |
(410) 0x1d506 VANDPD %XMM5,%XMM1,%XMM1 |
(410) 0x1d50a VADDSD %XMM1,%XMM0,%XMM0 |
(410) 0x1d50e VMOVSD %XMM0,(%R10) |
(410) 0x1d513 INC %RDX |
(410) 0x1d516 CMP %RDX,%RAX |
(410) 0x1d519 JNE 1d500 |
0x1d51b JMP 1d360 |
0x1d520 MOV %RDI,%R8 |
0x1d523 SHR $0x2,%R8 |
0x1d527 LEA 0x18(,%RAX,8),%RSI |
0x1d52f JMP 1d551 |
(417) 0x1d540 MOV -0x58(%RBP),%R12 |
(417) 0x1d544 ADD $0x20,%RSI |
(417) 0x1d548 DEC %R8 |
(417) 0x1d54b JE 1d3ce |
(417) 0x1d551 MOV -0x18(%R13,%RSI,1),%R9 |
(417) 0x1d556 MOV -0x30(%RBP),%R12 |
(417) 0x1d55a CMP (%R12,%R9,8),%RDX |
(417) 0x1d55e JNE 1d573 |
(417) 0x1d560 VMOVSD -0x18(%RBX,%RSI,1),%XMM1 |
(417) 0x1d566 VANDPD %XMM5,%XMM1,%XMM1 |
(417) 0x1d56a VADDSD %XMM1,%XMM0,%XMM0 |
(417) 0x1d56e VMOVSD %XMM0,(%R10) |
(417) 0x1d573 MOV -0x10(%R13,%RSI,1),%R9 |
(417) 0x1d578 MOV -0x30(%RBP),%R12 |
(417) 0x1d57c CMP (%R12,%R9,8),%RDX |
(417) 0x1d580 JNE 1d595 |
(417) 0x1d582 VMOVSD -0x10(%RBX,%RSI,1),%XMM1 |
(417) 0x1d588 VANDPD %XMM5,%XMM1,%XMM1 |
(417) 0x1d58c VADDSD %XMM1,%XMM0,%XMM0 |
(417) 0x1d590 VMOVSD %XMM0,(%R10) |
(417) 0x1d595 MOV -0x8(%R13,%RSI,1),%R9 |
(417) 0x1d59a MOV -0x30(%RBP),%R12 |
(417) 0x1d59e CMP (%R12,%R9,8),%RDX |
(417) 0x1d5a2 JNE 1d5b7 |
(417) 0x1d5a4 VMOVSD -0x8(%RBX,%RSI,1),%XMM1 |
(417) 0x1d5aa VANDPD %XMM5,%XMM1,%XMM1 |
(417) 0x1d5ae VADDSD %XMM1,%XMM0,%XMM0 |
(417) 0x1d5b2 VMOVSD %XMM0,(%R10) |
(417) 0x1d5b7 MOV (%R13,%RSI,1),%R9 |
(417) 0x1d5bc MOV -0x30(%RBP),%R12 |
(417) 0x1d5c0 CMP (%R12,%R9,8),%RDX |
(417) 0x1d5c4 JNE 1d540 |
(417) 0x1d5ca VMOVSD (%RBX,%RSI,1),%XMM1 |
(417) 0x1d5cf VANDPD %XMM5,%XMM1,%XMM1 |
(417) 0x1d5d3 VADDSD %XMM1,%XMM0,%XMM0 |
(417) 0x1d5d7 VMOVSD %XMM0,(%R10) |
(417) 0x1d5dc JMP 1d540 |
0x1d5e1 ADD %RSI,%RAX |
0x1d5e4 MOV -0x30(%RBP),%RDI |
0x1d5e8 JMP 1d5fc |
(416) 0x1d5f0 INC %RAX |
(416) 0x1d5f3 CMP %RAX,%R15 |
(416) 0x1d5f6 JE 1d3de |
(416) 0x1d5fc MOV (%R13,%RAX,8),%RSI |
(416) 0x1d601 CMP (%RDI,%RSI,8),%RDX |
(416) 0x1d605 JNE 1d5f0 |
(416) 0x1d607 VMOVSD (%RBX,%RAX,8),%XMM1 |
(416) 0x1d60c VANDPD %XMM5,%XMM1,%XMM1 |
(416) 0x1d610 VADDSD %XMM1,%XMM0,%XMM0 |
(416) 0x1d614 VMOVSD %XMM0,(%R10) |
(416) 0x1d619 JMP 1d5f0 |
0x1d61b MOV %R8,%RDI |
0x1d61e SHR $0x2,%RDI |
0x1d622 LEA 0x18(,%RAX,8),%RSI |
0x1d62a JMP 1d63d |
(415) 0x1d630 ADD $0x20,%RSI |
(415) 0x1d634 DEC %RDI |
(415) 0x1d637 JE 1d410 |
(415) 0x1d63d MOV -0x18(%R12,%RSI,1),%R9 |
(415) 0x1d642 CMP (%R15,%R9,8),%RDX |
(415) 0x1d646 JNE 1d65c |
(415) 0x1d648 VMOVSD -0x18(%R14,%RSI,1),%XMM1 |
(415) 0x1d64f VANDPD %XMM5,%XMM1,%XMM1 |
(415) 0x1d653 VADDSD %XMM1,%XMM0,%XMM0 |
(415) 0x1d657 VMOVSD %XMM0,(%R10) |
(415) 0x1d65c MOV -0x10(%R12,%RSI,1),%R9 |
(415) 0x1d661 CMP (%R15,%R9,8),%RDX |
(415) 0x1d665 JNE 1d67b |
(415) 0x1d667 VMOVSD -0x10(%R14,%RSI,1),%XMM1 |
(415) 0x1d66e VANDPD %XMM5,%XMM1,%XMM1 |
(415) 0x1d672 VADDSD %XMM1,%XMM0,%XMM0 |
(415) 0x1d676 VMOVSD %XMM0,(%R10) |
(415) 0x1d67b MOV -0x8(%R12,%RSI,1),%R9 |
(415) 0x1d680 CMP (%R15,%R9,8),%RDX |
(415) 0x1d684 JNE 1d69a |
(415) 0x1d686 VMOVSD -0x8(%R14,%RSI,1),%XMM1 |
(415) 0x1d68d VANDPD %XMM5,%XMM1,%XMM1 |
(415) 0x1d691 VADDSD %XMM1,%XMM0,%XMM0 |
(415) 0x1d695 VMOVSD %XMM0,(%R10) |
(415) 0x1d69a MOV (%R12,%RSI,1),%R9 |
(415) 0x1d69e CMP (%R15,%R9,8),%RDX |
(415) 0x1d6a2 JNE 1d630 |
(415) 0x1d6a4 VMOVSD (%R14,%RSI,1),%XMM1 |
(415) 0x1d6aa VANDPD %XMM5,%XMM1,%XMM1 |
(415) 0x1d6ae VADDSD %XMM1,%XMM0,%XMM0 |
(415) 0x1d6b2 VMOVSD %XMM0,(%R10) |
(415) 0x1d6b7 JMP 1d630 |
0x1d6bc MOV %RDI,%RSI |
0x1d6bf AND $-0x4,%RSI |
0x1d6c3 JE 1d769 |
0x1d6c9 LEA -0x1(%RSI),%R15 |
0x1d6cd VXORPD %XMM0,%XMM0,%XMM0 |
0x1d6d1 XOR %R9D,%R9D |
0x1d6d4 NOPW %CS:(%RAX,%RAX,1) |
(412) 0x1d6e0 VANDPD (%R8,%R9,8),%YMM6,%YMM1 |
(412) 0x1d6e6 VADDPD %YMM1,%YMM0,%YMM0 |
(412) 0x1d6ea ADD $0x4,%R9 |
(412) 0x1d6ee CMP %R15,%R9 |
(412) 0x1d6f1 JBE 1d6e0 |
0x1d6f3 VEXTRACTF128 $0x1,%YMM0,%XMM1 |
0x1d6f9 VADDPD %XMM1,%XMM0,%XMM0 |
0x1d6fd VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
0x1d702 VADDSD %XMM1,%XMM0,%XMM0 |
0x1d706 CMP %RSI,%RDI |
0x1d709 MOV -0x60(%RBP),%R15 |
0x1d70d JNE 1d76b |
0x1d70f JMP 1d785 |
0x1d711 MOV %RDI,%RSI |
0x1d714 AND $-0x4,%RSI |
0x1d718 JE 1d79a |
0x1d71e LEA -0x1(%RSI),%R11 |
0x1d722 VXORPD %XMM1,%XMM1,%XMM1 |
0x1d726 XOR %R15D,%R15D |
0x1d729 NOPL (%RAX) |
(409) 0x1d730 VANDPD (%R8,%R15,8),%YMM6,%YMM2 |
(409) 0x1d736 VADDPD %YMM2,%YMM1,%YMM1 |
(409) 0x1d73a ADD $0x4,%R15 |
(409) 0x1d73e CMP %R11,%R15 |
(409) 0x1d741 JBE 1d730 |
0x1d743 VEXTRACTF128 $0x1,%YMM1,%XMM2 |
0x1d749 VADDPD %XMM2,%XMM1,%XMM1 |
0x1d74d VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 |
0x1d752 VADDSD %XMM2,%XMM1,%XMM1 |
0x1d756 VADDSD %XMM1,%XMM0,%XMM0 |
0x1d75a CMP %RSI,%RDI |
0x1d75d MOV -0x60(%RBP),%R15 |
0x1d761 JE 1d34d |
0x1d767 JMP 1d79c |
0x1d769 XOR %ESI,%ESI |
0x1d76b ADD %RDX,%RSI |
0x1d76e XCHG %AX,%AX |
(411) 0x1d770 VMOVSD (%RBX,%RSI,8),%XMM1 |
(411) 0x1d775 VANDPD %XMM5,%XMM1,%XMM1 |
(411) 0x1d779 VADDSD %XMM1,%XMM0,%XMM0 |
(411) 0x1d77d INC %RSI |
(411) 0x1d780 CMP %RSI,%RAX |
(411) 0x1d783 JNE 1d770 |
0x1d785 VMOVSD %XMM0,(%R10) |
0x1d78a CMPQ $0,-0x80(%RBP) |
0x1d78f JNE 1d4c5 |
0x1d795 JMP 1d360 |
0x1d79a XOR %ESI,%ESI |
0x1d79c ADD %RDX,%RSI |
0x1d79f NOP |
(408) 0x1d7a0 VMOVSD (%R14,%RSI,8),%XMM1 |
(408) 0x1d7a6 VANDPD %XMM5,%XMM1,%XMM1 |
(408) 0x1d7aa VADDSD %XMM1,%XMM0,%XMM0 |
(408) 0x1d7ae INC %RSI |
(408) 0x1d7b1 CMP %RSI,%RAX |
(408) 0x1d7b4 JNE 1d7a0 |
0x1d7b6 JMP 1d34d |
/scratch_na/users/xoserete/qaas_runs/171-415-3872/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3363 - 3517 |
-------------------------------------------------------------------------------- |
3363: #pragma omp parallel for private(i,ii,j,k,ns,ne,rest,size,diag,cf_diag) HYPRE_SMP_SCHEDULE |
[...] |
3382: for (i = ns; i < ne; i++) |
3383: { |
3384: l1_norm[i] = 0.0; |
3385: if (cf_marker == NULL) |
3386: { |
3387: /* Add the l1 norm of the diag part of the ith row */ |
3388: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3389: l1_norm[i] += fabs(A_diag_data[j]); |
3390: /* Add the l1 norm of the offd part of the ith row */ |
3391: if (num_cols_offd) |
3392: { |
3393: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
3394: l1_norm[i] += fabs(A_offd_data[j]); |
3395: } |
3396: } |
3397: else |
3398: { |
3399: cf_diag = cf_marker[i]; |
3400: /* Add the CF l1 norm of the diag part of the ith row */ |
3401: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3402: if (cf_diag == cf_marker[A_diag_J[j]]) |
3403: l1_norm[i] += fabs(A_diag_data[j]); |
3404: /* Add the CF l1 norm of the offd part of the ith row */ |
3405: if (num_cols_offd) |
3406: { |
3407: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
3408: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
3409: l1_norm[i] += fabs(A_offd_data[j]); |
[...] |
3473: if (cf_marker == NULL) |
[...] |
3517: if (num_cols_offd) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.06 |
CQA speedup if FP arith vectorized | 2.92 |
CQA speedup if fully vectorized | 11.69 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.76 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3363-3363,ams.c:3382-3385,ams.c:3388-3394,ams.c:3399-3401,ams.c:3405-3409,ams.c:3473-3473,ams.c:3517-3517 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.67 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 7.42 |
CQA cycles if fully vectorized | 1.85 |
Front-end cycles | 21.67 |
DIV/SQRT cycles | 12.10 |
P0 cycles | 12.30 |
P1 cycles | 8.33 |
P2 cycles | 8.33 |
P3 cycles | 2.00 |
P4 cycles | 12.30 |
P5 cycles | 12.10 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 12.20 |
P10 cycles | 8.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 21.94 - 21.92 |
Stall cycles (UFS) | 0.00 |
Nb insns | 130.00 |
Nb uops | 130.00 |
Nb loads | 25.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.32 |
Nb FLOP add-sub | 7.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.71 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 21.28 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.67 |
Vector-efficiency ratio all | 14.76 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 10.94 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.42 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.06 |
CQA speedup if FP arith vectorized | 2.92 |
CQA speedup if fully vectorized | 11.69 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.76 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3363-3363,ams.c:3382-3385,ams.c:3388-3394,ams.c:3399-3401,ams.c:3405-3409,ams.c:3473-3473,ams.c:3517-3517 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.67 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 7.42 |
CQA cycles if fully vectorized | 1.85 |
Front-end cycles | 21.67 |
DIV/SQRT cycles | 12.10 |
P0 cycles | 12.30 |
P1 cycles | 8.33 |
P2 cycles | 8.33 |
P3 cycles | 2.00 |
P4 cycles | 12.30 |
P5 cycles | 12.10 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 12.20 |
P10 cycles | 8.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 21.94 - 21.92 |
Stall cycles (UFS) | 0.00 |
Nb insns | 130.00 |
Nb uops | 130.00 |
Nb loads | 25.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.32 |
Nb FLOP add-sub | 7.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.71 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 21.28 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.67 |
Vector-efficiency ratio all | 14.76 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 10.94 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.42 |
Path / |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3363-3517 |
Module | libparcsr_ls.so |
nb instructions | 130 |
nb uops | 130 |
loop length | 572 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 21.67 cycles |
front end | 21.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
cycles | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 21.94-21.92 |
Stall cycles | 0.00 |
Front-end | 21.67 |
Dispatch | 12.30 |
Overall L1 | 21.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 40% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 21% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 11% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 20% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 17% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x90(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0xa0(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 1dd0b <hypre_ParCSRComputeL1NormsThreads.extracted+0x160b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVQ $0,(%RAX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 1d460 <hypre_ParCSRComputeL1NormsThreads.extracted+0xd60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R8,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d3de <hypre_ParCSRComputeL1NormsThreads.extracted+0xcde> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 1d520 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe20> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 1d5e1 <hypre_ParCSRComputeL1NormsThreads.extracted+0xee1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0,-0x80(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 1d61b <hypre_ParCSRComputeL1NormsThreads.extracted+0xf1b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 1d43c <hypre_ParCSRComputeL1NormsThreads.extracted+0xd3c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d4ba <hypre_ParCSRComputeL1NormsThreads.extracted+0xdba> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%RBX,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RBX,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d6bc <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d6bc <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0x80(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%R14,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R14,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d711 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1011> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d711 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1011> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RDI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d551 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe51> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 1d5fc <hypre_ParCSRComputeL1NormsThreads.extracted+0xefc> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d63d <hypre_ParCSRComputeL1NormsThreads.extracted+0xf3d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 1d769 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1069> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 1d76b <hypre_ParCSRComputeL1NormsThreads.extracted+0x106b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 1d785 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1085> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 1d79a <hypre_ParCSRComputeL1NormsThreads.extracted+0x109a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 1d34d <hypre_ParCSRComputeL1NormsThreads.extracted+0xc4d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 1d79c <hypre_ParCSRComputeL1NormsThreads.extracted+0x109c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0x80(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 1d4c5 <hypre_ParCSRComputeL1NormsThreads.extracted+0xdc5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d34d <hypre_ParCSRComputeL1NormsThreads.extracted+0xc4d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3363-3517 |
Module | libparcsr_ls.so |
nb instructions | 130 |
nb uops | 130 |
loop length | 572 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 21.67 cycles |
front end | 21.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
cycles | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 21.94-21.92 |
Stall cycles | 0.00 |
Front-end | 21.67 |
Dispatch | 12.30 |
Overall L1 | 21.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 40% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 21% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 11% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 20% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 17% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x90(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0xa0(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 1dd0b <hypre_ParCSRComputeL1NormsThreads.extracted+0x160b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVQ $0,(%RAX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 1d460 <hypre_ParCSRComputeL1NormsThreads.extracted+0xd60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R8,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d3de <hypre_ParCSRComputeL1NormsThreads.extracted+0xcde> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 1d520 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe20> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 1d5e1 <hypre_ParCSRComputeL1NormsThreads.extracted+0xee1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0,-0x80(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 1d61b <hypre_ParCSRComputeL1NormsThreads.extracted+0xf1b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 1d43c <hypre_ParCSRComputeL1NormsThreads.extracted+0xd3c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d4ba <hypre_ParCSRComputeL1NormsThreads.extracted+0xdba> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%RBX,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RBX,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d6bc <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d6bc <hypre_ParCSRComputeL1NormsThreads.extracted+0xfbc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0x80(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%R14,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R14,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d711 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1011> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 1d711 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1011> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RDI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d551 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe51> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 1d5fc <hypre_ParCSRComputeL1NormsThreads.extracted+0xefc> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d63d <hypre_ParCSRComputeL1NormsThreads.extracted+0xf3d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 1d769 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1069> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 1d76b <hypre_ParCSRComputeL1NormsThreads.extracted+0x106b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 1d785 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1085> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 1d79a <hypre_ParCSRComputeL1NormsThreads.extracted+0x109a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x60(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 1d34d <hypre_ParCSRComputeL1NormsThreads.extracted+0xc4d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 1d79c <hypre_ParCSRComputeL1NormsThreads.extracted+0x109c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0x80(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 1d4c5 <hypre_ParCSRComputeL1NormsThreads.extracted+0xdc5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 1d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc60> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 1d34d <hypre_ParCSRComputeL1NormsThreads.extracted+0xc4d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |