Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.27% |
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Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.27% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-3872/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
[...] |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x4429d0 PUSH %RBP |
0x4429d1 MOV %RSP,%RBP |
0x4429d4 PUSH %R15 |
0x4429d6 PUSH %R14 |
0x4429d8 PUSH %R13 |
0x4429da PUSH %R12 |
0x4429dc PUSH %RBX |
0x4429dd SUB $0xe8,%RSP |
0x4429e4 MOV %R9,-0xc8(%RBP) |
0x4429eb MOV %R8,-0x90(%RBP) |
0x4429f2 MOV %RCX,-0xa0(%RBP) |
0x4429f9 MOV %RDX,-0x40(%RBP) |
0x4429fd MOV 0xe8(%RBP),%RAX |
0x442a04 MOV %RAX,-0x30(%RBP) |
0x442a08 MOV 0xe0(%RBP),%RAX |
0x442a0f MOV %RAX,-0x100(%RBP) |
0x442a16 MOV 0xd8(%RBP),%RDI |
0x442a1d MOV 0xd0(%RBP),%RAX |
0x442a24 MOV %RAX,-0x108(%RBP) |
0x442a2b MOV 0xc8(%RBP),%RAX |
0x442a32 MOV %RAX,-0xf8(%RBP) |
0x442a39 MOV 0xc0(%RBP),%RAX |
0x442a40 MOV %RAX,-0xc0(%RBP) |
0x442a47 MOV 0xb8(%RBP),%RAX |
0x442a4e MOV %RAX,-0xb8(%RBP) |
0x442a55 MOV 0xb0(%RBP),%RAX |
0x442a5c MOV %RAX,-0xe0(%RBP) |
0x442a63 MOV 0xa8(%RBP),%RAX |
0x442a6a MOV %RAX,-0xd8(%RBP) |
0x442a71 MOV 0xa0(%RBP),%RAX |
0x442a78 MOV %RAX,-0x50(%RBP) |
0x442a7c MOV 0x98(%RBP),%RAX |
0x442a83 MOV %RAX,-0xd0(%RBP) |
0x442a8a MOV 0x90(%RBP),%RBX |
0x442a91 MOV 0x88(%RBP),%R15 |
0x442a98 MOV 0x80(%RBP),%RAX |
0x442a9f MOV %RAX,-0xe8(%RBP) |
0x442aa6 MOV 0x78(%RBP),%RAX |
0x442aaa MOV %RAX,-0x110(%RBP) |
0x442ab1 MOV 0x70(%RBP),%RAX |
0x442ab5 MOV %RAX,-0xf0(%RBP) |
0x442abc MOV 0x68(%RBP),%RAX |
0x442ac0 MOV %RAX,-0x60(%RBP) |
0x442ac4 MOV 0x60(%RBP),%RAX |
0x442ac8 MOV %RAX,-0x68(%RBP) |
0x442acc MOV 0x58(%RBP),%RAX |
0x442ad0 MOV %RAX,-0xb0(%RBP) |
0x442ad7 MOV 0x50(%RBP),%RAX |
0x442adb MOV %RAX,-0x58(%RBP) |
0x442adf MOV 0x48(%RBP),%RAX |
0x442ae3 MOV %RAX,-0x88(%RBP) |
0x442aea MOV 0x40(%RBP),%RCX |
0x442aee MOV 0x38(%RBP),%RAX |
0x442af2 MOV %RAX,-0xa8(%RBP) |
0x442af9 MOV 0x30(%RBP),%RAX |
0x442afd MOV %RAX,-0x80(%RBP) |
0x442b01 MOV 0x28(%RBP),%RAX |
0x442b05 MOV %RAX,-0x98(%RBP) |
0x442b0c MOV 0x20(%RBP),%RAX |
0x442b10 MOV %RAX,-0x48(%RBP) |
0x442b14 MOV 0x18(%RBP),%RAX |
0x442b18 MOV %RAX,-0x70(%RBP) |
0x442b1c MOV 0x10(%RBP),%RAX |
0x442b20 MOV %RAX,-0x78(%RBP) |
0x442b24 TEST %RDI,%RDI |
0x442b27 MOV %RCX,-0x38(%RBP) |
0x442b2b JE 442bc3 |
0x442b31 MOV $0x8,%ESI |
0x442b36 MOV %RDI,%R12 |
0x442b39 CALL 4e6980 <hypre_CAlloc> |
0x442b3e MOV -0x38(%RBP),%RCX |
0x442b42 MOV %RAX,%R13 |
0x442b45 TEST %RCX,%RCX |
0x442b48 JE 442bce |
0x442b4e MOV $0x8,%ESI |
0x442b53 MOV %RCX,%RDI |
0x442b56 CALL 4e6980 <hypre_CAlloc> |
0x442b5b MOV %RAX,%R14 |
0x442b5e TEST %R12,%R12 |
0x442b61 JLE 442b77 |
0x442b63 SAL $0x3,%R12 |
0x442b67 MOV %R13,%RDI |
0x442b6a MOV $0xff,%ESI |
0x442b6f MOV %R12,%RDX |
0x442b72 CALL 4efbb0 <_intel_fast_memset> |
0x442b77 MOV -0x38(%RBP),%RDX |
0x442b7b TEST %RDX,%RDX |
0x442b7e JLE 442b91 |
0x442b80 SAL $0x3,%RDX |
0x442b84 MOV %R14,%RDI |
0x442b87 MOV $0xff,%ESI |
0x442b8c CALL 4efbb0 <_intel_fast_memset> |
0x442b91 CALL 4e86c0 <hypre_GetThreadNum> |
0x442b96 MOV %RAX,%R12 |
0x442b99 CALL 4e86b0 <hypre_NumActiveThreads> |
0x442b9e MOV %RAX,%RCX |
0x442ba1 MOV -0x50(%RBP),%RAX |
0x442ba5 MOV 0x8(%RAX),%RDI |
0x442ba9 MOV -0x30(%RBP),%R8 |
0x442bad MOV %R8,%RAX |
0x442bb0 OR %RCX,%RAX |
0x442bb3 SHR $0x20,%RAX |
0x442bb7 JE 442bd8 |
0x442bb9 MOV %R8,%RAX |
0x442bbc CQTO |
0x442bbe IDIV %RCX |
0x442bc1 JMP 442bdf |
0x442bc3 MOV %RDI,%R12 |
0x442bc6 XOR %R13D,%R13D |
0x442bc9 TEST %RCX,%RCX |
0x442bcc JNE 442b4e |
0x442bce XOR %R14D,%R14D |
0x442bd1 TEST %R12,%R12 |
0x442bd4 JG 442b63 |
0x442bd6 JMP 442b77 |
0x442bd8 MOV %R8D,%EAX |
0x442bdb XOR %EDX,%EDX |
0x442bdd DIV %ECX |
0x442bdf MOV -0x40(%RBP),%R10 |
0x442be3 MOV -0x48(%RBP),%R11 |
0x442be7 MOV %RAX,%RDX |
0x442bea IMUL %R12,%RDX |
0x442bee DEC %RCX |
0x442bf1 LEA 0x1(%R12),%RSI |
0x442bf6 IMUL %RAX,%RSI |
0x442bfa CMP %RCX,%R12 |
0x442bfd CMOVE %R8,%RSI |
0x442c01 MOV %RSI,-0x30(%RBP) |
0x442c05 CMP %RSI,%RDX |
0x442c08 JGE 4430f9 |
0x442c0e MOV -0x30(%RBP),%RAX |
0x442c12 ADD %RDI,%RAX |
0x442c15 MOV %RAX,-0x30(%RBP) |
0x442c19 ADD %RDI,%RDX |
0x442c1c VXORPD %XMM0,%XMM0,%XMM0 |
0x442c20 VMOVDDUP 0xbc4b8(%RIP),%XMM1 |
0x442c28 JMP 442c45 |
0x442c2a NOPW (%RAX,%RAX,1) |
(952) 0x442c30 MOV -0x50(%RBP),%RDX |
(952) 0x442c34 INC %RDX |
(952) 0x442c37 CMP -0x30(%RBP),%RDX |
(952) 0x442c3b MOV -0x48(%RBP),%R11 |
(952) 0x442c3f JGE 4430f9 |
(952) 0x442c45 MOV -0xd0(%RBP),%RAX |
(952) 0x442c4c MOV %RDX,-0x50(%RBP) |
(952) 0x442c50 MOV (%RAX,%RDX,8),%RAX |
(952) 0x442c54 MOV -0xd8(%RBP),%RCX |
(952) 0x442c5b MOV (%RCX,%RAX,8),%RDI |
(952) 0x442c5f MOV -0x58(%RBP),%RCX |
(952) 0x442c63 MOV (%RCX,%RAX,8),%RSI |
(952) 0x442c67 MOV 0x8(%RCX,%RAX,8),%RCX |
(952) 0x442c6c LEA (%RCX,%RDI,1),%RDX |
(952) 0x442c70 SUB %RSI,%RDX |
(952) 0x442c73 CMP %RDX,%RDI |
(952) 0x442c76 JGE 442d45 |
(952) 0x442c7c MOV -0xb8(%RBP),%RDX |
(952) 0x442c83 MOV 0x8(%RDX),%R8 |
(952) 0x442c87 SUB %RSI,%RCX |
(952) 0x442c8a CMP $0x8,%RCX |
(952) 0x442c8e JB 442d10 |
(952) 0x442c94 MOV %RCX,%R9 |
(952) 0x442c97 SHR $0x3,%R9 |
(952) 0x442c9b LEA 0x38(%R8,%RDI,8),%R10 |
(962) 0x442ca0 MOV -0x38(%R10),%RDX |
(962) 0x442ca4 MOV (%R15,%RDX,8),%RDX |
(962) 0x442ca8 MOV %RAX,(%R13,%RDX,8) |
(962) 0x442cad MOV -0x30(%R10),%RDX |
(962) 0x442cb1 MOV (%R15,%RDX,8),%RDX |
(962) 0x442cb5 MOV %RAX,(%R13,%RDX,8) |
(962) 0x442cba MOV -0x28(%R10),%RDX |
(962) 0x442cbe MOV (%R15,%RDX,8),%RDX |
(962) 0x442cc2 MOV %RAX,(%R13,%RDX,8) |
(962) 0x442cc7 MOV -0x20(%R10),%RDX |
(962) 0x442ccb MOV (%R15,%RDX,8),%RDX |
(962) 0x442ccf MOV %RAX,(%R13,%RDX,8) |
(962) 0x442cd4 MOV -0x18(%R10),%RDX |
(962) 0x442cd8 MOV (%R15,%RDX,8),%RDX |
(962) 0x442cdc MOV %RAX,(%R13,%RDX,8) |
(962) 0x442ce1 MOV -0x10(%R10),%RDX |
(962) 0x442ce5 MOV (%R15,%RDX,8),%RDX |
(962) 0x442ce9 MOV %RAX,(%R13,%RDX,8) |
(962) 0x442cee MOV -0x8(%R10),%RDX |
(962) 0x442cf2 MOV (%R15,%RDX,8),%RDX |
(962) 0x442cf6 MOV %RAX,(%R13,%RDX,8) |
(962) 0x442cfb MOV (%R10),%RDX |
(962) 0x442cfe MOV (%R15,%RDX,8),%RDX |
(962) 0x442d02 MOV %RAX,(%R13,%RDX,8) |
(962) 0x442d07 ADD $0x40,%R10 |
(962) 0x442d0b DEC %R9 |
(962) 0x442d0e JNE 442ca0 |
(952) 0x442d10 MOV %RCX,%R9 |
(952) 0x442d13 AND $-0x8,%R9 |
(952) 0x442d17 CMP %RCX,%R9 |
(952) 0x442d1a MOV -0x40(%RBP),%R10 |
(952) 0x442d1e JE 442d45 |
(952) 0x442d20 LEA (%R8,%RDI,8),%RDI |
(952) 0x442d24 NOPW %CS:(%RAX,%RAX,1) |
(961) 0x442d30 MOV (%RDI,%R9,8),%RDX |
(961) 0x442d34 MOV (%R15,%RDX,8),%RDX |
(961) 0x442d38 MOV %RAX,(%R13,%RDX,8) |
(961) 0x442d3d INC %R9 |
(961) 0x442d40 CMP %R9,%RCX |
(961) 0x442d43 JNE 442d30 |
(952) 0x442d45 MOV -0x58(%RBP),%RCX |
(952) 0x442d49 MOV (%RCX,%RAX,8),%R12 |
(952) 0x442d4d MOV -0x70(%RBP),%RCX |
(952) 0x442d51 MOV (%RCX,%RAX,8),%RDI |
(952) 0x442d55 MOV 0x8(%RCX,%RAX,8),%R8 |
(952) 0x442d5a INC %RDI |
(952) 0x442d5d VXORPD %XMM4,%XMM4,%XMM4 |
(952) 0x442d61 VXORPD %XMM3,%XMM3,%XMM3 |
(952) 0x442d65 CMP %R8,%RDI |
(952) 0x442d68 JGE 442e00 |
(952) 0x442d6e MOV -0xb0(%RBP),%RCX |
(952) 0x442d75 MOV -0x90(%RBP),%RSI |
(952) 0x442d7c JMP 442d88 |
0x442d7e XCHG %AX,%AX |
(960) 0x442d80 INC %RDI |
(960) 0x442d83 CMP %R8,%RDI |
(960) 0x442d86 JGE 442e00 |
(960) 0x442d88 MOV (%R11,%RDI,8),%R9 |
(960) 0x442d8c CMPQ $-0x3,(%R10,%R9,8) |
(960) 0x442d91 JE 442db0 |
(960) 0x442d93 CMPQ $0x1,-0xa0(%RBP) |
(960) 0x442d9b JE 442da7 |
(960) 0x442d9d MOV (%RSI,%RAX,8),%RDX |
(960) 0x442da1 CMP (%RSI,%R9,8),%RDX |
(960) 0x442da5 JNE 442db0 |
(960) 0x442da7 MOV -0x78(%RBP),%RDX |
(960) 0x442dab VADDSD (%RDX,%RDI,8),%XMM3,%XMM3 |
(960) 0x442db0 CMP $-0x1,%R9 |
(960) 0x442db4 JE 442d80 |
(960) 0x442db6 CMP %RAX,(%R13,%R9,8) |
(960) 0x442dbb JNE 442d80 |
(960) 0x442dbd MOV -0x78(%RBP),%RDX |
(960) 0x442dc1 VMOVSD (%RDX,%RDI,8),%XMM5 |
(960) 0x442dc6 MOV -0x88(%RBP),%RDX |
(960) 0x442dcd VMOVSD %XMM5,(%RDX,%R12,8) |
(960) 0x442dd3 MOV -0x100(%RBP),%RDX |
(960) 0x442dda MOV (%RDX,%R9,8),%RDX |
(960) 0x442dde MOV %RDX,(%RCX,%R12,8) |
(960) 0x442de2 INC %R12 |
(960) 0x442de5 VADDSD %XMM4,%XMM5,%XMM4 |
(960) 0x442de9 MOV -0x70(%RBP),%RDX |
(960) 0x442ded MOV 0x8(%RDX,%RAX,8),%R8 |
(960) 0x442df2 JMP 442d80 |
0x442df4 NOPW %CS:(%RAX,%RAX,1) |
(952) 0x442e00 MOV %R12,-0x38(%RBP) |
(952) 0x442e04 MOV -0xe0(%RBP),%RDX |
(952) 0x442e0b MOV (%RDX,%RAX,8),%R8 |
(952) 0x442e0f MOV -0x60(%RBP),%RCX |
(952) 0x442e13 MOV (%RCX,%RAX,8),%RSI |
(952) 0x442e17 MOV 0x8(%RCX,%RAX,8),%RDI |
(952) 0x442e1c LEA (%RDI,%R8,1),%RDX |
(952) 0x442e20 SUB %RSI,%RDX |
(952) 0x442e23 CMP %RDX,%R8 |
(952) 0x442e26 JGE 442ee4 |
(952) 0x442e2c MOV -0xc0(%RBP),%RDX |
(952) 0x442e33 MOV 0x8(%RDX),%R9 |
(952) 0x442e37 SUB %RSI,%RDI |
(952) 0x442e3a CMP $0x8,%RDI |
(952) 0x442e3e JB 442eb8 |
(952) 0x442e40 MOV %RDI,%R10 |
(952) 0x442e43 SHR $0x3,%R10 |
(952) 0x442e47 LEA 0x38(%R9,%R8,8),%R11 |
(952) 0x442e4c NOPL (%RAX) |
(959) 0x442e50 MOV -0x38(%R11),%RDX |
(959) 0x442e54 MOV (%RBX,%RDX,8),%RDX |
(959) 0x442e58 MOV %RAX,(%R14,%RDX,8) |
(959) 0x442e5c MOV -0x30(%R11),%RDX |
(959) 0x442e60 MOV (%RBX,%RDX,8),%RDX |
(959) 0x442e64 MOV %RAX,(%R14,%RDX,8) |
(959) 0x442e68 MOV -0x28(%R11),%RDX |
(959) 0x442e6c MOV (%RBX,%RDX,8),%RDX |
(959) 0x442e70 MOV %RAX,(%R14,%RDX,8) |
(959) 0x442e74 MOV -0x20(%R11),%RDX |
(959) 0x442e78 MOV (%RBX,%RDX,8),%RDX |
(959) 0x442e7c MOV %RAX,(%R14,%RDX,8) |
(959) 0x442e80 MOV -0x18(%R11),%RDX |
(959) 0x442e84 MOV (%RBX,%RDX,8),%RDX |
(959) 0x442e88 MOV %RAX,(%R14,%RDX,8) |
(959) 0x442e8c MOV -0x10(%R11),%RDX |
(959) 0x442e90 MOV (%RBX,%RDX,8),%RDX |
(959) 0x442e94 MOV %RAX,(%R14,%RDX,8) |
(959) 0x442e98 MOV -0x8(%R11),%RDX |
(959) 0x442e9c MOV (%RBX,%RDX,8),%RDX |
(959) 0x442ea0 MOV %RAX,(%R14,%RDX,8) |
(959) 0x442ea4 MOV (%R11),%RDX |
(959) 0x442ea7 MOV (%RBX,%RDX,8),%RDX |
(959) 0x442eab MOV %RAX,(%R14,%RDX,8) |
(959) 0x442eaf ADD $0x40,%R11 |
(959) 0x442eb3 DEC %R10 |
(959) 0x442eb6 JNE 442e50 |
(952) 0x442eb8 MOV %RDI,%R10 |
(952) 0x442ebb AND $-0x8,%R10 |
(952) 0x442ebf CMP %RDI,%R10 |
(952) 0x442ec2 JE 442ee4 |
(952) 0x442ec4 LEA (%R9,%R8,8),%R8 |
(952) 0x442ec8 NOPL (%RAX,%RAX,1) |
(958) 0x442ed0 MOV (%R8,%R10,8),%RDX |
(958) 0x442ed4 MOV (%RBX,%RDX,8),%RDX |
(958) 0x442ed8 MOV %RAX,(%R14,%RDX,8) |
(958) 0x442edc INC %R10 |
(958) 0x442edf CMP %R10,%RDI |
(958) 0x442ee2 JNE 442ed0 |
(952) 0x442ee4 MOV -0x60(%RBP),%RCX |
(952) 0x442ee8 MOV (%RCX,%RAX,8),%RDI |
(952) 0x442eec MOV -0x80(%RBP),%RCX |
(952) 0x442ef0 MOV (%RCX,%RAX,8),%R8 |
(952) 0x442ef4 MOV 0x8(%RCX,%RAX,8),%R10 |
(952) 0x442ef9 CMP %R10,%R8 |
(952) 0x442efc JGE 442fd0 |
(952) 0x442f02 MOV -0xa8(%RBP),%RCX |
(952) 0x442f09 LEA (%RCX,%R8,8),%R9 |
(952) 0x442f0d MOV -0xc8(%RBP),%RSI |
(952) 0x442f14 MOV -0xe8(%RBP),%R12 |
(952) 0x442f1b JMP 442f30 |
0x442f1d NOPL (%RAX) |
(957) 0x442f20 INC %R8 |
(957) 0x442f23 ADD $0x8,%R9 |
(957) 0x442f27 CMP %R10,%R8 |
(957) 0x442f2a JGE 442fd0 |
(957) 0x442f30 MOV %R9,%RDX |
(957) 0x442f33 TEST %RSI,%RSI |
(957) 0x442f36 JE 442f46 |
(957) 0x442f38 MOV (%R9),%RDX |
(957) 0x442f3b MOV -0x108(%RBP),%R11 |
(957) 0x442f42 LEA (%R11,%RDX,8),%RDX |
(957) 0x442f46 MOV (%RDX),%R11 |
(957) 0x442f49 MOV -0x110(%RBP),%RCX |
(957) 0x442f50 CMPQ $-0x3,(%RCX,%R11,8) |
(957) 0x442f55 JE 442f7f |
(957) 0x442f57 CMPQ $0x1,-0xa0(%RBP) |
(957) 0x442f5f JE 442f72 |
(957) 0x442f61 MOV -0x90(%RBP),%RDX |
(957) 0x442f68 MOV (%RDX,%RAX,8),%RDX |
(957) 0x442f6c CMP (%R12,%R11,8),%RDX |
(957) 0x442f70 JNE 442f7f |
(957) 0x442f72 MOV -0x98(%RBP),%RCX |
(957) 0x442f79 VADDSD (%RCX,%R8,8),%XMM3,%XMM3 |
(957) 0x442f7f CMP $-0x1,%R11 |
(957) 0x442f83 JE 442f20 |
(957) 0x442f85 CMP %RAX,(%R14,%R11,8) |
(957) 0x442f89 JNE 442f20 |
(957) 0x442f8b MOV -0x98(%RBP),%RCX |
(957) 0x442f92 VMOVSD (%RCX,%R8,8),%XMM5 |
(957) 0x442f98 MOV -0x68(%RBP),%RCX |
(957) 0x442f9c VMOVSD %XMM5,(%RCX,%RDI,8) |
(957) 0x442fa1 MOV -0xf8(%RBP),%RDX |
(957) 0x442fa8 MOV (%RDX,%R11,8),%RDX |
(957) 0x442fac MOV -0xf0(%RBP),%RCX |
(957) 0x442fb3 MOV %RDX,(%RCX,%RDI,8) |
(957) 0x442fb7 INC %RDI |
(957) 0x442fba VADDSD %XMM4,%XMM5,%XMM4 |
(957) 0x442fbe MOV -0x80(%RBP),%RCX |
(957) 0x442fc2 MOV 0x8(%RCX,%RAX,8),%R10 |
(957) 0x442fc7 JMP 442f20 |
0x442fcc NOPL (%RAX) |
(952) 0x442fd0 MOV -0x70(%RBP),%RCX |
(952) 0x442fd4 MOV (%RCX,%RAX,8),%RDX |
(952) 0x442fd8 MOV -0x78(%RBP),%RCX |
(952) 0x442fdc VMULSD (%RCX,%RDX,8),%XMM4,%XMM4 |
(952) 0x442fe1 VUCOMISD %XMM0,%XMM4 |
(952) 0x442fe5 JE 442fef |
(952) 0x442fe7 VXORPD %XMM1,%XMM3,%XMM2 |
(952) 0x442feb VDIVSD %XMM4,%XMM2,%XMM2 |
(952) 0x442fef MOV -0x58(%RBP),%RCX |
(952) 0x442ff3 MOV (%RCX,%RAX,8),%R9 |
(952) 0x442ff7 MOV -0x38(%RBP),%RDX |
(952) 0x442ffb MOV %RDX,%R10 |
(952) 0x442ffe SUB %R9,%R10 |
(952) 0x443001 MOV -0x68(%RBP),%R11 |
(952) 0x443005 MOV -0x88(%RBP),%RCX |
(952) 0x44300c JLE 443074 |
(952) 0x44300e MOV %R10,%R8 |
(952) 0x443011 AND $-0x4,%R8 |
(952) 0x443015 JE 443052 |
(952) 0x443017 LEA -0x1(%R8),%R11 |
(952) 0x44301b VBROADCASTSD %XMM2,%YMM3 |
(952) 0x443020 LEA (%RCX,%R9,8),%RSI |
(952) 0x443024 XOR %EDX,%EDX |
(952) 0x443026 NOPW %CS:(%RAX,%RAX,1) |
(956) 0x443030 VMULPD (%RSI,%RDX,8),%YMM3,%YMM4 |
(956) 0x443035 VMOVUPD %YMM4,(%RSI,%RDX,8) |
(956) 0x44303a ADD $0x4,%RDX |
(956) 0x44303e CMP %R11,%RDX |
(956) 0x443041 JBE 443030 |
(952) 0x443043 CMP %R8,%R10 |
(952) 0x443046 MOV -0x68(%RBP),%R11 |
(952) 0x44304a MOV -0x38(%RBP),%RDX |
(952) 0x44304e JNE 443055 |
(952) 0x443050 JMP 443074 |
(952) 0x443052 XOR %R8D,%R8D |
(952) 0x443055 ADD %R9,%R8 |
(952) 0x443058 NOPL (%RAX,%RAX,1) |
(955) 0x443060 VMULSD (%RCX,%R8,8),%XMM2,%XMM3 |
(955) 0x443066 VMOVSD %XMM3,(%RCX,%R8,8) |
(955) 0x44306c INC %R8 |
(955) 0x44306f CMP %R8,%RDX |
(955) 0x443072 JNE 443060 |
(952) 0x443074 MOV -0x60(%RBP),%RCX |
(952) 0x443078 MOV (%RCX,%RAX,8),%RCX |
(952) 0x44307c MOV %RDI,%R8 |
(952) 0x44307f SUB %RCX,%R8 |
(952) 0x443082 MOV -0x40(%RBP),%R10 |
(952) 0x443086 JLE 442c30 |
(952) 0x44308c MOV %R8,%RAX |
(952) 0x44308f AND $-0x4,%RAX |
(952) 0x443093 JE 4430ce |
(952) 0x443095 LEA -0x1(%RAX),%R9 |
(952) 0x443099 VBROADCASTSD %XMM2,%YMM3 |
(952) 0x44309e LEA (%R11,%RCX,8),%RSI |
(952) 0x4430a2 XOR %EDX,%EDX |
(952) 0x4430a4 NOPW %CS:(%RAX,%RAX,1) |
(954) 0x4430b0 VMULPD (%RSI,%RDX,8),%YMM3,%YMM4 |
(954) 0x4430b5 VMOVUPD %YMM4,(%RSI,%RDX,8) |
(954) 0x4430ba ADD $0x4,%RDX |
(954) 0x4430be CMP %R9,%RDX |
(954) 0x4430c1 JBE 4430b0 |
(952) 0x4430c3 CMP %RAX,%R8 |
(952) 0x4430c6 JE 442c30 |
(952) 0x4430cc JMP 4430d0 |
(952) 0x4430ce XOR %EAX,%EAX |
(952) 0x4430d0 ADD %RCX,%RAX |
(952) 0x4430d3 NOPW %CS:(%RAX,%RAX,1) |
(953) 0x4430e0 VMULSD (%R11,%RAX,8),%XMM2,%XMM3 |
(953) 0x4430e6 VMOVSD %XMM3,(%R11,%RAX,8) |
(953) 0x4430ec INC %RAX |
(953) 0x4430ef CMP %RAX,%RDI |
(953) 0x4430f2 JNE 4430e0 |
(952) 0x4430f4 JMP 442c30 |
0x4430f9 MOV %R13,%RDI |
0x4430fc VZEROUPPER |
0x4430ff CALL 4e6a60 <hypre_Free> |
0x443104 MOV %R14,%RDI |
0x443107 ADD $0xe8,%RSP |
0x44310e POP %RBX |
0x44310f POP %R12 |
0x443111 POP %R13 |
0x443113 POP %R14 |
0x443115 POP %R15 |
0x443117 POP %RBP |
0x443118 JMP 4e6a60 |
0x44311d NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 155 |
nb uops | 170 |
loop length | 668 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 57 |
micro-operation queue | 28.33 cycles |
front end | 28.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 8.00 | 14.33 | 14.33 | 22.00 | 7.60 | 7.50 | 22.00 | 22.00 | 22.00 | 7.40 | 14.33 |
cycles | 7.50 | 11.40 | 14.33 | 14.33 | 22.00 | 7.60 | 7.50 | 22.00 | 22.00 | 22.00 | 7.40 | 14.33 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 26.70-26.75 |
Stall cycles | 0.00 |
Front-end | 28.33 |
Dispatch | 22.00 |
DIV/SQRT | 16.00 |
Overall L1 | 28.33 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 442bc3 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 442bce <hypre_BoomerAMGBuildMultipass.extracted.27+0x1fe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 442b77 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 442b91 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 4e86c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e86b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 442bd8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x208> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 442bdf <hypre_BoomerAMGBuildMultipass.extracted.27+0x20f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 442b4e <hypre_BoomerAMGBuildMultipass.extracted.27+0x17e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JG 442b63 <hypre_BoomerAMGBuildMultipass.extracted.27+0x193> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 442b77 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R12),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %R8,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4430f9 <hypre_BoomerAMGBuildMultipass.extracted.27+0x729> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0xbc4b8(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 442c45 <hypre_BoomerAMGBuildMultipass.extracted.27+0x275> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4e6a60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 155 |
nb uops | 170 |
loop length | 668 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 57 |
micro-operation queue | 28.33 cycles |
front end | 28.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 8.00 | 14.33 | 14.33 | 22.00 | 7.60 | 7.50 | 22.00 | 22.00 | 22.00 | 7.40 | 14.33 |
cycles | 7.50 | 11.40 | 14.33 | 14.33 | 22.00 | 7.60 | 7.50 | 22.00 | 22.00 | 22.00 | 7.40 | 14.33 |
Cycles executing div or sqrt instructions | 16.00 |
FE+BE cycles | 26.70-26.75 |
Stall cycles | 0.00 |
Front-end | 28.33 |
Dispatch | 22.00 |
DIV/SQRT | 16.00 |
Overall L1 | 28.33 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 442bc3 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 442bce <hypre_BoomerAMGBuildMultipass.extracted.27+0x1fe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e6980 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 442b77 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 442b91 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4efbb0 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CALL 4e86c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4e86b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 442bd8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x208> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 442bdf <hypre_BoomerAMGBuildMultipass.extracted.27+0x20f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 442b4e <hypre_BoomerAMGBuildMultipass.extracted.27+0x17e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JG 442b63 <hypre_BoomerAMGBuildMultipass.extracted.27+0x193> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 442b77 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%R12),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %RCX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %R8,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4430f9 <hypre_BoomerAMGBuildMultipass.extracted.27+0x729> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0xbc4b8(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 442c45 <hypre_BoomerAMGBuildMultipass.extracted.27+0x275> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e6a60 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0xe8,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 4e6a60 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass.extracted.27– | 0.27 | 0.05 |
▼Loop 952 - par_multi_interp.c:1585-1660 - exec– | 0.04 | 0.01 |
○Loop 960 - par_multi_interp.c:1618-1628 - exec | 0.22 | 0.04 |
○Loop 961 - par_multi_interp.c:1612-1615 - exec | 0.01 | 0 |
○Loop 958 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 959 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 955 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 957 - par_multi_interp.c:1622-1652 - exec | 0 | 0 |
○Loop 962 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 956 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 953 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 954 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |