Loop Id: 1313 | Module: libparcsr_ls.so | Source: par_multi_interp.c:917-1125 [...] | Coverage: 0.05% |
---|
Loop Id: 1313 | Module: libparcsr_ls.so | Source: par_multi_interp.c:917-1125 [...] | Coverage: 0.05% |
---|
0x4f6b0 MOV -0x58(%RBP),%RDX |
0x4f6b4 INC %RDX |
0x4f6b7 CMP -0xe0(%RBP),%RDX |
0x4f6be JGE 4fb90 |
0x4f6c4 MOV %RDX,-0x58(%RBP) |
0x4f6c8 MOV -0x40(%RBP),%RSI |
0x4f6cc MOV (%RSI,%RDX,8),%RSI |
0x4f6d0 MOV -0xa0(%RBP),%RDX |
0x4f6d7 MOV (%RDX,%RSI,8),%R8 |
0x4f6db MOV %RSI,%RDI |
0x4f6de NOT %RDI |
0x4f6e1 CMP 0x8(%RDX,%RSI,8),%R8 |
0x4f6e6 JGE 4fa80 |
0x4f6ec MOV -0x110(%RBP),%RDX |
0x4f6f3 MOV (%RDX),%R9 |
0x4f6f6 MOV %R9,-0x60(%RBP) |
0x4f6fa JMP 4f71d |
(1316) 0x4f6fc MOV -0x38(%RBP),%RBX |
(1316) 0x4f700 MOV -0x70(%RBP),%R8 |
(1316) 0x4f704 MOV -0x60(%RBP),%R9 |
(1316) 0x4f708 INC %R8 |
(1316) 0x4f70b MOV -0xa0(%RBP),%RDX |
(1316) 0x4f712 CMP 0x8(%RDX,%RSI,8),%R8 |
(1316) 0x4f717 JGE 4fa80 |
(1316) 0x4f71d MOV -0x140(%RBP),%RDX |
(1316) 0x4f724 MOV (%RDX,%R8,8),%R12 |
(1316) 0x4f728 MOV (%R14),%RDX |
(1316) 0x4f72b DEC %RDX |
(1316) 0x4f72e CMP %RDX,(%R9,%R12,8) |
(1316) 0x4f732 JNE 4f708 |
(1316) 0x4f734 MOV %R8,-0x70(%RBP) |
(1316) 0x4f738 MOV -0xf8(%RBP),%RDX |
(1316) 0x4f73f MOV (%RDX),%RDX |
(1316) 0x4f742 MOV 0x8(%RDX,%R12,8),%R10 |
(1316) 0x4f747 TEST %R10,%R10 |
(1316) 0x4f74a JLE 4f7a7 |
(1316) 0x4f74c MOV -0x68(%RBP),%RDX |
(1316) 0x4f750 MOV %R12,-0x48(%RBP) |
(1316) 0x4f754 MOV (%RDX,%R12,8),%RDX |
(1316) 0x4f758 ADD %RDX,%R10 |
(1316) 0x4f75b MOV -0xa8(%RBP),%R8 |
(1316) 0x4f762 MOV (%R8),%R9 |
(1316) 0x4f765 LEA 0x1(%RDX),%R8 |
(1316) 0x4f769 CMP %R8,%R10 |
(1316) 0x4f76c CMOVLE %R8,%R10 |
(1316) 0x4f770 MOV %R10,-0xf0(%RBP) |
(1316) 0x4f777 SUB %RDX,%R10 |
(1316) 0x4f77a CMP $0x4,%R10 |
(1316) 0x4f77e MOV %R10,-0x50(%RBP) |
(1316) 0x4f782 JAE 4f856 |
(1316) 0x4f788 MOV -0x50(%RBP),%R10 |
(1316) 0x4f78c MOV %R10,%R8 |
(1316) 0x4f78f AND $-0x4,%R8 |
(1316) 0x4f793 CMP %R10,%R8 |
(1316) 0x4f796 JNE 4f94b |
(1316) 0x4f79c MOV -0x118(%RBP),%R15 |
(1316) 0x4f7a3 MOV -0x48(%RBP),%R12 |
(1316) 0x4f7a7 MOV -0x100(%RBP),%RDX |
(1316) 0x4f7ae MOV (%RDX),%RDX |
(1316) 0x4f7b1 MOV 0x8(%RDX,%R12,8),%R10 |
(1316) 0x4f7b6 TEST %R10,%R10 |
(1316) 0x4f7b9 JLE 4f700 |
(1316) 0x4f7bf MOV -0xe8(%RBP),%RDX |
(1316) 0x4f7c6 MOV (%RDX),%RDX |
(1316) 0x4f7c9 MOV (%RDX,%R12,8),%RDX |
(1316) 0x4f7cd ADD %RDX,%R10 |
(1316) 0x4f7d0 MOV -0x78(%RBP),%R8 |
(1316) 0x4f7d4 MOV (%R8),%R9 |
(1316) 0x4f7d7 LEA 0x1(%RDX),%R8 |
(1316) 0x4f7db CMP %R8,%R10 |
(1316) 0x4f7de CMOVLE %R8,%R10 |
(1316) 0x4f7e2 MOV %R10,-0x50(%RBP) |
(1316) 0x4f7e6 SUB %RDX,%R10 |
(1316) 0x4f7e9 CMP $0x4,%R10 |
(1316) 0x4f7ed MOV %R10,-0x48(%RBP) |
(1316) 0x4f7f1 JAE 4f9a6 |
(1316) 0x4f7f7 MOV -0x48(%RBP),%R10 |
(1316) 0x4f7fb MOV %R10,%R8 |
(1316) 0x4f7fe AND $-0x4,%R8 |
(1316) 0x4f802 CMP %R10,%R8 |
(1316) 0x4f805 JE 4f6fc |
(1316) 0x4f80b ADD %R8,%RDX |
(1316) 0x4f80e MOV -0x38(%RBP),%RBX |
(1316) 0x4f812 MOV -0x50(%RBP),%R12 |
(1316) 0x4f816 JMP 4f82c |
(1317) 0x4f820 INC %RDX |
(1317) 0x4f823 CMP %RDX,%R12 |
(1317) 0x4f826 JE 4f700 |
(1317) 0x4f82c MOV (%R14),%R10 |
(1317) 0x4f82f MOV -0x8(%R9,%R10,8),%R8 |
(1317) 0x4f834 MOV (%R8,%RDX,8),%R8 |
(1317) 0x4f838 MOV (%R15,%R8,8),%R11 |
(1317) 0x4f83c XOR %RSI,%R11 |
(1317) 0x4f83f CMP $-0x1,%R11 |
(1317) 0x4f843 JE 4f820 |
(1317) 0x4f845 MOV (%R9,%R10,8),%R10 |
(1317) 0x4f849 MOV %R8,(%R10,%RCX,8) |
(1317) 0x4f84d INC %RCX |
(1317) 0x4f850 MOV %RDI,(%R15,%R8,8) |
(1317) 0x4f854 JMP 4f820 |
(1316) 0x4f856 MOV %R10,%R13 |
(1316) 0x4f859 SHR $0x2,%R13 |
(1316) 0x4f85d LEA (,%RDX,8),%R12 |
(1316) 0x4f865 JMP 4f893 |
(1320) 0x4f870 MOV (%R9,%R10,8),%R10 |
(1320) 0x4f874 MOV %R8,(%R10,%RAX,8) |
(1320) 0x4f878 INC %RAX |
(1320) 0x4f87b MOV %R15,%RDI |
(1320) 0x4f87e MOV %R15,(%RBX,%R8,8) |
(1320) 0x4f882 MOV -0x30(%RBP),%R14 |
(1320) 0x4f886 ADD $0x20,%R12 |
(1320) 0x4f88a DEC %R13 |
(1320) 0x4f88d JE 4f788 |
(1320) 0x4f893 MOV %RDI,%R15 |
(1320) 0x4f896 MOV (%R14),%R10 |
(1320) 0x4f899 MOV -0x8(%R9,%R10,8),%R8 |
(1320) 0x4f89e MOV (%R8,%R12,1),%R11 |
(1320) 0x4f8a2 MOV %R14,%RDI |
(1320) 0x4f8a5 MOV %RBX,%R14 |
(1320) 0x4f8a8 MOV (%RBX,%R11,8),%RBX |
(1320) 0x4f8ac XOR %RSI,%RBX |
(1320) 0x4f8af CMP $-0x1,%RBX |
(1320) 0x4f8b3 JE 4f8cc |
(1320) 0x4f8b5 MOV (%R9,%R10,8),%R8 |
(1320) 0x4f8b9 MOV %R11,(%R8,%RAX,8) |
(1320) 0x4f8bd INC %RAX |
(1320) 0x4f8c0 MOV %R15,(%R14,%R11,8) |
(1320) 0x4f8c4 MOV (%RDI),%R10 |
(1320) 0x4f8c7 MOV -0x8(%R9,%R10,8),%R8 |
(1320) 0x4f8cc MOV 0x8(%R8,%R12,1),%R11 |
(1320) 0x4f8d1 MOV (%R14,%R11,8),%RBX |
(1320) 0x4f8d5 XOR %RSI,%RBX |
(1320) 0x4f8d8 CMP $-0x1,%RBX |
(1320) 0x4f8dc JE 4f8f9 |
(1320) 0x4f8de MOV (%R9,%R10,8),%R8 |
(1320) 0x4f8e2 MOV %R11,(%R8,%RAX,8) |
(1320) 0x4f8e6 INC %RAX |
(1320) 0x4f8e9 MOV %R15,(%R14,%R11,8) |
(1320) 0x4f8ed MOV -0x30(%RBP),%RDI |
(1320) 0x4f8f1 MOV (%RDI),%R10 |
(1320) 0x4f8f4 MOV -0x8(%R9,%R10,8),%R8 |
(1320) 0x4f8f9 MOV 0x10(%R8,%R12,1),%R11 |
(1320) 0x4f8fe MOV (%R14,%R11,8),%RBX |
(1320) 0x4f902 XOR %RSI,%RBX |
(1320) 0x4f905 CMP $-0x1,%RBX |
(1320) 0x4f909 JE 4f926 |
(1320) 0x4f90b MOV (%R9,%R10,8),%R8 |
(1320) 0x4f90f MOV %R11,(%R8,%RAX,8) |
(1320) 0x4f913 INC %RAX |
(1320) 0x4f916 MOV %R15,(%R14,%R11,8) |
(1320) 0x4f91a MOV -0x30(%RBP),%RDI |
(1320) 0x4f91e MOV (%RDI),%R10 |
(1320) 0x4f921 MOV -0x8(%R9,%R10,8),%R8 |
(1320) 0x4f926 MOV %R14,%RBX |
(1320) 0x4f929 MOV 0x18(%R8,%R12,1),%R8 |
(1320) 0x4f92e MOV (%R14,%R8,8),%R11 |
(1320) 0x4f932 XOR %RSI,%R11 |
(1320) 0x4f935 CMP $-0x1,%R11 |
(1320) 0x4f939 JNE 4f870 |
(1320) 0x4f93f MOV -0x30(%RBP),%R14 |
(1320) 0x4f943 MOV %R15,%RDI |
(1320) 0x4f946 JMP 4f886 |
(1316) 0x4f94b ADD %R8,%RDX |
(1316) 0x4f94e MOV -0x118(%RBP),%R15 |
(1316) 0x4f955 MOV -0x48(%RBP),%R12 |
(1316) 0x4f959 MOV -0xf0(%RBP),%R13 |
(1316) 0x4f960 JMP 4f97c |
(1319) 0x4f970 INC %RDX |
(1319) 0x4f973 CMP %RDX,%R13 |
(1319) 0x4f976 JE 4f7a7 |
(1319) 0x4f97c MOV (%R14),%R10 |
(1319) 0x4f97f MOV -0x8(%R9,%R10,8),%R8 |
(1319) 0x4f984 MOV (%R8,%RDX,8),%R8 |
(1319) 0x4f988 MOV (%RBX,%R8,8),%R11 |
(1319) 0x4f98c XOR %RSI,%R11 |
(1319) 0x4f98f CMP $-0x1,%R11 |
(1319) 0x4f993 JE 4f970 |
(1319) 0x4f995 MOV (%R9,%R10,8),%R10 |
(1319) 0x4f999 MOV %R8,(%R10,%RAX,8) |
(1319) 0x4f99d INC %RAX |
(1319) 0x4f9a0 MOV %RDI,(%RBX,%R8,8) |
(1319) 0x4f9a4 JMP 4f970 |
(1316) 0x4f9a6 MOV %R10,%R12 |
(1316) 0x4f9a9 SHR $0x2,%R12 |
(1316) 0x4f9ad LEA (,%RDX,8),%R13 |
(1316) 0x4f9b5 JMP 4f9cd |
(1318) 0x4f9c0 ADD $0x20,%R13 |
(1318) 0x4f9c4 DEC %R12 |
(1318) 0x4f9c7 JE 4f7f7 |
(1318) 0x4f9cd MOV (%R14),%R10 |
(1318) 0x4f9d0 MOV -0x8(%R9,%R10,8),%R8 |
(1318) 0x4f9d5 MOV (%R8,%R13,1),%R11 |
(1318) 0x4f9d9 MOV (%R15,%R11,8),%RBX |
(1318) 0x4f9dd XOR %RSI,%RBX |
(1318) 0x4f9e0 CMP $-0x1,%RBX |
(1318) 0x4f9e4 JE 4f9fd |
(1318) 0x4f9e6 MOV (%R9,%R10,8),%R8 |
(1318) 0x4f9ea MOV %R11,(%R8,%RCX,8) |
(1318) 0x4f9ee INC %RCX |
(1318) 0x4f9f1 MOV %RDI,(%R15,%R11,8) |
(1318) 0x4f9f5 MOV (%R14),%R10 |
(1318) 0x4f9f8 MOV -0x8(%R9,%R10,8),%R8 |
(1318) 0x4f9fd MOV 0x8(%R8,%R13,1),%R11 |
(1318) 0x4fa02 MOV (%R15,%R11,8),%RBX |
(1318) 0x4fa06 XOR %RSI,%RBX |
(1318) 0x4fa09 CMP $-0x1,%RBX |
(1318) 0x4fa0d JE 4fa26 |
(1318) 0x4fa0f MOV (%R9,%R10,8),%R8 |
(1318) 0x4fa13 MOV %R11,(%R8,%RCX,8) |
(1318) 0x4fa17 INC %RCX |
(1318) 0x4fa1a MOV %RDI,(%R15,%R11,8) |
(1318) 0x4fa1e MOV (%R14),%R10 |
(1318) 0x4fa21 MOV -0x8(%R9,%R10,8),%R8 |
(1318) 0x4fa26 MOV 0x10(%R8,%R13,1),%R11 |
(1318) 0x4fa2b MOV (%R15,%R11,8),%RBX |
(1318) 0x4fa2f XOR %RSI,%RBX |
(1318) 0x4fa32 CMP $-0x1,%RBX |
(1318) 0x4fa36 JE 4fa4f |
(1318) 0x4fa38 MOV (%R9,%R10,8),%R8 |
(1318) 0x4fa3c MOV %R11,(%R8,%RCX,8) |
(1318) 0x4fa40 INC %RCX |
(1318) 0x4fa43 MOV %RDI,(%R15,%R11,8) |
(1318) 0x4fa47 MOV (%R14),%R10 |
(1318) 0x4fa4a MOV -0x8(%R9,%R10,8),%R8 |
(1318) 0x4fa4f MOV 0x18(%R8,%R13,1),%R8 |
(1318) 0x4fa54 MOV (%R15,%R8,8),%R11 |
(1318) 0x4fa58 XOR %RSI,%R11 |
(1318) 0x4fa5b CMP $-0x1,%R11 |
(1318) 0x4fa5f JE 4f9c0 |
(1318) 0x4fa65 MOV (%R9,%R10,8),%R10 |
(1318) 0x4fa69 MOV %R8,(%R10,%RCX,8) |
(1318) 0x4fa6d INC %RCX |
(1318) 0x4fa70 MOV %RDI,(%R15,%R8,8) |
(1318) 0x4fa74 JMP 4f9c0 |
0x4fa80 MOV -0x98(%RBP),%R8 |
0x4fa87 MOV (%R8,%RSI,8),%RDX |
0x4fa8b MOV 0x8(%R8,%RSI,8),%R9 |
0x4fa90 JMP 4faaf |
(1314) 0x4faa0 MOV -0x98(%RBP),%R8 |
(1314) 0x4faa7 MOV 0x8(%R8,%RSI,8),%R9 |
(1314) 0x4faac INC %RDX |
(1314) 0x4faaf CMP %R9,%RDX |
(1314) 0x4fab2 JGE 4f6b0 |
(1314) 0x4fab8 MOV -0x148(%RBP),%R8 |
(1314) 0x4fabf MOV (%R8,%RDX,8),%R10 |
(1314) 0x4fac3 MOV (%R14),%R8 |
(1314) 0x4fac6 DEC %R8 |
(1314) 0x4fac9 MOV -0x138(%RBP),%R11 |
(1314) 0x4fad0 CMP %R8,(%R11,%R10,8) |
(1314) 0x4fad4 JNE 4faac |
(1314) 0x4fad6 MOV -0x130(%RBP),%R8 |
(1314) 0x4fadd MOV 0x8(%R8,%R10,8),%R8 |
(1314) 0x4fae2 TEST %R8,%R8 |
(1314) 0x4fae5 JLE 4faac |
(1314) 0x4fae7 MOV -0x120(%RBP),%R9 |
(1314) 0x4faee MOV (%R9,%R10,8),%R9 |
(1314) 0x4faf2 ADD %R9,%R8 |
(1314) 0x4faf5 MOV -0x128(%RBP),%R10 |
(1314) 0x4fafc MOV (%R10),%R10 |
(1314) 0x4faff JMP 4fb18 |
(1315) 0x4fb10 INC %R9 |
(1315) 0x4fb13 CMP %R8,%R9 |
(1315) 0x4fb16 JGE 4faa0 |
(1315) 0x4fb18 MOV (%R14),%R12 |
(1315) 0x4fb1b MOV (%R10,%R12,8),%R11 |
(1315) 0x4fb1f MOV (%R11,%R9,8),%R11 |
(1315) 0x4fb23 TEST %R11,%R11 |
(1315) 0x4fb26 JS 4fb60 |
(1315) 0x4fb28 MOV (%R15,%R11,8),%R13 |
(1315) 0x4fb2c XOR %RSI,%R13 |
(1315) 0x4fb2f CMP $-0x1,%R13 |
(1315) 0x4fb33 JE 4fb10 |
(1315) 0x4fb35 MOV -0x78(%RBP),%RBX |
(1315) 0x4fb39 MOV (%RBX),%R13 |
(1315) 0x4fb3c MOV -0x38(%RBP),%RBX |
(1315) 0x4fb40 MOV (%R13,%R12,8),%R12 |
(1315) 0x4fb45 MOV %R11,(%R12,%RCX,8) |
(1315) 0x4fb49 INC %RCX |
(1315) 0x4fb4c MOV %RDI,(%R15,%R11,8) |
(1315) 0x4fb50 JMP 4fb10 |
(1315) 0x4fb60 NOT %R11 |
(1315) 0x4fb63 MOV (%RBX,%R11,8),%R13 |
(1315) 0x4fb67 XOR %RSI,%R13 |
(1315) 0x4fb6a CMP $-0x1,%R13 |
(1315) 0x4fb6e JE 4fb10 |
(1315) 0x4fb70 MOV -0xa8(%RBP),%RBX |
(1315) 0x4fb77 MOV (%RBX),%R13 |
(1315) 0x4fb7a MOV -0x38(%RBP),%RBX |
(1315) 0x4fb7e MOV (%R13,%R12,8),%R12 |
(1315) 0x4fb83 MOV %R11,(%R12,%RAX,8) |
(1315) 0x4fb87 INC %RAX |
(1315) 0x4fb8a MOV %RDI,(%RBX,%R11,8) |
(1315) 0x4fb8e JMP 4fb10 |
/scratch_na/users/xoserete/qaas_runs/171-587-0005/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 1125 |
-------------------------------------------------------------------------------- |
917: for (i=0; i < n_coarse; i++) |
[...] |
1072: for (i=thread_start; i < thread_stop; i++) |
1073: { |
1074: i1 = pass_array[i]; |
1075: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1076: { |
1077: j1 = S_diag_j[j]; |
1078: if (assigned[j1] == pass-1) |
1079: { |
1080: j_start = P_diag_start[j1]; |
1081: j_end = j_start+P_diag_i[j1+1]; |
1082: for (k=j_start; k < j_end; k++) |
1083: { |
1084: k1 = P_diag_pass[pass-1][k]; |
1085: if (P_marker[k1] != -i1-1) |
1086: { |
1087: P_diag_pass[pass][cnt_nz++] = k1; |
1088: P_marker[k1] = -i1-1; |
1089: } |
1090: } |
1091: j_start = P_offd_start[j1]; |
1092: j_end = j_start+P_offd_i[j1+1]; |
1093: for (k=j_start; k < j_end; k++) |
1094: { |
1095: k1 = P_offd_pass[pass-1][k]; |
1096: if (P_marker_offd[k1] != -i1-1) |
1097: { |
1098: P_offd_pass[pass][cnt_nz_offd++] = k1; |
1099: P_marker_offd[k1] = -i1-1; |
1100: } |
1101: } |
1102: } |
1103: } |
1104: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1105: { |
1106: j1 = S_offd_j[j]; |
1107: if (assigned_offd[j1] == pass-1) |
1108: { |
1109: j_start = Pext_start[j1]; |
1110: j_end = j_start+Pext_i[j1+1]; |
1111: for (k=j_start; k < j_end; k++) |
1112: { |
1113: k1 = Pext_pass[pass][k]; |
1114: if (k1 < 0) |
1115: { |
1116: if (P_marker[-k1-1] != -i1-1) |
1117: { |
1118: P_diag_pass[pass][cnt_nz++] = -k1-1; |
1119: P_marker[-k1-1] = -i1-1; |
1120: } |
1121: } |
1122: else if (P_marker_offd[k1] != -i1-1) |
1123: { |
1124: P_offd_pass[pass][cnt_nz_offd++] = k1; |
1125: P_marker_offd[k1] = -i1-1; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.09 |
Bottlenecks | P2, P3, P11, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.00 |
CQA cycles if no scalar integer | 4.00 |
CQA cycles if FP arith vectorized | 4.00 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 3.67 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 4.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 5.14 |
Stall cycles (UFS) | 1.32 |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 12.00 |
Nb stores | 2.00 |
Nb stack references | 7.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 28.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.09 |
Bottlenecks | P2, P3, P11, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.00 |
CQA cycles if no scalar integer | 4.00 |
CQA cycles if FP arith vectorized | 4.00 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 3.67 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 4.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 5.14 |
Stall cycles (UFS) | 1.32 |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 12.00 |
Nb stores | 2.00 |
Nb stack references | 7.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 28.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-1125 |
Module | libparcsr_ls.so |
nb instructions | 21 |
nb uops | 21 |
loop length | 94 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 3.67 cycles |
front end | 3.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 4.00 | 4.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 |
cycles | 1.00 | 1.00 | 4.00 | 4.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 5.14 |
Stall cycles | 1.32 |
LM full (events) | 3.65 |
Front-end | 3.67 |
Dispatch | 4.00 |
Overall L1 | 4.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0xe0(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4fb90 <hypre_BoomerAMGBuildMultipass.extracted.34+0xe70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP 0x8(%RDX,%RSI,8),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4fa80 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4f71d <hypre_BoomerAMGBuildMultipass.extracted.34+0x9fd> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x98(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%RSI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R8,%RSI,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4faaf <hypre_BoomerAMGBuildMultipass.extracted.34+0xd8f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-1125 |
Module | libparcsr_ls.so |
nb instructions | 21 |
nb uops | 21 |
loop length | 94 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 3.67 cycles |
front end | 3.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 4.00 | 4.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 |
cycles | 1.00 | 1.00 | 4.00 | 4.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 5.14 |
Stall cycles | 1.32 |
LM full (events) | 3.65 |
Front-end | 3.67 |
Dispatch | 4.00 |
Overall L1 | 4.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0xe0(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4fb90 <hypre_BoomerAMGBuildMultipass.extracted.34+0xe70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP 0x8(%RDX,%RSI,8),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4fa80 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4f71d <hypre_BoomerAMGBuildMultipass.extracted.34+0x9fd> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x98(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%RSI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R8,%RSI,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4faaf <hypre_BoomerAMGBuildMultipass.extracted.34+0xd8f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |