Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.45% |
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Function: hypre_BoomerAMGBuildMultipass.extracted.27 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.45% |
---|
/home/eoseret/qaas_runs_CPU_9468/172-019-1763/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
[...] |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x4591f0 PUSH %RBP |
0x4591f1 MOV %RSP,%RBP |
0x4591f4 PUSH %R15 |
0x4591f6 PUSH %R14 |
0x4591f8 PUSH %R13 |
0x4591fa PUSH %R12 |
0x4591fc PUSH %RBX |
0x4591fd SUB $0xe8,%RSP |
0x459204 MOV %R9,-0x110(%RBP) |
0x45920b MOV %R8,-0x80(%RBP) |
0x45920f MOV %RCX,-0x90(%RBP) |
0x459216 MOV %RDX,-0x38(%RBP) |
0x45921a MOV 0xe8(%RBP),%RAX |
0x459221 MOV %RAX,-0x40(%RBP) |
0x459225 MOV 0xe0(%RBP),%RAX |
0x45922c MOV %RAX,-0xf8(%RBP) |
0x459233 MOV 0xd0(%RBP),%RAX |
0x45923a MOV 0xd8(%RBP),%RDI |
0x459241 MOV %RAX,-0x100(%RBP) |
0x459248 MOV 0xc8(%RBP),%RAX |
0x45924f MOV %RAX,-0xf0(%RBP) |
0x459256 MOV 0xc0(%RBP),%RAX |
0x45925d MOV %RAX,-0xb8(%RBP) |
0x459264 MOV 0xb8(%RBP),%RAX |
0x45926b MOV %RAX,-0xb0(%RBP) |
0x459272 MOV 0xb0(%RBP),%RAX |
0x459279 MOV %RAX,-0xd0(%RBP) |
0x459280 MOV 0xa8(%RBP),%RAX |
0x459287 MOV %RAX,-0xc8(%RBP) |
0x45928e MOV 0xa0(%RBP),%RAX |
0x459295 MOV %RAX,-0x98(%RBP) |
0x45929c MOV 0x98(%RBP),%RAX |
0x4592a3 MOV %RAX,-0xc0(%RBP) |
0x4592aa MOV 0x80(%RBP),%RAX |
0x4592b1 MOV 0x90(%RBP),%RBX |
0x4592b8 MOV 0x88(%RBP),%R15 |
0x4592bf MOV %RAX,-0xd8(%RBP) |
0x4592c6 MOV 0x70(%RBP),%RAX |
0x4592ca MOV 0x78(%RBP),%R12 |
0x4592ce MOV %RAX,-0xe8(%RBP) |
0x4592d5 MOV 0x68(%RBP),%RAX |
0x4592d9 MOV %RAX,-0x50(%RBP) |
0x4592dd MOV 0x60(%RBP),%RAX |
0x4592e1 MOV %RAX,-0x60(%RBP) |
0x4592e5 MOV 0x58(%RBP),%RAX |
0x4592e9 MOV %RAX,-0xe0(%RBP) |
0x4592f0 MOV 0x50(%RBP),%RAX |
0x4592f4 MOV %RAX,-0x48(%RBP) |
0x4592f8 MOV 0x48(%RBP),%RAX |
0x4592fc MOV %RAX,-0x58(%RBP) |
0x459300 MOV 0x38(%RBP),%RAX |
0x459304 MOV 0x40(%RBP),%RCX |
0x459308 MOV %RAX,-0xa8(%RBP) |
0x45930f MOV 0x30(%RBP),%RAX |
0x459313 MOV %RAX,-0x78(%RBP) |
0x459317 MOV 0x28(%RBP),%RAX |
0x45931b MOV %RAX,-0x88(%RBP) |
0x459322 MOV 0x20(%RBP),%RAX |
0x459326 MOV %RAX,-0x108(%RBP) |
0x45932d MOV 0x18(%RBP),%RAX |
0x459331 MOV %RAX,-0x68(%RBP) |
0x459335 MOV 0x10(%RBP),%RAX |
0x459339 MOV %RAX,-0x70(%RBP) |
0x45933d MOV %RCX,-0x30(%RBP) |
0x459341 MOV %RDI,-0xa0(%RBP) |
0x459348 TEST %RDI,%RDI |
0x45934b JE 45997b |
0x459351 MOV $0x8,%ESI |
0x459356 CALL 583040 <hypre_CAlloc> |
0x45935b MOV -0x30(%RBP),%RCX |
0x45935f MOV %RAX,%R13 |
0x459362 TEST %RCX,%RCX |
0x459365 JE 459987 |
0x45936b MOV $0x8,%ESI |
0x459370 MOV %RCX,%RDI |
0x459373 CALL 583040 <hypre_CAlloc> |
0x459378 MOV %RAX,%R14 |
0x45937b MOV -0xa0(%RBP),%RDX |
0x459382 TEST %RDX,%RDX |
0x459385 JLE 459398 |
0x459387 SAL $0x3,%RDX |
0x45938b MOV $0xff,%ESI |
0x459390 MOV %R13,%RDI |
0x459393 CALL 58e1b0 <_intel_fast_memset> |
0x459398 MOV -0x30(%RBP),%RDX |
0x45939c TEST %RDX,%RDX |
0x45939f JLE 4593b2 |
0x4593a1 SAL $0x3,%RDX |
0x4593a5 MOV $0xff,%ESI |
0x4593aa MOV %R14,%RDI |
0x4593ad CALL 58e1b0 <_intel_fast_memset> |
0x4593b2 CALL 586110 <hypre_GetThreadNum> |
0x4593b7 MOV %RAX,-0x30(%RBP) |
0x4593bb CALL 586100 <hypre_NumActiveThreads> |
0x4593c0 MOV -0x40(%RBP),%RSI |
0x4593c4 MOV %RAX,%RCX |
0x4593c7 MOV %RSI,%RAX |
0x4593ca CQTO |
0x4593cc IDIV %RCX |
0x4593cf MOV -0x30(%RBP),%RDI |
0x4593d3 DEC %RCX |
0x4593d6 LEA 0x1(%RDI),%RDX |
0x4593da IMUL %RAX,%RDX |
0x4593de MOV %RAX,%R8 |
0x4593e1 IMUL %RDI,%R8 |
0x4593e5 CMP %RCX,%RDI |
0x4593e8 CMOVE %RSI,%RDX |
0x4593ec MOV %RDX,-0x40(%RBP) |
0x4593f0 MOV -0x38(%RBP),%R10 |
0x4593f4 CMP %RDX,%R8 |
0x4593f7 JGE 459957 |
0x4593fd MOV -0x98(%RBP),%RAX |
0x459404 VMOVDDUP 0x144bf4(%RIP),%XMM0 |
0x45940c VMOVDQU64 0x149d6a(%RIP),%ZMM2 |
0x459416 VXORPD %XMM1,%XMM1,%XMM1 |
0x45941a MOV 0x8(%RAX),%RCX |
0x45941e ADD %RCX,-0x40(%RBP) |
0x459422 ADD %RCX,%R8 |
0x459425 JMP 459441 |
0x459427 NOPW (%RAX,%RAX,1) |
(1428) 0x459430 MOV -0x30(%RBP),%R8 |
(1428) 0x459434 INC %R8 |
(1428) 0x459437 CMP -0x40(%RBP),%R8 |
(1428) 0x45943b JGE 459957 |
(1428) 0x459441 MOV -0xc0(%RBP),%RCX |
(1428) 0x459448 MOV %R8,-0x30(%RBP) |
(1428) 0x45944c MOV -0xc8(%RBP),%RDX |
(1428) 0x459453 MOV -0x48(%RBP),%RAX |
(1428) 0x459457 MOV (%RCX,%R8,8),%RCX |
(1428) 0x45945b MOV (%RDX,%RCX,8),%RDI |
(1428) 0x45945f MOV 0x8(%RAX,%RCX,8),%RSI |
(1428) 0x459464 MOV (%RAX,%RCX,8),%R9 |
(1428) 0x459468 LEA (%RSI,%RDI,1),%RDX |
(1428) 0x45946c SUB %R9,%RDX |
(1428) 0x45946f CMP %RDX,%RDI |
(1428) 0x459472 JGE 459545 |
(1428) 0x459478 MOV -0xb0(%RBP),%RDX |
(1428) 0x45947f SUB %R9,%RSI |
(1428) 0x459482 MOV 0x8(%RDX),%R8 |
(1428) 0x459486 CMP $0x8,%RSI |
(1428) 0x45948a JB 459510 |
(1428) 0x459490 LEA 0x38(%R8,%RDI,8),%R10 |
(1428) 0x459495 MOV %RSI,%R9 |
(1428) 0x459498 SHR $0x3,%R9 |
(1428) 0x45949c NOPL (%RAX) |
(1436) 0x4594a0 MOV -0x38(%R10),%RDX |
(1436) 0x4594a4 MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594a8 MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594ad MOV -0x30(%R10),%RDX |
(1436) 0x4594b1 MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594b5 MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594ba MOV -0x28(%R10),%RDX |
(1436) 0x4594be MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594c2 MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594c7 MOV -0x20(%R10),%RDX |
(1436) 0x4594cb MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594cf MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594d4 MOV -0x18(%R10),%RDX |
(1436) 0x4594d8 MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594dc MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594e1 MOV -0x10(%R10),%RDX |
(1436) 0x4594e5 MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594e9 MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594ee MOV -0x8(%R10),%RDX |
(1436) 0x4594f2 MOV (%R15,%RDX,8),%RDX |
(1436) 0x4594f6 MOV %RCX,(%R13,%RDX,8) |
(1436) 0x4594fb MOV (%R10),%RDX |
(1436) 0x4594fe ADD $0x40,%R10 |
(1436) 0x459502 DEC %R9 |
(1436) 0x459505 MOV (%R15,%RDX,8),%RDX |
(1436) 0x459509 MOV %RCX,(%R13,%RDX,8) |
(1436) 0x45950e JNE 4594a0 |
(1428) 0x459510 MOV -0x38(%RBP),%R10 |
(1428) 0x459514 MOV %RSI,%R9 |
(1428) 0x459517 AND $-0x8,%R9 |
(1428) 0x45951b CMP %RSI,%R9 |
(1428) 0x45951e JAE 459545 |
(1428) 0x459520 LEA (%R8,%RDI,8),%RDI |
(1428) 0x459524 NOPW %CS:(%RAX,%RAX,1) |
(1435) 0x459530 MOV (%RDI,%R9,8),%RDX |
(1435) 0x459534 INC %R9 |
(1435) 0x459537 MOV (%R15,%RDX,8),%RDX |
(1435) 0x45953b MOV %RCX,(%R13,%RDX,8) |
(1435) 0x459540 CMP %R9,%RSI |
(1435) 0x459543 JNE 459530 |
(1428) 0x459545 MOV -0x68(%RBP),%RDX |
(1428) 0x459549 MOV -0x48(%RBP),%RAX |
(1428) 0x45954d VXORPD %XMM7,%XMM7,%XMM7 |
(1428) 0x459551 VXORPD %XMM6,%XMM6,%XMM6 |
(1428) 0x459555 MOV (%RDX,%RCX,8),%RDI |
(1428) 0x459559 MOV (%RAX,%RCX,8),%RAX |
(1428) 0x45955d MOV 0x8(%RDX,%RCX,8),%R8 |
(1428) 0x459562 INC %RDI |
(1428) 0x459565 CMP %R8,%RDI |
(1428) 0x459568 JGE 459610 |
(1428) 0x45956e MOV -0xe0(%RBP),%RSI |
(1428) 0x459575 JMP 45958c |
0x459577 NOPW (%RAX,%RAX,1) |
(1434) 0x459580 INC %RDI |
(1434) 0x459583 CMP %R8,%RDI |
(1434) 0x459586 JGE 459610 |
(1434) 0x45958c MOV -0x108(%RBP),%RDX |
(1434) 0x459593 MOV (%RDX,%RDI,8),%R9 |
(1434) 0x459597 CMPQ $-0x3,(%R10,%R9,8) |
(1434) 0x45959c JE 4595c3 |
(1434) 0x45959e CMPQ $0x1,-0x90(%RBP) |
(1434) 0x4595a6 JE 4595ba |
(1434) 0x4595a8 MOV -0x80(%RBP),%R10 |
(1434) 0x4595ac MOV (%R10,%RCX,8),%RDX |
(1434) 0x4595b0 CMP (%R10,%R9,8),%RDX |
(1434) 0x4595b4 MOV -0x38(%RBP),%R10 |
(1434) 0x4595b8 JNE 4595c3 |
(1434) 0x4595ba MOV -0x70(%RBP),%RDX |
(1434) 0x4595be VADDSD (%RDX,%RDI,8),%XMM6,%XMM6 |
(1434) 0x4595c3 CMP $-0x1,%R9 |
(1434) 0x4595c7 JE 459580 |
(1434) 0x4595c9 CMP %RCX,(%R13,%R9,8) |
(1434) 0x4595ce JNE 459580 |
(1434) 0x4595d0 MOV -0x70(%RBP),%R8 |
(1434) 0x4595d4 MOV -0x58(%RBP),%RDX |
(1434) 0x4595d8 MOV -0xf8(%RBP),%R11 |
(1434) 0x4595df VMOVQ (%R8,%RDI,8),%XMM8 |
(1434) 0x4595e5 VMOVQ %XMM8,(%RDX,%RAX,8) |
(1434) 0x4595ea MOV (%R11,%R9,8),%RDX |
(1434) 0x4595ee MOV %RDX,(%RSI,%RAX,8) |
(1434) 0x4595f2 MOV -0x68(%RBP),%RDX |
(1434) 0x4595f6 INC %RAX |
(1434) 0x4595f9 VADDSD (%R8,%RDI,8),%XMM7,%XMM7 |
(1434) 0x4595ff MOV 0x8(%RDX,%RCX,8),%R8 |
(1434) 0x459604 JMP 459580 |
0x459609 NOPL (%RAX) |
(1428) 0x459610 MOV -0x50(%RBP),%RSI |
(1428) 0x459614 MOV -0xd0(%RBP),%RDX |
(1428) 0x45961b MOV (%RDX,%RCX,8),%R8 |
(1428) 0x45961f MOV 0x8(%RSI,%RCX,8),%RDI |
(1428) 0x459624 MOV (%RSI,%RCX,8),%R10 |
(1428) 0x459628 LEA (%RDI,%R8,1),%RDX |
(1428) 0x45962c SUB %R10,%RDX |
(1428) 0x45962f CMP %RDX,%R8 |
(1428) 0x459632 JGE 4596f4 |
(1428) 0x459638 MOV -0xb8(%RBP),%RDX |
(1428) 0x45963f SUB %R10,%RDI |
(1428) 0x459642 MOV 0x8(%RDX),%R9 |
(1428) 0x459646 CMP $0x8,%RDI |
(1428) 0x45964a JB 4596c8 |
(1428) 0x459650 LEA 0x38(%R9,%R8,8),%R11 |
(1428) 0x459655 MOV %RDI,%R10 |
(1428) 0x459658 SHR $0x3,%R10 |
(1428) 0x45965c NOPL (%RAX) |
(1433) 0x459660 MOV -0x38(%R11),%RDX |
(1433) 0x459664 MOV (%RBX,%RDX,8),%RDX |
(1433) 0x459668 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x45966c MOV -0x30(%R11),%RDX |
(1433) 0x459670 MOV (%RBX,%RDX,8),%RDX |
(1433) 0x459674 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x459678 MOV -0x28(%R11),%RDX |
(1433) 0x45967c MOV (%RBX,%RDX,8),%RDX |
(1433) 0x459680 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x459684 MOV -0x20(%R11),%RDX |
(1433) 0x459688 MOV (%RBX,%RDX,8),%RDX |
(1433) 0x45968c MOV %RCX,(%R14,%RDX,8) |
(1433) 0x459690 MOV -0x18(%R11),%RDX |
(1433) 0x459694 MOV (%RBX,%RDX,8),%RDX |
(1433) 0x459698 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x45969c MOV -0x10(%R11),%RDX |
(1433) 0x4596a0 MOV (%RBX,%RDX,8),%RDX |
(1433) 0x4596a4 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x4596a8 MOV -0x8(%R11),%RDX |
(1433) 0x4596ac MOV (%RBX,%RDX,8),%RDX |
(1433) 0x4596b0 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x4596b4 MOV (%R11),%RDX |
(1433) 0x4596b7 ADD $0x40,%R11 |
(1433) 0x4596bb DEC %R10 |
(1433) 0x4596be MOV (%RBX,%RDX,8),%RDX |
(1433) 0x4596c2 MOV %RCX,(%R14,%RDX,8) |
(1433) 0x4596c6 JNE 459660 |
(1428) 0x4596c8 MOV %RDI,%R10 |
(1428) 0x4596cb AND $-0x8,%R10 |
(1428) 0x4596cf CMP %RDI,%R10 |
(1428) 0x4596d2 JAE 4596f4 |
(1428) 0x4596d4 LEA (%R9,%R8,8),%R8 |
(1428) 0x4596d8 NOPL (%RAX,%RAX,1) |
(1432) 0x4596e0 MOV (%R8,%R10,8),%RDX |
(1432) 0x4596e4 INC %R10 |
(1432) 0x4596e7 MOV (%RBX,%RDX,8),%RDX |
(1432) 0x4596eb MOV %RCX,(%R14,%RDX,8) |
(1432) 0x4596ef CMP %R10,%RDI |
(1432) 0x4596f2 JNE 4596e0 |
(1428) 0x4596f4 MOV -0x78(%RBP),%RSI |
(1428) 0x4596f8 MOV -0x50(%RBP),%RDX |
(1428) 0x4596fc MOV (%RDX,%RCX,8),%RDI |
(1428) 0x459700 MOV (%RSI,%RCX,8),%R8 |
(1428) 0x459704 MOV 0x8(%RSI,%RCX,8),%R10 |
(1428) 0x459709 CMP %R10,%R8 |
(1428) 0x45970c JGE 4597e0 |
(1428) 0x459712 MOV -0xa8(%RBP),%RDX |
(1428) 0x459719 LEA (%RDX,%R8,8),%R9 |
(1428) 0x45971d JMP 459730 |
0x45971f NOP |
(1431) 0x459720 INC %R8 |
(1431) 0x459723 ADD $0x8,%R9 |
(1431) 0x459727 CMP %R10,%R8 |
(1431) 0x45972a JGE 4597e0 |
(1431) 0x459730 CMPQ $0,-0x110(%RBP) |
(1431) 0x459738 MOV %R9,%RDX |
(1431) 0x45973b JE 45974b |
(1431) 0x45973d MOV (%R9),%RDX |
(1431) 0x459740 MOV -0x100(%RBP),%R11 |
(1431) 0x459747 LEA (%R11,%RDX,8),%RDX |
(1431) 0x45974b MOV (%RDX),%R11 |
(1431) 0x45974e CMPQ $-0x3,(%R12,%R11,8) |
(1431) 0x459753 JE 459787 |
(1431) 0x459755 CMPQ $0x1,-0x90(%RBP) |
(1431) 0x45975d JE 45977a |
(1431) 0x45975f MOV -0x80(%RBP),%RDX |
(1431) 0x459763 MOV %R12,%RSI |
(1431) 0x459766 MOV -0xd8(%RBP),%R12 |
(1431) 0x45976d MOV (%RDX,%RCX,8),%RDX |
(1431) 0x459771 CMP (%R12,%R11,8),%RDX |
(1431) 0x459775 MOV %RSI,%R12 |
(1431) 0x459778 JNE 459787 |
(1431) 0x45977a MOV -0x88(%RBP),%RDX |
(1431) 0x459781 VADDSD (%RDX,%R8,8),%XMM6,%XMM6 |
(1431) 0x459787 CMP $-0x1,%R11 |
(1431) 0x45978b JE 459720 |
(1431) 0x45978d CMP %RCX,(%R14,%R11,8) |
(1431) 0x459791 JNE 459720 |
(1431) 0x459793 MOV -0x88(%RBP),%R10 |
(1431) 0x45979a MOV -0x60(%RBP),%RDX |
(1431) 0x45979e MOV -0xf0(%RBP),%RSI |
(1431) 0x4597a5 VMOVQ (%R10,%R8,8),%XMM8 |
(1431) 0x4597ab VMOVQ %XMM8,(%RDX,%RDI,8) |
(1431) 0x4597b0 MOV (%RSI,%R11,8),%RDX |
(1431) 0x4597b4 MOV -0xe8(%RBP),%RSI |
(1431) 0x4597bb MOV %RDX,(%RSI,%RDI,8) |
(1431) 0x4597bf MOV -0x78(%RBP),%RDX |
(1431) 0x4597c3 INC %RDI |
(1431) 0x4597c6 VADDSD (%R10,%R8,8),%XMM7,%XMM7 |
(1431) 0x4597cc MOV 0x8(%RDX,%RCX,8),%R10 |
(1431) 0x4597d1 JMP 459720 |
0x4597d6 NOPW %CS:(%RAX,%RAX,1) |
(1428) 0x4597e0 MOV -0x68(%RBP),%RDX |
(1428) 0x4597e4 MOV -0x70(%RBP),%RSI |
(1428) 0x4597e8 MOV (%RDX,%RCX,8),%RDX |
(1428) 0x4597ec VMULSD (%RSI,%RDX,8),%XMM7,%XMM7 |
(1428) 0x4597f1 VUCOMISD %XMM1,%XMM7 |
(1428) 0x4597f5 JE 4597ff |
(1428) 0x4597f7 VXORPD %XMM0,%XMM6,%XMM5 |
(1428) 0x4597fb VDIVSD %XMM7,%XMM5,%XMM5 |
(1428) 0x4597ff MOV -0x48(%RBP),%RDX |
(1428) 0x459803 MOV -0x38(%RBP),%R10 |
(1428) 0x459807 MOV (%RDX,%RCX,8),%R8 |
(1428) 0x45980b SUB %R8,%RAX |
(1428) 0x45980e JLE 4598ab |
(1428) 0x459814 MOV %RAX,%R9 |
(1428) 0x459817 AND $-0x8,%R9 |
(1428) 0x45981b JE 459868 |
(1428) 0x45981d MOV -0x58(%RBP),%RDX |
(1428) 0x459821 VBROADCASTSD %XMM5,%ZMM6 |
(1428) 0x459827 LEA -0x1(%R9),%R10 |
(1428) 0x45982b LEA (%RDX,%R8,8),%R11 |
(1428) 0x45982f XOR %EDX,%EDX |
(1428) 0x459831 NOPW %CS:(%RAX,%RAX,1) |
(1430) 0x459840 VMULPD (%R11,%RDX,8),%ZMM6,%ZMM7 |
(1430) 0x459847 VMOVUPD %ZMM7,(%R11,%RDX,8) |
(1430) 0x45984e ADD $0x8,%RDX |
(1430) 0x459852 CMP %R10,%RDX |
(1430) 0x459855 JBE 459840 |
(1428) 0x459857 MOV -0x38(%RBP),%R10 |
(1428) 0x45985b CMP %R9,%RAX |
(1428) 0x45985e JE 4598ab |
(1428) 0x459860 VPBROADCASTQ %RAX,%ZMM7 |
(1428) 0x459866 JMP 459877 |
(1428) 0x459868 VPBROADCASTQ %RAX,%ZMM7 |
(1428) 0x45986e VBROADCASTSD %XMM5,%ZMM6 |
(1428) 0x459874 XOR %R9D,%R9D |
(1428) 0x459877 MOV -0x58(%RBP),%RAX |
(1428) 0x45987b VPBROADCASTQ %R9,%ZMM8 |
(1428) 0x459881 ADD %R9,%R8 |
(1428) 0x459884 VPSUBQ %ZMM8,%ZMM7,%ZMM7 |
(1428) 0x45988a VPCMPNLEUQ %ZMM2,%ZMM7,%K1 |
(1428) 0x459891 VMOVUPD (%RAX,%R8,8),%ZMM7{%K1}{z} |
(1428) 0x459898 VMOVAPD %ZMM7,%ZMM3{%K1} |
(1428) 0x45989e VMULPD %ZMM6,%ZMM3,%ZMM6 |
(1428) 0x4598a4 VMOVUPD %ZMM6,(%RAX,%R8,8){%K1} |
(1428) 0x4598ab MOV -0x50(%RBP),%RAX |
(1428) 0x4598af MOV (%RAX,%RCX,8),%RCX |
(1428) 0x4598b3 SUB %RCX,%RDI |
(1428) 0x4598b6 JLE 459430 |
(1428) 0x4598bc MOV %RDI,%RSI |
(1428) 0x4598bf AND $-0x8,%RSI |
(1428) 0x4598c3 JE 45990c |
(1428) 0x4598c5 MOV -0x60(%RBP),%RAX |
(1428) 0x4598c9 VBROADCASTSD %XMM5,%ZMM6 |
(1428) 0x4598cf LEA -0x1(%RSI),%R8 |
(1428) 0x4598d3 XOR %EDX,%EDX |
(1428) 0x4598d5 LEA (%RAX,%RCX,8),%R9 |
(1428) 0x4598d9 NOPL (%RAX) |
(1429) 0x4598e0 VMULPD (%R9,%RDX,8),%ZMM6,%ZMM7 |
(1429) 0x4598e7 VMOVUPD %ZMM7,(%R9,%RDX,8) |
(1429) 0x4598ee ADD $0x8,%RDX |
(1429) 0x4598f2 CMP %R8,%RDX |
(1429) 0x4598f5 JBE 4598e0 |
(1428) 0x4598f7 MOV -0x30(%RBP),%R8 |
(1428) 0x4598fb CMP %RSI,%RDI |
(1428) 0x4598fe JE 459434 |
(1428) 0x459904 VPBROADCASTQ %RDI,%ZMM7 |
(1428) 0x45990a JMP 45991e |
(1428) 0x45990c MOV -0x30(%RBP),%R8 |
(1428) 0x459910 VPBROADCASTQ %RDI,%ZMM7 |
(1428) 0x459916 VBROADCASTSD %XMM5,%ZMM6 |
(1428) 0x45991c XOR %ESI,%ESI |
(1428) 0x45991e MOV -0x60(%RBP),%RAX |
(1428) 0x459922 VPBROADCASTQ %RSI,%ZMM8 |
(1428) 0x459928 ADD %RSI,%RCX |
(1428) 0x45992b VPSUBQ %ZMM8,%ZMM7,%ZMM7 |
(1428) 0x459931 VPCMPNLEUQ %ZMM2,%ZMM7,%K1 |
(1428) 0x459938 VMOVUPD (%RAX,%RCX,8),%ZMM7{%K1}{z} |
(1428) 0x45993f VMOVAPD %ZMM7,%ZMM4{%K1} |
(1428) 0x459945 VMULPD %ZMM6,%ZMM4,%ZMM6 |
(1428) 0x45994b VMOVUPD %ZMM6,(%RAX,%RCX,8){%K1} |
(1428) 0x459952 JMP 459434 |
0x459957 MOV %R13,%RDI |
0x45995a VZEROUPPER |
0x45995d CALL 583110 <hypre_Free> |
0x459962 MOV %R14,%RDI |
0x459965 ADD $0xe8,%RSP |
0x45996c POP %RBX |
0x45996d POP %R12 |
0x45996f POP %R13 |
0x459971 POP %R14 |
0x459973 POP %R15 |
0x459975 POP %RBP |
0x459976 JMP 583110 |
0x45997b XOR %R13D,%R13D |
0x45997e TEST %RCX,%RCX |
0x459981 JNE 45936b |
0x459987 XOR %R14D,%R14D |
0x45998a MOV -0xa0(%RBP),%RDX |
0x459991 TEST %RDX,%RDX |
0x459994 JG 459387 |
0x45999a JMP 459398 |
0x45999f NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 145 |
nb uops | 147 |
loop length | 676 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 1 |
nb stack references | 57 |
micro-operation queue | 24.50 cycles |
front end | 24.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.50 | 7.75 | 7.75 | 7.50 | 9.50 | 26.00 | 26.00 | 26.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 9.50 | 7.75 | 7.75 | 7.50 | 9.50 | 26.33 | 26.33 | 26.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 7.00-12.00 |
Front-end | 24.50 |
Dispatch | 26.33 |
DIV/SQRT | 7.00-12.00 |
Overall L1 | 26.33 |
all | 3% |
load | 10% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 4% |
load | 9% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 13% |
load | 21% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 13% |
load | 20% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SUB $0xe8,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
MOV %R9,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %R8,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RCX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RDX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0xd8(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x90(%RBP),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV 0x88(%RBP),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x78(%RBP),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RDI,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
TEST %RDI,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JE 45997b <hypre_BoomerAMGBuildMultipass.extracted.27+0x78b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV $0x8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CALL 583040 <hypre_CAlloc> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
TEST %RCX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JE 459987 <hypre_BoomerAMGBuildMultipass.extracted.27+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV $0x8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CALL 583040 <hypre_CAlloc> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JLE 459398 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
SAL $0x3,%RDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV $0xff,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CALL 58e1b0 <_intel_fast_memset> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JLE 4593b2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
SAL $0x3,%RDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV $0xff,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CALL 58e1b0 <_intel_fast_memset> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
CALL 586110 <hypre_GetThreadNum> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
CALL 586100 <hypre_NumActiveThreads> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CQTO | scal (12.5%) | |||||||||||||||||
IDIV %RCX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 | scal (12.5%) |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
DEC %RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
LEA 0x1(%RDI),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
IMUL %RDI,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
CMP %RCX,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
CMOVE %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
CMP %RDX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JGE 459957 <hypre_BoomerAMGBuildMultipass.extracted.27+0x767> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV -0x98(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
VMOVDDUP 0x144bf4(%RIP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
VMOVDQU64 0x149d6a(%RIP),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
MOV 0x8(%RAX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
ADD %RCX,-0x40(%RBP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
ADD %RCX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JMP 459441 <hypre_BoomerAMGBuildMultipass.extracted.27+0x251> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
CALL 583110 <hypre_Free> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
ADD $0xe8,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
JMP 583110 <hypre_Free> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
TEST %RCX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JNE 45936b <hypre_BoomerAMGBuildMultipass.extracted.27+0x17b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
JG 459387 <hypre_BoomerAMGBuildMultipass.extracted.27+0x197> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
JMP 459398 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 145 |
nb uops | 147 |
loop length | 676 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 1 |
nb stack references | 57 |
micro-operation queue | 24.50 cycles |
front end | 24.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.50 | 7.75 | 7.75 | 7.50 | 9.50 | 26.00 | 26.00 | 26.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 9.50 | 7.75 | 7.75 | 7.50 | 9.50 | 26.33 | 26.33 | 26.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 7.00-12.00 |
Front-end | 24.50 |
Dispatch | 26.33 |
DIV/SQRT | 7.00-12.00 |
Overall L1 | 26.33 |
all | 3% |
load | 10% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 4% |
load | 9% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 13% |
load | 21% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 13% |
load | 20% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SUB $0xe8,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
MOV %R9,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %R8,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RCX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RDX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xe8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xe0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xf8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0xd8(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x100(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xb8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xc0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x80(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x90(%RBP),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV 0x88(%RBP),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x78(%RBP),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x20(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x108(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x18(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV %RDI,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
TEST %RDI,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JE 45997b <hypre_BoomerAMGBuildMultipass.extracted.27+0x78b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV $0x8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CALL 583040 <hypre_CAlloc> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
TEST %RCX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JE 459987 <hypre_BoomerAMGBuildMultipass.extracted.27+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV $0x8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CALL 583040 <hypre_CAlloc> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JLE 459398 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
SAL $0x3,%RDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV $0xff,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CALL 58e1b0 <_intel_fast_memset> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JLE 4593b2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
SAL $0x3,%RDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV $0xff,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CALL 58e1b0 <_intel_fast_memset> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
CALL 586110 <hypre_GetThreadNum> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
CALL 586100 <hypre_NumActiveThreads> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CQTO | scal (12.5%) | |||||||||||||||||
IDIV %RCX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 | scal (12.5%) |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
DEC %RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
LEA 0x1(%RDI),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
IMUL %RDI,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
CMP %RCX,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
CMOVE %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
CMP %RDX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JGE 459957 <hypre_BoomerAMGBuildMultipass.extracted.27+0x767> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV -0x98(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
VMOVDDUP 0x144bf4(%RIP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
VMOVDQU64 0x149d6a(%RIP),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
MOV 0x8(%RAX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
ADD %RCX,-0x40(%RBP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
ADD %RCX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JMP 459441 <hypre_BoomerAMGBuildMultipass.extracted.27+0x251> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
CALL 583110 <hypre_Free> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
ADD $0xe8,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
JMP 583110 <hypre_Free> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
TEST %RCX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
JNE 45936b <hypre_BoomerAMGBuildMultipass.extracted.27+0x17b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
JG 459387 <hypre_BoomerAMGBuildMultipass.extracted.27+0x197> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
JMP 459398 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass.extracted.27– | 0.45 | 0.33 |
▼Loop 1428 - par_multi_interp.c:1585-1660 - exec– | 0.12 | 0.08 |
○Loop 1434 - par_multi_interp.c:1618-1628 - exec | 0.33 | 0.23 |
○Loop 1435 - par_multi_interp.c:1612-1615 - exec | 0.01 | 0.01 |
○Loop 1431 - par_multi_interp.c:1622-1652 - exec | 0.00 | 0.00 |
○Loop 1432 - par_multi_interp.c:1633-1636 - exec | 0.00 | 0.00 |
○Loop 1430 - par_multi_interp.c:1657-1658 - exec | 0.00 | 0.00 |
○Loop 1436 - par_multi_interp.c:1612-1615 - exec | 0.00 | 0.00 |
○Loop 1429 - par_multi_interp.c:1659-1660 - exec | 0.00 | 0.00 |
○Loop 1433 - par_multi_interp.c:1633-1636 - exec | 0.00 | 0.00 |