Loop Id: 2120 | Module: libparcsr_ls.so | Source: par_strength.c:1714-1797 [...] | Coverage: 0.01% |
---|
Loop Id: 2120 | Module: libparcsr_ls.so | Source: par_strength.c:1714-1797 [...] | Coverage: 0.01% |
---|
0x8d2a0 INC %R12 |
0x8d2a3 CMP -0xb8(%RBP),%R12 |
0x8d2aa JE 8da6a |
0x8d2b0 MOV -0xc8(%RBP),%RAX |
0x8d2b7 MOV -0x38(%RBP),%R10 |
0x8d2bb MOV -0xc0(%RBP),%RDX |
0x8d2c2 MOV 0x18(%RBP),%RCX |
0x8d2c6 MOV -0x30(%RBP),%R11 |
0x8d2ca MOV (%RAX,%R12,8),%RAX |
0x8d2ce MOV %R10,(%RDX,%R12,8) |
0x8d2d2 CMPQ $0,(%RCX) |
0x8d2d6 MOV %RAX,-0x60(%RBP) |
0x8d2da JE 8d2eb |
0x8d2dc MOV -0x30(%RBP),%RAX |
0x8d2e0 MOV -0xd8(%RBP),%RCX |
0x8d2e7 MOV %RAX,(%RCX,%R12,8) |
0x8d2eb MOV -0x50(%RBP),%RAX |
0x8d2ef MOV -0x60(%RBP),%RDX |
0x8d2f3 MOV (%RAX,%RDX,8),%RCX |
0x8d2f7 CMP 0x8(%RAX,%RDX,8),%RCX |
0x8d2fc JGE 8d480 |
0x8d302 MOV 0x78(%RBP),%RAX |
0x8d306 MOV 0x88(%RBP),%RSI |
0x8d30d MOV 0x90(%RBP),%RDX |
0x8d314 MOV (%RAX),%RAX |
0x8d317 MOV %RAX,-0xd0(%RBP) |
0x8d31e MOV (%RSI),%RAX |
0x8d321 MOV %RAX,-0x68(%RBP) |
0x8d325 MOV (%RDX),%RAX |
0x8d328 MOV %RAX,-0x88(%RBP) |
0x8d32f JMP 8d356 |
(2124) 0x8d340 MOV -0x50(%RBP),%RAX |
(2124) 0x8d344 MOV -0x60(%RBP),%RDX |
(2124) 0x8d348 INC %RCX |
(2124) 0x8d34b CMP 0x8(%RAX,%RDX,8),%RCX |
(2124) 0x8d350 JGE 8d480 |
(2124) 0x8d356 MOV -0x40(%RBP),%RAX |
(2124) 0x8d35a MOV -0x80(%RBP),%RDX |
(2124) 0x8d35e MOV (%RAX,%RCX,8),%RAX |
(2124) 0x8d362 CMPQ $0,(%RDX,%RAX,8) |
(2124) 0x8d367 JLE 8d386 |
(2124) 0x8d369 MOV -0xd0(%RBP),%RDX |
(2124) 0x8d370 MOV (%RDX,%RAX,8),%RDX |
(2124) 0x8d374 CMP %R10,(%R14,%RDX,8) |
(2124) 0x8d378 JGE 8d386 |
(2124) 0x8d37a MOV -0x38(%RBP),%RDI |
(2124) 0x8d37e MOV %RDI,(%R14,%RDX,8) |
(2124) 0x8d382 INCQ -0x38(%RBP) |
(2124) 0x8d386 MOV -0x50(%RBP),%RDX |
(2124) 0x8d38a MOV (%RDX,%RAX,8),%RDI |
(2124) 0x8d38e MOV 0x8(%RDX,%RAX,8),%R8 |
(2124) 0x8d393 CMP %R8,%RDI |
(2124) 0x8d396 JGE 8d400 |
(2124) 0x8d398 MOV 0x78(%RBP),%RDX |
(2124) 0x8d39c MOV (%RDX),%R9 |
(2124) 0x8d39f JMP 8d3b8 |
(2126) 0x8d3b0 INC %RDI |
(2126) 0x8d3b3 CMP %R8,%RDI |
(2126) 0x8d3b6 JGE 8d400 |
(2126) 0x8d3b8 MOV -0x40(%RBP),%RDX |
(2126) 0x8d3bc MOV -0x80(%RBP),%RSI |
(2126) 0x8d3c0 MOV (%RDX,%RDI,8),%RDX |
(2126) 0x8d3c4 CMPQ $0,(%RSI,%RDX,8) |
(2126) 0x8d3c9 JLE 8d3b0 |
(2126) 0x8d3cb MOV (%R9,%RDX,8),%RDX |
(2126) 0x8d3cf CMP %R12,%RDX |
(2126) 0x8d3d2 JE 8d3b0 |
(2126) 0x8d3d4 CMP %R10,(%R14,%RDX,8) |
(2126) 0x8d3d8 JGE 8d3b0 |
(2126) 0x8d3da MOV -0x38(%RBP),%R8 |
(2126) 0x8d3de MOV -0x50(%RBP),%RSI |
(2126) 0x8d3e2 MOV %R8,(%R14,%RDX,8) |
(2126) 0x8d3e6 INCQ -0x38(%RBP) |
(2126) 0x8d3ea MOV 0x8(%RSI,%RAX,8),%R8 |
(2126) 0x8d3ef JMP 8d3b0 |
(2124) 0x8d400 MOV -0x48(%RBP),%RDX |
(2124) 0x8d404 MOV (%RDX,%RAX,8),%RDI |
(2124) 0x8d408 MOV 0x8(%RDX,%RAX,8),%R8 |
(2124) 0x8d40d CMP %R8,%RDI |
(2124) 0x8d410 JGE 8d340 |
(2124) 0x8d416 MOV 0x98(%RBP),%RDX |
(2124) 0x8d41d MOV (%RDX),%R9 |
(2124) 0x8d420 JMP 8d43c |
(2125) 0x8d430 INC %RDI |
(2125) 0x8d433 CMP %R8,%RDI |
(2125) 0x8d436 JGE 8d340 |
(2125) 0x8d43c MOV -0x68(%RBP),%RDX |
(2125) 0x8d440 MOV -0x88(%RBP),%RSI |
(2125) 0x8d447 MOV (%RDX,%RDI,8),%RDX |
(2125) 0x8d44b CMPQ $0,(%RSI,%RDX,8) |
(2125) 0x8d450 JLE 8d430 |
(2125) 0x8d452 MOV (%R9,%RDX,8),%RDX |
(2125) 0x8d456 CMP %R11,(%R13,%RDX,8) |
(2125) 0x8d45b JGE 8d430 |
(2125) 0x8d45d MOV -0x30(%RBP),%R8 |
(2125) 0x8d461 MOV -0x48(%RBP),%RSI |
(2125) 0x8d465 MOV %R8,(%R13,%RDX,8) |
(2125) 0x8d46a INCQ -0x30(%RBP) |
(2125) 0x8d46e MOV 0x8(%RSI,%RAX,8),%R8 |
(2125) 0x8d473 JMP 8d430 |
0x8d480 MOV -0x48(%RBP),%RAX |
0x8d484 MOV -0x60(%RBP),%RDX |
0x8d488 MOV (%RAX,%RDX,8),%RCX |
0x8d48c CMP 0x8(%RAX,%RDX,8),%RCX |
0x8d491 JGE 8d2a0 |
0x8d497 MOV 0x98(%RBP),%RAX |
0x8d49e MOV 0xa8(%RBP),%RDX |
0x8d4a5 MOV 0xb8(%RBP),%RSI |
0x8d4ac MOV (%RAX),%RAX |
0x8d4af MOV (%RDX),%RDX |
0x8d4b2 MOV (%RSI),%RSI |
0x8d4b5 MOV %RAX,-0x68(%RBP) |
0x8d4b9 JMP 8d4d6 |
(2121) 0x8d4c0 MOV -0x48(%RBP),%RAX |
(2121) 0x8d4c4 MOV -0x60(%RBP),%RDI |
(2121) 0x8d4c8 INC %RCX |
(2121) 0x8d4cb CMP 0x8(%RAX,%RDI,8),%RCX |
(2121) 0x8d4d0 JGE 8d2a0 |
(2121) 0x8d4d6 MOV -0x90(%RBP),%RAX |
(2121) 0x8d4dd MOV -0xa0(%RBP),%RDI |
(2121) 0x8d4e4 MOV (%RAX,%RCX,8),%RAX |
(2121) 0x8d4e8 CMPQ $0,(%RDI,%RAX,8) |
(2121) 0x8d4ed JLE 8d50b |
(2121) 0x8d4ef MOV -0x68(%RBP),%RDI |
(2121) 0x8d4f3 MOV (%RDI,%RAX,8),%RDI |
(2121) 0x8d4f7 CMP %R11,(%R13,%RDI,8) |
(2121) 0x8d4fc JGE 8d50b |
(2121) 0x8d4fe MOV -0x30(%RBP),%R8 |
(2121) 0x8d502 MOV %R8,(%R13,%RDI,8) |
(2121) 0x8d507 INCQ -0x30(%RBP) |
(2121) 0x8d50b MOV -0x58(%RBP),%R8 |
(2121) 0x8d50f MOV (%R8,%RAX,8),%RDI |
(2121) 0x8d513 MOV 0x8(%R8,%RAX,8),%R8 |
(2121) 0x8d518 JMP 8d523 |
(2123) 0x8d520 INC %RDI |
(2123) 0x8d523 CMP %R8,%RDI |
(2123) 0x8d526 JGE 8d550 |
(2123) 0x8d528 MOV (%RDX,%RDI,8),%R9 |
(2123) 0x8d52c CMP %R12,%R9 |
(2123) 0x8d52f JE 8d520 |
(2123) 0x8d531 CMP %R10,(%R14,%R9,8) |
(2123) 0x8d535 JGE 8d520 |
(2123) 0x8d537 MOV -0x38(%RBP),%R8 |
(2123) 0x8d53b MOV %R8,(%R14,%R9,8) |
(2123) 0x8d53f MOV -0x58(%RBP),%R9 |
(2123) 0x8d543 INCQ -0x38(%RBP) |
(2123) 0x8d547 MOV 0x8(%R9,%RAX,8),%R8 |
(2123) 0x8d54c JMP 8d520 |
(2121) 0x8d550 MOV -0x78(%RBP),%R8 |
(2121) 0x8d554 MOV (%R8,%RAX,8),%RDI |
(2121) 0x8d558 MOV 0x8(%R8,%RAX,8),%R8 |
(2121) 0x8d55d JMP 8d563 |
(2122) 0x8d560 INC %RDI |
(2122) 0x8d563 CMP %R8,%RDI |
(2122) 0x8d566 JGE 8d4c0 |
(2122) 0x8d56c MOV (%RSI,%RDI,8),%R9 |
(2122) 0x8d570 CMP %R11,(%R13,%R9,8) |
(2122) 0x8d575 JGE 8d560 |
(2122) 0x8d577 MOV -0x30(%RBP),%R8 |
(2122) 0x8d57b MOV %R8,(%R13,%R9,8) |
(2122) 0x8d580 MOV -0x78(%RBP),%R9 |
(2122) 0x8d584 INCQ -0x30(%RBP) |
(2122) 0x8d588 MOV 0x8(%R9,%RAX,8),%R8 |
(2122) 0x8d58d JMP 8d560 |
/home/eoseret/qaas_runs_CPU_9468/172-019-1763/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1714 - 1797 |
-------------------------------------------------------------------------------- |
1714: for (ic = ic_begin; ic < ic_end; ic++) |
[...] |
1720: HYPRE_Int i1 = coarse_to_fine[ic]; |
1721: |
1722: HYPRE_Int jj_row_begin_diag = num_nonzeros_diag; |
1723: HYPRE_Int jj_row_begin_offd = num_nonzeros_offd; |
1724: |
1725: C_diag_i[ic] = num_nonzeros_diag; |
1726: if (num_cols_offd_C) |
1727: { |
1728: C_offd_i[ic] = num_nonzeros_offd; |
1729: } |
1730: |
1731: for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++) |
1732: { |
1733: i2 = S_diag_j[jj1]; |
1734: if (CF_marker[i2] > 0) |
1735: { |
1736: index = fine_to_coarse[i2]; |
1737: if (S_marker[index] < jj_row_begin_diag) |
1738: { |
1739: S_marker[index] = num_nonzeros_diag; |
1740: num_nonzeros_diag++; |
1741: } |
1742: } |
1743: for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++) |
1744: { |
1745: i3 = S_diag_j[jj2]; |
1746: if (CF_marker[i3] > 0) |
1747: { |
1748: index = fine_to_coarse[i3]; |
1749: if (index != ic && S_marker[index] < jj_row_begin_diag) |
1750: { |
1751: S_marker[index] = num_nonzeros_diag; |
1752: num_nonzeros_diag++; |
1753: } |
1754: } |
1755: } |
1756: for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++) |
1757: { |
1758: i3 = S_offd_j[jj2]; |
1759: if (CF_marker_offd[i3] > 0) |
1760: { |
1761: index = map_S_to_C[i3]; |
1762: if (S_marker_offd[index] < jj_row_begin_offd) |
1763: { |
1764: S_marker_offd[index] = num_nonzeros_offd; |
1765: num_nonzeros_offd++; |
1766: } |
1767: } |
1768: } |
1769: } |
1770: for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++) |
1771: { |
1772: i2 = S_offd_j[jj1]; |
1773: if (CF_marker_offd[i2] > 0) |
1774: { |
1775: index = map_S_to_C[i2]; |
1776: if (S_marker_offd[index] < jj_row_begin_offd) |
1777: { |
1778: S_marker_offd[index] = num_nonzeros_offd; |
1779: num_nonzeros_offd++; |
1780: } |
1781: } |
1782: for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++) |
1783: { |
1784: i3 = S_ext_diag_j[jj2]; |
1785: if (i3 != ic && S_marker[i3] < jj_row_begin_diag) |
1786: { |
1787: S_marker[i3] = num_nonzeros_diag; |
1788: num_nonzeros_diag++; |
1789: } |
1790: } |
1791: for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++) |
1792: { |
1793: i3 = S_ext_offd_j[jj2]; |
1794: if (S_marker_offd[i3] < jj_row_begin_offd) |
1795: { |
1796: S_marker_offd[i3] = num_nonzeros_offd; |
1797: num_nonzeros_offd++; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libomp.so | |
○ | __kmp_invoke_task_func | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.42 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.68 |
Bottlenecks | P5, P6, P7, |
Function | .omp_outlined..20.572 |
Source | par_strength.c:1714-1714,par_strength.c:1720-1728,par_strength.c:1731-1731,par_strength.c:1756-1756,par_strength.c:1770-1770 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.33 |
CQA cycles if no scalar integer | 12.33 |
CQA cycles if FP arith vectorized | 12.33 |
CQA cycles if fully vectorized | 2.79 |
Front-end cycles | 7.33 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 1.75 |
P1 cycles | 1.75 |
P2 cycles | 1.50 |
P3 cycles | 3.00 |
P4 cycles | 12.33 |
P5 cycles | 12.33 |
P6 cycles | 12.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 44.00 |
Nb uops | 44.00 |
Nb loads | 30.00 |
Nb stores | 7.00 |
Nb stack references | 19.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 240.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.42 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.68 |
Bottlenecks | P5, P6, P7, |
Function | .omp_outlined..20.572 |
Source | par_strength.c:1714-1714,par_strength.c:1720-1728,par_strength.c:1731-1731,par_strength.c:1756-1756,par_strength.c:1770-1770 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.33 |
CQA cycles if no scalar integer | 12.33 |
CQA cycles if FP arith vectorized | 12.33 |
CQA cycles if fully vectorized | 2.79 |
Front-end cycles | 7.33 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 1.75 |
P1 cycles | 1.75 |
P2 cycles | 1.50 |
P3 cycles | 3.00 |
P4 cycles | 12.33 |
P5 cycles | 12.33 |
P6 cycles | 12.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 44.00 |
Nb uops | 44.00 |
Nb loads | 30.00 |
Nb stores | 7.00 |
Nb stack references | 19.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 240.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | .omp_outlined..20.572 |
Source file and lines | par_strength.c:1714-1797 |
Module | libparcsr_ls.so |
nb instructions | 44 |
nb uops | 44 |
loop length | 204 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 19 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 1.75 | 1.75 | 1.50 | 3.00 | 12.33 | 12.33 | 12.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.00 | 1.75 | 1.75 | 1.50 | 3.00 | 12.33 | 12.33 | 12.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.33 |
Dispatch | 12.33 |
Overall L1 | 12.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INC %R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMP -0xb8(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
JE 8da6a <.omp_outlined..20.572+0xa1a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV -0xc8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV (%RAX,%R12,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %R10,(%RDX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
CMPQ $0,(%RCX) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
JE 8d2eb <.omp_outlined..20.572+0x29b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0xd8(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,(%RCX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX,%RDX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
CMP 0x8(%RAX,%RDX,8),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
JGE 8d480 <.omp_outlined..20.572+0x430> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x90(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV (%RSI),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV (%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
JMP 8d356 <.omp_outlined..20.572+0x306> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX,%RDX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
CMP 0x8(%RAX,%RDX,8),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
JGE 8d2a0 <.omp_outlined..20.572+0x250> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0xa8(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0xb8(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RSI),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
JMP 8d4d6 <.omp_outlined..20.572+0x486> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
Function | .omp_outlined..20.572 |
Source file and lines | par_strength.c:1714-1797 |
Module | libparcsr_ls.so |
nb instructions | 44 |
nb uops | 44 |
loop length | 204 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 19 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 1.75 | 1.75 | 1.50 | 3.00 | 12.33 | 12.33 | 12.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.00 | 1.75 | 1.75 | 1.50 | 3.00 | 12.33 | 12.33 | 12.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.33 |
Dispatch | 12.33 |
Overall L1 | 12.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INC %R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMP -0xb8(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
JE 8da6a <.omp_outlined..20.572+0xa1a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV -0xc8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x38(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x30(%RBP),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV (%RAX,%R12,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %R10,(%RDX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
CMPQ $0,(%RCX) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
JE 8d2eb <.omp_outlined..20.572+0x29b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0xd8(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,(%RCX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX,%RDX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
CMP 0x8(%RAX,%RDX,8),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
JGE 8d480 <.omp_outlined..20.572+0x430> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0x90(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV (%RSI),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
MOV (%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
JMP 8d356 <.omp_outlined..20.572+0x306> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX,%RDX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
CMP 0x8(%RAX,%RDX,8),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
JGE 8d2a0 <.omp_outlined..20.572+0x250> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0xa8(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV 0xb8(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV (%RSI),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | N/A |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
JMP 8d4d6 <.omp_outlined..20.572+0x486> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |