Function: hypre_Rand | Module: libHYPRE_utilities.so | Source: random.c:76-115 [...] | Coverage: 0.02% |
---|
Function: hypre_Rand | Module: libHYPRE_utilities.so | Source: random.c:76-115 [...] | Coverage: 0.02% |
---|
/home/eoseret/qaas_runs_CPU_9468/172-019-1763/intel/AMG/build/AMG/AMG/utilities/random.c: 76 - 115 |
-------------------------------------------------------------------------------- |
76: high = Seed / q; |
77: low = Seed % q; |
78: test = a * low - r * high; |
79: if(test > 0) |
[...] |
99: { |
[...] |
115: return ((HYPRE_Real)(hypre_RandI()) / m); |
0xb390 PUSH %RBP |
0xb391 MOV %RSP,%RBP |
0xb394 MOV 0x5b5d(%RIP),%RCX |
0xb39b MOV $0x41a705af1fe3fb79,%RDX |
0xb3a5 MOV %RCX,%RAX |
0xb3a8 IMUL %RDX |
0xb3ab MOV %RDX,%RAX |
0xb3ae SHR $0x3f,%RAX |
0xb3b2 SAR $0xf,%RDX |
0xb3b6 ADD %RAX,%RDX |
0xb3b9 IMUL $0x1f31d,%RDX,%RAX |
0xb3c0 IMUL $-0xb14,%RDX,%RSI |
0xb3c7 SUB %RAX,%RCX |
0xb3ca IMUL $0x41a7,%RCX,%RAX |
0xb3d1 LEA (%RSI,%RAX,1),%RDX |
0xb3d5 LEA 0x7fffffff(%RSI,%RAX,1),%RAX |
0xb3dd TEST %RDX,%RDX |
0xb3e0 CMOVG %RDX,%RAX |
0xb3e4 VCVTSI2SD %RAX,%XMM0,%XMM0 |
0xb3e9 VDIVSD -0x7949(%RIP),%XMM0,%XMM0 |
0xb3f1 MOV %RAX,0x5b00(%RIP) |
0xb3f8 POP %RBP |
0xb3f9 RET |
0xb3fa INT $0x3 |
0xb3fb INT $0x3 |
0xb3fc INT $0x3 |
0xb3fd INT $0x3 |
0xb3fe INT $0x3 |
0xb3ff INT $0x3 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►91.67+ | hypre_BoomerAMGCoarsenPMIS | par_indepset.c:67 | libparcsr_ls.so |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:0 | libparcsr_ls.so |
○ | hypre_PCGSetup | pcg.c:234 | libkrylov.so |
○ | main | amg.c:398 | exec |
○ | __libc_start_call_main | libc.so.6 | |
►4.28+ | hypre_BoomerAMGCoarsenPMIS | par_indepset.c:67 | libparcsr_ls.so |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:626 | libparcsr_ls.so |
○ | hypre_PCGSetup | pcg.c:234 | libkrylov.so |
○ | main | amg.c:398 | exec |
○ | __libc_start_call_main | libc.so.6 | |
►1.80+ | hypre_BoomerAMGCoarsenPMIS | par_indepset.c:67 | libparcsr_ls.so |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:626 | libparcsr_ls.so |
Path / |
Source file and lines | random.c:76-115 |
Module | libHYPRE_utilities.so |
nb instructions | 29 |
nb uops | 26 |
loop length | 112 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 4.00 | 3.25 | 3.25 | 1.00 | 1.33 | 1.33 | 1.33 | 0.50 | 0.50 | 0.50 | 0.50 | 0.00 | 0.00 |
cycles | 3.50 | 4.00 | 3.25 | 3.25 | 1.00 | 1.33 | 1.33 | 1.33 | 0.50 | 0.50 | 0.50 | 0.50 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 5.00 |
Front-end | 4.33 |
Dispatch | 4.00 |
DIV/SQRT | 5.00 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
MOV 0x5b5d(%RIP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV $0x41a705af1fe3fb79,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
IMUL %RDX | 2 | 0.25 | 1.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
SHR $0x3f,%RAX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SAR $0xf,%RDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
ADD %RAX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
IMUL $0x1f31d,%RDX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
IMUL $-0xb14,%RDX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
SUB %RAX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
IMUL $0x41a7,%RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
LEA (%RSI,%RAX,1),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
LEA 0x7fffffff(%RSI,%RAX,1),%RAX | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMOVG %RDX,%RAX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
VCVTSI2SD %RAX,%XMM0,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1.25 | scal (12.5%) |
VDIVSD -0x7949(%RIP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 | scal (12.5%) |
MOV %RAX,0x5b00(%RIP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A |
Source file and lines | random.c:76-115 |
Module | libHYPRE_utilities.so |
nb instructions | 29 |
nb uops | 26 |
loop length | 112 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 4.00 | 3.25 | 3.25 | 1.00 | 1.33 | 1.33 | 1.33 | 0.50 | 0.50 | 0.50 | 0.50 | 0.00 | 0.00 |
cycles | 3.50 | 4.00 | 3.25 | 3.25 | 1.00 | 1.33 | 1.33 | 1.33 | 0.50 | 0.50 | 0.50 | 0.50 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 5.00 |
Front-end | 4.33 |
Dispatch | 4.00 |
DIV/SQRT | 5.00 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
MOV 0x5b5d(%RIP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV $0x41a705af1fe3fb79,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
IMUL %RDX | 2 | 0.25 | 1.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
SHR $0x3f,%RAX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SAR $0xf,%RDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
ADD %RAX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
IMUL $0x1f31d,%RDX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
IMUL $-0xb14,%RDX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
SUB %RAX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
IMUL $0x41a7,%RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
LEA (%RSI,%RAX,1),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
LEA 0x7fffffff(%RSI,%RAX,1),%RAX | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
TEST %RDX,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMOVG %RDX,%RAX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
VCVTSI2SD %RAX,%XMM0,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1.25 | scal (12.5%) |
VDIVSD -0x7949(%RIP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 | scal (12.5%) |
MOV %RAX,0x5b00(%RIP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A | |||||||||||||||||
INT $0x3 | N/A |
Name | Coverage (%) | Time (s) |
---|---|---|
○hypre_Rand | 0.02 | 0.01 |