Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.54% |
---|
Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.54% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
48: post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
0x424f40 PUSH %RBP |
0x424f41 MOV %RSP,%RBP |
0x424f44 PUSH %R15 |
0x424f46 PUSH %R14 |
0x424f48 PUSH %R13 |
0x424f4a PUSH %R12 |
0x424f4c MOV %RDI,%R12 |
0x424f4f PUSH %RBX |
0x424f50 AND $-0x40,%RSP |
0x424f54 SUB $0xc0,%RSP |
0x424f5b MOV 0x30(%RDI),%EAX |
0x424f5e MOV 0x34(%RDI),%ECX |
0x424f61 MOV 0x28(%RDI),%EDI |
0x424f64 MOV 0x2c(%R12),%EDX |
0x424f69 ADD $0x4,%ECX |
0x424f6c LEA -0x1(%RAX),%R15D |
0x424f70 DEC %EDI |
0x424f72 MOV %ECX,0x5c(%RSP) |
0x424f76 MOV %EDI,0x58(%RSP) |
0x424f7a CMP %ECX,%R15D |
0x424f7d JGE 4256d3 |
0x424f83 MOV %ECX,%EBX |
0x424f85 LEA 0x4(%RDX),%R14D |
0x424f89 SUB %R15D,%EBX |
0x424f8c CMP %R14D,%EDI |
0x424f8f JGE 4256d3 |
0x424f95 MOV %R14D,%ESI |
0x424f98 SUB %EDI,%ESI |
0x424f9a MOV %ESI,0x88(%RSP) |
0x424fa1 CALL 4046c0 <omp_get_num_threads@plt> |
0x424fa6 MOV %EAX,%R13D |
0x424fa9 CALL 4045b0 <omp_get_thread_num@plt> |
0x424fae XOR %EDX,%EDX |
0x424fb0 MOV %EAX,%R8D |
0x424fb3 MOV 0x88(%RSP),%EAX |
0x424fba IMUL %EBX,%EAX |
0x424fbd DIV %R13D |
0x424fc0 MOV %EAX,%ESI |
0x424fc2 CMP %EDX,%R8D |
0x424fc5 JB 425707 |
0x424fcb IMUL %ESI,%R8D |
0x424fcf LEA (%R8,%RDX,1),%R9D |
0x424fd3 LEA (%RSI,%R9,1),%R10D |
0x424fd7 MOV %R10D,0x54(%RSP) |
0x424fdc CMP %R10D,%R9D |
0x424fdf JAE 4256d3 |
0x424fe5 MOV %R9D,%EAX |
0x424fe8 XOR %EDX,%EDX |
0x424fea MOV 0x58(%RSP),%R11D |
0x424fef MOV (%R12),%RCX |
0x424ff3 DIVL 0x88(%RSP) |
0x424ffa MOV 0x8(%R12),%RDI |
0x424fff MOV 0x18(%R12),%RBX |
0x425004 MOV %RCX,0x48(%RSP) |
0x425009 MOV %RDI,0x40(%RSP) |
0x42500e MOV %RBX,0x30(%RSP) |
0x425013 MOV %R14D,%R10D |
0x425016 MOV 0x10(%R12),%R14 |
0x42501b MOV 0x20(%R12),%R12 |
0x425020 MOV %R14,0x38(%RSP) |
0x425025 MOV %R12,0x28(%RSP) |
0x42502a ADD %EDX,%R11D |
0x42502d LEA (%RAX,%R15,1),%R15D |
0x425031 MOV %R11D,0xa0(%RSP) |
0x425039 SUB %R11D,%R10D |
0x42503c MOVSXD %R15D,%RCX |
0x42503f NOP |
(105) 0x425040 CMP %R10D,%ESI |
(105) 0x425043 CMOVBE %ESI,%R10D |
(105) 0x425047 LEA (%R9,%R10,1),%ESI |
(105) 0x42504b MOV %R10D,%EDX |
(105) 0x42504e MOV %ESI,0x8c(%RSP) |
(105) 0x425055 CMP %ESI,%R9D |
(105) 0x425058 JAE 4256e8 |
(105) 0x42505e MOV 0x38(%RSP),%RAX |
(105) 0x425063 LEA 0x1(%RCX),%R14 |
(105) 0x425067 MOV 0x48(%RSP),%R8 |
(105) 0x42506c MOV 0x40(%RSP),%R10 |
(105) 0x425071 MOV 0x30(%RSP),%R13 |
(105) 0x425076 MOV %R14,0x60(%RSP) |
(105) 0x42507b MOV (%RAX),%R12 |
(105) 0x42507e MOV (%R8),%RSI |
(105) 0x425081 MOV (%R10),%R11 |
(105) 0x425084 MOV 0x10(%RAX),%RDI |
(105) 0x425088 IMUL %R12,%R14 |
(105) 0x42508c MOV 0x28(%RSP),%RAX |
(105) 0x425091 MOV 0x10(%R8),%R15 |
(105) 0x425095 IMUL %RCX,%RSI |
(105) 0x425099 MOV 0x10(%R10),%R8 |
(105) 0x42509d MOV 0x10(%R13),%R10 |
(105) 0x4250a1 IMUL %RCX,%R11 |
(105) 0x4250a5 MOV %R15,0x98(%RSP) |
(105) 0x4250ad MOV %R14,%RBX |
(105) 0x4250b0 MOV %R14,0x78(%RSP) |
(105) 0x4250b5 SUB %R12,%RBX |
(105) 0x4250b8 MOV (%R13),%R12 |
(105) 0x4250bc MOV 0x10(%RAX),%R13 |
(105) 0x4250c0 MOV %RSI,0x68(%RSP) |
(105) 0x4250c5 MOV %R11,0x70(%RSP) |
(105) 0x4250ca IMUL %RCX,%R12 |
(105) 0x4250ce MOV %RBX,0x80(%RSP) |
(105) 0x4250d6 IMUL (%RAX),%RCX |
(105) 0x4250da MOV %R10,0xa8(%RSP) |
(105) 0x4250e2 MOV %R13,0xb8(%RSP) |
(105) 0x4250ea MOV %R12,0x90(%RSP) |
(105) 0x4250f2 MOV %RCX,0xb0(%RSP) |
(105) 0x4250fa LEA -0x1(%RDX),%ECX |
(105) 0x4250fd CMP $0x6,%ECX |
(105) 0x425100 JBE 4256f8 |
(105) 0x425106 MOVSXD 0xa0(%RSP),%RAX |
(105) 0x42510e LEA 0x1(%R11,%RAX,1),%R11 |
(105) 0x425113 LEA (%RSI,%RAX,1),%R10 |
(105) 0x425117 SAL $0x3,%R11 |
(105) 0x42511b LEA (%R14,%RAX,1),%R14 |
(105) 0x42511f LEA (%RBX,%RAX,1),%RBX |
(105) 0x425123 LEA (%R8,%R11,1),%RCX |
(105) 0x425127 LEA -0x8(%R8,%R11,1),%RSI |
(105) 0x42512c MOV 0xb0(%RSP),%R11 |
(105) 0x425134 LEA (%R12,%RAX,1),%R12 |
(105) 0x425138 LEA (%R15,%R10,8),%R15 |
(105) 0x42513c MOV 0xa8(%RSP),%R10 |
(105) 0x425144 ADD %R11,%RAX |
(105) 0x425147 MOV %EDX,%R11D |
(105) 0x42514a LEA (%RDI,%R14,8),%R13 |
(105) 0x42514e SHR $0x3,%R11D |
(105) 0x425152 LEA (%R10,%R12,8),%R12 |
(105) 0x425156 LEA (%RDI,%RBX,8),%R14 |
(105) 0x42515a MOV 0xb8(%RSP),%RBX |
(105) 0x425162 SAL $0x6,%R11 |
(105) 0x425166 LEA -0x40(%R11),%R10 |
(105) 0x42516a LEA (%RBX,%RAX,8),%RBX |
(105) 0x42516e XOR %EAX,%EAX |
(105) 0x425170 SHR $0x6,%R10 |
(105) 0x425174 INC %R10 |
(105) 0x425177 AND $0x3,%R10D |
(105) 0x42517b JE 425283 |
(105) 0x425181 CMP $0x1,%R10 |
(105) 0x425185 JE 42522a |
(105) 0x42518b CMP $0x2,%R10 |
(105) 0x42518f JE 4251da |
(105) 0x425191 VMOVUPD (%RCX),%ZMM4 |
(105) 0x425197 VMOVUPD (%R14),%ZMM5 |
(105) 0x42519d MOV $0x40,%EAX |
(105) 0x4251a2 VADDPD (%R15),%ZMM4,%ZMM0 |
(105) 0x4251a8 VADDPD (%RSI),%ZMM5,%ZMM1 |
(105) 0x4251ae VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(105) 0x4251b4 VADDPD (%R13),%ZMM2,%ZMM3 |
(105) 0x4251bb VMOVUPD %ZMM3,(%R12) |
(105) 0x4251c2 VMOVUPD (%RSI),%ZMM6 |
(105) 0x4251c8 VSUBPD (%RCX),%ZMM6,%ZMM7 |
(105) 0x4251ce VADDPD %ZMM3,%ZMM7,%ZMM8 |
(105) 0x4251d4 VMOVUPD %ZMM8,(%RBX) |
(105) 0x4251da VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(105) 0x4251e1 VMOVUPD (%R14,%RAX,1),%ZMM11 |
(105) 0x4251e8 VADDPD (%R15,%RAX,1),%ZMM9,%ZMM10 |
(105) 0x4251ef VADDPD (%RSI,%RAX,1),%ZMM11,%ZMM12 |
(105) 0x4251f6 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(105) 0x4251fc VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(105) 0x425204 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(105) 0x42520b VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(105) 0x425212 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM4 |
(105) 0x425219 VADDPD %ZMM14,%ZMM4,%ZMM0 |
(105) 0x42521f VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(105) 0x425226 ADD $0x40,%RAX |
(105) 0x42522a VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(105) 0x425231 VMOVUPD (%R14,%RAX,1),%ZMM1 |
(105) 0x425238 VADDPD (%R15,%RAX,1),%ZMM5,%ZMM2 |
(105) 0x42523f VADDPD (%RSI,%RAX,1),%ZMM1,%ZMM3 |
(105) 0x425246 VSUBPD %ZMM3,%ZMM2,%ZMM6 |
(105) 0x42524c VADDPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(105) 0x425254 VMOVUPD %ZMM7,(%R12,%RAX,1) |
(105) 0x42525b VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(105) 0x425262 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(105) 0x425269 VADDPD %ZMM7,%ZMM9,%ZMM10 |
(105) 0x42526f VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(105) 0x425276 ADD $0x40,%RAX |
(105) 0x42527a CMP %RAX,%R11 |
(105) 0x42527d JE 4253da |
(106) 0x425283 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(106) 0x42528a VMOVUPD (%R14,%RAX,1),%ZMM13 |
(106) 0x425291 VADDPD (%R15,%RAX,1),%ZMM11,%ZMM12 |
(106) 0x425298 VADDPD (%RSI,%RAX,1),%ZMM13,%ZMM14 |
(106) 0x42529f VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(106) 0x4252a5 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM4 |
(106) 0x4252ad VMOVUPD %ZMM4,(%R12,%RAX,1) |
(106) 0x4252b4 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(106) 0x4252bb VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM5 |
(106) 0x4252c2 VADDPD %ZMM4,%ZMM5,%ZMM2 |
(106) 0x4252c8 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(106) 0x4252cf VMOVUPD 0x40(%RCX,%RAX,1),%ZMM1 |
(106) 0x4252d7 VMOVUPD 0x40(%R14,%RAX,1),%ZMM6 |
(106) 0x4252df VADDPD 0x40(%R15,%RAX,1),%ZMM1,%ZMM3 |
(106) 0x4252e7 VADDPD 0x40(%RSI,%RAX,1),%ZMM6,%ZMM7 |
(106) 0x4252ef VSUBPD %ZMM7,%ZMM3,%ZMM8 |
(106) 0x4252f5 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(106) 0x4252fd VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(106) 0x425305 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(106) 0x42530d VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(106) 0x425315 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(106) 0x42531b VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(106) 0x425323 VMOVUPD 0x80(%RCX,%RAX,1),%ZMM13 |
(106) 0x42532b VMOVUPD 0x80(%R14,%RAX,1),%ZMM15 |
(106) 0x425333 VADDPD 0x80(%R15,%RAX,1),%ZMM13,%ZMM14 |
(106) 0x42533b VADDPD 0x80(%RSI,%RAX,1),%ZMM15,%ZMM4 |
(106) 0x425343 VSUBPD %ZMM4,%ZMM14,%ZMM0 |
(106) 0x425349 VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM5 |
(106) 0x425351 VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(106) 0x425359 VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(106) 0x425361 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(106) 0x425369 VADDPD %ZMM5,%ZMM1,%ZMM3 |
(106) 0x42536f VMOVUPD %ZMM3,0x80(%RBX,%RAX,1) |
(106) 0x425377 VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM6 |
(106) 0x42537f VMOVUPD 0xc0(%R14,%RAX,1),%ZMM8 |
(106) 0x425387 VADDPD 0xc0(%R15,%RAX,1),%ZMM6,%ZMM7 |
(106) 0x42538f VADDPD 0xc0(%RSI,%RAX,1),%ZMM8,%ZMM9 |
(106) 0x425397 VSUBPD %ZMM9,%ZMM7,%ZMM10 |
(106) 0x42539d VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(106) 0x4253a5 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(106) 0x4253ad VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(106) 0x4253b5 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(106) 0x4253bd VADDPD %ZMM11,%ZMM13,%ZMM14 |
(106) 0x4253c3 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(106) 0x4253cb ADD $0x100,%RAX |
(106) 0x4253d1 CMP %RAX,%R11 |
(106) 0x4253d4 JNE 425283 |
(105) 0x4253da MOV 0xa0(%RSP),%R15D |
(105) 0x4253e2 MOV %EDX,%R13D |
(105) 0x4253e5 AND $-0x8,%R13D |
(105) 0x4253e9 ADD %R13D,%R9D |
(105) 0x4253ec LEA (%R13,%R15,1),%ESI |
(105) 0x4253f1 TEST $0x7,%DL |
(105) 0x4253f4 JE 42569b |
(105) 0x4253fa SUB %R13D,%EDX |
(105) 0x4253fd LEA -0x1(%RDX),%ECX |
(105) 0x425400 CMP $0x2,%ECX |
(105) 0x425403 JBE 4254d0 |
(105) 0x425409 MOVSXD 0xa0(%RSP),%RAX |
(105) 0x425411 MOV 0x70(%RSP),%R14 |
(105) 0x425416 MOV 0x78(%RSP),%R15 |
(105) 0x42541b MOV 0x68(%RSP),%R10 |
(105) 0x425420 LEA (%R14,%RAX,1),%R12 |
(105) 0x425424 LEA 0x1(%R13,%R12,1),%R11 |
(105) 0x425429 LEA (%R15,%RAX,1),%R12 |
(105) 0x42542d MOV 0x90(%RSP),%R15 |
(105) 0x425435 SAL $0x3,%R11 |
(105) 0x425439 ADD %R13,%R12 |
(105) 0x42543c LEA (%R10,%RAX,1),%R14 |
(105) 0x425440 MOV 0x80(%RSP),%R10 |
(105) 0x425448 LEA (%R8,%R11,1),%RBX |
(105) 0x42544c VMOVUPD (%RDI,%R12,8),%YMM15 |
(105) 0x425452 LEA -0x8(%R8,%R11,1),%RCX |
(105) 0x425457 MOV 0x98(%RSP),%R11 |
(105) 0x42545f VMOVUPD (%RBX),%YMM0 |
(105) 0x425463 ADD %R13,%R14 |
(105) 0x425466 LEA (%R15,%RAX,1),%R12 |
(105) 0x42546a VADDPD (%R11,%R14,8),%YMM15,%YMM4 |
(105) 0x425470 LEA (%R10,%RAX,1),%R14 |
(105) 0x425474 MOV 0xa8(%RSP),%R11 |
(105) 0x42547c ADD %R13,%R12 |
(105) 0x42547f VSUBPD (%RCX),%YMM0,%YMM5 |
(105) 0x425483 ADD %R13,%R14 |
(105) 0x425486 VADDPD %YMM5,%YMM4,%YMM2 |
(105) 0x42548a VSUBPD (%RDI,%R14,8),%YMM2,%YMM3 |
(105) 0x425490 VMOVUPD %YMM3,(%R11,%R12,8) |
(105) 0x425496 VMOVUPD (%RCX),%YMM1 |
(105) 0x42549a VSUBPD (%RBX),%YMM1,%YMM6 |
(105) 0x42549e MOV 0xb0(%RSP),%RBX |
(105) 0x4254a6 ADD %RBX,%RAX |
(105) 0x4254a9 VADDPD %YMM3,%YMM6,%YMM7 |
(105) 0x4254ad ADD %R13,%RAX |
(105) 0x4254b0 MOV 0xb8(%RSP),%R13 |
(105) 0x4254b8 VMOVUPD %YMM7,(%R13,%RAX,8) |
(105) 0x4254bf TEST $0x3,%DL |
(105) 0x4254c2 JE 42569b |
(105) 0x4254c8 AND $-0x4,%EDX |
(105) 0x4254cb ADD %EDX,%R9D |
(105) 0x4254ce ADD %EDX,%ESI |
(105) 0x4254d0 MOV 0x70(%RSP),%R15 |
(105) 0x4254d5 LEA 0x1(%RSI),%EDX |
(105) 0x4254d8 MOV 0x68(%RSP),%R14 |
(105) 0x4254dd MOVSXD %ESI,%RAX |
(105) 0x4254e0 MOVSXD %EDX,%RDX |
(105) 0x4254e3 MOV 0x98(%RSP),%R12 |
(105) 0x4254eb MOV 0x78(%RSP),%R13 |
(105) 0x4254f0 LEA (%R15,%RDX,1),%RCX |
(105) 0x4254f4 LEA (%R14,%RAX,1),%RBX |
(105) 0x4254f8 LEA (%R8,%RCX,8),%RCX |
(105) 0x4254fc VMOVSD (%R12,%RBX,8),%XMM8 |
(105) 0x425502 LEA (%R15,%RAX,1),%R10 |
(105) 0x425506 MOV 0x80(%RSP),%R12 |
(105) 0x42550e VMOVSD (%RCX),%XMM10 |
(105) 0x425512 LEA (%R8,%R10,8),%R10 |
(105) 0x425516 LEA (%R13,%RAX,1),%R11 |
(105) 0x42551b VADDSD (%RDI,%R11,8),%XMM8,%XMM9 |
(105) 0x425521 LEA (%R12,%RAX,1),%RBX |
(105) 0x425525 MOV 0x90(%RSP),%R11 |
(105) 0x42552d VSUBSD (%R10),%XMM10,%XMM11 |
(105) 0x425532 LEA (%R11,%RAX,1),%R11 |
(105) 0x425536 VADDSD %XMM11,%XMM9,%XMM12 |
(105) 0x42553b VSUBSD (%RDI,%RBX,8),%XMM12,%XMM13 |
(105) 0x425540 MOV 0xa8(%RSP),%RBX |
(105) 0x425548 VMOVSD %XMM13,(%RBX,%R11,8) |
(105) 0x42554e MOV 0xb0(%RSP),%R11 |
(105) 0x425556 MOV 0x8c(%RSP),%EBX |
(105) 0x42555d VMOVSD (%R10),%XMM14 |
(105) 0x425562 MOV 0xb8(%RSP),%R10 |
(105) 0x42556a ADD %R11,%RAX |
(105) 0x42556d VSUBSD (%RCX),%XMM14,%XMM15 |
(105) 0x425571 VADDSD %XMM13,%XMM15,%XMM4 |
(105) 0x425576 VMOVSD %XMM4,(%R10,%RAX,8) |
(105) 0x42557c LEA 0x1(%R9),%EAX |
(105) 0x425580 CMP %EBX,%EAX |
(105) 0x425582 JAE 42569b |
(105) 0x425588 LEA 0x2(%RSI),%EAX |
(105) 0x42558b MOV %R15,%RBX |
(105) 0x42558e LEA (%RDX,%R14,1),%R11 |
(105) 0x425592 ADD $0x2,%R9D |
(105) 0x425596 CLTQ |
(105) 0x425598 LEA (%R15,%RAX,1),%R15 |
(105) 0x42559c LEA (%R8,%R15,8),%R10 |
(105) 0x4255a0 MOV 0x98(%RSP),%R15 |
(105) 0x4255a8 MOV %R10,0xa0(%RSP) |
(105) 0x4255b0 VMOVSD (%R15,%R11,8),%XMM0 |
(105) 0x4255b6 MOV %R12,%R15 |
(105) 0x4255b9 LEA (%R12,%RDX,1),%R12 |
(105) 0x4255bd VMOVSD (%RDI,%R12,8),%XMM2 |
(105) 0x4255c3 MOV 0x90(%RSP),%R12 |
(105) 0x4255cb VADDSD (%R10),%XMM0,%XMM5 |
(105) 0x4255d0 LEA (%R13,%RDX,1),%R10 |
(105) 0x4255d5 VADDSD (%RCX),%XMM2,%XMM3 |
(105) 0x4255d9 LEA (%R12,%RDX,1),%R11 |
(105) 0x4255dd VSUBSD %XMM3,%XMM5,%XMM1 |
(105) 0x4255e1 VADDSD (%RDI,%R10,8),%XMM1,%XMM6 |
(105) 0x4255e7 MOV 0xa8(%RSP),%R10 |
(105) 0x4255ef VMOVSD %XMM6,(%R10,%R11,8) |
(105) 0x4255f5 MOV 0xb0(%RSP),%R11 |
(105) 0x4255fd VMOVSD (%RCX),%XMM7 |
(105) 0x425601 MOV 0xa0(%RSP),%RCX |
(105) 0x425609 ADD %R11,%RDX |
(105) 0x42560c VSUBSD (%RCX),%XMM7,%XMM8 |
(105) 0x425610 MOV 0xb8(%RSP),%RCX |
(105) 0x425618 VADDSD %XMM6,%XMM8,%XMM9 |
(105) 0x42561c VMOVSD %XMM9,(%RCX,%RDX,8) |
(105) 0x425621 MOV 0x8c(%RSP),%EDX |
(105) 0x425628 CMP %EDX,%R9D |
(105) 0x42562b JAE 42569b |
(105) 0x42562d ADD $0x3,%ESI |
(105) 0x425630 ADD %RAX,%R14 |
(105) 0x425633 ADD %RAX,%R15 |
(105) 0x425636 ADD %RAX,%R13 |
(105) 0x425639 MOVSXD %ESI,%R9 |
(105) 0x42563c MOV 0x98(%RSP),%RSI |
(105) 0x425644 VMOVSD (%RDI,%R15,8),%XMM12 |
(105) 0x42564a ADD %RAX,%R12 |
(105) 0x42564d ADD %RBX,%R9 |
(105) 0x425650 MOV 0xa0(%RSP),%RBX |
(105) 0x425658 ADD %RAX,%R11 |
(105) 0x42565b VMOVSD (%RSI,%R14,8),%XMM10 |
(105) 0x425661 LEA (%R8,%R9,8),%R8 |
(105) 0x425665 VADDSD (%RBX),%XMM12,%XMM13 |
(105) 0x425669 VADDSD (%R8),%XMM10,%XMM11 |
(105) 0x42566e VSUBSD %XMM13,%XMM11,%XMM14 |
(105) 0x425673 VADDSD (%RDI,%R13,8),%XMM14,%XMM15 |
(105) 0x425679 MOV 0xb8(%RSP),%RDI |
(105) 0x425681 VMOVSD %XMM15,(%R10,%R12,8) |
(105) 0x425687 VMOVSD (%RBX),%XMM4 |
(105) 0x42568b VSUBSD (%R8),%XMM4,%XMM0 |
(105) 0x425690 VADDSD %XMM15,%XMM0,%XMM5 |
(105) 0x425695 VMOVSD %XMM5,(%RDI,%R11,8) |
(105) 0x42569b MOV 0x8c(%RSP),%R9D |
(105) 0x4256a3 MOV 0x60(%RSP),%RCX |
(105) 0x4256a8 LEA (%RCX),%EAX |
(105) 0x4256aa CMP %EAX,0x5c(%RSP) |
(105) 0x4256ae JLE 4256d0 |
(105) 0x4256b0 MOV 0x54(%RSP),%ESI |
(105) 0x4256b4 MOV 0x58(%RSP),%EDX |
(105) 0x4256b8 MOV 0x88(%RSP),%R10D |
(105) 0x4256c0 MOV %EDX,0xa0(%RSP) |
(105) 0x4256c7 SUB %R9D,%ESI |
(105) 0x4256ca JMP 425040 |
0x4256cf NOP |
0x4256d0 VZEROUPPER |
0x4256d3 LEA -0x28(%RBP),%RSP |
0x4256d7 POP %RBX |
0x4256d8 POP %R12 |
0x4256da POP %R13 |
0x4256dc POP %R14 |
0x4256de POP %R15 |
0x4256e0 POP %RBP |
0x4256e1 RET |
0x4256e2 NOPW (%RAX,%RAX,1) |
(105) 0x4256e8 LEA 0x1(%RCX),%R13 |
(105) 0x4256ec MOV %R13,0x60(%RSP) |
(105) 0x4256f1 JMP 4256a3 |
0x4256f3 NOPL (%RAX,%RAX,1) |
(105) 0x4256f8 MOV 0xa0(%RSP),%ESI |
(105) 0x4256ff XOR %R13D,%R13D |
(105) 0x425702 JMP 4253fa |
0x425707 INC %ESI |
0x425709 XOR %EDX,%EDX |
0x42570b JMP 424fcb |
Path / |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 425707 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4256d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 424fcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 425707 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4256d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 424fcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0– | 1.54 | 1.15 |
▼Loop 105 - advec_cell.cpp:44-48 - exec– | 0 | 0 |
○Loop 106 - advec_cell.cpp:47-48 - exec | 1.53 | 1.14 |