Function: _Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0 | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
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Function: _Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0 | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp: 77 - 82 |
-------------------------------------------------------------------------------- |
77: #pragma omp parallel for simd collapse(2) |
78: for (int j = (0); j < (yrange1); j++) { |
79: for (int i = (0); i < (xrange1); i++) { |
80: field.volume(i, j) = dx * dy; |
81: field.xarea(i, j) = field.celldy[j]; |
82: field.yarea(i, j) = field.celldx[i]; |
0x43b830 PUSH %RBP |
0x43b831 MOV %RSP,%RBP |
0x43b834 PUSH %R15 |
0x43b836 PUSH %R14 |
0x43b838 PUSH %R13 |
0x43b83a PUSH %R12 |
0x43b83c PUSH %RBX |
0x43b83d AND $-0x40,%RSP |
0x43b841 SUB $0x40,%RSP |
0x43b845 MOV 0x1c(%RDI),%R14D |
0x43b849 MOV 0x18(%RDI),%R15D |
0x43b84d MOV %R14D,0x10(%RSP) |
0x43b852 MOV %R15D,0x4(%RSP) |
0x43b857 TEST %R14D,%R14D |
0x43b85a JLE 43bdb3 |
0x43b860 TEST %R15D,%R15D |
0x43b863 JLE 43bdb3 |
0x43b869 MOV %RDI,%R12 |
0x43b86c CALL 4046c0 <omp_get_num_threads@plt> |
0x43b871 MOV %EAX,%EBX |
0x43b873 CALL 4045b0 <omp_get_thread_num@plt> |
0x43b878 XOR %EDX,%EDX |
0x43b87a MOV %EAX,%ESI |
0x43b87c MOV %R14D,%EAX |
0x43b87f IMUL %R15D,%EAX |
0x43b883 DIV %EBX |
0x43b885 MOV %EAX,%ECX |
0x43b887 CMP %EDX,%ESI |
0x43b889 JB 43bdd4 |
0x43b88f IMUL %ECX,%ESI |
0x43b892 LEA (%RSI,%RDX,1),%R10D |
0x43b896 LEA (%RCX,%R10,1),%EDI |
0x43b89a MOV %EDI,(%RSP) |
0x43b89d CMP %EDI,%R10D |
0x43b8a0 JAE 43bdb3 |
0x43b8a6 MOV 0x4(%RSP),%R8D |
0x43b8ab MOV %R10D,%EAX |
0x43b8ae XOR %EDX,%EDX |
0x43b8b0 VMOVSD 0x8(%R12),%XMM2 |
0x43b8b7 MOV 0x10(%R12),%R13 |
0x43b8bc DIV %R8D |
0x43b8bf VMULSD (%R12),%XMM2,%XMM8 |
0x43b8c5 VBROADCASTSD %XMM8,%YMM3 |
0x43b8ca VBROADCASTSD %XMM8,%ZMM0 |
0x43b8d0 SUB %EDX,%R8D |
0x43b8d3 MOV %EDX,0x30(%RSP) |
0x43b8d7 MOVSXD %EAX,%RBX |
0x43b8da MOV %R8D,%EDX |
0x43b8dd NOPL (%RAX) |
(213) 0x43b8e0 CMP %EDX,%ECX |
(213) 0x43b8e2 CMOVBE %ECX,%EDX |
(213) 0x43b8e5 LEA (%R10,%RDX,1),%ECX |
(213) 0x43b8e9 MOV %ECX,0x14(%RSP) |
(213) 0x43b8ed CMP %ECX,%R10D |
(213) 0x43b8f0 JAE 43bd88 |
(213) 0x43b8f6 MOV 0x290(%R13),%R11 |
(213) 0x43b8fd MOV 0x2a8(%R13),%RDI |
(213) 0x43b904 LEA -0x1(%RDX),%R8D |
(213) 0x43b908 MOV 0x2c0(%R13),%RAX |
(213) 0x43b90f MOV 0x248(%R13),%R9 |
(213) 0x43b916 IMUL %RBX,%R11 |
(213) 0x43b91a MOV 0x2d0(%R13),%RSI |
(213) 0x43b921 MOV 0x2a0(%R13),%R15 |
(213) 0x43b928 IMUL %RBX,%RDI |
(213) 0x43b92c MOV 0x2b8(%R13),%R14 |
(213) 0x43b933 MOV 0x228(%R13),%R12 |
(213) 0x43b93a LEA (%R9,%RBX,8),%RCX |
(213) 0x43b93e IMUL %RBX,%RAX |
(213) 0x43b942 MOV %RSI,0x38(%RSP) |
(213) 0x43b947 MOV %R11,0x18(%RSP) |
(213) 0x43b94c MOV %RDI,0x20(%RSP) |
(213) 0x43b951 MOV %RAX,0x28(%RSP) |
(213) 0x43b956 CMP $0x6,%R8D |
(213) 0x43b95a JBE 43bdc8 |
(213) 0x43b960 MOVSXD 0x30(%RSP),%RAX |
(213) 0x43b965 LEA (%RDI,%RAX,1),%RSI |
(213) 0x43b969 MOV 0x28(%RSP),%RDI |
(213) 0x43b96e LEA (%R11,%RAX,1),%R11 |
(213) 0x43b972 LEA (%R14,%RSI,8),%R9 |
(213) 0x43b976 MOV 0x38(%RSP),%RSI |
(213) 0x43b97b LEA (%R12,%RAX,8),%R8 |
(213) 0x43b97f ADD %RDI,%RAX |
(213) 0x43b982 LEA (%R15,%R11,8),%R11 |
(213) 0x43b986 LEA (%RSI,%RAX,8),%RDI |
(213) 0x43b98a MOV %EDX,%ESI |
(213) 0x43b98c XOR %EAX,%EAX |
(213) 0x43b98e SHR $0x3,%ESI |
(213) 0x43b991 SAL $0x6,%RSI |
(213) 0x43b995 MOV %RSI,0x8(%RSP) |
(213) 0x43b99a SUB $0x40,%RSI |
(213) 0x43b99e SHR $0x6,%RSI |
(213) 0x43b9a2 INC %RSI |
(213) 0x43b9a5 AND $0x7,%ESI |
(213) 0x43b9a8 JE 43baf0 |
(213) 0x43b9ae CMP $0x1,%RSI |
(213) 0x43b9b2 JE 43babf |
(213) 0x43b9b8 CMP $0x2,%RSI |
(213) 0x43b9bc JE 43ba99 |
(213) 0x43b9c2 CMP $0x3,%RSI |
(213) 0x43b9c6 JE 43ba73 |
(213) 0x43b9cc CMP $0x4,%RSI |
(213) 0x43b9d0 JE 43ba4d |
(213) 0x43b9d2 CMP $0x5,%RSI |
(213) 0x43b9d6 JE 43ba27 |
(213) 0x43b9d8 CMP $0x6,%RSI |
(213) 0x43b9dc JE 43ba01 |
(213) 0x43b9de VMOVUPD %ZMM0,(%R11) |
(213) 0x43b9e4 MOV $0x40,%EAX |
(213) 0x43b9e9 VBROADCASTSD (%RCX),%ZMM1 |
(213) 0x43b9ef VMOVUPD %ZMM1,(%R9) |
(213) 0x43b9f5 VMOVUPD (%R8),%ZMM5 |
(213) 0x43b9fb VMOVUPD %ZMM5,(%RDI) |
(213) 0x43ba01 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba08 VBROADCASTSD (%RCX),%ZMM4 |
(213) 0x43ba0e VMOVUPD %ZMM4,(%R9,%RAX,1) |
(213) 0x43ba15 VMOVUPD (%R8,%RAX,1),%ZMM7 |
(213) 0x43ba1c VMOVUPD %ZMM7,(%RDI,%RAX,1) |
(213) 0x43ba23 ADD $0x40,%RAX |
(213) 0x43ba27 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba2e VBROADCASTSD (%RCX),%ZMM6 |
(213) 0x43ba34 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(213) 0x43ba3b VMOVUPD (%R8,%RAX,1),%ZMM9 |
(213) 0x43ba42 VMOVUPD %ZMM9,(%RDI,%RAX,1) |
(213) 0x43ba49 ADD $0x40,%RAX |
(213) 0x43ba4d VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba54 VBROADCASTSD (%RCX),%ZMM10 |
(213) 0x43ba5a VMOVUPD %ZMM10,(%R9,%RAX,1) |
(213) 0x43ba61 VMOVUPD (%R8,%RAX,1),%ZMM11 |
(213) 0x43ba68 VMOVUPD %ZMM11,(%RDI,%RAX,1) |
(213) 0x43ba6f ADD $0x40,%RAX |
(213) 0x43ba73 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba7a VBROADCASTSD (%RCX),%ZMM12 |
(213) 0x43ba80 VMOVUPD %ZMM12,(%R9,%RAX,1) |
(213) 0x43ba87 VMOVUPD (%R8,%RAX,1),%ZMM13 |
(213) 0x43ba8e VMOVUPD %ZMM13,(%RDI,%RAX,1) |
(213) 0x43ba95 ADD $0x40,%RAX |
(213) 0x43ba99 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43baa0 VBROADCASTSD (%RCX),%ZMM14 |
(213) 0x43baa6 VMOVUPD %ZMM14,(%R9,%RAX,1) |
(213) 0x43baad VMOVUPD (%R8,%RAX,1),%ZMM15 |
(213) 0x43bab4 VMOVUPD %ZMM15,(%RDI,%RAX,1) |
(213) 0x43babb ADD $0x40,%RAX |
(213) 0x43babf VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43bac6 VBROADCASTSD (%RCX),%ZMM2 |
(213) 0x43bacc VMOVUPD %ZMM2,(%R9,%RAX,1) |
(213) 0x43bad3 VMOVUPD (%R8,%RAX,1),%ZMM1 |
(213) 0x43bada VMOVUPD %ZMM1,(%RDI,%RAX,1) |
(213) 0x43bae1 ADD $0x40,%RAX |
(213) 0x43bae5 CMP %RAX,0x8(%RSP) |
(213) 0x43baea JE 43bc2d |
(214) 0x43baf0 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(214) 0x43baf7 VBROADCASTSD (%RCX),%ZMM5 |
(214) 0x43bafd VMOVUPD %ZMM5,(%R9,%RAX,1) |
(214) 0x43bb04 VMOVUPD (%R8,%RAX,1),%ZMM4 |
(214) 0x43bb0b VMOVUPD %ZMM4,(%RDI,%RAX,1) |
(214) 0x43bb12 VMOVUPD %ZMM0,0x40(%R11,%RAX,1) |
(214) 0x43bb1a VBROADCASTSD (%RCX),%ZMM7 |
(214) 0x43bb20 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(214) 0x43bb28 VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 |
(214) 0x43bb30 VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) |
(214) 0x43bb38 VMOVUPD %ZMM0,0x80(%R11,%RAX,1) |
(214) 0x43bb40 VBROADCASTSD (%RCX),%ZMM9 |
(214) 0x43bb46 VMOVUPD %ZMM9,0x80(%R9,%RAX,1) |
(214) 0x43bb4e VMOVUPD 0x80(%R8,%RAX,1),%ZMM10 |
(214) 0x43bb56 VMOVUPD %ZMM10,0x80(%RDI,%RAX,1) |
(214) 0x43bb5e VMOVUPD %ZMM0,0xc0(%R11,%RAX,1) |
(214) 0x43bb66 VBROADCASTSD (%RCX),%ZMM11 |
(214) 0x43bb6c VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(214) 0x43bb74 VMOVUPD 0xc0(%R8,%RAX,1),%ZMM12 |
(214) 0x43bb7c VMOVUPD %ZMM12,0xc0(%RDI,%RAX,1) |
(214) 0x43bb84 VMOVUPD %ZMM0,0x100(%R11,%RAX,1) |
(214) 0x43bb8c VBROADCASTSD (%RCX),%ZMM13 |
(214) 0x43bb92 VMOVUPD %ZMM13,0x100(%R9,%RAX,1) |
(214) 0x43bb9a VMOVUPD 0x100(%R8,%RAX,1),%ZMM14 |
(214) 0x43bba2 VMOVUPD %ZMM14,0x100(%RDI,%RAX,1) |
(214) 0x43bbaa VMOVUPD %ZMM0,0x140(%R11,%RAX,1) |
(214) 0x43bbb2 VBROADCASTSD (%RCX),%ZMM15 |
(214) 0x43bbb8 VMOVUPD %ZMM15,0x140(%R9,%RAX,1) |
(214) 0x43bbc0 VMOVUPD 0x140(%R8,%RAX,1),%ZMM2 |
(214) 0x43bbc8 VMOVUPD %ZMM2,0x140(%RDI,%RAX,1) |
(214) 0x43bbd0 VMOVUPD %ZMM0,0x180(%R11,%RAX,1) |
(214) 0x43bbd8 VBROADCASTSD (%RCX),%ZMM1 |
(214) 0x43bbde VMOVUPD %ZMM1,0x180(%R9,%RAX,1) |
(214) 0x43bbe6 VMOVUPD 0x180(%R8,%RAX,1),%ZMM5 |
(214) 0x43bbee VMOVUPD %ZMM5,0x180(%RDI,%RAX,1) |
(214) 0x43bbf6 VMOVUPD %ZMM0,0x1c0(%R11,%RAX,1) |
(214) 0x43bbfe VBROADCASTSD (%RCX),%ZMM4 |
(214) 0x43bc04 VMOVUPD %ZMM4,0x1c0(%R9,%RAX,1) |
(214) 0x43bc0c VMOVUPD 0x1c0(%R8,%RAX,1),%ZMM7 |
(214) 0x43bc14 VMOVUPD %ZMM7,0x1c0(%RDI,%RAX,1) |
(214) 0x43bc1c ADD $0x200,%RAX |
(214) 0x43bc22 CMP %RAX,0x8(%RSP) |
(214) 0x43bc27 JNE 43baf0 |
(213) 0x43bc2d MOV 0x30(%RSP),%R11D |
(213) 0x43bc32 MOV %EDX,%R9D |
(213) 0x43bc35 AND $-0x8,%R9D |
(213) 0x43bc39 ADD %R9D,%R10D |
(213) 0x43bc3c LEA (%R9,%R11,1),%EDI |
(213) 0x43bc40 TEST $0x7,%DL |
(213) 0x43bc43 JE 43bd83 |
(213) 0x43bc49 SUB %R9D,%EDX |
(213) 0x43bc4c LEA -0x1(%RDX),%R8D |
(213) 0x43bc50 CMP $0x2,%R8D |
(213) 0x43bc54 JBE 43bcb9 |
(213) 0x43bc56 MOVSXD 0x30(%RSP),%RAX |
(213) 0x43bc5b MOV 0x18(%RSP),%RSI |
(213) 0x43bc60 MOV 0x20(%RSP),%R8 |
(213) 0x43bc65 VMOVSD (%RCX),%XMM6 |
(213) 0x43bc69 LEA (%RSI,%RAX,1),%R11 |
(213) 0x43bc6d LEA (%R8,%RAX,1),%RSI |
(213) 0x43bc71 MOV 0x28(%RSP),%R8 |
(213) 0x43bc76 ADD %R9,%R11 |
(213) 0x43bc79 VBROADCASTSD %XMM6,%YMM9 |
(213) 0x43bc7e ADD %R9,%RSI |
(213) 0x43bc81 VMOVUPD %YMM3,(%R15,%R11,8) |
(213) 0x43bc87 LEA (%RAX,%R9,1),%R11 |
(213) 0x43bc8b VMOVUPD %YMM9,(%R14,%RSI,8) |
(213) 0x43bc91 ADD %R8,%RAX |
(213) 0x43bc94 ADD %R9,%RAX |
(213) 0x43bc97 VMOVUPD (%R12,%R11,8),%YMM10 |
(213) 0x43bc9d MOV 0x38(%RSP),%R9 |
(213) 0x43bca2 VMOVUPD %YMM10,(%R9,%RAX,8) |
(213) 0x43bca8 TEST $0x3,%DL |
(213) 0x43bcab JE 43bd83 |
(213) 0x43bcb1 AND $-0x4,%EDX |
(213) 0x43bcb4 ADD %EDX,%R10D |
(213) 0x43bcb7 ADD %EDX,%EDI |
(213) 0x43bcb9 MOV 0x18(%RSP),%R9 |
(213) 0x43bcbe MOVSXD %EDI,%RAX |
(213) 0x43bcc1 MOV 0x20(%RSP),%R11 |
(213) 0x43bcc6 LEA (,%RAX,8),%R8 |
(213) 0x43bcce LEA (%R9,%RAX,1),%RDX |
(213) 0x43bcd2 LEA (%R11,%RAX,1),%RSI |
(213) 0x43bcd6 MOV %R8,0x30(%RSP) |
(213) 0x43bcdb MOV 0x28(%RSP),%R8 |
(213) 0x43bce0 VMOVSD %XMM8,(%R15,%RDX,8) |
(213) 0x43bce6 MOV 0x38(%RSP),%RDX |
(213) 0x43bceb VMOVSD (%RCX),%XMM11 |
(213) 0x43bcef VMOVSD %XMM11,(%R14,%RSI,8) |
(213) 0x43bcf5 LEA 0x1(%R10),%ESI |
(213) 0x43bcf9 VMOVSD (%R12,%RAX,8),%XMM12 |
(213) 0x43bcff ADD %R8,%RAX |
(213) 0x43bd02 VMOVSD %XMM12,(%RDX,%RAX,8) |
(213) 0x43bd07 MOV 0x14(%RSP),%EDX |
(213) 0x43bd0b LEA 0x1(%RDI),%EAX |
(213) 0x43bd0e CMP %EDX,%ESI |
(213) 0x43bd10 JAE 43bd83 |
(213) 0x43bd12 CLTQ |
(213) 0x43bd14 ADD $0x2,%R10D |
(213) 0x43bd18 ADD $0x2,%EDI |
(213) 0x43bd1b LEA (%R9,%RAX,1),%RSI |
(213) 0x43bd1f VMOVSD %XMM8,(%R15,%RSI,8) |
(213) 0x43bd25 LEA (%R11,%RAX,1),%RSI |
(213) 0x43bd29 ADD %R8,%RAX |
(213) 0x43bd2c VMOVSD (%RCX),%XMM13 |
(213) 0x43bd30 VMOVSD %XMM13,(%R14,%RSI,8) |
(213) 0x43bd36 MOV 0x30(%RSP),%RSI |
(213) 0x43bd3b VMOVSD 0x8(%R12,%RSI,1),%XMM14 |
(213) 0x43bd42 MOV %R8,%RSI |
(213) 0x43bd45 MOV 0x38(%RSP),%R8 |
(213) 0x43bd4a VMOVSD %XMM14,(%R8,%RAX,8) |
(213) 0x43bd50 CMP %EDX,%R10D |
(213) 0x43bd53 JAE 43bd83 |
(213) 0x43bd55 MOVSXD %EDI,%R10 |
(213) 0x43bd58 ADD %R10,%R9 |
(213) 0x43bd5b ADD %R10,%R11 |
(213) 0x43bd5e ADD %R10,%RSI |
(213) 0x43bd61 VMOVSD %XMM8,(%R15,%R9,8) |
(213) 0x43bd67 MOV 0x30(%RSP),%R15 |
(213) 0x43bd6c VMOVSD (%RCX),%XMM15 |
(213) 0x43bd70 VMOVSD %XMM15,(%R14,%R11,8) |
(213) 0x43bd76 VMOVSD 0x10(%R12,%R15,1),%XMM2 |
(213) 0x43bd7d VMOVSD %XMM2,(%R8,%RSI,8) |
(213) 0x43bd83 MOV 0x14(%RSP),%R10D |
(213) 0x43bd88 INC %RBX |
(213) 0x43bd8b CMP %EBX,0x10(%RSP) |
(213) 0x43bd8f JLE 43bdb0 |
(213) 0x43bd91 MOV (%RSP),%ECX |
(213) 0x43bd94 MOV 0x4(%RSP),%EDX |
(213) 0x43bd98 MOVL $0,0x30(%RSP) |
(213) 0x43bda0 SUB %R10D,%ECX |
(213) 0x43bda3 JMP 43b8e0 |
0x43bda8 NOPL (%RAX,%RAX,1) |
0x43bdb0 VZEROUPPER |
0x43bdb3 LEA -0x28(%RBP),%RSP |
0x43bdb7 POP %RBX |
0x43bdb8 POP %R12 |
0x43bdba POP %R13 |
0x43bdbc POP %R14 |
0x43bdbe POP %R15 |
0x43bdc0 POP %RBP |
0x43bdc1 RET |
0x43bdc2 NOPW (%RAX,%RAX,1) |
(213) 0x43bdc8 MOV 0x30(%RSP),%EDI |
(213) 0x43bdcc XOR %R9D,%R9D |
(213) 0x43bdcf JMP 43bc49 |
0x43bdd4 INC %ECX |
0x43bdd6 XOR %EDX,%EDX |
0x43bdd8 JMP 43b88f |
0x43bddd NOPL (%RAX) |
Path / |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bdb3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bdb3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43bdd4 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43bdb3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43b88f <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bdb3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bdb3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43bdd4 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43bdb3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43b88f <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0– | 0.03 | 0.02 |
▼Loop 213 - initialise_chunk.cpp:77-82 - exec– | 0 | 0 |
○Loop 214 - initialise_chunk.cpp:80-82 - exec | 0.03 | 0.02 |