Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.97% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.97% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 157 - 160 |
-------------------------------------------------------------------------------- |
157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
160: node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1)); |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42c4e0 PUSH %RBP |
0x42c4e1 MOV %RSP,%RBP |
0x42c4e4 PUSH %R15 |
0x42c4e6 PUSH %R14 |
0x42c4e8 PUSH %R13 |
0x42c4ea PUSH %R12 |
0x42c4ec PUSH %RBX |
0x42c4ed AND $-0x40,%RSP |
0x42c4f1 SUB $0x40,%RSP |
0x42c4f5 MOV 0x18(%RDI),%EAX |
0x42c4f8 MOV 0x1c(%RDI),%EDX |
0x42c4fb MOV 0x10(%RDI),%ESI |
0x42c4fe MOV 0x14(%RDI),%EBX |
0x42c501 ADD $0x4,%EDX |
0x42c504 LEA -0x1(%RAX),%R15D |
0x42c508 LEA 0x1(%RSI),%ECX |
0x42c50b MOV %EDX,0x20(%RSP) |
0x42c50f MOV %ECX,0x1c(%RSP) |
0x42c513 CMP %EDX,%R15D |
0x42c516 JGE 42c97b |
0x42c51c LEA 0x3(%RBX),%R13D |
0x42c520 MOV %EDX,%EBX |
0x42c522 SUB %R15D,%EBX |
0x42c525 CMP %R13D,%ECX |
0x42c528 JGE 42c97b |
0x42c52e MOV %RDI,%R14 |
0x42c531 MOV %R13D,%EDI |
0x42c534 SUB %ECX,%EDI |
0x42c536 MOV %EDI,0x24(%RSP) |
0x42c53a CALL 4046c0 <omp_get_num_threads@plt> |
0x42c53f MOV %EAX,%R12D |
0x42c542 CALL 4045b0 <omp_get_thread_num@plt> |
0x42c547 MOV 0x24(%RSP),%R9D |
0x42c54c XOR %EDX,%EDX |
0x42c54e MOV %EAX,%R8D |
0x42c551 IMUL %R9D,%EBX |
0x42c555 MOV %EBX,%EAX |
0x42c557 DIV %R12D |
0x42c55a MOV %EAX,%EDI |
0x42c55c CMP %EDX,%R8D |
0x42c55f JB 42c99b |
0x42c565 IMUL %EDI,%R8D |
0x42c569 LEA (%R8,%RDX,1),%R12D |
0x42c56d LEA (%RDI,%R12,1),%R10D |
0x42c571 MOV %R10D,0x18(%RSP) |
0x42c576 CMP %R10D,%R12D |
0x42c579 JAE 42c97b |
0x42c57f MOV %R12D,%EAX |
0x42c582 XOR %EDX,%EDX |
0x42c584 MOV 0x1c(%RSP),%R11D |
0x42c589 MOV 0x8(%R14),%RCX |
0x42c58d DIVL 0x24(%RSP) |
0x42c591 VMOVSD 0x3632f(%RIP),%XMM3 |
0x42c599 MOV %RCX,0x8(%RSP) |
0x42c59e VBROADCASTSD %XMM3,%YMM4 |
0x42c5a3 VBROADCASTSD %XMM3,%ZMM2 |
0x42c5a9 ADD %R15D,%EAX |
0x42c5ac MOV (%R14),%R15 |
0x42c5af LEA (%RDX,%R11,1),%ESI |
0x42c5b3 MOV %R13D,%EDX |
0x42c5b6 CLTQ |
0x42c5b8 MOV %ESI,0x3c(%RSP) |
0x42c5bc SUB %ESI,%EDX |
0x42c5be MOV %R15,0x10(%RSP) |
0x42c5c3 MOV %RAX,0x30(%RSP) |
0x42c5c8 NOPL (%RAX,%RAX,1) |
(141) 0x42c5d0 CMP %EDX,%EDI |
(141) 0x42c5d2 CMOVBE %EDI,%EDX |
(141) 0x42c5d5 LEA (%R12,%RDX,1),%R13D |
(141) 0x42c5d9 MOV %R13D,0x38(%RSP) |
(141) 0x42c5de CMP %R13D,%R12D |
(141) 0x42c5e1 JAE 42c944 |
(141) 0x42c5e7 MOV 0x10(%RSP),%RBX |
(141) 0x42c5ec MOV 0x30(%RSP),%R9 |
(141) 0x42c5f1 LEA -0x1(%RDX),%EDI |
(141) 0x42c5f4 MOV 0x8(%RSP),%R14 |
(141) 0x42c5f9 MOV (%RBX),%R8 |
(141) 0x42c5fc MOV %R9,%R10 |
(141) 0x42c5ff MOV 0x10(%RBX),%RCX |
(141) 0x42c603 IMUL (%R14),%R9 |
(141) 0x42c607 MOV 0x10(%R14),%R15 |
(141) 0x42c60b IMUL %R8,%R10 |
(141) 0x42c60f MOV %R9,0x28(%RSP) |
(141) 0x42c614 ADD %R10,%R8 |
(141) 0x42c617 CMP $0x6,%EDI |
(141) 0x42c61a JBE 42c990 |
(141) 0x42c620 MOVSXD 0x3c(%RSP),%R11 |
(141) 0x42c625 XOR %EAX,%EAX |
(141) 0x42c627 LEA (%R10,%R11,1),%RSI |
(141) 0x42c62b LEA (%R8,%R11,1),%RDI |
(141) 0x42c62f ADD %R9,%R11 |
(141) 0x42c632 LEA (%R15,%R11,8),%RBX |
(141) 0x42c636 SAL $0x3,%RSI |
(141) 0x42c63a MOV %EDX,%R11D |
(141) 0x42c63d SAL $0x3,%RDI |
(141) 0x42c641 SHR $0x3,%R11D |
(141) 0x42c645 LEA -0x8(%RCX,%RSI,1),%R13 |
(141) 0x42c64a LEA -0x8(%RCX,%RDI,1),%R14 |
(141) 0x42c64f ADD %RCX,%RSI |
(141) 0x42c652 SAL $0x6,%R11 |
(141) 0x42c656 ADD %RCX,%RDI |
(141) 0x42c659 LEA -0x40(%R11),%R9 |
(141) 0x42c65d SHR $0x6,%R9 |
(141) 0x42c661 INC %R9 |
(141) 0x42c664 AND $0x3,%R9D |
(141) 0x42c668 JE 42c71b |
(141) 0x42c66e CMP $0x1,%R9 |
(141) 0x42c672 JE 42c6de |
(141) 0x42c674 CMP $0x2,%R9 |
(141) 0x42c678 JE 42c6aa |
(141) 0x42c67a VMOVUPD (%RDI),%ZMM7 |
(141) 0x42c680 VMOVUPD (%RSI),%ZMM1 |
(141) 0x42c686 MOV $0x40,%EAX |
(141) 0x42c68b VADDPD (%R14),%ZMM7,%ZMM0 |
(141) 0x42c691 VADDPD (%R13),%ZMM1,%ZMM5 |
(141) 0x42c698 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(141) 0x42c69e VMULPD %ZMM2,%ZMM6,%ZMM8 |
(141) 0x42c6a4 VMOVUPD %ZMM8,(%RBX) |
(141) 0x42c6aa VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(141) 0x42c6b1 VMOVUPD (%RSI,%RAX,1),%ZMM11 |
(141) 0x42c6b8 VADDPD (%R14,%RAX,1),%ZMM9,%ZMM10 |
(141) 0x42c6bf VADDPD (%R13,%RAX,1),%ZMM11,%ZMM12 |
(141) 0x42c6c7 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(141) 0x42c6cd VMULPD %ZMM2,%ZMM13,%ZMM14 |
(141) 0x42c6d3 VMOVUPD %ZMM14,(%RBX,%RAX,1) |
(141) 0x42c6da ADD $0x40,%RAX |
(141) 0x42c6de VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(141) 0x42c6e5 VMOVUPD (%RSI,%RAX,1),%ZMM7 |
(141) 0x42c6ec VADDPD (%R14,%RAX,1),%ZMM15,%ZMM0 |
(141) 0x42c6f3 VADDPD (%R13,%RAX,1),%ZMM7,%ZMM1 |
(141) 0x42c6fb VADDPD %ZMM1,%ZMM0,%ZMM5 |
(141) 0x42c701 VMULPD %ZMM2,%ZMM5,%ZMM6 |
(141) 0x42c707 VMOVUPD %ZMM6,(%RBX,%RAX,1) |
(141) 0x42c70e ADD $0x40,%RAX |
(141) 0x42c712 CMP %R11,%RAX |
(141) 0x42c715 JE 42c7f6 |
(142) 0x42c71b VMOVUPD (%RDI,%RAX,1),%ZMM8 |
(142) 0x42c722 VMOVUPD (%RSI,%RAX,1),%ZMM10 |
(142) 0x42c729 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM9 |
(142) 0x42c730 VADDPD (%R13,%RAX,1),%ZMM10,%ZMM11 |
(142) 0x42c738 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(142) 0x42c73e VMULPD %ZMM2,%ZMM12,%ZMM13 |
(142) 0x42c744 VMOVUPD %ZMM13,(%RBX,%RAX,1) |
(142) 0x42c74b VMOVUPD 0x40(%RDI,%RAX,1),%ZMM14 |
(142) 0x42c753 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM0 |
(142) 0x42c75b VADDPD 0x40(%R14,%RAX,1),%ZMM14,%ZMM15 |
(142) 0x42c763 VADDPD 0x40(%R13,%RAX,1),%ZMM0,%ZMM7 |
(142) 0x42c76b VADDPD %ZMM7,%ZMM15,%ZMM1 |
(142) 0x42c771 VMULPD %ZMM2,%ZMM1,%ZMM5 |
(142) 0x42c777 VMOVUPD %ZMM5,0x40(%RBX,%RAX,1) |
(142) 0x42c77f VMOVUPD 0x80(%RDI,%RAX,1),%ZMM6 |
(142) 0x42c787 VMOVUPD 0x80(%RSI,%RAX,1),%ZMM9 |
(142) 0x42c78f VADDPD 0x80(%R14,%RAX,1),%ZMM6,%ZMM8 |
(142) 0x42c797 VADDPD 0x80(%R13,%RAX,1),%ZMM9,%ZMM10 |
(142) 0x42c79f VADDPD %ZMM10,%ZMM8,%ZMM11 |
(142) 0x42c7a5 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(142) 0x42c7ab VMOVUPD %ZMM12,0x80(%RBX,%RAX,1) |
(142) 0x42c7b3 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM13 |
(142) 0x42c7bb VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM15 |
(142) 0x42c7c3 VADDPD 0xc0(%R14,%RAX,1),%ZMM13,%ZMM14 |
(142) 0x42c7cb VADDPD 0xc0(%R13,%RAX,1),%ZMM15,%ZMM0 |
(142) 0x42c7d3 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(142) 0x42c7d9 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(142) 0x42c7df VMOVUPD %ZMM1,0xc0(%RBX,%RAX,1) |
(142) 0x42c7e7 ADD $0x100,%RAX |
(142) 0x42c7ed CMP %R11,%RAX |
(142) 0x42c7f0 JNE 42c71b |
(141) 0x42c7f6 MOV 0x3c(%RSP),%ESI |
(141) 0x42c7fa MOV %EDX,%EAX |
(141) 0x42c7fc AND $-0x8,%EAX |
(141) 0x42c7ff ADD %EAX,%R12D |
(141) 0x42c802 ADD %EAX,%ESI |
(141) 0x42c804 TEST $0x7,%DL |
(141) 0x42c807 JE 42c93f |
(141) 0x42c80d SUB %EAX,%EDX |
(141) 0x42c80f LEA -0x1(%RDX),%R13D |
(141) 0x42c813 CMP $0x2,%R13D |
(141) 0x42c817 JBE 42c86d |
(141) 0x42c819 MOVSXD 0x3c(%RSP),%R14 |
(141) 0x42c81e MOV 0x28(%RSP),%R11 |
(141) 0x42c823 LEA (%R10,%R14,1),%RDI |
(141) 0x42c827 LEA (%R8,%R14,1),%RBX |
(141) 0x42c82b ADD %RAX,%RDI |
(141) 0x42c82e ADD %RAX,%RBX |
(141) 0x42c831 ADD %R11,%RAX |
(141) 0x42c834 VMOVUPD -0x8(%RCX,%RDI,8),%YMM5 |
(141) 0x42c83a VMOVUPD (%RCX,%RBX,8),%YMM8 |
(141) 0x42c83f ADD %R14,%RAX |
(141) 0x42c842 VADDPD -0x8(%RCX,%RBX,8),%YMM5,%YMM6 |
(141) 0x42c848 VADDPD (%RCX,%RDI,8),%YMM8,%YMM9 |
(141) 0x42c84d VADDPD %YMM9,%YMM6,%YMM10 |
(141) 0x42c852 VMULPD %YMM4,%YMM10,%YMM11 |
(141) 0x42c856 VMOVUPD %YMM11,(%R15,%RAX,8) |
(141) 0x42c85c TEST $0x3,%DL |
(141) 0x42c85f JE 42c93f |
(141) 0x42c865 AND $-0x4,%EDX |
(141) 0x42c868 ADD %EDX,%R12D |
(141) 0x42c86b ADD %EDX,%ESI |
(141) 0x42c86d MOVSXD %ESI,%RDX |
(141) 0x42c870 LEA -0x1(%RSI),%EAX |
(141) 0x42c873 MOV 0x28(%RSP),%RBX |
(141) 0x42c878 LEA (%RDX,%R10,1),%R9 |
(141) 0x42c87c CLTQ |
(141) 0x42c87e LEA (%R8,%RDX,1),%R14 |
(141) 0x42c882 LEA (%RCX,%R9,8),%R13 |
(141) 0x42c886 LEA (%R10,%RAX,1),%R11 |
(141) 0x42c88a ADD %R8,%RAX |
(141) 0x42c88d ADD %RBX,%RDX |
(141) 0x42c890 VMOVSD (%RCX,%R11,8),%XMM12 |
(141) 0x42c896 VMOVSD (%R13),%XMM14 |
(141) 0x42c89c LEA (%RCX,%R14,8),%RDI |
(141) 0x42c8a0 MOV 0x38(%RSP),%R9D |
(141) 0x42c8a5 VADDSD (%RCX,%RAX,8),%XMM12,%XMM13 |
(141) 0x42c8aa VADDSD (%RDI),%XMM14,%XMM15 |
(141) 0x42c8ae LEA 0x1(%RSI),%EAX |
(141) 0x42c8b1 VADDSD %XMM15,%XMM13,%XMM0 |
(141) 0x42c8b6 VMULSD %XMM3,%XMM0,%XMM7 |
(141) 0x42c8ba VMOVSD %XMM7,(%R15,%RDX,8) |
(141) 0x42c8c0 LEA 0x1(%R12),%EDX |
(141) 0x42c8c5 CMP %R9D,%EDX |
(141) 0x42c8c8 JAE 42c93f |
(141) 0x42c8ca CLTQ |
(141) 0x42c8cc VMOVSD (%RDI),%XMM1 |
(141) 0x42c8d0 ADD $0x2,%R12D |
(141) 0x42c8d4 ADD $0x2,%ESI |
(141) 0x42c8d7 LEA (%R10,%RAX,1),%R14 |
(141) 0x42c8db LEA (%R8,%RAX,1),%RDX |
(141) 0x42c8df ADD %RBX,%RAX |
(141) 0x42c8e2 LEA (%RCX,%R14,8),%R11 |
(141) 0x42c8e6 LEA (%RCX,%RDX,8),%R14 |
(141) 0x42c8ea VMOVSD (%R14),%XMM6 |
(141) 0x42c8ef VADDSD (%R13),%XMM1,%XMM5 |
(141) 0x42c8f5 VADDSD (%R11),%XMM6,%XMM8 |
(141) 0x42c8fa VADDSD %XMM8,%XMM5,%XMM9 |
(141) 0x42c8ff VMULSD %XMM3,%XMM9,%XMM10 |
(141) 0x42c903 VMOVSD %XMM10,(%R15,%RAX,8) |
(141) 0x42c909 CMP %R9D,%R12D |
(141) 0x42c90c JAE 42c93f |
(141) 0x42c90e MOVSXD %ESI,%R12 |
(141) 0x42c911 ADD %R12,%RBX |
(141) 0x42c914 ADD %R12,%R10 |
(141) 0x42c917 ADD %R8,%R12 |
(141) 0x42c91a VMOVSD (%RCX,%R10,8),%XMM11 |
(141) 0x42c920 VMOVSD (%RCX,%R12,8),%XMM13 |
(141) 0x42c926 VADDSD (%R11),%XMM11,%XMM12 |
(141) 0x42c92b VADDSD (%R14),%XMM13,%XMM14 |
(141) 0x42c930 VADDSD %XMM14,%XMM12,%XMM15 |
(141) 0x42c935 VMULSD %XMM3,%XMM15,%XMM0 |
(141) 0x42c939 VMOVSD %XMM0,(%R15,%RBX,8) |
(141) 0x42c93f MOV 0x38(%RSP),%R12D |
(141) 0x42c944 INCQ 0x30(%RSP) |
(141) 0x42c949 MOV 0x30(%RSP),%RCX |
(141) 0x42c94e ADD $0,%ECX |
(141) 0x42c951 CMP %ECX,0x20(%RSP) |
(141) 0x42c955 JLE 42c978 |
(141) 0x42c957 MOV 0x18(%RSP),%EDI |
(141) 0x42c95b MOV 0x1c(%RSP),%R8D |
(141) 0x42c960 MOV 0x24(%RSP),%EDX |
(141) 0x42c964 MOV %R8D,0x3c(%RSP) |
(141) 0x42c969 SUB %R12D,%EDI |
(141) 0x42c96c JMP 42c5d0 |
0x42c971 NOPL (%RAX) |
0x42c978 VZEROUPPER |
0x42c97b LEA -0x28(%RBP),%RSP |
0x42c97f POP %RBX |
0x42c980 POP %R12 |
0x42c982 POP %R13 |
0x42c984 POP %R14 |
0x42c986 POP %R15 |
0x42c988 POP %RBP |
0x42c989 RET |
0x42c98a NOPW (%RAX,%RAX,1) |
(141) 0x42c990 MOV 0x3c(%RSP),%ESI |
(141) 0x42c994 XOR %EAX,%EAX |
(141) 0x42c996 JMP 42c80d |
0x42c99b INC %EDI |
0x42c99d XOR %EDX,%EDX |
0x42c99f JMP 42c565 |
0x42c9a4 NOPW %CS:(%RAX,%RAX,1) |
0x42c9af NOP |
Path / |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.70 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42c99b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x3632f(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c565 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.70 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42c99b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x3632f(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c565 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8– | 0.97 | 0.72 |
▼Loop 141 - advec_mom.cpp:160-160 - exec– | 0 | 0 |
○Loop 142 - advec_mom.cpp:160-160 - exec | 0.96 | 0.72 |