Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0 ... | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 2.62% |
---|
Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0 ... | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 2.62% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
46: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
47: xvel0(i, j) = xvel1(i, j); |
48: yvel0(i, j) = yvel1(i, j); |
0x43ed70 PUSH %RBP |
0x43ed71 MOV %RSP,%RBP |
0x43ed74 PUSH %R15 |
0x43ed76 PUSH %R14 |
0x43ed78 PUSH %R13 |
0x43ed7a PUSH %R12 |
0x43ed7c PUSH %RBX |
0x43ed7d AND $-0x40,%RSP |
0x43ed81 ADD $-0x80,%RSP |
0x43ed85 MOV 0x28(%RDI),%EAX |
0x43ed88 MOV 0x2c(%RDI),%EDX |
0x43ed8b MOV 0x20(%RDI),%EBX |
0x43ed8e MOV 0x24(%RDI),%ECX |
0x43ed91 ADD $0x3,%EDX |
0x43ed94 LEA 0x1(%RAX),%R15D |
0x43ed98 LEA 0x1(%RBX),%ESI |
0x43ed9b MOV %EDX,0x50(%RSP) |
0x43ed9f MOV %ESI,0x4c(%RSP) |
0x43eda3 CMP %EDX,%R15D |
0x43eda6 JGE 43f2a3 |
0x43edac MOV %EDX,%EBX |
0x43edae LEA 0x3(%RCX),%R14D |
0x43edb2 SUB %R15D,%EBX |
0x43edb5 CMP %R14D,%ESI |
0x43edb8 JGE 43f2a3 |
0x43edbe MOV %RDI,%R13 |
0x43edc1 MOV %R14D,%EDI |
0x43edc4 SUB %ESI,%EDI |
0x43edc6 MOV %EDI,0x54(%RSP) |
0x43edca CALL 4046c0 <omp_get_num_threads@plt> |
0x43edcf MOV %EAX,%R12D |
0x43edd2 CALL 4045b0 <omp_get_thread_num@plt> |
0x43edd7 XOR %EDX,%EDX |
0x43edd9 MOV %EAX,%R8D |
0x43eddc MOV 0x54(%RSP),%EAX |
0x43ede0 IMUL %EBX,%EAX |
0x43ede3 DIV %R12D |
0x43ede6 MOV %EAX,%R12D |
0x43ede9 CMP %EDX,%R8D |
0x43edec JB 43f2c4 |
0x43edf2 IMUL %R12D,%R8D |
0x43edf6 LEA (%R8,%RDX,1),%R9D |
0x43edfa LEA (%R12,%R9,1),%R10D |
0x43edfe MOV %R10D,0x48(%RSP) |
0x43ee03 CMP %R10D,%R9D |
0x43ee06 JAE 43f2a3 |
0x43ee0c MOV %R9D,%EAX |
0x43ee0f XOR %EDX,%EDX |
0x43ee11 MOV 0x4c(%RSP),%R11D |
0x43ee16 MOV (%R13),%RSI |
0x43ee1a DIVL 0x54(%RSP) |
0x43ee1e MOV 0x10(%R13),%RBX |
0x43ee22 MOV %RSI,0x38(%RSP) |
0x43ee27 MOV %RBX,0x28(%RSP) |
0x43ee2c ADD %EDX,%R11D |
0x43ee2f ADD %R15D,%EAX |
0x43ee32 MOV %R14D,%EDX |
0x43ee35 MOV 0x8(%R13),%R15 |
0x43ee39 MOV 0x18(%R13),%R14 |
0x43ee3d MOV %R11D,0x7c(%RSP) |
0x43ee42 SUB %R11D,%EDX |
0x43ee45 MOVSXD %EAX,%RBX |
0x43ee48 MOV %R15,0x40(%RSP) |
0x43ee4d MOV %R14,0x30(%RSP) |
0x43ee52 NOPW (%RAX,%RAX,1) |
(231) 0x43ee58 CMP %EDX,%R12D |
(231) 0x43ee5b CMOVBE %R12D,%EDX |
(231) 0x43ee5f LEA (%R9,%RDX,1),%ECX |
(231) 0x43ee63 MOV %ECX,0x78(%RSP) |
(231) 0x43ee67 CMP %ECX,%R9D |
(231) 0x43ee6a JAE 43f26d |
(231) 0x43ee70 MOV 0x30(%RSP),%R12 |
(231) 0x43ee75 MOV 0x38(%RSP),%RDI |
(231) 0x43ee7a LEA -0x1(%RDX),%EAX |
(231) 0x43ee7d MOV 0x28(%RSP),%RCX |
(231) 0x43ee82 MOV 0x40(%RSP),%R13 |
(231) 0x43ee87 MOV (%R12),%RSI |
(231) 0x43ee8b MOV (%RDI),%R8 |
(231) 0x43ee8e MOV (%RCX),%R10 |
(231) 0x43ee91 MOV (%R13),%R11 |
(231) 0x43ee95 IMUL %RBX,%R8 |
(231) 0x43ee99 MOV 0x10(%R13),%R15 |
(231) 0x43ee9d MOV 0x10(%RDI),%R14 |
(231) 0x43eea1 IMUL %RBX,%RSI |
(231) 0x43eea5 MOV 0x10(%R12),%R13 |
(231) 0x43eeaa MOV 0x10(%RCX),%R12 |
(231) 0x43eeae IMUL %RBX,%R10 |
(231) 0x43eeb2 IMUL %RBX,%R11 |
(231) 0x43eeb6 MOV %R8,0x60(%RSP) |
(231) 0x43eebb MOV %RSI,0x68(%RSP) |
(231) 0x43eec0 MOV %R10,0x70(%RSP) |
(231) 0x43eec5 CMP $0x6,%EAX |
(231) 0x43eec8 JBE 43f2b8 |
(231) 0x43eece MOVSXD 0x7c(%RSP),%RAX |
(231) 0x43eed3 LEA (%R8,%RAX,1),%RCX |
(231) 0x43eed7 LEA (%R11,%RAX,1),%RDI |
(231) 0x43eedb LEA (%R14,%RCX,8),%R8 |
(231) 0x43eedf MOV 0x70(%RSP),%RCX |
(231) 0x43eee4 LEA (%RSI,%RAX,1),%RSI |
(231) 0x43eee8 LEA (%R15,%RDI,8),%R10 |
(231) 0x43eeec LEA (%R13,%RSI,8),%RDI |
(231) 0x43eef1 ADD %RCX,%RAX |
(231) 0x43eef4 MOV %EDX,%ECX |
(231) 0x43eef6 SHR $0x3,%ECX |
(231) 0x43eef9 LEA (%R12,%RAX,8),%RSI |
(231) 0x43eefd XOR %EAX,%EAX |
(231) 0x43eeff SAL $0x6,%RCX |
(231) 0x43ef03 MOV %RCX,0x58(%RSP) |
(231) 0x43ef08 SUB $0x40,%RCX |
(231) 0x43ef0c SHR $0x6,%RCX |
(231) 0x43ef10 INC %RCX |
(231) 0x43ef13 AND $0x7,%ECX |
(231) 0x43ef16 JE 43f034 |
(231) 0x43ef1c CMP $0x1,%RCX |
(231) 0x43ef20 JE 43f009 |
(231) 0x43ef26 CMP $0x2,%RCX |
(231) 0x43ef2a JE 43efe9 |
(231) 0x43ef30 CMP $0x3,%RCX |
(231) 0x43ef34 JE 43efc9 |
(231) 0x43ef3a CMP $0x4,%RCX |
(231) 0x43ef3e JE 43efa9 |
(231) 0x43ef40 CMP $0x5,%RCX |
(231) 0x43ef44 JE 43ef89 |
(231) 0x43ef46 CMP $0x6,%RCX |
(231) 0x43ef4a JE 43ef69 |
(231) 0x43ef4c VMOVUPD (%R10),%ZMM3 |
(231) 0x43ef52 MOV $0x40,%EAX |
(231) 0x43ef57 VMOVUPD %ZMM3,(%R8) |
(231) 0x43ef5d VMOVUPD (%RDI),%ZMM4 |
(231) 0x43ef63 VMOVUPD %ZMM4,(%RSI) |
(231) 0x43ef69 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(231) 0x43ef70 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(231) 0x43ef77 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(231) 0x43ef7e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(231) 0x43ef85 ADD $0x40,%RAX |
(231) 0x43ef89 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(231) 0x43ef90 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(231) 0x43ef97 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(231) 0x43ef9e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(231) 0x43efa5 ADD $0x40,%RAX |
(231) 0x43efa9 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(231) 0x43efb0 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(231) 0x43efb7 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(231) 0x43efbe VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(231) 0x43efc5 ADD $0x40,%RAX |
(231) 0x43efc9 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(231) 0x43efd0 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(231) 0x43efd7 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(231) 0x43efde VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(231) 0x43efe5 ADD $0x40,%RAX |
(231) 0x43efe9 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(231) 0x43eff0 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(231) 0x43eff7 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(231) 0x43effe VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(231) 0x43f005 ADD $0x40,%RAX |
(231) 0x43f009 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(231) 0x43f010 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(231) 0x43f017 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(231) 0x43f01e VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(231) 0x43f025 ADD $0x40,%RAX |
(231) 0x43f029 CMP %RAX,0x58(%RSP) |
(231) 0x43f02e JE 43f141 |
(232) 0x43f034 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(232) 0x43f03b VMOVUPD %ZMM14,(%R8,%RAX,1) |
(232) 0x43f042 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(232) 0x43f049 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(232) 0x43f050 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(232) 0x43f058 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(232) 0x43f060 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(232) 0x43f068 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(232) 0x43f070 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(232) 0x43f078 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(232) 0x43f080 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(232) 0x43f088 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(232) 0x43f090 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(232) 0x43f098 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(232) 0x43f0a0 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(232) 0x43f0a8 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(232) 0x43f0b0 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(232) 0x43f0b8 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(232) 0x43f0c0 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(232) 0x43f0c8 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(232) 0x43f0d0 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(232) 0x43f0d8 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(232) 0x43f0e0 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(232) 0x43f0e8 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(232) 0x43f0f0 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(232) 0x43f0f8 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(232) 0x43f100 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(232) 0x43f108 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(232) 0x43f110 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(232) 0x43f118 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(232) 0x43f120 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(232) 0x43f128 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(232) 0x43f130 ADD $0x200,%RAX |
(232) 0x43f136 CMP %RAX,0x58(%RSP) |
(232) 0x43f13b JNE 43f034 |
(231) 0x43f141 MOV 0x7c(%RSP),%R10D |
(231) 0x43f146 MOV %EDX,%R8D |
(231) 0x43f149 AND $-0x8,%R8D |
(231) 0x43f14d ADD %R8D,%R9D |
(231) 0x43f150 LEA (%R8,%R10,1),%ESI |
(231) 0x43f154 TEST $0x7,%DL |
(231) 0x43f157 JE 43f268 |
(231) 0x43f15d SUB %R8D,%EDX |
(231) 0x43f160 LEA -0x1(%RDX),%EDI |
(231) 0x43f163 CMP $0x2,%EDI |
(231) 0x43f166 JBE 43f1bf |
(231) 0x43f168 MOVSXD 0x7c(%RSP),%RCX |
(231) 0x43f16d MOV 0x60(%RSP),%R10 |
(231) 0x43f172 MOV 0x68(%RSP),%RDI |
(231) 0x43f177 LEA (%R11,%RCX,1),%RAX |
(231) 0x43f17b ADD %RCX,%R10 |
(231) 0x43f17e ADD %R8,%RAX |
(231) 0x43f181 ADD %RCX,%RDI |
(231) 0x43f184 ADD %R8,%R10 |
(231) 0x43f187 VMOVUPD (%R15,%RAX,8),%YMM14 |
(231) 0x43f18d MOV 0x70(%RSP),%RAX |
(231) 0x43f192 ADD %R8,%RDI |
(231) 0x43f195 VMOVUPD %YMM14,(%R14,%R10,8) |
(231) 0x43f19b ADD %RAX,%RCX |
(231) 0x43f19e VMOVUPD (%R13,%RDI,8),%YMM15 |
(231) 0x43f1a5 ADD %R8,%RCX |
(231) 0x43f1a8 VMOVUPD %YMM15,(%R12,%RCX,8) |
(231) 0x43f1ae TEST $0x3,%DL |
(231) 0x43f1b1 JE 43f268 |
(231) 0x43f1b7 AND $-0x4,%EDX |
(231) 0x43f1ba ADD %EDX,%R9D |
(231) 0x43f1bd ADD %EDX,%ESI |
(231) 0x43f1bf MOVSXD %ESI,%R10 |
(231) 0x43f1c2 MOV 0x60(%RSP),%RCX |
(231) 0x43f1c7 MOV 0x68(%RSP),%RDI |
(231) 0x43f1cc LEA (%R11,%R10,1),%RDX |
(231) 0x43f1d0 VMOVSD (%R15,%RDX,8),%XMM3 |
(231) 0x43f1d6 LEA (%RCX,%R10,1),%R8 |
(231) 0x43f1da LEA (%RDI,%R10,1),%RAX |
(231) 0x43f1de LEA 0x1(%R9),%EDX |
(231) 0x43f1e2 VMOVSD %XMM3,(%R14,%R8,8) |
(231) 0x43f1e8 MOV 0x70(%RSP),%R8 |
(231) 0x43f1ed VMOVSD (%R13,%RAX,8),%XMM4 |
(231) 0x43f1f4 LEA 0x1(%RSI),%EAX |
(231) 0x43f1f7 ADD %R8,%R10 |
(231) 0x43f1fa VMOVSD %XMM4,(%R12,%R10,8) |
(231) 0x43f200 MOV 0x78(%RSP),%R10D |
(231) 0x43f205 CMP %R10D,%EDX |
(231) 0x43f208 JAE 43f268 |
(231) 0x43f20a CLTQ |
(231) 0x43f20c ADD $0x2,%R9D |
(231) 0x43f210 ADD $0x2,%ESI |
(231) 0x43f213 LEA (%R11,%RAX,1),%RDX |
(231) 0x43f217 VMOVSD (%R15,%RDX,8),%XMM1 |
(231) 0x43f21d LEA (%RCX,%RAX,1),%RDX |
(231) 0x43f221 VMOVSD %XMM1,(%R14,%RDX,8) |
(231) 0x43f227 LEA (%RDI,%RAX,1),%RDX |
(231) 0x43f22b ADD %R8,%RAX |
(231) 0x43f22e VMOVSD (%R13,%RDX,8),%XMM2 |
(231) 0x43f235 VMOVSD %XMM2,(%R12,%RAX,8) |
(231) 0x43f23b CMP %R10D,%R9D |
(231) 0x43f23e JAE 43f268 |
(231) 0x43f240 MOVSXD %ESI,%R9 |
(231) 0x43f243 ADD %R9,%R11 |
(231) 0x43f246 ADD %R9,%RCX |
(231) 0x43f249 ADD %R9,%RDI |
(231) 0x43f24c ADD %R9,%R8 |
(231) 0x43f24f VMOVSD (%R15,%R11,8),%XMM0 |
(231) 0x43f255 VMOVSD %XMM0,(%R14,%RCX,8) |
(231) 0x43f25b VMOVSD (%R13,%RDI,8),%XMM5 |
(231) 0x43f262 VMOVSD %XMM5,(%R12,%R8,8) |
(231) 0x43f268 MOV 0x78(%RSP),%R9D |
(231) 0x43f26d INC %RBX |
(231) 0x43f270 MOV 0x50(%RSP),%R11D |
(231) 0x43f275 LEA (%RBX),%R15D |
(231) 0x43f278 CMP %R11D,%R15D |
(231) 0x43f27b JGE 43f2a0 |
(231) 0x43f27d MOV 0x48(%RSP),%R12D |
(231) 0x43f282 MOV 0x4c(%RSP),%R14D |
(231) 0x43f287 MOV 0x54(%RSP),%EDX |
(231) 0x43f28b MOV %R14D,0x7c(%RSP) |
(231) 0x43f290 SUB %R9D,%R12D |
(231) 0x43f293 JMP 43ee58 |
0x43f298 NOPL (%RAX,%RAX,1) |
0x43f2a0 VZEROUPPER |
0x43f2a3 LEA -0x28(%RBP),%RSP |
0x43f2a7 POP %RBX |
0x43f2a8 POP %R12 |
0x43f2aa POP %R13 |
0x43f2ac POP %R14 |
0x43f2ae POP %R15 |
0x43f2b0 POP %RBP |
0x43f2b1 RET |
0x43f2b2 NOPW (%RAX,%RAX,1) |
(231) 0x43f2b8 MOV 0x7c(%RSP),%ESI |
(231) 0x43f2bc XOR %R8D,%R8D |
(231) 0x43f2bf JMP 43f15d |
0x43f2c4 INC %R12D |
0x43f2c7 XOR %EDX,%EDX |
0x43f2c9 JMP 43edf2 |
0x43f2ce XCHG %AX,%AX |
Path / |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f2a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f2a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43f2c4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43f2a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43edf2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f2a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f2a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43f2c4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43f2a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43edf2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0– | 2.62 | 1.96 |
▼Loop 231 - reset_field.cpp:47-48 - exec– | 0 | 0.01 |
○Loop 232 - reset_field.cpp:47-48 - exec | 2.62 | 1.96 |