Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.28% |
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Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.28% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 54 - 58 |
-------------------------------------------------------------------------------- |
54: #pragma omp parallel for simd collapse(2) |
55: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
56: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
57: pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
58: post_vol(i, j) = volume(i, j); |
0x425710 PUSH %RBP |
0x425711 MOV %RSP,%RBP |
0x425714 PUSH %R15 |
0x425716 PUSH %R14 |
0x425718 PUSH %R13 |
0x42571a PUSH %R12 |
0x42571c PUSH %RBX |
0x42571d AND $-0x40,%RSP |
0x425721 ADD $-0x80,%RSP |
0x425725 MOV 0x28(%RDI),%EAX |
0x425728 MOV 0x2c(%RDI),%ECX |
0x42572b MOV 0x20(%RDI),%ESI |
0x42572e MOV 0x24(%RDI),%EDX |
0x425731 ADD $0x4,%ECX |
0x425734 LEA -0x1(%RAX),%R15D |
0x425738 DEC %ESI |
0x42573a MOV %ECX,0x48(%RSP) |
0x42573e MOV %ESI,0x44(%RSP) |
0x425742 CMP %ECX,%R15D |
0x425745 JGE 425bf3 |
0x42574b MOV %ECX,%EBX |
0x42574d LEA 0x4(%RDX),%R14D |
0x425751 SUB %R15D,%EBX |
0x425754 CMP %R14D,%ESI |
0x425757 JGE 425bf3 |
0x42575d MOV %RDI,%R13 |
0x425760 MOV %R14D,%EDI |
0x425763 SUB %ESI,%EDI |
0x425765 MOV %EDI,0x4c(%RSP) |
0x425769 CALL 4046c0 <omp_get_num_threads@plt> |
0x42576e MOV %EAX,%R12D |
0x425771 CALL 4045b0 <omp_get_thread_num@plt> |
0x425776 XOR %EDX,%EDX |
0x425778 MOV %EAX,%R8D |
0x42577b MOV 0x4c(%RSP),%EAX |
0x42577f IMUL %EBX,%EAX |
0x425782 DIV %R12D |
0x425785 MOV %EAX,%ECX |
0x425787 CMP %EDX,%R8D |
0x42578a JB 425c13 |
0x425790 IMUL %ECX,%R8D |
0x425794 LEA (%R8,%RDX,1),%R11D |
0x425798 LEA (%RCX,%R11,1),%R9D |
0x42579c MOV %R9D,0x40(%RSP) |
0x4257a1 CMP %R9D,%R11D |
0x4257a4 JAE 425bf3 |
0x4257aa MOV %R11D,%EAX |
0x4257ad XOR %EDX,%EDX |
0x4257af MOV 0x44(%RSP),%R10D |
0x4257b4 MOV 0x8(%R13),%RSI |
0x4257b8 DIVL 0x4c(%RSP) |
0x4257bc MOV 0x18(%R13),%RBX |
0x4257c0 MOV %RSI,0x30(%RSP) |
0x4257c5 MOV %RBX,0x20(%RSP) |
0x4257ca ADD %EDX,%R10D |
0x4257cd ADD %R15D,%EAX |
0x4257d0 MOV %R14D,%EDX |
0x4257d3 MOV (%R13),%R15 |
0x4257d7 MOV 0x10(%R13),%R14 |
0x4257db MOV %R10D,0x74(%RSP) |
0x4257e0 SUB %R10D,%EDX |
0x4257e3 MOVSXD %EAX,%R12 |
0x4257e6 MOV %R15,0x38(%RSP) |
0x4257eb MOV %R14,0x28(%RSP) |
(107) 0x4257f0 CMP %EDX,%ECX |
(107) 0x4257f2 CMOVBE %ECX,%EDX |
(107) 0x4257f5 LEA (%R11,%RDX,1),%ECX |
(107) 0x4257f9 MOV %ECX,0x70(%RSP) |
(107) 0x4257fd CMP %ECX,%R11D |
(107) 0x425800 JAE 425bc2 |
(107) 0x425806 MOV 0x38(%RSP),%R13 |
(107) 0x42580b MOV 0x28(%RSP),%R9 |
(107) 0x425810 MOV 0x20(%RSP),%RAX |
(107) 0x425815 MOV 0x30(%RSP),%RDI |
(107) 0x42581a MOV (%R13),%RBX |
(107) 0x42581e MOV 0x10(%R9),%R8 |
(107) 0x425822 MOV (%R9),%R10 |
(107) 0x425825 MOV (%RAX),%R9 |
(107) 0x425828 IMUL %R12,%RBX |
(107) 0x42582c MOV (%RDI),%R14 |
(107) 0x42582f MOV 0x10(%RAX),%RCX |
(107) 0x425833 MOV %R8,0x60(%RSP) |
(107) 0x425838 IMUL %R12,%R10 |
(107) 0x42583c MOV 0x10(%R13),%R15 |
(107) 0x425840 LEA -0x1(%RDX),%R13D |
(107) 0x425844 MOV 0x10(%RDI),%RSI |
(107) 0x425848 IMUL %R12,%R9 |
(107) 0x42584c MOV %RCX,0x78(%RSP) |
(107) 0x425851 MOV %RBX,0x50(%RSP) |
(107) 0x425856 IMUL %R12,%R14 |
(107) 0x42585a MOV %R10,0x58(%RSP) |
(107) 0x42585f MOV %R9,0x68(%RSP) |
(107) 0x425864 CMP $0x6,%R13D |
(107) 0x425868 JBE 425c08 |
(107) 0x42586e MOVSXD 0x74(%RSP),%RAX |
(107) 0x425873 LEA (%R10,%RAX,1),%R10 |
(107) 0x425877 LEA (%RBX,%RAX,1),%RBX |
(107) 0x42587b LEA (%R8,%R10,8),%R10 |
(107) 0x42587f MOV 0x78(%RSP),%R8 |
(107) 0x425884 LEA 0x1(%R14,%RAX,1),%RDI |
(107) 0x425889 ADD %R9,%RAX |
(107) 0x42588c SAL $0x3,%RDI |
(107) 0x425890 LEA (%R15,%RBX,8),%RCX |
(107) 0x425894 LEA (%R8,%RAX,8),%R9 |
(107) 0x425898 MOV %EDX,%R8D |
(107) 0x42589b LEA (%RSI,%RDI,1),%R13 |
(107) 0x42589f XOR %EAX,%EAX |
(107) 0x4258a1 SHR $0x3,%R8D |
(107) 0x4258a5 LEA -0x8(%RSI,%RDI,1),%RBX |
(107) 0x4258aa SAL $0x6,%R8 |
(107) 0x4258ae LEA -0x40(%R8),%RDI |
(107) 0x4258b2 SHR $0x6,%RDI |
(107) 0x4258b6 INC %RDI |
(107) 0x4258b9 AND $0x3,%EDI |
(107) 0x4258bc JE 42595f |
(107) 0x4258c2 CMP $0x1,%RDI |
(107) 0x4258c6 JE 425927 |
(107) 0x4258c8 CMP $0x2,%RDI |
(107) 0x4258cc JE 4258f8 |
(107) 0x4258ce VMOVUPD (%R13),%ZMM6 |
(107) 0x4258d5 MOV $0x40,%EAX |
(107) 0x4258da VADDPD (%RCX),%ZMM6,%ZMM0 |
(107) 0x4258e0 VSUBPD (%RBX),%ZMM0,%ZMM1 |
(107) 0x4258e6 VMOVUPD %ZMM1,(%R10) |
(107) 0x4258ec VMOVUPD (%RCX),%ZMM7 |
(107) 0x4258f2 VMOVUPD %ZMM7,(%R9) |
(107) 0x4258f8 VMOVUPD (%R13,%RAX,1),%ZMM2 |
(107) 0x425900 VADDPD (%RCX,%RAX,1),%ZMM2,%ZMM3 |
(107) 0x425907 VSUBPD (%RBX,%RAX,1),%ZMM3,%ZMM4 |
(107) 0x42590e VMOVUPD %ZMM4,(%R10,%RAX,1) |
(107) 0x425915 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(107) 0x42591c VMOVUPD %ZMM5,(%R9,%RAX,1) |
(107) 0x425923 ADD $0x40,%RAX |
(107) 0x425927 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(107) 0x42592f VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(107) 0x425936 VSUBPD (%RBX,%RAX,1),%ZMM9,%ZMM10 |
(107) 0x42593d VMOVUPD %ZMM10,(%R10,%RAX,1) |
(107) 0x425944 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(107) 0x42594b VMOVUPD %ZMM11,(%R9,%RAX,1) |
(107) 0x425952 ADD $0x40,%RAX |
(107) 0x425956 CMP %RAX,%R8 |
(107) 0x425959 JE 425a29 |
(108) 0x42595f VMOVUPD (%R13,%RAX,1),%ZMM12 |
(108) 0x425967 VADDPD (%RCX,%RAX,1),%ZMM12,%ZMM13 |
(108) 0x42596e VSUBPD (%RBX,%RAX,1),%ZMM13,%ZMM14 |
(108) 0x425975 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(108) 0x42597c VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(108) 0x425983 VMOVUPD %ZMM15,(%R9,%RAX,1) |
(108) 0x42598a VMOVUPD 0x40(%R13,%RAX,1),%ZMM6 |
(108) 0x425992 VADDPD 0x40(%RCX,%RAX,1),%ZMM6,%ZMM0 |
(108) 0x42599a VSUBPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM1 |
(108) 0x4259a2 VMOVUPD %ZMM1,0x40(%R10,%RAX,1) |
(108) 0x4259aa VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(108) 0x4259b2 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(108) 0x4259ba VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 |
(108) 0x4259c2 VADDPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM3 |
(108) 0x4259ca VSUBPD 0x80(%RBX,%RAX,1),%ZMM3,%ZMM4 |
(108) 0x4259d2 VMOVUPD %ZMM4,0x80(%R10,%RAX,1) |
(108) 0x4259da VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(108) 0x4259e2 VMOVUPD %ZMM5,0x80(%R9,%RAX,1) |
(108) 0x4259ea VMOVUPD 0xc0(%R13,%RAX,1),%ZMM8 |
(108) 0x4259f2 VADDPD 0xc0(%RCX,%RAX,1),%ZMM8,%ZMM9 |
(108) 0x4259fa VSUBPD 0xc0(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(108) 0x425a02 VMOVUPD %ZMM10,0xc0(%R10,%RAX,1) |
(108) 0x425a0a VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(108) 0x425a12 VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(108) 0x425a1a ADD $0x100,%RAX |
(108) 0x425a20 CMP %RAX,%R8 |
(108) 0x425a23 JNE 42595f |
(107) 0x425a29 MOV 0x74(%RSP),%EAX |
(107) 0x425a2d MOV %EDX,%EDI |
(107) 0x425a2f AND $-0x8,%EDI |
(107) 0x425a32 ADD %EDI,%R11D |
(107) 0x425a35 ADD %EDI,%EAX |
(107) 0x425a37 TEST $0x7,%DL |
(107) 0x425a3a JE 425bbd |
(107) 0x425a40 SUB %EDI,%EDX |
(107) 0x425a42 LEA -0x1(%RDX),%ECX |
(107) 0x425a45 CMP $0x2,%ECX |
(107) 0x425a48 JBE 425abb |
(107) 0x425a4a MOVSXD 0x74(%RSP),%R13 |
(107) 0x425a4f MOV 0x50(%RSP),%RBX |
(107) 0x425a54 LEA (%R14,%R13,1),%R8 |
(107) 0x425a58 LEA (%RBX,%R13,1),%R10 |
(107) 0x425a5c MOV 0x58(%RSP),%RBX |
(107) 0x425a61 LEA 0x1(%RDI,%R8,1),%RCX |
(107) 0x425a66 ADD %RDI,%R10 |
(107) 0x425a69 MOV 0x60(%RSP),%R8 |
(107) 0x425a6e VMOVUPD (%RSI,%RCX,8),%YMM12 |
(107) 0x425a73 LEA (%R15,%R10,8),%R9 |
(107) 0x425a77 LEA (%RBX,%R13,1),%R10 |
(107) 0x425a7b ADD %RDI,%R10 |
(107) 0x425a7e VSUBPD -0x8(%RSI,%RCX,8),%YMM12,%YMM13 |
(107) 0x425a84 VADDPD (%R9),%YMM13,%YMM14 |
(107) 0x425a89 VMOVUPD %YMM14,(%R8,%R10,8) |
(107) 0x425a8f VMOVUPD (%R9),%YMM15 |
(107) 0x425a94 MOV 0x68(%RSP),%R9 |
(107) 0x425a99 ADD %R9,%R13 |
(107) 0x425a9c ADD %RDI,%R13 |
(107) 0x425a9f MOV 0x78(%RSP),%RDI |
(107) 0x425aa4 VMOVUPD %YMM15,(%RDI,%R13,8) |
(107) 0x425aaa TEST $0x3,%DL |
(107) 0x425aad JE 425bbd |
(107) 0x425ab3 AND $-0x4,%EDX |
(107) 0x425ab6 ADD %EDX,%R11D |
(107) 0x425ab9 ADD %EDX,%EAX |
(107) 0x425abb MOV 0x50(%RSP),%RBX |
(107) 0x425ac0 MOVSXD %EAX,%RCX |
(107) 0x425ac3 LEA 0x1(%RAX),%R13D |
(107) 0x425ac7 LEA (%RBX,%RCX,1),%RDX |
(107) 0x425acb LEA (%R15,%RDX,8),%RDI |
(107) 0x425acf MOVSXD %R13D,%RDX |
(107) 0x425ad2 MOV 0x58(%RSP),%R13 |
(107) 0x425ad7 LEA (%R14,%RDX,1),%R10 |
(107) 0x425adb LEA (%RSI,%R10,8),%R8 |
(107) 0x425adf LEA (%R14,%RCX,1),%R10 |
(107) 0x425ae3 VMOVSD (%R8),%XMM6 |
(107) 0x425ae8 LEA (%R13,%RCX,1),%R9 |
(107) 0x425aed VSUBSD (%RSI,%R10,8),%XMM6,%XMM0 |
(107) 0x425af3 MOV 0x60(%RSP),%R10 |
(107) 0x425af8 VADDSD (%RDI),%XMM0,%XMM1 |
(107) 0x425afc VMOVSD %XMM1,(%R10,%R9,8) |
(107) 0x425b02 MOV 0x78(%RSP),%R9 |
(107) 0x425b07 MOV 0x70(%RSP),%R10D |
(107) 0x425b0c VMOVSD (%RDI),%XMM7 |
(107) 0x425b10 MOV 0x68(%RSP),%RDI |
(107) 0x425b15 ADD %RDI,%RCX |
(107) 0x425b18 VMOVSD %XMM7,(%R9,%RCX,8) |
(107) 0x425b1e LEA 0x1(%R11),%ECX |
(107) 0x425b22 CMP %R10D,%ECX |
(107) 0x425b25 JAE 425bbd |
(107) 0x425b2b LEA 0x2(%RAX),%R9D |
(107) 0x425b2f LEA (%RDX,%RBX,1),%RDI |
(107) 0x425b33 ADD $0x2,%R11D |
(107) 0x425b37 MOVSXD %R9D,%RCX |
(107) 0x425b3a LEA (%R15,%RDI,8),%RDI |
(107) 0x425b3e LEA (%R14,%RCX,1),%R10 |
(107) 0x425b42 LEA (%RSI,%R10,8),%R9 |
(107) 0x425b46 LEA (%R13,%RDX,1),%R10 |
(107) 0x425b4b VMOVSD (%R9),%XMM2 |
(107) 0x425b50 VADDSD (%RDI),%XMM2,%XMM3 |
(107) 0x425b54 VSUBSD (%R8),%XMM3,%XMM4 |
(107) 0x425b59 MOV 0x60(%RSP),%R8 |
(107) 0x425b5e VMOVSD %XMM4,(%R8,%R10,8) |
(107) 0x425b64 MOV 0x68(%RSP),%R10 |
(107) 0x425b69 VMOVSD (%RDI),%XMM5 |
(107) 0x425b6d MOV 0x78(%RSP),%RDI |
(107) 0x425b72 ADD %R10,%RDX |
(107) 0x425b75 VMOVSD %XMM5,(%RDI,%RDX,8) |
(107) 0x425b7a MOV 0x70(%RSP),%EDX |
(107) 0x425b7e CMP %EDX,%R11D |
(107) 0x425b81 JAE 425bbd |
(107) 0x425b83 ADD $0x3,%EAX |
(107) 0x425b86 ADD %RCX,%RBX |
(107) 0x425b89 ADD %RCX,%R13 |
(107) 0x425b8c ADD %RCX,%R10 |
(107) 0x425b8f CLTQ |
(107) 0x425b91 LEA (%R15,%RBX,8),%R11 |
(107) 0x425b95 MOV 0x78(%RSP),%R15 |
(107) 0x425b9a ADD %R14,%RAX |
(107) 0x425b9d VMOVSD (%RSI,%RAX,8),%XMM8 |
(107) 0x425ba2 VADDSD (%R11),%XMM8,%XMM9 |
(107) 0x425ba7 VSUBSD (%R9),%XMM9,%XMM10 |
(107) 0x425bac VMOVSD %XMM10,(%R8,%R13,8) |
(107) 0x425bb2 VMOVSD (%R11),%XMM11 |
(107) 0x425bb7 VMOVSD %XMM11,(%R15,%R10,8) |
(107) 0x425bbd MOV 0x70(%RSP),%R11D |
(107) 0x425bc2 INC %R12 |
(107) 0x425bc5 LEA (%R12),%ESI |
(107) 0x425bc9 CMP %ESI,0x48(%RSP) |
(107) 0x425bcd JLE 425bf0 |
(107) 0x425bcf MOV 0x40(%RSP),%ECX |
(107) 0x425bd3 MOV 0x44(%RSP),%R14D |
(107) 0x425bd8 MOV 0x4c(%RSP),%EDX |
(107) 0x425bdc MOV %R14D,0x74(%RSP) |
(107) 0x425be1 SUB %R11D,%ECX |
(107) 0x425be4 JMP 4257f0 |
0x425be9 NOPL (%RAX) |
0x425bf0 VZEROUPPER |
0x425bf3 LEA -0x28(%RBP),%RSP |
0x425bf7 POP %RBX |
0x425bf8 POP %R12 |
0x425bfa POP %R13 |
0x425bfc POP %R14 |
0x425bfe POP %R15 |
0x425c00 POP %RBP |
0x425c01 RET |
0x425c02 NOPW (%RAX,%RAX,1) |
(107) 0x425c08 MOV 0x74(%RSP),%EAX |
(107) 0x425c0c XOR %EDI,%EDI |
(107) 0x425c0e JMP 425a40 |
0x425c13 INC %ECX |
0x425c15 XOR %EDX,%EDX |
0x425c17 JMP 425790 |
0x425c1c NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 425c13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 425790 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 425c13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 425790 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0– | 1.28 | 0.96 |
▼Loop 107 - advec_cell.cpp:57-58 - exec– | 0 | 0 |
○Loop 108 - advec_cell.cpp:57-58 - exec | 1.28 | 0.95 |