Function: __svml_idiv8_l9 | Module: exec | Source: :0-0 | Coverage: 0.02% |
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Function: __svml_idiv8_l9 | Module: exec | Source: :0-0 | Coverage: 0.02% |
---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x45b710 ENDBR64 |
0x45b714 VPXOR %XMM2,%XMM2,%XMM2 |
0x45b718 VPCMPEQD %YMM2,%YMM1,%YMM2 |
0x45b71c VTESTPS %YMM2,%YMM2 |
0x45b721 JE 45b72a |
0x45b723 MOV $0,%EAX |
0x45b728 DIV %AL |
0x45b72a VCVTDQ2PS %YMM1,%YMM2 |
0x45b72e VRCPPS %YMM2,%YMM2 |
0x45b732 VEXTRACTF128 $0x1,%YMM2,%XMM3 |
0x45b738 VCVTPS2PD %XMM3,%YMM3 |
0x45b73c VEXTRACTF128 $0x1,%YMM1,%XMM4 |
0x45b742 VCVTDQ2PD %XMM4,%YMM4 |
0x45b746 VBROADCASTSD 0x11931(%RIP),%YMM5 |
0x45b74f VMOVAPD %YMM4,%YMM6 |
0x45b753 VFNMADD213PD %YMM5,%YMM3,%YMM6 |
0x45b758 VMULPD %YMM3,%YMM6,%YMM3 |
0x45b75c VEXTRACTF128 $0x1,%YMM0,%XMM6 |
0x45b762 VCVTDQ2PD %XMM6,%YMM6 |
0x45b766 VMULPD %YMM6,%YMM3,%YMM6 |
0x45b76a VBROADCASTSD 0x2691d(%RIP),%YMM7 |
0x45b773 VCVTPS2PD %XMM2,%YMM2 |
0x45b777 VFNMADD213PD %YMM7,%YMM4,%YMM3 |
0x45b77c VCVTDQ2PD %XMM1,%YMM1 |
0x45b780 VFNMADD231PD %YMM1,%YMM2,%YMM5 |
0x45b785 VMULPD %YMM2,%YMM5,%YMM2 |
0x45b789 VCVTDQ2PD %XMM0,%YMM0 |
0x45b78d VMULPD %YMM0,%YMM2,%YMM0 |
0x45b791 VFNMADD213PD %YMM7,%YMM1,%YMM2 |
0x45b796 VMULPD %YMM2,%YMM0,%YMM0 |
0x45b79a VCVTTPD2DQ %YMM0,%XMM0 |
0x45b79e VMULPD %YMM3,%YMM6,%YMM1 |
0x45b7a2 VCVTTPD2DQ %YMM1,%XMM1 |
0x45b7a6 VINSERTF128 $0x1,%XMM1,%YMM0,%YMM0 |
0x45b7ac RET |
0x45b7ad NOPL (%RAX) |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 34 |
nb uops | 42.50 |
loop length | 153.50 |
used x86 registers | 0.50 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 8 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.08 cycles |
front end | 7.08 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.75 | 11.75 | 1.00 | 1.00 | 0.00 | 12.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 1.00 |
cycles | 11.75 | 11.75 | 1.00 | 1.00 | 0.00 | 12.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 1.00 |
Cycles executing div or sqrt instructions | 3.00 |
FE+BE cycles | 56.39-56.92 |
Stall cycles | 48.95-49.49 |
RS full (events) | 55.91-56.45 |
Front-end | 7.08 |
Dispatch | 12.25 |
DIV/SQRT | 3.00 |
Overall L1 | 12.25 |
all | 93% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 93% |
all | 91% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 83% |
all | 91% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 87% |
all | 30% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 30% |
all | 40% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 31% |
all | 37% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 30% |
Source file and lines | |
Module | exec |
nb instructions | 35 |
nb uops | 45 |
loop length | 157 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 8 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.50 cycles |
front end | 7.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.50 | 12.50 | 1.00 | 1.00 | 0.00 | 12.00 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 1.00 |
cycles | 12.50 | 12.50 | 1.00 | 1.00 | 0.00 | 12.00 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 55.82-56.89 |
Stall cycles | 48.04-49.11 |
RS full (events) | 55.32-56.39 |
Front-end | 7.50 |
Dispatch | 12.50 |
DIV/SQRT | 6.00 |
Overall L1 | 12.50 |
all | 87% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 87% |
all | 91% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 83% |
all | 90% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 85% |
all | 28% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 28% |
all | 40% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 31% |
all | 37% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 30% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %YMM2,%YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VTESTPS %YMM2,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 |
JE 45b72a <__svml_idiv8_l9+0x1a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DIV %AL | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VCVTDQ2PS %YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRCPPS %YMM2,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTF128 $0x1,%YMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTPS2PD %XMM3,%YMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VEXTRACTF128 $0x1,%YMM1,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTDQ2PD %XMM4,%YMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VBROADCASTSD 0x11931(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VMOVAPD %YMM4,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFNMADD213PD %YMM5,%YMM3,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM3,%YMM6,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF128 $0x1,%YMM0,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTDQ2PD %XMM6,%YMM6 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM6,%YMM3,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x2691d(%RIP),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VCVTPS2PD %XMM2,%YMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VFNMADD213PD %YMM7,%YMM4,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTDQ2PD %XMM1,%YMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VFNMADD231PD %YMM1,%YMM2,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM2,%YMM5,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTDQ2PD %XMM0,%YMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM0,%YMM2,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD213PD %YMM7,%YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM2,%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTPD2DQ %YMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM3,%YMM6,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTPD2DQ %YMM1,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VINSERTF128 $0x1,%XMM1,%YMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
Source file and lines | |
Module | exec |
nb instructions | 33 |
nb uops | 40 |
loop length | 150 |
used x86 registers | 0 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 8 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.00 | 11.00 | 1.00 | 1.00 | 0.00 | 12.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.00 |
cycles | 11.00 | 11.00 | 1.00 | 1.00 | 0.00 | 12.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 56.95 |
Stall cycles | 49.87 |
RS full (events) | 56.50 |
Front-end | 6.67 |
Dispatch | 12.00 |
Overall L1 | 12.00 |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 91% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 83% |
all | 93% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 89% |
all | 32% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 32% |
all | 40% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 31% |
all | 38% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 31% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %YMM2,%YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VTESTPS %YMM2,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 |
JE 45b72a <__svml_idiv8_l9+0x1a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VCVTDQ2PS %YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRCPPS %YMM2,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTF128 $0x1,%YMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTPS2PD %XMM3,%YMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VEXTRACTF128 $0x1,%YMM1,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTDQ2PD %XMM4,%YMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VBROADCASTSD 0x11931(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VMOVAPD %YMM4,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFNMADD213PD %YMM5,%YMM3,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM3,%YMM6,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF128 $0x1,%YMM0,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTDQ2PD %XMM6,%YMM6 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM6,%YMM3,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x2691d(%RIP),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VCVTPS2PD %XMM2,%YMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VFNMADD213PD %YMM7,%YMM4,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTDQ2PD %XMM1,%YMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VFNMADD231PD %YMM1,%YMM2,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM2,%YMM5,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTDQ2PD %XMM0,%YMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM0,%YMM2,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD213PD %YMM7,%YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM2,%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTPD2DQ %YMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM3,%YMM6,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTPD2DQ %YMM1,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VINSERTF128 $0x1,%XMM1,%YMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
Name | Coverage (%) | Time (s) |
---|---|---|
○__svml_idiv8_l9 | 0.02 | 0.01 |