Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.97% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.97% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 85 - 88 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
87: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
88: node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0)); |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42a860 PUSH %RBP |
0x42a861 MOV %RSP,%RBP |
0x42a864 PUSH %R15 |
0x42a866 PUSH %R14 |
0x42a868 MOV %RDI,%R14 |
0x42a86b PUSH %R13 |
0x42a86d PUSH %R12 |
0x42a86f PUSH %RBX |
0x42a870 AND $-0x40,%RSP |
0x42a874 SUB $0x40,%RSP |
0x42a878 MOV 0x18(%RDI),%EAX |
0x42a87b MOV 0x1c(%RDI),%EDX |
0x42a87e MOV 0x10(%RDI),%ESI |
0x42a881 MOV 0x14(%R14),%ECX |
0x42a885 ADD $0x3,%EDX |
0x42a888 LEA 0x1(%RAX),%R13D |
0x42a88c LEA -0x1(%RSI),%EDI |
0x42a88f MOV %EDX,0x1c(%RSP) |
0x42a893 MOV %EDI,0x18(%RSP) |
0x42a897 CMP %EDX,%R13D |
0x42a89a JGE 42ad0b |
0x42a8a0 MOV %EDX,%EBX |
0x42a8a2 LEA 0x4(%RCX),%R15D |
0x42a8a6 SUB %R13D,%EBX |
0x42a8a9 CMP %R15D,%EDI |
0x42a8ac JGE 42ad0b |
0x42a8b2 MOV %R15D,%R8D |
0x42a8b5 SUB %EDI,%R8D |
0x42a8b8 MOV %R8D,0x28(%RSP) |
0x42a8bd CALL 4046c0 <omp_get_num_threads@plt> |
0x42a8c2 MOV %EAX,%R12D |
0x42a8c5 CALL 4045b0 <omp_get_thread_num@plt> |
0x42a8ca XOR %EDX,%EDX |
0x42a8cc MOV %EAX,%R9D |
0x42a8cf MOV 0x28(%RSP),%EAX |
0x42a8d3 IMUL %EBX,%EAX |
0x42a8d6 DIV %R12D |
0x42a8d9 MOV %EAX,%EDI |
0x42a8db CMP %EDX,%R9D |
0x42a8de JB 42ad2c |
0x42a8e4 IMUL %EDI,%R9D |
0x42a8e8 LEA (%R9,%RDX,1),%R12D |
0x42a8ec LEA (%RDI,%R12,1),%R10D |
0x42a8f0 MOV %R10D,0x14(%RSP) |
0x42a8f5 CMP %R10D,%R12D |
0x42a8f8 JAE 42ad0b |
0x42a8fe MOV %R12D,%EAX |
0x42a901 XOR %EDX,%EDX |
0x42a903 MOV 0x18(%RSP),%R11D |
0x42a908 MOV (%R14),%RSI |
0x42a90b DIVL 0x28(%RSP) |
0x42a90f MOV 0x8(%R14),%R14 |
0x42a913 VMOVSD 0x37fad(%RIP),%XMM3 |
0x42a91b MOV %RSI,0x8(%RSP) |
0x42a920 MOV %R14,(%RSP) |
0x42a924 VBROADCASTSD %XMM3,%YMM4 |
0x42a929 VBROADCASTSD %XMM3,%ZMM2 |
0x42a92f ADD %R13D,%EAX |
0x42a932 ADD %EDX,%R11D |
0x42a935 MOV %R15D,%EDX |
0x42a938 MOV %EAX,0x38(%RSP) |
0x42a93c CLTQ |
0x42a93e SUB %R11D,%EDX |
0x42a941 MOV %R11D,0x3c(%RSP) |
0x42a946 MOV %RAX,0x20(%RSP) |
0x42a94b NOPL (%RAX,%RAX,1) |
(132) 0x42a950 CMP %EDX,%EDI |
(132) 0x42a952 CMOVBE %EDI,%EDX |
(132) 0x42a955 LEA (%R12,%RDX,1),%R13D |
(132) 0x42a959 MOV %R13D,0x2c(%RSP) |
(132) 0x42a95e CMP %R13D,%R12D |
(132) 0x42a961 JAE 42acd6 |
(132) 0x42a967 MOV 0x8(%RSP),%RDI |
(132) 0x42a96c MOV 0x38(%RSP),%R15D |
(132) 0x42a971 LEA -0x1(%RDX),%R9D |
(132) 0x42a975 MOV 0x20(%RSP),%R10 |
(132) 0x42a97a MOV (%RSP),%R8 |
(132) 0x42a97e LEA -0x1(%R15),%EBX |
(132) 0x42a982 MOV 0x10(%RDI),%RCX |
(132) 0x42a986 MOV (%RDI),%RDI |
(132) 0x42a989 MOVSXD %EBX,%RSI |
(132) 0x42a98c MOV 0x10(%R8),%R15 |
(132) 0x42a990 IMUL %RDI,%RSI |
(132) 0x42a994 IMUL %R10,%RDI |
(132) 0x42a998 IMUL (%R8),%R10 |
(132) 0x42a99c MOV %R10,0x30(%RSP) |
(132) 0x42a9a1 CMP $0x6,%R9D |
(132) 0x42a9a5 JBE 42ad20 |
(132) 0x42a9ab MOVSXD 0x3c(%RSP),%RAX |
(132) 0x42a9b0 MOV %EDX,%R9D |
(132) 0x42a9b3 SHR $0x3,%R9D |
(132) 0x42a9b7 LEA (%RSI,%RAX,1),%R11 |
(132) 0x42a9bb LEA (%RDI,%RAX,1),%R8 |
(132) 0x42a9bf SAL $0x6,%R9 |
(132) 0x42a9c3 ADD %R10,%RAX |
(132) 0x42a9c6 SAL $0x3,%R11 |
(132) 0x42a9ca SAL $0x3,%R8 |
(132) 0x42a9ce LEA (%R15,%RAX,8),%R10 |
(132) 0x42a9d2 XOR %EAX,%EAX |
(132) 0x42a9d4 LEA (%RCX,%R11,1),%R14 |
(132) 0x42a9d8 LEA (%RCX,%R8,1),%R13 |
(132) 0x42a9dc LEA 0x8(%RCX,%R11,1),%RBX |
(132) 0x42a9e1 LEA 0x8(%RCX,%R8,1),%R11 |
(132) 0x42a9e6 LEA -0x40(%R9),%R8 |
(132) 0x42a9ea SHR $0x6,%R8 |
(132) 0x42a9ee INC %R8 |
(132) 0x42a9f1 AND $0x3,%R8D |
(132) 0x42a9f5 JE 42aaa8 |
(132) 0x42a9fb CMP $0x1,%R8 |
(132) 0x42a9ff JE 42aa6b |
(132) 0x42aa01 CMP $0x2,%R8 |
(132) 0x42aa05 JE 42aa37 |
(132) 0x42aa07 VMOVUPD (%R13),%ZMM7 |
(132) 0x42aa0e VMOVUPD (%R11),%ZMM1 |
(132) 0x42aa14 MOV $0x40,%EAX |
(132) 0x42aa19 VADDPD (%R14),%ZMM7,%ZMM0 |
(132) 0x42aa1f VADDPD (%RBX),%ZMM1,%ZMM5 |
(132) 0x42aa25 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(132) 0x42aa2b VMULPD %ZMM2,%ZMM6,%ZMM8 |
(132) 0x42aa31 VMOVUPD %ZMM8,(%R10) |
(132) 0x42aa37 VMOVUPD (%R13,%RAX,1),%ZMM9 |
(132) 0x42aa3f VMOVUPD (%R11,%RAX,1),%ZMM11 |
(132) 0x42aa46 VADDPD (%R14,%RAX,1),%ZMM9,%ZMM10 |
(132) 0x42aa4d VADDPD (%RBX,%RAX,1),%ZMM11,%ZMM12 |
(132) 0x42aa54 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(132) 0x42aa5a VMULPD %ZMM2,%ZMM13,%ZMM14 |
(132) 0x42aa60 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(132) 0x42aa67 ADD $0x40,%RAX |
(132) 0x42aa6b VMOVUPD (%R13,%RAX,1),%ZMM15 |
(132) 0x42aa73 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(132) 0x42aa7a VADDPD (%R14,%RAX,1),%ZMM15,%ZMM0 |
(132) 0x42aa81 VADDPD (%RBX,%RAX,1),%ZMM7,%ZMM1 |
(132) 0x42aa88 VADDPD %ZMM1,%ZMM0,%ZMM5 |
(132) 0x42aa8e VMULPD %ZMM2,%ZMM5,%ZMM6 |
(132) 0x42aa94 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(132) 0x42aa9b ADD $0x40,%RAX |
(132) 0x42aa9f CMP %RAX,%R9 |
(132) 0x42aaa2 JE 42ab83 |
(133) 0x42aaa8 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(133) 0x42aab0 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(133) 0x42aab7 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM9 |
(133) 0x42aabe VADDPD (%RBX,%RAX,1),%ZMM10,%ZMM11 |
(133) 0x42aac5 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(133) 0x42aacb VMULPD %ZMM2,%ZMM12,%ZMM13 |
(133) 0x42aad1 VMOVUPD %ZMM13,(%R10,%RAX,1) |
(133) 0x42aad8 VMOVUPD 0x40(%R13,%RAX,1),%ZMM14 |
(133) 0x42aae0 VMOVUPD 0x40(%R11,%RAX,1),%ZMM0 |
(133) 0x42aae8 VADDPD 0x40(%R14,%RAX,1),%ZMM14,%ZMM15 |
(133) 0x42aaf0 VADDPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM7 |
(133) 0x42aaf8 VADDPD %ZMM7,%ZMM15,%ZMM1 |
(133) 0x42aafe VMULPD %ZMM2,%ZMM1,%ZMM5 |
(133) 0x42ab04 VMOVUPD %ZMM5,0x40(%R10,%RAX,1) |
(133) 0x42ab0c VMOVUPD 0x80(%R13,%RAX,1),%ZMM6 |
(133) 0x42ab14 VMOVUPD 0x80(%R11,%RAX,1),%ZMM9 |
(133) 0x42ab1c VADDPD 0x80(%R14,%RAX,1),%ZMM6,%ZMM8 |
(133) 0x42ab24 VADDPD 0x80(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(133) 0x42ab2c VADDPD %ZMM10,%ZMM8,%ZMM11 |
(133) 0x42ab32 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(133) 0x42ab38 VMOVUPD %ZMM12,0x80(%R10,%RAX,1) |
(133) 0x42ab40 VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 |
(133) 0x42ab48 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM15 |
(133) 0x42ab50 VADDPD 0xc0(%R14,%RAX,1),%ZMM13,%ZMM14 |
(133) 0x42ab58 VADDPD 0xc0(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(133) 0x42ab60 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(133) 0x42ab66 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(133) 0x42ab6c VMOVUPD %ZMM1,0xc0(%R10,%RAX,1) |
(133) 0x42ab74 ADD $0x100,%RAX |
(133) 0x42ab7a CMP %RAX,%R9 |
(133) 0x42ab7d JNE 42aaa8 |
(132) 0x42ab83 MOV 0x3c(%RSP),%EAX |
(132) 0x42ab87 MOV %EDX,%R14D |
(132) 0x42ab8a AND $-0x8,%R14D |
(132) 0x42ab8e ADD %R14D,%R12D |
(132) 0x42ab91 ADD %R14D,%EAX |
(132) 0x42ab94 TEST $0x7,%DL |
(132) 0x42ab97 JE 42acd1 |
(132) 0x42ab9d SUB %R14D,%EDX |
(132) 0x42aba0 LEA -0x1(%RDX),%R13D |
(132) 0x42aba4 CMP $0x2,%R13D |
(132) 0x42aba8 JBE 42ac00 |
(132) 0x42abaa MOVSXD 0x3c(%RSP),%R9 |
(132) 0x42abaf MOV 0x30(%RSP),%R10 |
(132) 0x42abb4 LEA (%RSI,%R9,1),%RBX |
(132) 0x42abb8 LEA (%RDI,%R9,1),%R11 |
(132) 0x42abbc ADD %R10,%R9 |
(132) 0x42abbf ADD %R14,%RBX |
(132) 0x42abc2 ADD %R14,%R11 |
(132) 0x42abc5 ADD %R14,%R9 |
(132) 0x42abc8 VMOVUPD 0x8(%RCX,%RBX,8),%YMM5 |
(132) 0x42abce VMOVUPD (%RCX,%R11,8),%YMM8 |
(132) 0x42abd4 VADDPD 0x8(%RCX,%R11,8),%YMM5,%YMM6 |
(132) 0x42abdb VADDPD (%RCX,%RBX,8),%YMM8,%YMM9 |
(132) 0x42abe0 VADDPD %YMM9,%YMM6,%YMM10 |
(132) 0x42abe5 VMULPD %YMM4,%YMM10,%YMM11 |
(132) 0x42abe9 VMOVUPD %YMM11,(%R15,%R9,8) |
(132) 0x42abef TEST $0x3,%DL |
(132) 0x42abf2 JE 42acd1 |
(132) 0x42abf8 AND $-0x4,%EDX |
(132) 0x42abfb ADD %EDX,%R12D |
(132) 0x42abfe ADD %EDX,%EAX |
(132) 0x42ac00 LEA 0x1(%RAX),%R14D |
(132) 0x42ac04 MOVSXD %EAX,%RDX |
(132) 0x42ac07 MOVSXD %R14D,%R8 |
(132) 0x42ac0a MOV 0x30(%RSP),%R14 |
(132) 0x42ac0f LEA (%R8,%RSI,1),%R13 |
(132) 0x42ac13 LEA (%R8,%RDI,1),%RBX |
(132) 0x42ac17 LEA (%RCX,%R13,8),%R9 |
(132) 0x42ac1b LEA (%RDI,%RDX,1),%R13 |
(132) 0x42ac1f VMOVSD (%RCX,%R13,8),%XMM12 |
(132) 0x42ac25 VMOVSD (%R9),%XMM14 |
(132) 0x42ac2a LEA (%R14,%RDX,1),%R11 |
(132) 0x42ac2e LEA (%RCX,%RBX,8),%R10 |
(132) 0x42ac32 ADD %RSI,%RDX |
(132) 0x42ac35 MOV 0x2c(%RSP),%R13D |
(132) 0x42ac3a VADDSD (%RCX,%RDX,8),%XMM12,%XMM13 |
(132) 0x42ac3f VADDSD (%R10),%XMM14,%XMM15 |
(132) 0x42ac44 LEA 0x1(%R12),%EDX |
(132) 0x42ac49 VADDSD %XMM15,%XMM13,%XMM0 |
(132) 0x42ac4e VMULSD %XMM3,%XMM0,%XMM7 |
(132) 0x42ac52 VMOVSD %XMM7,(%R15,%R11,8) |
(132) 0x42ac58 CMP %R13D,%EDX |
(132) 0x42ac5b JAE 42acd1 |
(132) 0x42ac5d LEA 0x2(%RAX),%EBX |
(132) 0x42ac60 VMOVSD (%R10),%XMM1 |
(132) 0x42ac65 ADD %R14,%R8 |
(132) 0x42ac68 ADD $0x2,%R12D |
(132) 0x42ac6c MOVSXD %EBX,%RDX |
(132) 0x42ac6f LEA (%RSI,%RDX,1),%R11 |
(132) 0x42ac73 VADDSD (%R9),%XMM1,%XMM5 |
(132) 0x42ac78 LEA (%RCX,%R11,8),%RBX |
(132) 0x42ac7c LEA (%RDI,%RDX,1),%R11 |
(132) 0x42ac80 LEA (%RCX,%R11,8),%R11 |
(132) 0x42ac84 VMOVSD (%R11),%XMM6 |
(132) 0x42ac89 VADDSD (%RBX),%XMM6,%XMM8 |
(132) 0x42ac8d VADDSD %XMM8,%XMM5,%XMM9 |
(132) 0x42ac92 VMULSD %XMM3,%XMM9,%XMM10 |
(132) 0x42ac96 VMOVSD %XMM10,(%R15,%R8,8) |
(132) 0x42ac9c CMP %R13D,%R12D |
(132) 0x42ac9f JAE 42acd1 |
(132) 0x42aca1 ADD $0x3,%EAX |
(132) 0x42aca4 VMOVSD (%RBX),%XMM13 |
(132) 0x42aca8 ADD %RDX,%R14 |
(132) 0x42acab CLTQ |
(132) 0x42acad ADD %RAX,%RSI |
(132) 0x42acb0 ADD %RDI,%RAX |
(132) 0x42acb3 VADDSD (%R11),%XMM13,%XMM14 |
(132) 0x42acb8 VMOVSD (%RCX,%RSI,8),%XMM11 |
(132) 0x42acbd VADDSD (%RCX,%RAX,8),%XMM11,%XMM12 |
(132) 0x42acc2 VADDSD %XMM14,%XMM12,%XMM15 |
(132) 0x42acc7 VMULSD %XMM3,%XMM15,%XMM0 |
(132) 0x42accb VMOVSD %XMM0,(%R15,%R14,8) |
(132) 0x42acd1 MOV 0x2c(%RSP),%R12D |
(132) 0x42acd6 INCL 0x38(%RSP) |
(132) 0x42acda INCQ 0x20(%RSP) |
(132) 0x42acdf MOV 0x38(%RSP),%ECX |
(132) 0x42ace3 CMP %ECX,0x1c(%RSP) |
(132) 0x42ace7 JLE 42ad08 |
(132) 0x42ace9 MOV 0x14(%RSP),%EDI |
(132) 0x42aced MOV 0x18(%RSP),%ESI |
(132) 0x42acf1 MOV 0x28(%RSP),%EDX |
(132) 0x42acf5 MOV %ESI,0x3c(%RSP) |
(132) 0x42acf9 SUB %R12D,%EDI |
(132) 0x42acfc JMP 42a950 |
0x42ad01 NOPL (%RAX) |
0x42ad08 VZEROUPPER |
0x42ad0b LEA -0x28(%RBP),%RSP |
0x42ad0f POP %RBX |
0x42ad10 POP %R12 |
0x42ad12 POP %R13 |
0x42ad14 POP %R14 |
0x42ad16 POP %R15 |
0x42ad18 POP %RBP |
0x42ad19 RET |
0x42ad1a NOPW (%RAX,%RAX,1) |
(132) 0x42ad20 MOV 0x3c(%RSP),%EAX |
(132) 0x42ad24 XOR %R14D,%R14D |
(132) 0x42ad27 JMP 42ab9d |
0x42ad2c INC %EDI |
0x42ad2e XOR %EDX,%EDX |
0x42ad30 JMP 42a8e4 |
0x42ad35 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ad0b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ad0b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42ad2c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42ad0b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x37fad(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42a8e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ad0b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ad0b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42ad2c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42ad0b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x37fad(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42a8e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4– | 0.97 | 0.72 |
▼Loop 132 - advec_mom.cpp:87-88 - exec– | 0.01 | 0 |
○Loop 133 - advec_mom.cpp:88-88 - exec | 0.96 | 0.72 |