Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.31% |
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Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.31% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 146 - 150 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
148: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
149: pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
150: post_vol(i, j) = volume(i, j); |
0x4275b0 PUSH %RBP |
0x4275b1 MOV %RSP,%RBP |
0x4275b4 PUSH %R15 |
0x4275b6 PUSH %R14 |
0x4275b8 PUSH %R13 |
0x4275ba PUSH %R12 |
0x4275bc PUSH %RBX |
0x4275bd AND $-0x40,%RSP |
0x4275c1 ADD $-0x80,%RSP |
0x4275c5 MOV 0x28(%RDI),%EAX |
0x4275c8 MOV 0x2c(%RDI),%EDX |
0x4275cb MOV 0x20(%RDI),%EBX |
0x4275ce MOV 0x24(%RDI),%ECX |
0x4275d1 ADD $0x4,%EDX |
0x4275d4 LEA -0x1(%RAX),%R15D |
0x4275d8 LEA -0x1(%RBX),%ESI |
0x4275db MOV %EDX,0x40(%RSP) |
0x4275df MOV %ESI,0x3c(%RSP) |
0x4275e3 CMP %EDX,%R15D |
0x4275e6 JGE 427ac3 |
0x4275ec MOV %EDX,%EBX |
0x4275ee LEA 0x4(%RCX),%R14D |
0x4275f2 SUB %R15D,%EBX |
0x4275f5 CMP %R14D,%ESI |
0x4275f8 JGE 427ac3 |
0x4275fe MOV %RDI,%R13 |
0x427601 MOV %R14D,%EDI |
0x427604 SUB %ESI,%EDI |
0x427606 MOV %EDI,0x44(%RSP) |
0x42760a CALL 4046c0 <omp_get_num_threads@plt> |
0x42760f MOV %EAX,%R12D |
0x427612 CALL 4045b0 <omp_get_thread_num@plt> |
0x427617 XOR %EDX,%EDX |
0x427619 MOV %EAX,%R8D |
0x42761c MOV 0x44(%RSP),%EAX |
0x427620 IMUL %EBX,%EAX |
0x427623 DIV %R12D |
0x427626 MOV %EAX,%EDI |
0x427628 CMP %EDX,%R8D |
0x42762b JB 427ae4 |
0x427631 IMUL %EDI,%R8D |
0x427635 LEA (%R8,%RDX,1),%EBX |
0x427639 LEA (%RDI,%RBX,1),%R9D |
0x42763d MOV %R9D,0x38(%RSP) |
0x427642 CMP %R9D,%EBX |
0x427645 JAE 427ac3 |
0x42764b XOR %EDX,%EDX |
0x42764d MOV %EBX,%EAX |
0x42764f MOV 0x3c(%RSP),%R10D |
0x427654 MOV 0x8(%R13),%RCX |
0x427658 DIVL 0x44(%RSP) |
0x42765c MOV %RCX,0x28(%RSP) |
0x427661 ADD %EDX,%R10D |
0x427664 MOV %R14D,%EDX |
0x427667 LEA (%RAX,%R15,1),%R11D |
0x42766b MOV 0x10(%R13),%R14 |
0x42766f SUB %R10D,%EDX |
0x427672 MOV (%R13),%R15 |
0x427676 MOV 0x18(%R13),%R13 |
0x42767a MOV %R10D,0x74(%RSP) |
0x42767f CMP %EDX,%EDI |
0x427681 MOV %R14,0x20(%RSP) |
0x427686 MOVSXD %R11D,%RCX |
0x427689 CMOVBE %EDI,%EDX |
0x42768c MOV %R15,0x30(%RSP) |
0x427691 MOV %R13,0x18(%RSP) |
0x427696 LEA (%RBX,%RDX,1),%ESI |
0x427699 MOV %ESI,0x70(%RSP) |
0x42769d CMP %ESI,%EBX |
0x42769f JAE 427aa3 |
0x4276a5 NOPL (%RAX) |
(116) 0x4276a8 MOV 0x28(%RSP),%R8 |
(116) 0x4276ad MOV 0x30(%RSP),%R12 |
(116) 0x4276b2 MOV 0x20(%RSP),%RAX |
(116) 0x4276b7 MOV 0x18(%RSP),%R13 |
(116) 0x4276bc MOV (%R8),%R9 |
(116) 0x4276bf MOV 0x10(%R8),%RSI |
(116) 0x4276c3 LEA 0x1(%RCX),%R8 |
(116) 0x4276c7 MOV (%R12),%R11 |
(116) 0x4276cb MOV 0x10(%R13),%RDI |
(116) 0x4276cf MOV %R8,0x48(%RSP) |
(116) 0x4276d4 IMUL %R9,%R8 |
(116) 0x4276d8 MOV 0x10(%R12),%R15 |
(116) 0x4276dd MOV 0x10(%RAX),%R14 |
(116) 0x4276e1 IMUL %RCX,%R11 |
(116) 0x4276e5 MOV %RDI,0x78(%RSP) |
(116) 0x4276ea MOV %R8,%R10 |
(116) 0x4276ed SUB %R9,%R10 |
(116) 0x4276f0 MOV (%RAX),%R9 |
(116) 0x4276f3 MOV %R11,0x50(%RSP) |
(116) 0x4276f8 MOV %R10,0x58(%RSP) |
(116) 0x4276fd IMUL %RCX,%R9 |
(116) 0x427701 IMUL (%R13),%RCX |
(116) 0x427706 MOV %R9,0x60(%RSP) |
(116) 0x42770b MOV %RCX,0x68(%RSP) |
(116) 0x427710 LEA -0x1(%RDX),%ECX |
(116) 0x427713 CMP $0x6,%ECX |
(116) 0x427716 JBE 427ad8 |
(116) 0x42771c MOVSXD 0x74(%RSP),%RAX |
(116) 0x427721 MOV 0x68(%RSP),%RDI |
(116) 0x427726 LEA (%R11,%RAX,1),%R11 |
(116) 0x42772a LEA (%R9,%RAX,1),%R9 |
(116) 0x42772e LEA (%R15,%R11,8),%RCX |
(116) 0x427732 LEA (%R14,%R9,8),%R11 |
(116) 0x427736 MOV %EDX,%R9D |
(116) 0x427739 SHR $0x3,%R9D |
(116) 0x42773d LEA (%R10,%RAX,1),%R10 |
(116) 0x427741 LEA (%R8,%RAX,1),%R13 |
(116) 0x427745 ADD %RDI,%RAX |
(116) 0x427748 SAL $0x6,%R9 |
(116) 0x42774c LEA (%RSI,%R10,8),%R12 |
(116) 0x427750 MOV 0x78(%RSP),%R10 |
(116) 0x427755 LEA (%RSI,%R13,8),%R13 |
(116) 0x427759 LEA -0x40(%R9),%RDI |
(116) 0x42775d SHR $0x6,%RDI |
(116) 0x427761 LEA (%R10,%RAX,8),%R10 |
(116) 0x427765 XOR %EAX,%EAX |
(116) 0x427767 INC %RDI |
(116) 0x42776a AND $0x3,%EDI |
(116) 0x42776d JE 427811 |
(116) 0x427773 CMP $0x1,%RDI |
(116) 0x427777 JE 4277d9 |
(116) 0x427779 CMP $0x2,%RDI |
(116) 0x42777d JE 4277aa |
(116) 0x42777f VMOVUPD (%R13),%ZMM6 |
(116) 0x427786 MOV $0x40,%EAX |
(116) 0x42778b VADDPD (%RCX),%ZMM6,%ZMM0 |
(116) 0x427791 VSUBPD (%R12),%ZMM0,%ZMM1 |
(116) 0x427798 VMOVUPD %ZMM1,(%R11) |
(116) 0x42779e VMOVUPD (%RCX),%ZMM7 |
(116) 0x4277a4 VMOVUPD %ZMM7,(%R10) |
(116) 0x4277aa VMOVUPD (%R13,%RAX,1),%ZMM2 |
(116) 0x4277b2 VADDPD (%RCX,%RAX,1),%ZMM2,%ZMM3 |
(116) 0x4277b9 VSUBPD (%R12,%RAX,1),%ZMM3,%ZMM4 |
(116) 0x4277c0 VMOVUPD %ZMM4,(%R11,%RAX,1) |
(116) 0x4277c7 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(116) 0x4277ce VMOVUPD %ZMM5,(%R10,%RAX,1) |
(116) 0x4277d5 ADD $0x40,%RAX |
(116) 0x4277d9 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(116) 0x4277e1 VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(116) 0x4277e8 VSUBPD (%R12,%RAX,1),%ZMM9,%ZMM10 |
(116) 0x4277ef VMOVUPD %ZMM10,(%R11,%RAX,1) |
(116) 0x4277f6 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(116) 0x4277fd VMOVUPD %ZMM11,(%R10,%RAX,1) |
(116) 0x427804 ADD $0x40,%RAX |
(116) 0x427808 CMP %RAX,%R9 |
(116) 0x42780b JE 4278db |
(117) 0x427811 VMOVUPD (%R13,%RAX,1),%ZMM12 |
(117) 0x427819 VADDPD (%RCX,%RAX,1),%ZMM12,%ZMM13 |
(117) 0x427820 VSUBPD (%R12,%RAX,1),%ZMM13,%ZMM14 |
(117) 0x427827 VMOVUPD %ZMM14,(%R11,%RAX,1) |
(117) 0x42782e VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(117) 0x427835 VMOVUPD %ZMM15,(%R10,%RAX,1) |
(117) 0x42783c VMOVUPD 0x40(%R13,%RAX,1),%ZMM6 |
(117) 0x427844 VADDPD 0x40(%RCX,%RAX,1),%ZMM6,%ZMM0 |
(117) 0x42784c VSUBPD 0x40(%R12,%RAX,1),%ZMM0,%ZMM1 |
(117) 0x427854 VMOVUPD %ZMM1,0x40(%R11,%RAX,1) |
(117) 0x42785c VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(117) 0x427864 VMOVUPD %ZMM7,0x40(%R10,%RAX,1) |
(117) 0x42786c VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 |
(117) 0x427874 VADDPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM3 |
(117) 0x42787c VSUBPD 0x80(%R12,%RAX,1),%ZMM3,%ZMM4 |
(117) 0x427884 VMOVUPD %ZMM4,0x80(%R11,%RAX,1) |
(117) 0x42788c VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(117) 0x427894 VMOVUPD %ZMM5,0x80(%R10,%RAX,1) |
(117) 0x42789c VMOVUPD 0xc0(%R13,%RAX,1),%ZMM8 |
(117) 0x4278a4 VADDPD 0xc0(%RCX,%RAX,1),%ZMM8,%ZMM9 |
(117) 0x4278ac VSUBPD 0xc0(%R12,%RAX,1),%ZMM9,%ZMM10 |
(117) 0x4278b4 VMOVUPD %ZMM10,0xc0(%R11,%RAX,1) |
(117) 0x4278bc VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(117) 0x4278c4 VMOVUPD %ZMM11,0xc0(%R10,%RAX,1) |
(117) 0x4278cc ADD $0x100,%RAX |
(117) 0x4278d2 CMP %RAX,%R9 |
(117) 0x4278d5 JNE 427811 |
(116) 0x4278db MOV 0x74(%RSP),%ECX |
(116) 0x4278df MOV %EDX,%R12D |
(116) 0x4278e2 AND $-0x8,%R12D |
(116) 0x4278e6 ADD %R12D,%EBX |
(116) 0x4278e9 LEA (%R12,%RCX,1),%EDI |
(116) 0x4278ed TEST $0x7,%DL |
(116) 0x4278f0 JE 427a6a |
(116) 0x4278f6 SUB %R12D,%EDX |
(116) 0x4278f9 LEA -0x1(%RDX),%R13D |
(116) 0x4278fd CMP $0x2,%R13D |
(116) 0x427901 JBE 427978 |
(116) 0x427903 MOVSXD 0x74(%RSP),%RAX |
(116) 0x427908 MOV 0x50(%RSP),%R11 |
(116) 0x42790d MOV 0x58(%RSP),%R13 |
(116) 0x427912 LEA (%R8,%RAX,1),%R9 |
(116) 0x427916 LEA (%R11,%RAX,1),%R10 |
(116) 0x42791a ADD %R12,%R9 |
(116) 0x42791d ADD %R12,%R10 |
(116) 0x427920 LEA (%R13,%RAX,1),%R11 |
(116) 0x427925 VMOVUPD (%RSI,%R9,8),%YMM12 |
(116) 0x42792b LEA (%R15,%R10,8),%RCX |
(116) 0x42792f ADD %R12,%R11 |
(116) 0x427932 MOV 0x60(%RSP),%R10 |
(116) 0x427937 VADDPD (%RCX),%YMM12,%YMM13 |
(116) 0x42793b LEA (%R10,%RAX,1),%R9 |
(116) 0x42793f ADD %R12,%R9 |
(116) 0x427942 VSUBPD (%RSI,%R11,8),%YMM13,%YMM14 |
(116) 0x427948 VMOVUPD %YMM14,(%R14,%R9,8) |
(116) 0x42794e VMOVUPD (%RCX),%YMM15 |
(116) 0x427952 MOV 0x68(%RSP),%RCX |
(116) 0x427957 ADD %RCX,%RAX |
(116) 0x42795a ADD %R12,%RAX |
(116) 0x42795d MOV 0x78(%RSP),%R12 |
(116) 0x427962 VMOVUPD %YMM15,(%R12,%RAX,8) |
(116) 0x427968 TEST $0x3,%DL |
(116) 0x42796b JE 427a6a |
(116) 0x427971 AND $-0x4,%EDX |
(116) 0x427974 ADD %EDX,%EBX |
(116) 0x427976 ADD %EDX,%EDI |
(116) 0x427978 MOVSXD %EDI,%RAX |
(116) 0x42797b MOV 0x50(%RSP),%R10 |
(116) 0x427980 MOV 0x58(%RSP),%R12 |
(116) 0x427985 LEA (%R8,%RAX,1),%R9 |
(116) 0x427989 MOV 0x60(%RSP),%R11 |
(116) 0x42798e VMOVSD (%RSI,%R9,8),%XMM6 |
(116) 0x427994 LEA (%R10,%RAX,1),%RDX |
(116) 0x427998 LEA 0x1(%RBX),%R9D |
(116) 0x42799c LEA (%R15,%RDX,8),%R13 |
(116) 0x4279a0 LEA (%R12,%RAX,1),%RDX |
(116) 0x4279a4 VADDSD (%R13),%XMM6,%XMM0 |
(116) 0x4279aa LEA (%R11,%RAX,1),%RCX |
(116) 0x4279ae VSUBSD (%RSI,%RDX,8),%XMM0,%XMM1 |
(116) 0x4279b3 MOV 0x70(%RSP),%EDX |
(116) 0x4279b7 VMOVSD %XMM1,(%R14,%RCX,8) |
(116) 0x4279bd MOV 0x78(%RSP),%RCX |
(116) 0x4279c2 VMOVSD (%R13),%XMM7 |
(116) 0x4279c8 MOV 0x68(%RSP),%R13 |
(116) 0x4279cd ADD %R13,%RAX |
(116) 0x4279d0 VMOVSD %XMM7,(%RCX,%RAX,8) |
(116) 0x4279d5 LEA 0x1(%RDI),%EAX |
(116) 0x4279d8 CMP %EDX,%R9D |
(116) 0x4279db JAE 427a6a |
(116) 0x4279e1 CLTQ |
(116) 0x4279e3 ADD $0x2,%EBX |
(116) 0x4279e6 ADD $0x2,%EDI |
(116) 0x4279e9 LEA (%R8,%RAX,1),%R9 |
(116) 0x4279ed LEA (%R10,%RAX,1),%RCX |
(116) 0x4279f1 VMOVSD (%RSI,%R9,8),%XMM2 |
(116) 0x4279f7 LEA (%R15,%RCX,8),%RDX |
(116) 0x4279fb LEA (%R12,%RAX,1),%R9 |
(116) 0x4279ff LEA (%R11,%RAX,1),%RCX |
(116) 0x427a03 ADD %R13,%RAX |
(116) 0x427a06 VADDSD (%RDX),%XMM2,%XMM3 |
(116) 0x427a0a VSUBSD (%RSI,%R9,8),%XMM3,%XMM4 |
(116) 0x427a10 MOV %R13,%R9 |
(116) 0x427a13 MOV 0x78(%RSP),%R13 |
(116) 0x427a18 VMOVSD %XMM4,(%R14,%RCX,8) |
(116) 0x427a1e VMOVSD (%RDX),%XMM5 |
(116) 0x427a22 VMOVSD %XMM5,(%R13,%RAX,8) |
(116) 0x427a29 MOV 0x70(%RSP),%EAX |
(116) 0x427a2d CMP %EAX,%EBX |
(116) 0x427a2f JAE 427a6a |
(116) 0x427a31 MOVSXD %EDI,%RBX |
(116) 0x427a34 ADD %RBX,%R8 |
(116) 0x427a37 ADD %RBX,%R10 |
(116) 0x427a3a ADD %RBX,%R12 |
(116) 0x427a3d ADD %RBX,%R11 |
(116) 0x427a40 VMOVSD (%RSI,%R8,8),%XMM8 |
(116) 0x427a46 LEA (%R15,%R10,8),%R15 |
(116) 0x427a4a ADD %RBX,%R9 |
(116) 0x427a4d VADDSD (%R15),%XMM8,%XMM9 |
(116) 0x427a52 VSUBSD (%RSI,%R12,8),%XMM9,%XMM10 |
(116) 0x427a58 VMOVSD %XMM10,(%R14,%R11,8) |
(116) 0x427a5e VMOVSD (%R15),%XMM11 |
(116) 0x427a63 VMOVSD %XMM11,(%R13,%R9,8) |
(116) 0x427a6a MOV 0x48(%RSP),%RCX |
(116) 0x427a6f MOV 0x70(%RSP),%EBX |
(116) 0x427a73 LEA (%RCX),%ESI |
(116) 0x427a75 CMP %ESI,0x40(%RSP) |
(116) 0x427a79 JLE 427ac0 |
(116) 0x427a7b MOV 0x38(%RSP),%EDI |
(116) 0x427a7f MOV 0x44(%RSP),%EDX |
(116) 0x427a83 MOV 0x3c(%RSP),%R8D |
(116) 0x427a88 SUB %EBX,%EDI |
(116) 0x427a8a CMP %EDX,%EDI |
(116) 0x427a8c MOV %R8D,0x74(%RSP) |
(116) 0x427a91 CMOVBE %EDI,%EDX |
(116) 0x427a94 LEA (%RBX,%RDX,1),%ESI |
(116) 0x427a97 MOV %ESI,0x70(%RSP) |
(116) 0x427a9b CMP %ESI,%EBX |
(116) 0x427a9d JB 4276a8 |
(118) 0x427aa3 LEA 0x1(%RCX),%RDI |
(118) 0x427aa7 MOV %RDI,0x48(%RSP) |
(118) 0x427aac MOV 0x48(%RSP),%RCX |
(118) 0x427ab1 LEA (%RCX),%ESI |
(118) 0x427ab3 CMP %ESI,0x40(%RSP) |
(118) 0x427ab7 JG 427a7b |
0x427ab9 NOPL (%RAX) |
0x427ac0 VZEROUPPER |
0x427ac3 LEA -0x28(%RBP),%RSP |
0x427ac7 POP %RBX |
0x427ac8 POP %R12 |
0x427aca POP %R13 |
0x427acc POP %R14 |
0x427ace POP %R15 |
0x427ad0 POP %RBP |
0x427ad1 RET |
0x427ad2 NOPW (%RAX,%RAX,1) |
(116) 0x427ad8 MOV 0x74(%RSP),%EDI |
(116) 0x427adc XOR %R12D,%R12D |
(116) 0x427adf JMP 4278f6 |
0x427ae4 INC %EDI |
0x427ae6 XOR %EDX,%EDX |
0x427ae8 JMP 427631 |
0x427aed NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 86 |
nb uops | 97 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
cycles | 7.20 | 12.33 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.54 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 12.33 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427ac3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427ac3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 427ae4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x534> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427ac3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RCX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMOVBE %EDI,%EDX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RDX,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ESI,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x4f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427631 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 86 |
nb uops | 97 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
cycles | 7.20 | 12.33 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.54 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 12.33 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427ac3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427ac3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 427ae4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x534> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427ac3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RCX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMOVBE %EDI,%EDX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RDX,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ESI,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x4f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427631 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0– | 1.31 | 0.98 |
▼Loop 118 - advec_cell.cpp:149-150 - exec– | 0 | 0 |
▼Loop 116 - advec_cell.cpp:149-150 - exec– | 0 | 0 |
○Loop 117 - advec_cell.cpp:149-150 - exec | 1.31 | 0.98 |