Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 4.48% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 4.48% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 146 - 149 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
148: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
149: vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42bfd0 PUSH %RBP |
0x42bfd1 MOV %RSP,%RBP |
0x42bfd4 PUSH %R15 |
0x42bfd6 PUSH %R14 |
0x42bfd8 PUSH %R13 |
0x42bfda PUSH %R12 |
0x42bfdc PUSH %RBX |
0x42bfdd AND $-0x40,%RSP |
0x42bfe1 ADD $-0x80,%RSP |
0x42bfe5 MOV 0x28(%RDI),%EAX |
0x42bfe8 MOV 0x2c(%RDI),%EDX |
0x42bfeb MOV 0x20(%RDI),%EBX |
0x42bfee MOV 0x24(%RDI),%ECX |
0x42bff1 ADD $0x3,%EDX |
0x42bff4 LEA 0x1(%RAX),%R15D |
0x42bff8 LEA 0x1(%RBX),%ESI |
0x42bffb MOV %EDX,0x44(%RSP) |
0x42bfff MOV %ESI,0x40(%RSP) |
0x42c003 CMP %EDX,%R15D |
0x42c006 JGE 42c4b3 |
0x42c00c MOV %EDX,%EBX |
0x42c00e LEA 0x3(%RCX),%R14D |
0x42c012 SUB %R15D,%EBX |
0x42c015 CMP %R14D,%ESI |
0x42c018 JGE 42c4b3 |
0x42c01e MOV %RDI,%R13 |
0x42c021 MOV %R14D,%EDI |
0x42c024 SUB %ESI,%EDI |
0x42c026 MOV %EDI,0x68(%RSP) |
0x42c02a CALL 4046c0 <omp_get_num_threads@plt> |
0x42c02f MOV %EAX,%R12D |
0x42c032 CALL 4045b0 <omp_get_thread_num@plt> |
0x42c037 XOR %EDX,%EDX |
0x42c039 MOV %EAX,%R8D |
0x42c03c MOV 0x68(%RSP),%EAX |
0x42c040 IMUL %EBX,%EAX |
0x42c043 DIV %R12D |
0x42c046 MOV %EAX,%EDI |
0x42c048 CMP %EDX,%R8D |
0x42c04b JB 42c4d2 |
0x42c051 IMUL %EDI,%R8D |
0x42c055 LEA (%R8,%RDX,1),%EBX |
0x42c059 LEA (%RDI,%RBX,1),%R9D |
0x42c05d MOV %R9D,0x3c(%RSP) |
0x42c062 CMP %R9D,%EBX |
0x42c065 JAE 42c4b3 |
0x42c06b MOV %EBX,%EAX |
0x42c06d XOR %EDX,%EDX |
0x42c06f MOV 0x40(%RSP),%ESI |
0x42c073 MOV (%R13),%R10 |
0x42c077 DIVL 0x68(%RSP) |
0x42c07b MOV 0x10(%R13),%R11 |
0x42c07f MOV %R10,0x30(%RSP) |
0x42c084 MOV %R11,0x28(%RSP) |
0x42c089 ADD %EDX,%ESI |
0x42c08b ADD %R15D,%EAX |
0x42c08e MOV %R14D,%EDX |
0x42c091 MOV 0x18(%R13),%R15 |
0x42c095 MOV 0x8(%R13),%R14 |
0x42c099 SUB %ESI,%EDX |
0x42c09b MOVSXD %EAX,%R12 |
0x42c09e MOV %R15,0x20(%RSP) |
0x42c0a3 MOV %R14,0x18(%RSP) |
0x42c0a8 NOPL (%RAX,%RAX,1) |
(139) 0x42c0b0 CMP %EDX,%EDI |
(139) 0x42c0b2 CMOVBE %EDI,%EDX |
(139) 0x42c0b5 LEA (%RBX,%RDX,1),%ECX |
(139) 0x42c0b8 MOV %ECX,0x6c(%RSP) |
(139) 0x42c0bc CMP %ECX,%EBX |
(139) 0x42c0be JAE 42c489 |
(139) 0x42c0c4 MOV 0x30(%RSP),%R13 |
(139) 0x42c0c9 MOV 0x28(%RSP),%RDI |
(139) 0x42c0ce MOV 0x18(%RSP),%RAX |
(139) 0x42c0d3 MOV 0x20(%RSP),%R9 |
(139) 0x42c0d8 MOV 0x10(%R13),%R14 |
(139) 0x42c0dc MOV (%R13),%RCX |
(139) 0x42c0e0 MOV (%RAX),%R10 |
(139) 0x42c0e3 MOV (%RDI),%R13 |
(139) 0x42c0e6 IMUL %R12,%RCX |
(139) 0x42c0ea MOV 0x10(%RDI),%R15 |
(139) 0x42c0ee MOV (%R9),%R11 |
(139) 0x42c0f1 LEA -0x1(%RDX),%EDI |
(139) 0x42c0f4 IMUL %R12,%R13 |
(139) 0x42c0f8 MOV 0x10(%R9),%R8 |
(139) 0x42c0fc MOV 0x10(%RAX),%R9 |
(139) 0x42c100 MOV %R14,0x50(%RSP) |
(139) 0x42c105 IMUL %R12,%R10 |
(139) 0x42c109 MOV %R15,0x70(%RSP) |
(139) 0x42c10e MOV %RCX,0x48(%RSP) |
(139) 0x42c113 IMUL %R12,%R11 |
(139) 0x42c117 MOV %R13,0x58(%RSP) |
(139) 0x42c11c MOV %R9,0x78(%RSP) |
(139) 0x42c121 MOV %R10,0x60(%RSP) |
(139) 0x42c126 CMP $0x6,%EDI |
(139) 0x42c129 JBE 42c4c8 |
(139) 0x42c12f MOVSXD %ESI,%RAX |
(139) 0x42c132 ADD %RAX,%R13 |
(139) 0x42c135 ADD %RAX,%RCX |
(139) 0x42c138 LEA (%R11,%RAX,1),%RDI |
(139) 0x42c13c ADD %R10,%RAX |
(139) 0x42c13f MOV %EDX,%R10D |
(139) 0x42c142 LEA (%R15,%R13,8),%R15 |
(139) 0x42c146 LEA (%R9,%RAX,8),%R13 |
(139) 0x42c14a SAL $0x3,%RDI |
(139) 0x42c14e SHR $0x3,%R10D |
(139) 0x42c152 LEA (%R14,%RCX,8),%RCX |
(139) 0x42c156 LEA -0x8(%R8,%RDI,1),%R14 |
(139) 0x42c15b XOR %EAX,%EAX |
(139) 0x42c15d SAL $0x6,%R10 |
(139) 0x42c161 ADD %R8,%RDI |
(139) 0x42c164 LEA -0x40(%R10),%R9 |
(139) 0x42c168 SHR $0x6,%R9 |
(139) 0x42c16c INC %R9 |
(139) 0x42c16f AND $0x3,%R9D |
(139) 0x42c173 JE 42c216 |
(139) 0x42c179 CMP $0x1,%R9 |
(139) 0x42c17d JE 42c1de |
(139) 0x42c17f CMP $0x2,%R9 |
(139) 0x42c183 JE 42c1af |
(139) 0x42c185 VMOVUPD (%R15),%ZMM0 |
(139) 0x42c18b VMOVUPD (%RDI),%ZMM3 |
(139) 0x42c191 MOV $0x40,%EAX |
(139) 0x42c196 VFMSUB132PD (%RCX),%ZMM3,%ZMM0 |
(139) 0x42c19c VADDPD (%R14),%ZMM0,%ZMM1 |
(139) 0x42c1a2 VDIVPD (%R13),%ZMM1,%ZMM2 |
(139) 0x42c1a9 VMOVUPD %ZMM2,(%RCX) |
(139) 0x42c1af VMOVUPD (%R15,%RAX,1),%ZMM4 |
(139) 0x42c1b6 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(139) 0x42c1bd VFMSUB132PD (%RCX,%RAX,1),%ZMM5,%ZMM4 |
(139) 0x42c1c4 VADDPD (%R14,%RAX,1),%ZMM4,%ZMM6 |
(139) 0x42c1cb VDIVPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(139) 0x42c1d3 VMOVUPD %ZMM7,(%RCX,%RAX,1) |
(139) 0x42c1da ADD $0x40,%RAX |
(139) 0x42c1de VMOVUPD (%R15,%RAX,1),%ZMM8 |
(139) 0x42c1e5 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(139) 0x42c1ec VFMSUB132PD (%RCX,%RAX,1),%ZMM9,%ZMM8 |
(139) 0x42c1f3 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM10 |
(139) 0x42c1fa VDIVPD (%R13,%RAX,1),%ZMM10,%ZMM11 |
(139) 0x42c202 VMOVUPD %ZMM11,(%RCX,%RAX,1) |
(139) 0x42c209 ADD $0x40,%RAX |
(139) 0x42c20d CMP %R10,%RAX |
(139) 0x42c210 JE 42c2e0 |
(140) 0x42c216 VMOVUPD (%R15,%RAX,1),%ZMM12 |
(140) 0x42c21d VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(140) 0x42c224 VFMSUB132PD (%RCX,%RAX,1),%ZMM13,%ZMM12 |
(140) 0x42c22b VADDPD (%R14,%RAX,1),%ZMM12,%ZMM14 |
(140) 0x42c232 VDIVPD (%R13,%RAX,1),%ZMM14,%ZMM15 |
(140) 0x42c23a VMOVUPD %ZMM15,(%RCX,%RAX,1) |
(140) 0x42c241 VMOVUPD 0x40(%R15,%RAX,1),%ZMM0 |
(140) 0x42c249 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM3 |
(140) 0x42c251 VFMSUB132PD 0x40(%RCX,%RAX,1),%ZMM3,%ZMM0 |
(140) 0x42c259 VADDPD 0x40(%R14,%RAX,1),%ZMM0,%ZMM1 |
(140) 0x42c261 VDIVPD 0x40(%R13,%RAX,1),%ZMM1,%ZMM2 |
(140) 0x42c269 VMOVUPD %ZMM2,0x40(%RCX,%RAX,1) |
(140) 0x42c271 VMOVUPD 0x80(%R15,%RAX,1),%ZMM5 |
(140) 0x42c279 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM4 |
(140) 0x42c281 VFMSUB132PD 0x80(%RCX,%RAX,1),%ZMM4,%ZMM5 |
(140) 0x42c289 VADDPD 0x80(%R14,%RAX,1),%ZMM5,%ZMM6 |
(140) 0x42c291 VDIVPD 0x80(%R13,%RAX,1),%ZMM6,%ZMM7 |
(140) 0x42c299 VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) |
(140) 0x42c2a1 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM8 |
(140) 0x42c2a9 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM9 |
(140) 0x42c2b1 VFMSUB132PD 0xc0(%RCX,%RAX,1),%ZMM9,%ZMM8 |
(140) 0x42c2b9 VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM10 |
(140) 0x42c2c1 VDIVPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(140) 0x42c2c9 VMOVUPD %ZMM11,0xc0(%RCX,%RAX,1) |
(140) 0x42c2d1 ADD $0x100,%RAX |
(140) 0x42c2d7 CMP %R10,%RAX |
(140) 0x42c2da JNE 42c216 |
(139) 0x42c2e0 MOV %EDX,%R13D |
(139) 0x42c2e3 AND $-0x8,%R13D |
(139) 0x42c2e7 ADD %R13D,%EBX |
(139) 0x42c2ea LEA (%R13,%RSI,1),%ECX |
(139) 0x42c2ef TEST $0x7,%DL |
(139) 0x42c2f2 JE 42c485 |
(139) 0x42c2f8 SUB %R13D,%EDX |
(139) 0x42c2fb LEA -0x1(%RDX),%R15D |
(139) 0x42c2ff CMP $0x2,%R15D |
(139) 0x42c303 JBE 42c378 |
(139) 0x42c305 MOV 0x48(%RSP),%RDI |
(139) 0x42c30a MOVSXD %ESI,%RSI |
(139) 0x42c30d MOV 0x50(%RSP),%R14 |
(139) 0x42c312 MOV 0x60(%RSP),%R9 |
(139) 0x42c317 MOV 0x58(%RSP),%RAX |
(139) 0x42c31c ADD %RSI,%RDI |
(139) 0x42c31f ADD %R13,%RDI |
(139) 0x42c322 LEA (%R9,%RSI,1),%R15 |
(139) 0x42c326 LEA (%R14,%RDI,8),%R10 |
(139) 0x42c32a LEA (%R11,%RSI,1),%RDI |
(139) 0x42c32e ADD %RAX,%RSI |
(139) 0x42c331 ADD %R13,%R15 |
(139) 0x42c334 ADD %R13,%RDI |
(139) 0x42c337 ADD %R13,%RSI |
(139) 0x42c33a VMOVUPD (%R10),%YMM12 |
(139) 0x42c33f MOV 0x70(%RSP),%R13 |
(139) 0x42c344 VMOVUPD -0x8(%R8,%RDI,8),%YMM13 |
(139) 0x42c34b VFMADD132PD (%R13,%RSI,8),%YMM13,%YMM12 |
(139) 0x42c352 MOV 0x78(%RSP),%RSI |
(139) 0x42c357 VSUBPD (%R8,%RDI,8),%YMM12,%YMM14 |
(139) 0x42c35d VDIVPD (%RSI,%R15,8),%YMM14,%YMM15 |
(139) 0x42c363 VMOVUPD %YMM15,(%R10) |
(139) 0x42c368 TEST $0x3,%DL |
(139) 0x42c36b JE 42c485 |
(139) 0x42c371 AND $-0x4,%EDX |
(139) 0x42c374 ADD %EDX,%EBX |
(139) 0x42c376 ADD %EDX,%ECX |
(139) 0x42c378 MOV 0x48(%RSP),%R15 |
(139) 0x42c37d MOVSXD %ECX,%RAX |
(139) 0x42c380 MOV 0x50(%RSP),%R14 |
(139) 0x42c385 LEA -0x1(%RCX),%R10D |
(139) 0x42c389 MOV 0x58(%RSP),%R9 |
(139) 0x42c38e MOVSXD %R10D,%R13 |
(139) 0x42c391 MOV 0x60(%RSP),%R10 |
(139) 0x42c396 LEA (%R15,%RAX,1),%RDX |
(139) 0x42c39a ADD %R11,%R13 |
(139) 0x42c39d LEA (%R14,%RDX,8),%RSI |
(139) 0x42c3a1 MOV 0x70(%RSP),%RDX |
(139) 0x42c3a6 LEA (%R9,%RAX,1),%RDI |
(139) 0x42c3aa VMOVSD (%R8,%R13,8),%XMM3 |
(139) 0x42c3b0 MOV 0x78(%RSP),%R13 |
(139) 0x42c3b5 VMOVSD (%RDX,%RDI,8),%XMM0 |
(139) 0x42c3ba LEA (%R11,%RAX,1),%RDI |
(139) 0x42c3be ADD %R10,%RAX |
(139) 0x42c3c1 LEA (%R8,%RDI,8),%RDX |
(139) 0x42c3c5 MOV 0x6c(%RSP),%EDI |
(139) 0x42c3c9 VFMADD132SD (%RSI),%XMM3,%XMM0 |
(139) 0x42c3ce VSUBSD (%RDX),%XMM0,%XMM1 |
(139) 0x42c3d2 VDIVSD (%R13,%RAX,8),%XMM1,%XMM2 |
(139) 0x42c3d9 VMOVSD %XMM2,(%RSI) |
(139) 0x42c3dd LEA 0x1(%RBX),%ESI |
(139) 0x42c3e0 LEA 0x1(%RCX),%EAX |
(139) 0x42c3e3 CMP %EDI,%ESI |
(139) 0x42c3e5 JAE 42c485 |
(139) 0x42c3eb CLTQ |
(139) 0x42c3ed MOV %R14,%R13 |
(139) 0x42c3f0 ADD $0x2,%EBX |
(139) 0x42c3f3 ADD $0x2,%ECX |
(139) 0x42c3f6 LEA (%R15,%RAX,1),%RSI |
(139) 0x42c3fa LEA (%R14,%RSI,8),%RSI |
(139) 0x42c3fe LEA (%R11,%RAX,1),%R14 |
(139) 0x42c402 LEA (%R8,%R14,8),%RDI |
(139) 0x42c406 MOV %R9,%R14 |
(139) 0x42c409 LEA (%R9,%RAX,1),%R9 |
(139) 0x42c40d ADD %R10,%RAX |
(139) 0x42c410 MOV %RDI,0x60(%RSP) |
(139) 0x42c415 MOV 0x70(%RSP),%RDI |
(139) 0x42c41a VMOVSD (%RDI,%R9,8),%XMM5 |
(139) 0x42c420 MOV 0x60(%RSP),%R9 |
(139) 0x42c425 VMOVSD (%R9),%XMM4 |
(139) 0x42c42a MOV %R10,%R9 |
(139) 0x42c42d MOV 0x78(%RSP),%R10 |
(139) 0x42c432 VFMSUB132SD (%RSI),%XMM4,%XMM5 |
(139) 0x42c437 VADDSD (%RDX),%XMM5,%XMM6 |
(139) 0x42c43b MOV 0x6c(%RSP),%EDX |
(139) 0x42c43f VDIVSD (%R10,%RAX,8),%XMM6,%XMM7 |
(139) 0x42c445 VMOVSD %XMM7,(%RSI) |
(139) 0x42c449 CMP %EDX,%EBX |
(139) 0x42c44b JAE 42c485 |
(139) 0x42c44d MOVSXD %ECX,%RCX |
(139) 0x42c450 MOV 0x60(%RSP),%RBX |
(139) 0x42c455 ADD %RCX,%R14 |
(139) 0x42c458 ADD %RCX,%R11 |
(139) 0x42c45b ADD %RCX,%R15 |
(139) 0x42c45e ADD %RCX,%R9 |
(139) 0x42c461 VMOVSD (%RDI,%R14,8),%XMM8 |
(139) 0x42c467 VMOVSD (%R8,%R11,8),%XMM9 |
(139) 0x42c46d LEA (%R13,%R15,8),%RAX |
(139) 0x42c472 VFMSUB132SD (%RAX),%XMM9,%XMM8 |
(139) 0x42c477 VADDSD (%RBX),%XMM8,%XMM10 |
(139) 0x42c47b VDIVSD (%R10,%R9,8),%XMM10,%XMM11 |
(139) 0x42c481 VMOVSD %XMM11,(%RAX) |
(139) 0x42c485 MOV 0x6c(%RSP),%EBX |
(139) 0x42c489 INC %R12 |
(139) 0x42c48c LEA (%R12),%R8D |
(139) 0x42c490 CMP %R8D,0x44(%RSP) |
(139) 0x42c495 JLE 42c4b0 |
(139) 0x42c497 MOV 0x3c(%RSP),%EDI |
(139) 0x42c49b MOV 0x68(%RSP),%EDX |
(139) 0x42c49f MOV 0x40(%RSP),%ESI |
(139) 0x42c4a3 SUB %EBX,%EDI |
(139) 0x42c4a5 JMP 42c0b0 |
0x42c4aa NOPW (%RAX,%RAX,1) |
0x42c4b0 VZEROUPPER |
0x42c4b3 LEA -0x28(%RBP),%RSP |
0x42c4b7 POP %RBX |
0x42c4b8 POP %R12 |
0x42c4ba POP %R13 |
0x42c4bc POP %R14 |
0x42c4be POP %R15 |
0x42c4c0 POP %RBP |
0x42c4c1 RET |
0x42c4c2 NOPW (%RAX,%RAX,1) |
(139) 0x42c4c8 MOV %ESI,%ECX |
(139) 0x42c4ca XOR %R13D,%R13D |
(139) 0x42c4cd JMP 42c2f8 |
0x42c4d2 INC %EDI |
0x42c4d4 XOR %EDX,%EDX |
0x42c4d6 JMP 42c051 |
0x42c4db NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.18 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c4b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c4b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x68(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42c4d2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x502> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42c4b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x68(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c051 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.18 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c4b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c4b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x68(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42c4d2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x502> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42c4b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x68(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c051 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7– | 4.48 | 3.35 |
▼Loop 139 - advec_mom.cpp:149-149 - exec– | 0 | 0 |
○Loop 140 - advec_mom.cpp:149-149 - exec | 4.48 | 3.35 |