Function: _Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0 | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.04% |
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Function: _Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0 | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.04% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 74 - 80 |
-------------------------------------------------------------------------------- |
74: #pragma omp parallel for simd collapse(2) |
75: for (int j = (0); j < (yrange); j++) { |
76: for (int i = (0); i < (xrange); i++) { |
77: field.energy0(i, j) = state_energy[0]; |
78: field.density0(i, j) = state_density[0]; |
79: field.xvel0(i, j) = state_xvel[0]; |
80: field.yvel0(i, j) = state_yvel[0]; |
0x439ee0 PUSH %RBP |
0x439ee1 MOV %RSP,%RBP |
0x439ee4 PUSH %R15 |
0x439ee6 PUSH %R14 |
0x439ee8 PUSH %R13 |
0x439eea PUSH %R12 |
0x439eec PUSH %RBX |
0x439eed AND $-0x40,%RSP |
0x439ef1 ADD $-0x80,%RSP |
0x439ef5 MOV 0x2c(%RDI),%R14D |
0x439ef9 MOV 0x28(%RDI),%R15D |
0x439efd MOV %R14D,0x48(%RSP) |
0x439f02 MOV %R15D,0x2c(%RSP) |
0x439f07 TEST %R14D,%R14D |
0x439f0a JLE 43a47b |
0x439f10 TEST %R15D,%R15D |
0x439f13 JLE 43a47b |
0x439f19 MOV %RDI,%RBX |
0x439f1c CALL 4046c0 <omp_get_num_threads@plt> |
0x439f21 MOV %EAX,%R12D |
0x439f24 CALL 4045b0 <omp_get_thread_num@plt> |
0x439f29 XOR %EDX,%EDX |
0x439f2b MOV %EAX,%ESI |
0x439f2d MOV %R14D,%EAX |
0x439f30 IMUL %R15D,%EAX |
0x439f34 DIV %R12D |
0x439f37 MOV %EAX,%R12D |
0x439f3a CMP %EDX,%ESI |
0x439f3c JB 43a49d |
0x439f42 IMUL %R12D,%ESI |
0x439f46 LEA (%RSI,%RDX,1),%R14D |
0x439f4a LEA (%R12,%R14,1),%EDI |
0x439f4e MOV %EDI,0x28(%RSP) |
0x439f52 CMP %EDI,%R14D |
0x439f55 JAE 43a47b |
0x439f5b MOV 0x2c(%RSP),%R8D |
0x439f60 MOV %R14D,%EAX |
0x439f63 XOR %EDX,%EDX |
0x439f65 MOV 0x8(%RBX),%R9 |
0x439f69 MOV (%RBX),%R10 |
0x439f6c MOV 0x10(%RBX),%R11 |
0x439f70 DIV %R8D |
0x439f73 MOV 0x18(%RBX),%R15 |
0x439f77 MOV 0x20(%RBX),%R13 |
0x439f7b MOV %R9,0x20(%RSP) |
0x439f80 MOV %R10,0x18(%RSP) |
0x439f85 MOV %R11,0x10(%RSP) |
0x439f8a MOV %R15,0x8(%RSP) |
0x439f8f MOV %EDX,0x60(%RSP) |
0x439f93 SUB %EDX,%R8D |
0x439f96 MOVSXD %EAX,%RBX |
0x439f99 NOPL (%RAX) |
(207) 0x439fa0 CMP %R8D,%R12D |
(207) 0x439fa3 CMOVBE %R12D,%R8D |
(207) 0x439fa7 LEA (%R14,%R8,1),%ECX |
(207) 0x439fab MOV %R8D,0x64(%RSP) |
(207) 0x439fb0 MOV %ECX,0x4c(%RSP) |
(207) 0x439fb4 CMP %ECX,%R14D |
(207) 0x439fb7 JAE 43a44f |
(207) 0x439fbd MOV 0x18(%RSP),%RSI |
(207) 0x439fc2 MOV 0x10(%RSP),%R9 |
(207) 0x439fc7 MOV 0xb8(%R13),%R11 |
(207) 0x439fce MOV 0x10(%R13),%RAX |
(207) 0x439fd2 MOV 0x8(%RSP),%R15 |
(207) 0x439fd7 MOV 0x30(%R13),%RDX |
(207) 0x439fdb MOV 0x8(%RSI),%RDI |
(207) 0x439fdf MOV (%R13),%R10 |
(207) 0x439fe3 MOV %R11,0x70(%RSP) |
(207) 0x439fe8 MOV 0x8(%R9),%RSI |
(207) 0x439fec MOV 0xa8(%R13),%R11 |
(207) 0x439ff3 IMUL %RBX,%RDX |
(207) 0x439ff7 MOV %RAX,0x68(%RSP) |
(207) 0x439ffc MOV 0xd8(%R13),%R9 |
(207) 0x43a003 MOV 0x20(%RSP),%R12 |
(207) 0x43a008 IMUL %RBX,%R10 |
(207) 0x43a00c MOV 0xe8(%R13),%RAX |
(207) 0x43a013 IMUL %RBX,%R11 |
(207) 0x43a017 MOV 0x8(%R15),%RCX |
(207) 0x43a01b IMUL %RBX,%R9 |
(207) 0x43a01f MOV 0x64(%RSP),%R15D |
(207) 0x43a024 MOV 0x8(%R12),%R8 |
(207) 0x43a029 MOV %RDX,0x30(%RSP) |
(207) 0x43a02e MOV 0x40(%R13),%R12 |
(207) 0x43a032 MOV %RAX,0x78(%RSP) |
(207) 0x43a037 LEA -0x1(%R15),%EAX |
(207) 0x43a03b MOV %R10,0x38(%RSP) |
(207) 0x43a040 MOV %R12,0x50(%RSP) |
(207) 0x43a045 MOV %R11,0x40(%RSP) |
(207) 0x43a04a MOV %R9,0x58(%RSP) |
(207) 0x43a04f CMP $0x6,%EAX |
(207) 0x43a052 JBE 43a490 |
(207) 0x43a058 MOVSXD 0x60(%RSP),%RAX |
(207) 0x43a05d LEA (%R10,%RAX,1),%R9 |
(207) 0x43a061 MOV 0x68(%RSP),%R10 |
(207) 0x43a066 LEA (%RDX,%RAX,1),%RDX |
(207) 0x43a06a LEA (%R12,%RDX,8),%R15 |
(207) 0x43a06e MOV 0x70(%RSP),%RDX |
(207) 0x43a073 LEA (%R11,%RAX,1),%R11 |
(207) 0x43a077 LEA (%R10,%R9,8),%R12 |
(207) 0x43a07b MOV 0x58(%RSP),%R9 |
(207) 0x43a080 MOV 0x78(%RSP),%R10 |
(207) 0x43a085 LEA (%RDX,%R11,8),%RDX |
(207) 0x43a089 ADD %R9,%RAX |
(207) 0x43a08c LEA (%R10,%RAX,8),%R11 |
(207) 0x43a090 MOV 0x64(%RSP),%R10D |
(207) 0x43a095 XOR %EAX,%EAX |
(207) 0x43a097 SHR $0x3,%R10D |
(207) 0x43a09b SAL $0x6,%R10 |
(207) 0x43a09f LEA -0x40(%R10),%R9 |
(207) 0x43a0a3 SHR $0x6,%R9 |
(207) 0x43a0a7 INC %R9 |
(207) 0x43a0aa AND $0x3,%R9D |
(207) 0x43a0ae JE 43a16f |
(207) 0x43a0b4 CMP $0x1,%R9 |
(207) 0x43a0b8 JE 43a12e |
(207) 0x43a0ba CMP $0x2,%R9 |
(207) 0x43a0be JE 43a0f6 |
(207) 0x43a0c0 VBROADCASTSD (%R8),%ZMM0 |
(207) 0x43a0c6 MOV $0x40,%EAX |
(207) 0x43a0cb VMOVUPD %ZMM0,(%R15) |
(207) 0x43a0d1 VBROADCASTSD (%RDI),%ZMM1 |
(207) 0x43a0d7 VMOVUPD %ZMM1,(%R12) |
(207) 0x43a0de VBROADCASTSD (%RSI),%ZMM2 |
(207) 0x43a0e4 VMOVUPD %ZMM2,(%RDX) |
(207) 0x43a0ea VBROADCASTSD (%RCX),%ZMM3 |
(207) 0x43a0f0 VMOVUPD %ZMM3,(%R11) |
(207) 0x43a0f6 VBROADCASTSD (%R8),%ZMM4 |
(207) 0x43a0fc VMOVUPD %ZMM4,(%R15,%RAX,1) |
(207) 0x43a103 VBROADCASTSD (%RDI),%ZMM5 |
(207) 0x43a109 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(207) 0x43a110 VBROADCASTSD (%RSI),%ZMM6 |
(207) 0x43a116 VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(207) 0x43a11d VBROADCASTSD (%RCX),%ZMM7 |
(207) 0x43a123 VMOVUPD %ZMM7,(%R11,%RAX,1) |
(207) 0x43a12a ADD $0x40,%RAX |
(207) 0x43a12e VBROADCASTSD (%R8),%ZMM8 |
(207) 0x43a134 VMOVUPD %ZMM8,(%R15,%RAX,1) |
(207) 0x43a13b VBROADCASTSD (%RDI),%ZMM9 |
(207) 0x43a141 VMOVUPD %ZMM9,(%R12,%RAX,1) |
(207) 0x43a148 VBROADCASTSD (%RSI),%ZMM10 |
(207) 0x43a14e VMOVUPD %ZMM10,(%RDX,%RAX,1) |
(207) 0x43a155 VBROADCASTSD (%RCX),%ZMM11 |
(207) 0x43a15b VMOVUPD %ZMM11,(%R11,%RAX,1) |
(207) 0x43a162 ADD $0x40,%RAX |
(207) 0x43a166 CMP %RAX,%R10 |
(207) 0x43a169 JE 43a25a |
(208) 0x43a16f VBROADCASTSD (%R8),%ZMM12 |
(208) 0x43a175 VMOVUPD %ZMM12,(%R15,%RAX,1) |
(208) 0x43a17c VBROADCASTSD (%RDI),%ZMM13 |
(208) 0x43a182 VMOVUPD %ZMM13,(%R12,%RAX,1) |
(208) 0x43a189 VBROADCASTSD (%RSI),%ZMM14 |
(208) 0x43a18f VMOVUPD %ZMM14,(%RDX,%RAX,1) |
(208) 0x43a196 VBROADCASTSD (%RCX),%ZMM15 |
(208) 0x43a19c VMOVUPD %ZMM15,(%R11,%RAX,1) |
(208) 0x43a1a3 VBROADCASTSD (%R8),%ZMM0 |
(208) 0x43a1a9 VMOVUPD %ZMM0,0x40(%R15,%RAX,1) |
(208) 0x43a1b1 VBROADCASTSD (%RDI),%ZMM1 |
(208) 0x43a1b7 VMOVUPD %ZMM1,0x40(%R12,%RAX,1) |
(208) 0x43a1bf VBROADCASTSD (%RSI),%ZMM2 |
(208) 0x43a1c5 VMOVUPD %ZMM2,0x40(%RDX,%RAX,1) |
(208) 0x43a1cd VBROADCASTSD (%RCX),%ZMM3 |
(208) 0x43a1d3 VMOVUPD %ZMM3,0x40(%R11,%RAX,1) |
(208) 0x43a1db VBROADCASTSD (%R8),%ZMM4 |
(208) 0x43a1e1 VMOVUPD %ZMM4,0x80(%R15,%RAX,1) |
(208) 0x43a1e9 VBROADCASTSD (%RDI),%ZMM5 |
(208) 0x43a1ef VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(208) 0x43a1f7 VBROADCASTSD (%RSI),%ZMM6 |
(208) 0x43a1fd VMOVUPD %ZMM6,0x80(%RDX,%RAX,1) |
(208) 0x43a205 VBROADCASTSD (%RCX),%ZMM7 |
(208) 0x43a20b VMOVUPD %ZMM7,0x80(%R11,%RAX,1) |
(208) 0x43a213 VBROADCASTSD (%R8),%ZMM8 |
(208) 0x43a219 VMOVUPD %ZMM8,0xc0(%R15,%RAX,1) |
(208) 0x43a221 VBROADCASTSD (%RDI),%ZMM9 |
(208) 0x43a227 VMOVUPD %ZMM9,0xc0(%R12,%RAX,1) |
(208) 0x43a22f VBROADCASTSD (%RSI),%ZMM10 |
(208) 0x43a235 VMOVUPD %ZMM10,0xc0(%RDX,%RAX,1) |
(208) 0x43a23d VBROADCASTSD (%RCX),%ZMM11 |
(208) 0x43a243 VMOVUPD %ZMM11,0xc0(%R11,%RAX,1) |
(208) 0x43a24b ADD $0x100,%RAX |
(208) 0x43a251 CMP %RAX,%R10 |
(208) 0x43a254 JNE 43a16f |
(207) 0x43a25a MOV 0x64(%RSP),%R15D |
(207) 0x43a25f MOV 0x60(%RSP),%EDX |
(207) 0x43a263 MOV %R15D,%R12D |
(207) 0x43a266 AND $-0x8,%R12D |
(207) 0x43a26a ADD %R12D,%R14D |
(207) 0x43a26d LEA (%R12,%RDX,1),%R10D |
(207) 0x43a271 TEST $0x7,%R15B |
(207) 0x43a275 JE 43a44a |
(207) 0x43a27b MOV 0x64(%RSP),%EDX |
(207) 0x43a27f SUB %R12D,%EDX |
(207) 0x43a282 LEA -0x1(%RDX),%R11D |
(207) 0x43a286 CMP $0x2,%R11D |
(207) 0x43a28a JBE 43a322 |
(207) 0x43a290 MOVSXD 0x60(%RSP),%RAX |
(207) 0x43a295 MOV 0x30(%RSP),%R9 |
(207) 0x43a29a VBROADCASTSD (%R8),%YMM15 |
(207) 0x43a29f MOV 0x50(%RSP),%R15 |
(207) 0x43a2a4 LEA (%R9,%RAX,1),%R11 |
(207) 0x43a2a8 MOV 0x38(%RSP),%R9 |
(207) 0x43a2ad VMOVSD (%RDI),%XMM12 |
(207) 0x43a2b1 ADD %R12,%R11 |
(207) 0x43a2b4 VMOVSD (%RSI),%XMM13 |
(207) 0x43a2b8 VMOVSD (%RCX),%XMM14 |
(207) 0x43a2bc VMOVUPD %YMM15,(%R15,%R11,8) |
(207) 0x43a2c2 LEA (%R9,%RAX,1),%R11 |
(207) 0x43a2c6 MOV 0x68(%RSP),%R15 |
(207) 0x43a2cb MOV 0x40(%RSP),%R9 |
(207) 0x43a2d0 VBROADCASTSD %XMM12,%YMM0 |
(207) 0x43a2d5 VBROADCASTSD %XMM13,%YMM1 |
(207) 0x43a2da VBROADCASTSD %XMM14,%YMM2 |
(207) 0x43a2df ADD %R12,%R11 |
(207) 0x43a2e2 VMOVUPD %YMM0,(%R15,%R11,8) |
(207) 0x43a2e8 LEA (%R9,%RAX,1),%R11 |
(207) 0x43a2ec MOV 0x58(%RSP),%R9 |
(207) 0x43a2f1 MOV 0x70(%RSP),%R15 |
(207) 0x43a2f6 ADD %R12,%R11 |
(207) 0x43a2f9 ADD %R9,%RAX |
(207) 0x43a2fc VMOVUPD %YMM1,(%R15,%R11,8) |
(207) 0x43a302 ADD %R12,%RAX |
(207) 0x43a305 MOV 0x78(%RSP),%R12 |
(207) 0x43a30a VMOVUPD %YMM2,(%R12,%RAX,8) |
(207) 0x43a310 TEST $0x3,%DL |
(207) 0x43a313 JE 43a44a |
(207) 0x43a319 AND $-0x4,%EDX |
(207) 0x43a31c ADD %EDX,%R14D |
(207) 0x43a31f ADD %EDX,%R10D |
(207) 0x43a322 MOV 0x30(%RSP),%R9 |
(207) 0x43a327 VMOVSD (%R8),%XMM3 |
(207) 0x43a32c MOVSXD %R10D,%RAX |
(207) 0x43a32f MOV 0x50(%RSP),%R11 |
(207) 0x43a334 MOV 0x38(%RSP),%R15 |
(207) 0x43a339 LEA (%R9,%RAX,1),%RDX |
(207) 0x43a33d VMOVSD %XMM3,(%R11,%RDX,8) |
(207) 0x43a343 MOV 0x68(%RSP),%RDX |
(207) 0x43a348 LEA (%R15,%RAX,1),%R12 |
(207) 0x43a34c MOV 0x40(%RSP),%R11 |
(207) 0x43a351 VMOVSD (%RDI),%XMM4 |
(207) 0x43a355 VMOVSD %XMM4,(%RDX,%R12,8) |
(207) 0x43a35b MOV 0x70(%RSP),%R12 |
(207) 0x43a360 LEA (%R11,%RAX,1),%RDX |
(207) 0x43a364 VMOVSD (%RSI),%XMM5 |
(207) 0x43a368 VMOVSD %XMM5,(%R12,%RDX,8) |
(207) 0x43a36e MOV 0x58(%RSP),%RDX |
(207) 0x43a373 MOV 0x78(%RSP),%R12 |
(207) 0x43a378 VMOVSD (%RCX),%XMM6 |
(207) 0x43a37c ADD %RDX,%RAX |
(207) 0x43a37f LEA 0x1(%R14),%EDX |
(207) 0x43a383 VMOVSD %XMM6,(%R12,%RAX,8) |
(207) 0x43a389 MOV 0x4c(%RSP),%R12D |
(207) 0x43a38e LEA 0x1(%R10),%EAX |
(207) 0x43a392 CMP %R12D,%EDX |
(207) 0x43a395 JAE 43a44a |
(207) 0x43a39b VMOVSD (%R8),%XMM7 |
(207) 0x43a3a0 CLTQ |
(207) 0x43a3a2 MOV 0x50(%RSP),%R12 |
(207) 0x43a3a7 ADD $0x2,%R14D |
(207) 0x43a3ab LEA (%R9,%RAX,1),%RDX |
(207) 0x43a3af ADD $0x2,%R10D |
(207) 0x43a3b3 VMOVSD %XMM7,(%R12,%RDX,8) |
(207) 0x43a3b9 MOV 0x68(%RSP),%R12 |
(207) 0x43a3be LEA (%R15,%RAX,1),%RDX |
(207) 0x43a3c2 VMOVSD (%RDI),%XMM8 |
(207) 0x43a3c6 VMOVSD %XMM8,(%R12,%RDX,8) |
(207) 0x43a3cc MOV 0x70(%RSP),%R12 |
(207) 0x43a3d1 LEA (%R11,%RAX,1),%RDX |
(207) 0x43a3d5 VMOVSD (%RSI),%XMM9 |
(207) 0x43a3d9 VMOVSD %XMM9,(%R12,%RDX,8) |
(207) 0x43a3df MOV 0x58(%RSP),%RDX |
(207) 0x43a3e4 MOV 0x78(%RSP),%R12 |
(207) 0x43a3e9 VMOVSD (%RCX),%XMM10 |
(207) 0x43a3ed ADD %RDX,%RAX |
(207) 0x43a3f0 VMOVSD %XMM10,(%R12,%RAX,8) |
(207) 0x43a3f6 MOV 0x4c(%RSP),%EAX |
(207) 0x43a3fa CMP %EAX,%R14D |
(207) 0x43a3fd JAE 43a44a |
(207) 0x43a3ff VMOVSD (%R8),%XMM11 |
(207) 0x43a404 MOVSXD %R10D,%R14 |
(207) 0x43a407 MOV 0x50(%RSP),%R8 |
(207) 0x43a40c ADD %R14,%R9 |
(207) 0x43a40f ADD %R14,%R15 |
(207) 0x43a412 ADD %R14,%R11 |
(207) 0x43a415 ADD %R14,%RDX |
(207) 0x43a418 VMOVSD %XMM11,(%R8,%R9,8) |
(207) 0x43a41e VMOVSD (%RDI),%XMM12 |
(207) 0x43a422 MOV 0x68(%RSP),%RDI |
(207) 0x43a427 VMOVSD %XMM12,(%RDI,%R15,8) |
(207) 0x43a42d VMOVSD (%RSI),%XMM13 |
(207) 0x43a431 MOV 0x70(%RSP),%RSI |
(207) 0x43a436 VMOVSD %XMM13,(%RSI,%R11,8) |
(207) 0x43a43c VMOVSD (%RCX),%XMM14 |
(207) 0x43a440 MOV 0x78(%RSP),%RCX |
(207) 0x43a445 VMOVSD %XMM14,(%RCX,%RDX,8) |
(207) 0x43a44a MOV 0x4c(%RSP),%R14D |
(207) 0x43a44f INC %RBX |
(207) 0x43a452 CMP %EBX,0x48(%RSP) |
(207) 0x43a456 JLE 43a478 |
(207) 0x43a458 MOV 0x28(%RSP),%R12D |
(207) 0x43a45d MOV 0x2c(%RSP),%R8D |
(207) 0x43a462 MOVL $0,0x60(%RSP) |
(207) 0x43a46a SUB %R14D,%R12D |
(207) 0x43a46d JMP 439fa0 |
0x43a472 NOPW (%RAX,%RAX,1) |
0x43a478 VZEROUPPER |
0x43a47b LEA -0x28(%RBP),%RSP |
0x43a47f POP %RBX |
0x43a480 POP %R12 |
0x43a482 POP %R13 |
0x43a484 POP %R14 |
0x43a486 POP %R15 |
0x43a488 POP %RBP |
0x43a489 RET |
0x43a48a NOPW (%RAX,%RAX,1) |
(207) 0x43a490 MOV 0x60(%RSP),%R10D |
(207) 0x43a495 XOR %R12D,%R12D |
(207) 0x43a498 JMP 43a27b |
0x43a49d INC %R12D |
0x43a4a0 XOR %EDX,%EDX |
0x43a4a2 JMP 439f42 |
0x43a4a7 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a47b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a47b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43a49d <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43a47b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 439f42 <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a47b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a47b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43a49d <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43a47b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 439f42 <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0– | 0.04 | 0.03 |
▼Loop 207 - generate_chunk.cpp:74-80 - exec– | 0 | 0 |
○Loop 208 - generate_chunk.cpp:77-80 - exec | 0.04 | 0.03 |