Loop Id: 188 | Module: exec | Source: build_field.cpp:143-148 | Coverage: 0.01% |
---|
Loop Id: 188 | Module: exec | Source: build_field.cpp:143-148 | Coverage: 0.01% |
---|
0x422a50 LEA (%RSI,%RDI,1),%RAX |
0x422a54 VPBROADCASTQ %RAX,%ZMM0 |
0x422a5a VPADDQ %ZMM18,%ZMM0,%ZMM16 |
0x422a60 VPBROADCASTQ %RBX,%ZMM17 |
0x422a66 VMOVDQA64 %ZMM16,%ZMM0 |
0x422a6c VMOVDQA64 %ZMM17,%ZMM1 |
0x422a72 LEA 0x38d37(%RIP),%RAX |
0x422a79 CALL %RAX |
0x422a7b VPXOR %XMM1,%XMM1,%XMM1 |
0x422a7f VPMULLQ %ZMM17,%ZMM0,%ZMM1 |
0x422a85 VPSUBQ %ZMM1,%ZMM16,%ZMM1 |
0x422a8b VPSLLQ $0x20,%ZMM0,%ZMM0 |
0x422a92 VPSRAQ $0x20,%ZMM0,%ZMM0 |
0x422a99 VPXOR %XMM2,%XMM2,%XMM2 |
0x422a9d VPMULLQ %ZMM0,%ZMM19,%ZMM2 |
0x422aa3 VPADDQ %ZMM2,%ZMM1,%ZMM2 |
0x422aa9 KXNORW %K0,%K0,%K1 |
0x422aad VSCATTERQPD %ZMM20,(%R15,%ZMM2,8){%K1} [3] |
0x422ab4 VPXOR %XMM2,%XMM2,%XMM2 |
0x422ab8 VPMULLQ %ZMM0,%ZMM21,%ZMM2 |
0x422abe VPADDQ %ZMM2,%ZMM1,%ZMM2 |
0x422ac4 KXNORW %K0,%K0,%K1 |
0x422ac8 VSCATTERQPD %ZMM20,(%R12,%ZMM2,8){%K1} [1] |
0x422acf VPMULLQ %ZMM0,%ZMM22,%ZMM0 |
0x422ad5 VPADDQ %ZMM0,%ZMM1,%ZMM0 |
0x422adb KXNORW %K0,%K0,%K1 |
0x422adf VSCATTERQPD %ZMM20,(%R13,%ZMM0,8){%K1} [2] |
0x422ae7 ADD $0x8,%RDI |
0x422aeb CMP %R14,%RDI |
0x422aee JBE 422a50 |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp: 143 - 148 |
-------------------------------------------------------------------------------- |
143: #pragma omp parallel for simd collapse(2) |
144: for (int j = (0); j < (yrange + 1); j++) { |
145: for (int i = (0); i < (xrange); i++) { |
146: field.vol_flux_y(i, j) = 0.0; |
147: field.mass_flux_y(i, j) = 0.0; |
148: field.yarea(i, j) = 0.0; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.07 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | micro-operation queue, |
Function | _Z11build_fieldR16global_variables.extracted.22 |
Source | build_field.cpp:143-148 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 17.17 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 17.17 |
CQA cycles if fully vectorized | 16.17 |
Front-end cycles | 17.17 |
DIV/SQRT cycles | 15.00 |
P0 cycles | 1.60 |
P1 cycles | 0.00 |
P2 cycles | 0.00 |
P3 cycles | 12.50 |
P4 cycles | 15.00 |
P5 cycles | 2.00 |
P6 cycles | 12.50 |
P7 cycles | 12.50 |
P8 cycles | 12.50 |
P9 cycles | 1.40 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 15.61 - 15.78 |
Stall cycles (UFS) | 2.93 - 3.10 |
Nb insns | 30.00 |
Nb uops | 103.00 |
Nb loads | 0.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.18 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 192.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 90.48 |
Vectorization ratio load | NA |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 77.78 |
Vector-efficiency ratio all | 80.95 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 55.56 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.07 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | micro-operation queue, |
Function | _Z11build_fieldR16global_variables.extracted.22 |
Source | build_field.cpp:143-148 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 17.17 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 17.17 |
CQA cycles if fully vectorized | 16.17 |
Front-end cycles | 17.17 |
DIV/SQRT cycles | 15.00 |
P0 cycles | 1.60 |
P1 cycles | 0.00 |
P2 cycles | 0.00 |
P3 cycles | 12.50 |
P4 cycles | 15.00 |
P5 cycles | 2.00 |
P6 cycles | 12.50 |
P7 cycles | 12.50 |
P8 cycles | 12.50 |
P9 cycles | 1.40 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 15.61 - 15.78 |
Stall cycles (UFS) | 2.93 - 3.10 |
Nb insns | 30.00 |
Nb uops | 103.00 |
Nb loads | 0.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.18 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 192.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 90.48 |
Vectorization ratio load | NA |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 77.78 |
Vector-efficiency ratio all | 80.95 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 55.56 |
Path / |
Function | _Z11build_fieldR16global_variables.extracted.22 |
Source file and lines | build_field.cpp:143-148 |
Module | exec |
nb instructions | 30 |
nb uops | 103 |
loop length | 164 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 0 |
micro-operation queue | 17.17 cycles |
front end | 17.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 15.00 | 1.60 | 0.00 | 0.00 | 12.50 | 15.00 | 2.00 | 12.50 | 12.50 | 12.50 | 1.40 | 0.00 |
cycles | 15.00 | 1.60 | 0.00 | 0.00 | 12.50 | 15.00 | 2.00 | 12.50 | 12.50 | 12.50 | 1.40 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 15.61-15.78 |
Stall cycles | 2.93-3.10 |
ROB full (events) | 2.98-3.45 |
RS full (events) | 1.94-0.75 |
Front-end | 17.17 |
Dispatch | 15.00 |
Data deps. | 1.00 |
Overall L1 | 17.17 |
all | 88% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 77% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 90% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 77% |
all | 77% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 55% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 80% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 55% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA (%RSI,%RDI,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %RAX,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM18,%ZMM0,%ZMM16 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %RBX,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA64 %ZMM16,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQA64 %ZMM17,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
LEA 0x38d37(%RIP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL %RAX | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 2.14 |
VPXOR %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM17,%ZMM0,%ZMM1 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPSUBQ %ZMM1,%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPSLLQ $0x20,%ZMM0,%ZMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 1 |
VPSRAQ $0x20,%ZMM0,%ZMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 1 |
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM0,%ZMM19,%ZMM2 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM2,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VSCATTERQPD %ZMM20,(%R15,%ZMM2,8){%K1} | 20 | 2.20 | 0.20 | 0 | 0 | 4 | 0.20 | 0.20 | 4 | 4 | 4 | 0.20 | 0 | 2-12 | 7 |
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM0,%ZMM21,%ZMM2 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM2,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VSCATTERQPD %ZMM20,(%R12,%ZMM2,8){%K1} | 20 | 2.20 | 0.20 | 0 | 0 | 4 | 0.20 | 0.20 | 4 | 4 | 4 | 0.20 | 0 | 2-12 | 7 |
VPMULLQ %ZMM0,%ZMM22,%ZMM0 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM0,%ZMM1,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VSCATTERQPD %ZMM20,(%R13,%ZMM0,8){%K1} | 20 | 2.20 | 0.20 | 0 | 0 | 4 | 0.20 | 0.20 | 4 | 4 | 4 | 0.20 | 0 | 2-12 | 7 |
ADD $0x8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R14,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 422a50 <_Z11build_fieldR16global_variables.extracted.22+0x110> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | _Z11build_fieldR16global_variables.extracted.22 |
Source file and lines | build_field.cpp:143-148 |
Module | exec |
nb instructions | 30 |
nb uops | 103 |
loop length | 164 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 0 |
micro-operation queue | 17.17 cycles |
front end | 17.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 15.00 | 1.60 | 0.00 | 0.00 | 12.50 | 15.00 | 2.00 | 12.50 | 12.50 | 12.50 | 1.40 | 0.00 |
cycles | 15.00 | 1.60 | 0.00 | 0.00 | 12.50 | 15.00 | 2.00 | 12.50 | 12.50 | 12.50 | 1.40 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 15.61-15.78 |
Stall cycles | 2.93-3.10 |
ROB full (events) | 2.98-3.45 |
RS full (events) | 1.94-0.75 |
Front-end | 17.17 |
Dispatch | 15.00 |
Data deps. | 1.00 |
Overall L1 | 17.17 |
all | 88% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 77% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 90% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 77% |
all | 77% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 55% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 80% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 55% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA (%RSI,%RDI,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %RAX,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM18,%ZMM0,%ZMM16 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %RBX,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA64 %ZMM16,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQA64 %ZMM17,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
LEA 0x38d37(%RIP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL %RAX | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 2.14 |
VPXOR %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM17,%ZMM0,%ZMM1 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPSUBQ %ZMM1,%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPSLLQ $0x20,%ZMM0,%ZMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 1 |
VPSRAQ $0x20,%ZMM0,%ZMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 1 |
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM0,%ZMM19,%ZMM2 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM2,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VSCATTERQPD %ZMM20,(%R15,%ZMM2,8){%K1} | 20 | 2.20 | 0.20 | 0 | 0 | 4 | 0.20 | 0.20 | 4 | 4 | 4 | 0.20 | 0 | 2-12 | 7 |
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM0,%ZMM21,%ZMM2 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM2,%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VSCATTERQPD %ZMM20,(%R12,%ZMM2,8){%K1} | 20 | 2.20 | 0.20 | 0 | 0 | 4 | 0.20 | 0.20 | 4 | 4 | 4 | 0.20 | 0 | 2-12 | 7 |
VPMULLQ %ZMM0,%ZMM22,%ZMM0 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM0,%ZMM1,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VSCATTERQPD %ZMM20,(%R13,%ZMM0,8){%K1} | 20 | 2.20 | 0.20 | 0 | 0 | 4 | 0.20 | 0.20 | 4 | 4 | 4 | 0.20 | 0 | 2-12 | 7 |
ADD $0x8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R14,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 422a50 <_Z11build_fieldR16global_variables.extracted.22+0x110> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |