Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 3% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 3% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 53 - 57 |
-------------------------------------------------------------------------------- |
53: #pragma omp parallel for simd collapse(2) |
54: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
55: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
56: post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
57: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x429540 PUSH %RBP |
0x429541 MOV %RSP,%RBP |
0x429544 PUSH %R15 |
0x429546 PUSH %R14 |
0x429548 PUSH %R13 |
0x42954a PUSH %R12 |
0x42954c PUSH %RBX |
0x42954d AND $-0x40,%RSP |
0x429551 SUB $0xc0,%RSP |
0x429558 MOV 0x30(%RDI),%EAX |
0x42955b MOV 0x34(%RDI),%EDX |
0x42955e MOV 0x28(%RDI),%ECX |
0x429561 MOV 0x2c(%RDI),%EBX |
0x429564 ADD $0x4,%EDX |
0x429567 LEA -0x1(%RAX),%R15D |
0x42956b LEA -0x1(%RCX),%ESI |
0x42956e MOV %EDX,0x5c(%RSP) |
0x429572 MOV %ESI,0x58(%RSP) |
0x429576 CMP %EDX,%R15D |
0x429579 JGE 429bf3 |
0x42957f LEA 0x4(%RBX),%R14D |
0x429583 MOV %EDX,%EBX |
0x429585 SUB %R15D,%EBX |
0x429588 CMP %R14D,%ESI |
0x42958b JGE 429bf3 |
0x429591 MOV %RDI,%R12 |
0x429594 MOV %R14D,%EDI |
0x429597 SUB %ESI,%EDI |
0x429599 MOV %EDI,0x90(%RSP) |
0x4295a0 CALL 4046c0 <omp_get_num_threads@plt> |
0x4295a5 MOV %EAX,%R13D |
0x4295a8 CALL 4045b0 <omp_get_thread_num@plt> |
0x4295ad XOR %EDX,%EDX |
0x4295af MOV %EAX,%R8D |
0x4295b2 MOV 0x90(%RSP),%EAX |
0x4295b9 IMUL %EBX,%EAX |
0x4295bc DIV %R13D |
0x4295bf MOV %EAX,%EDI |
0x4295c1 CMP %EDX,%R8D |
0x4295c4 JB 429c27 |
0x4295ca IMUL %EDI,%R8D |
0x4295ce LEA (%R8,%RDX,1),%R8D |
0x4295d2 LEA (%RDI,%R8,1),%R9D |
0x4295d6 MOV %R9D,0x54(%RSP) |
0x4295db CMP %R9D,%R8D |
0x4295de JAE 429bf3 |
0x4295e4 MOV %R8D,%EAX |
0x4295e7 XOR %EDX,%EDX |
0x4295e9 MOV 0x58(%RSP),%R10D |
0x4295ee MOV (%R12),%RSI |
0x4295f2 DIVL 0x90(%RSP) |
0x4295f9 MOV 0x8(%R12),%RBX |
0x4295fe MOV %RSI,0x40(%RSP) |
0x429603 MOV %RBX,0x30(%RSP) |
0x429608 ADD %EDX,%R10D |
0x42960b LEA (%RAX,%R15,1),%R11D |
0x42960f MOV %R14D,%EDX |
0x429612 MOV 0x10(%R12),%R15 |
0x429617 MOV 0x20(%R12),%R14 |
0x42961c MOV 0x18(%R12),%R12 |
0x429621 MOV %R10D,0xb0(%RSP) |
0x429629 SUB %R10D,%EDX |
0x42962c MOV %R15,0x48(%RSP) |
0x429631 MOVSXD %R11D,%R9 |
0x429634 MOV %R14,0x38(%RSP) |
0x429639 MOV %R12,0x28(%RSP) |
0x42963e XCHG %AX,%AX |
(126) 0x429640 CMP %EDX,%EDI |
(126) 0x429642 CMOVBE %EDI,%EDX |
(126) 0x429645 LEA (%R8,%RDX,1),%ECX |
(126) 0x429649 MOV %ECX,0x94(%RSP) |
(126) 0x429650 CMP %ECX,%R8D |
(126) 0x429653 JAE 429c08 |
(126) 0x429659 MOV 0x48(%RSP),%R13 |
(126) 0x42965e MOV 0x30(%RSP),%R11 |
(126) 0x429663 LEA 0x1(%R9),%RBX |
(126) 0x429667 MOV 0x40(%RSP),%RAX |
(126) 0x42966c MOV 0x38(%RSP),%R10 |
(126) 0x429671 MOV %RBX,0x60(%RSP) |
(126) 0x429676 MOV 0x10(%R13),%R15 |
(126) 0x42967a MOV (%R13),%RDI |
(126) 0x42967e MOV (%R11),%R13 |
(126) 0x429681 MOV (%RAX),%R14 |
(126) 0x429684 MOV 0x10(%R10),%R12 |
(126) 0x429688 MOV 0x10(%RAX),%RSI |
(126) 0x42968c IMUL %R9,%RDI |
(126) 0x429690 MOV %R15,0xa0(%RSP) |
(126) 0x429698 IMUL %R13,%RBX |
(126) 0x42969c MOV 0x28(%RSP),%RAX |
(126) 0x4296a1 MOV (%R10),%R10 |
(126) 0x4296a4 IMUL %R9,%R14 |
(126) 0x4296a8 MOV 0x10(%R11),%RCX |
(126) 0x4296ac MOV %R12,0xa8(%RSP) |
(126) 0x4296b4 IMUL %R9,%R10 |
(126) 0x4296b8 MOV %RDI,0x68(%RSP) |
(126) 0x4296bd IMUL (%RAX),%R9 |
(126) 0x4296c1 MOV %RBX,%R11 |
(126) 0x4296c4 MOV %RBX,0x80(%RSP) |
(126) 0x4296cc SUB %R13,%R11 |
(126) 0x4296cf MOV 0x10(%RAX),%R13 |
(126) 0x4296d3 LEA -0x1(%RDX),%EAX |
(126) 0x4296d6 MOV %R14,0x70(%RSP) |
(126) 0x4296db MOV %R10,0x78(%RSP) |
(126) 0x4296e0 MOV %R11,0x98(%RSP) |
(126) 0x4296e8 MOV %R13,0xb8(%RSP) |
(126) 0x4296f0 MOV %R9,0x88(%RSP) |
(126) 0x4296f8 CMP $0x6,%EAX |
(126) 0x4296fb JBE 429c18 |
(126) 0x429701 MOVSXD 0xb0(%RSP),%RAX |
(126) 0x429709 ADD %RAX,%RDI |
(126) 0x42970c LEA (%R10,%RAX,1),%R10 |
(126) 0x429710 LEA (%RBX,%RAX,1),%RBX |
(126) 0x429714 LEA (%R11,%RAX,1),%R11 |
(126) 0x429718 LEA (%R15,%RDI,8),%R15 |
(126) 0x42971c LEA 0x1(%R14,%RAX,1),%RDI |
(126) 0x429721 ADD %R9,%RAX |
(126) 0x429724 MOV 0xb8(%RSP),%R9 |
(126) 0x42972c LEA (%R12,%R10,8),%R12 |
(126) 0x429730 SAL $0x3,%RDI |
(126) 0x429734 LEA (%RCX,%RBX,8),%RBX |
(126) 0x429738 LEA (%RCX,%R11,8),%R11 |
(126) 0x42973c LEA (%R9,%RAX,8),%R10 |
(126) 0x429740 MOV %EDX,%R9D |
(126) 0x429743 LEA (%RSI,%RDI,1),%R14 |
(126) 0x429747 XOR %EAX,%EAX |
(126) 0x429749 SHR $0x3,%R9D |
(126) 0x42974d LEA -0x8(%RSI,%RDI,1),%R13 |
(126) 0x429752 SAL $0x6,%R9 |
(126) 0x429756 LEA -0x40(%R9),%RDI |
(126) 0x42975a SHR $0x6,%RDI |
(126) 0x42975e INC %RDI |
(126) 0x429761 AND $0x3,%EDI |
(126) 0x429764 JE 42982e |
(126) 0x42976a CMP $0x1,%RDI |
(126) 0x42976e JE 4297e9 |
(126) 0x429770 CMP $0x2,%RDI |
(126) 0x429774 JE 4297ad |
(126) 0x429776 VMOVUPD (%R14),%ZMM7 |
(126) 0x42977c MOV $0x40,%EAX |
(126) 0x429781 VADDPD (%R15),%ZMM7,%ZMM0 |
(126) 0x429787 VSUBPD (%R13),%ZMM0,%ZMM2 |
(126) 0x42978e VMOVUPD %ZMM2,(%R12) |
(126) 0x429795 VMOVUPD (%RBX),%ZMM1 |
(126) 0x42979b VSUBPD (%R11),%ZMM1,%ZMM3 |
(126) 0x4297a1 VADDPD %ZMM2,%ZMM3,%ZMM4 |
(126) 0x4297a7 VMOVUPD %ZMM4,(%R10) |
(126) 0x4297ad VMOVUPD (%R14,%RAX,1),%ZMM5 |
(126) 0x4297b4 VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(126) 0x4297bb VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(126) 0x4297c3 VMOVUPD %ZMM8,(%R12,%RAX,1) |
(126) 0x4297ca VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(126) 0x4297d1 VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(126) 0x4297d8 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(126) 0x4297de VMOVUPD %ZMM11,(%R10,%RAX,1) |
(126) 0x4297e5 ADD $0x40,%RAX |
(126) 0x4297e9 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(126) 0x4297f0 VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(126) 0x4297f7 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(126) 0x4297ff VMOVUPD %ZMM14,(%R12,%RAX,1) |
(126) 0x429806 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(126) 0x42980d VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(126) 0x429814 VADDPD %ZMM14,%ZMM7,%ZMM0 |
(126) 0x42981a VMOVUPD %ZMM0,(%R10,%RAX,1) |
(126) 0x429821 ADD $0x40,%RAX |
(126) 0x429825 CMP %RAX,%R9 |
(126) 0x429828 JE 42992f |
(127) 0x42982e VMOVUPD (%R14,%RAX,1),%ZMM2 |
(127) 0x429835 VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(127) 0x42983c VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(127) 0x429844 VMOVUPD %ZMM3,(%R12,%RAX,1) |
(127) 0x42984b VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(127) 0x429852 VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(127) 0x429859 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(127) 0x42985f VMOVUPD %ZMM6,(%R10,%RAX,1) |
(127) 0x429866 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(127) 0x42986e VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(127) 0x429876 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(127) 0x42987e VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(127) 0x429886 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(127) 0x42988e VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(127) 0x429896 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(127) 0x42989c VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(127) 0x4298a4 VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(127) 0x4298ac VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(127) 0x4298b4 VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(127) 0x4298bc VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(127) 0x4298c4 VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(127) 0x4298cc VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(127) 0x4298d4 VADDPD %ZMM7,%ZMM2,%ZMM1 |
(127) 0x4298da VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(127) 0x4298e2 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(127) 0x4298ea VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(127) 0x4298f2 VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(127) 0x4298fa VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(127) 0x429902 VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(127) 0x42990a VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(127) 0x429912 VADDPD %ZMM6,%ZMM8,%ZMM9 |
(127) 0x429918 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(127) 0x429920 ADD $0x100,%RAX |
(127) 0x429926 CMP %RAX,%R9 |
(127) 0x429929 JNE 42982e |
(126) 0x42992f MOV 0xb0(%RSP),%EAX |
(126) 0x429936 MOV %EDX,%R9D |
(126) 0x429939 AND $-0x8,%R9D |
(126) 0x42993d ADD %R9D,%R8D |
(126) 0x429940 ADD %R9D,%EAX |
(126) 0x429943 TEST $0x7,%DL |
(126) 0x429946 JE 429bb5 |
(126) 0x42994c SUB %R9D,%EDX |
(126) 0x42994f LEA -0x1(%RDX),%R15D |
(126) 0x429953 CMP $0x2,%R15D |
(126) 0x429957 JBE 429a0e |
(126) 0x42995d MOVSXD 0xb0(%RSP),%R14 |
(126) 0x429965 MOV 0x70(%RSP),%R13 |
(126) 0x42996a MOV 0x68(%RSP),%R11 |
(126) 0x42996f MOV 0xa0(%RSP),%RDI |
(126) 0x429977 LEA (%R13,%R14,1),%R12 |
(126) 0x42997c MOV 0x78(%RSP),%R15 |
(126) 0x429981 LEA 0x1(%R9,%R12,1),%RBX |
(126) 0x429986 LEA (%R11,%R14,1),%R10 |
(126) 0x42998a MOV 0xa8(%RSP),%R12 |
(126) 0x429992 VMOVUPD (%RSI,%RBX,8),%YMM10 |
(126) 0x429997 ADD %R9,%R10 |
(126) 0x42999a LEA (%R15,%R14,1),%R13 |
(126) 0x42999e MOV 0x88(%RSP),%R15 |
(126) 0x4299a6 ADD %R9,%R13 |
(126) 0x4299a9 VSUBPD -0x8(%RSI,%RBX,8),%YMM10,%YMM11 |
(126) 0x4299af MOV 0x80(%RSP),%RBX |
(126) 0x4299b7 LEA (%RBX,%R14,1),%R11 |
(126) 0x4299bb VADDPD (%RDI,%R10,8),%YMM11,%YMM12 |
(126) 0x4299c1 MOV 0x98(%RSP),%R10 |
(126) 0x4299c9 ADD %R9,%R11 |
(126) 0x4299cc LEA (%R10,%R14,1),%RDI |
(126) 0x4299d0 ADD %R15,%R14 |
(126) 0x4299d3 VMOVUPD %YMM12,(%R12,%R13,8) |
(126) 0x4299d9 ADD %R9,%RDI |
(126) 0x4299dc ADD %R9,%R14 |
(126) 0x4299df MOV 0xb8(%RSP),%R9 |
(126) 0x4299e7 VMOVUPD (%RCX,%R11,8),%YMM13 |
(126) 0x4299ed VSUBPD (%RCX,%RDI,8),%YMM13,%YMM14 |
(126) 0x4299f2 VADDPD %YMM12,%YMM14,%YMM15 |
(126) 0x4299f7 VMOVUPD %YMM15,(%R9,%R14,8) |
(126) 0x4299fd TEST $0x3,%DL |
(126) 0x429a00 JE 429bb5 |
(126) 0x429a06 AND $-0x4,%EDX |
(126) 0x429a09 ADD %EDX,%R8D |
(126) 0x429a0c ADD %EDX,%EAX |
(126) 0x429a0e MOV 0x70(%RSP),%RBX |
(126) 0x429a13 LEA 0x1(%RAX),%R14D |
(126) 0x429a17 MOVSXD %EAX,%RDX |
(126) 0x429a1a MOV 0x68(%RSP),%R15 |
(126) 0x429a1f MOVSXD %R14D,%RDI |
(126) 0x429a22 MOV 0xa0(%RSP),%R9 |
(126) 0x429a2a MOV 0x78(%RSP),%R14 |
(126) 0x429a2f LEA (%RBX,%RDI,1),%R13 |
(126) 0x429a33 LEA (%RBX,%RDX,1),%R11 |
(126) 0x429a37 LEA (%RSI,%R13,8),%R12 |
(126) 0x429a3b LEA (%R15,%RDX,1),%R10 |
(126) 0x429a3f MOV 0xa8(%RSP),%R13 |
(126) 0x429a47 VMOVSD (%R12),%XMM7 |
(126) 0x429a4d MOV %R12,0xb0(%RSP) |
(126) 0x429a55 LEA (%R14,%RDX,1),%R12 |
(126) 0x429a59 VSUBSD (%RSI,%R11,8),%XMM7,%XMM0 |
(126) 0x429a5f VADDSD (%R9,%R10,8),%XMM0,%XMM2 |
(126) 0x429a65 MOV 0x98(%RSP),%R9 |
(126) 0x429a6d VMOVSD %XMM2,(%R13,%R12,8) |
(126) 0x429a74 MOV 0x80(%RSP),%R12 |
(126) 0x429a7c MOV 0x88(%RSP),%R13 |
(126) 0x429a84 LEA (%R12,%RDX,1),%R11 |
(126) 0x429a88 LEA (%R13,%RDX,1),%R10 |
(126) 0x429a8d ADD %R9,%RDX |
(126) 0x429a90 VMOVSD (%RCX,%R11,8),%XMM1 |
(126) 0x429a96 LEA 0x1(%R8),%R11D |
(126) 0x429a9a VSUBSD (%RCX,%RDX,8),%XMM1,%XMM3 |
(126) 0x429a9f MOV 0xb8(%RSP),%RDX |
(126) 0x429aa7 VADDSD %XMM2,%XMM3,%XMM4 |
(126) 0x429aab VMOVSD %XMM4,(%RDX,%R10,8) |
(126) 0x429ab1 MOV 0x94(%RSP),%R10D |
(126) 0x429ab9 CMP %R10D,%R11D |
(126) 0x429abc JAE 429bb5 |
(126) 0x429ac2 LEA 0x2(%RAX),%R9D |
(126) 0x429ac6 ADD $0x2,%R8D |
(126) 0x429aca MOVSXD %R9D,%RDX |
(126) 0x429acd MOV 0xa0(%RSP),%R9 |
(126) 0x429ad5 LEA (%RBX,%RDX,1),%R11 |
(126) 0x429ad9 LEA (%RSI,%R11,8),%R10 |
(126) 0x429add LEA (%RDI,%R15,1),%R11 |
(126) 0x429ae1 VMOVSD (%R9,%R11,8),%XMM6 |
(126) 0x429ae7 MOV 0xb0(%RSP),%R11 |
(126) 0x429aef LEA (%R14,%RDI,1),%R9 |
(126) 0x429af3 VADDSD (%R10),%XMM6,%XMM5 |
(126) 0x429af8 VSUBSD (%R11),%XMM5,%XMM8 |
(126) 0x429afd MOV 0xa8(%RSP),%R11 |
(126) 0x429b05 VMOVSD %XMM8,(%R11,%R9,8) |
(126) 0x429b0b LEA (%R13,%RDI,1),%R9 |
(126) 0x429b10 LEA (%R12,%RDI,1),%R11 |
(126) 0x429b14 MOV %R9,0xb0(%RSP) |
(126) 0x429b1c MOV 0x98(%RSP),%R9 |
(126) 0x429b24 VMOVSD (%RCX,%R11,8),%XMM9 |
(126) 0x429b2a ADD %R9,%RDI |
(126) 0x429b2d VSUBSD (%RCX,%RDI,8),%XMM9,%XMM10 |
(126) 0x429b32 MOV 0xb0(%RSP),%R11 |
(126) 0x429b3a MOV 0xb8(%RSP),%RDI |
(126) 0x429b42 VADDSD %XMM8,%XMM10,%XMM11 |
(126) 0x429b47 VMOVSD %XMM11,(%RDI,%R11,8) |
(126) 0x429b4d MOV 0x94(%RSP),%EDI |
(126) 0x429b54 CMP %EDI,%R8D |
(126) 0x429b57 JAE 429bb5 |
(126) 0x429b59 ADD $0x3,%EAX |
(126) 0x429b5c MOV 0xa0(%RSP),%R8 |
(126) 0x429b64 ADD %RDX,%R15 |
(126) 0x429b67 ADD %RDX,%R14 |
(126) 0x429b6a CLTQ |
(126) 0x429b6c ADD %RDX,%R12 |
(126) 0x429b6f ADD %RDX,%R9 |
(126) 0x429b72 ADD %RDX,%R13 |
(126) 0x429b75 ADD %RBX,%RAX |
(126) 0x429b78 VMOVSD (%RSI,%RAX,8),%XMM12 |
(126) 0x429b7d MOV 0xa8(%RSP),%RSI |
(126) 0x429b85 VADDSD (%R8,%R15,8),%XMM12,%XMM13 |
(126) 0x429b8b VSUBSD (%R10),%XMM13,%XMM14 |
(126) 0x429b90 VMOVSD %XMM14,(%RSI,%R14,8) |
(126) 0x429b96 VMOVSD (%RCX,%R12,8),%XMM15 |
(126) 0x429b9c VSUBSD (%RCX,%R9,8),%XMM15,%XMM7 |
(126) 0x429ba2 MOV 0xb8(%RSP),%RCX |
(126) 0x429baa VADDSD %XMM14,%XMM7,%XMM0 |
(126) 0x429baf VMOVSD %XMM0,(%RCX,%R13,8) |
(126) 0x429bb5 MOV 0x94(%RSP),%R8D |
(126) 0x429bbd MOV 0x60(%RSP),%R9 |
(126) 0x429bc2 LEA (%R9),%EAX |
(126) 0x429bc5 CMP %EAX,0x5c(%RSP) |
(126) 0x429bc9 JLE 429bf0 |
(126) 0x429bcb MOV 0x54(%RSP),%EDI |
(126) 0x429bcf MOV 0x58(%RSP),%EBX |
(126) 0x429bd3 MOV 0x90(%RSP),%EDX |
(126) 0x429bda MOV %EBX,0xb0(%RSP) |
(126) 0x429be1 SUB %R8D,%EDI |
(126) 0x429be4 JMP 429640 |
0x429be9 NOPL (%RAX) |
0x429bf0 VZEROUPPER |
0x429bf3 LEA -0x28(%RBP),%RSP |
0x429bf7 POP %RBX |
0x429bf8 POP %R12 |
0x429bfa POP %R13 |
0x429bfc POP %R14 |
0x429bfe POP %R15 |
0x429c00 POP %RBP |
0x429c01 RET |
0x429c02 NOPW (%RAX,%RAX,1) |
(126) 0x429c08 LEA 0x1(%R9),%RDI |
(126) 0x429c0c MOV %RDI,0x60(%RSP) |
(126) 0x429c11 JMP 429bbd |
0x429c13 NOPL (%RAX,%RAX,1) |
(126) 0x429c18 MOV 0xb0(%RSP),%EAX |
(126) 0x429c1f XOR %R9D,%R9D |
(126) 0x429c22 JMP 42994c |
0x429c27 INC %EDI |
0x429c29 XOR %EDX,%EDX |
0x429c2b JMP 4295ca |
Path / |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 301 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.60-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RCX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429bf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x4(%RBX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429bf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429c27 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 429bf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x90(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4295ca <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 301 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.60-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RCX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429bf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x4(%RBX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429bf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429c27 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 429bf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x90(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4295ca <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1– | 3 | 2.25 |
▼Loop 126 - advec_mom.cpp:53-57 - exec– | 0.01 | 0.01 |
○Loop 127 - advec_mom.cpp:56-57 - exec | 3 | 2.24 |