Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:136-140 [...] | Coverage: 1.49% |
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Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:136-140 [...] | Coverage: 1.49% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 136 - 140 |
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136: #pragma omp parallel for simd collapse(2) |
137: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
138: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
139: pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
140: post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
0x426dc0 PUSH %RBP |
0x426dc1 MOV %RSP,%RBP |
0x426dc4 PUSH %R15 |
0x426dc6 PUSH %R14 |
0x426dc8 PUSH %R13 |
0x426dca PUSH %R12 |
0x426dcc MOV %RDI,%R12 |
0x426dcf PUSH %RBX |
0x426dd0 AND $-0x40,%RSP |
0x426dd4 SUB $0xc0,%RSP |
0x426ddb MOV 0x30(%RDI),%EAX |
0x426dde MOV 0x34(%RDI),%ECX |
0x426de1 MOV 0x28(%RDI),%EDI |
0x426de4 MOV 0x2c(%R12),%EDX |
0x426de9 ADD $0x4,%ECX |
0x426dec LEA -0x1(%RAX),%R15D |
0x426df0 DEC %EDI |
0x426df2 MOV %ECX,0x5c(%RSP) |
0x426df6 MOV %EDI,0x58(%RSP) |
0x426dfa CMP %ECX,%R15D |
0x426dfd JGE 42756b |
0x426e03 MOV %ECX,%EBX |
0x426e05 LEA 0x4(%RDX),%R14D |
0x426e09 SUB %R15D,%EBX |
0x426e0c CMP %R14D,%EDI |
0x426e0f JGE 42756b |
0x426e15 MOV %R14D,%ESI |
0x426e18 SUB %EDI,%ESI |
0x426e1a MOV %ESI,0x78(%RSP) |
0x426e1e CALL 4046c0 <omp_get_num_threads@plt> |
0x426e23 MOV %EAX,%R13D |
0x426e26 CALL 4045b0 <omp_get_thread_num@plt> |
0x426e2b XOR %EDX,%EDX |
0x426e2d MOV %EAX,%R8D |
0x426e30 MOV 0x78(%RSP),%EAX |
0x426e34 IMUL %EBX,%EAX |
0x426e37 DIV %R13D |
0x426e3a MOV %EAX,%R13D |
0x426e3d CMP %EDX,%R8D |
0x426e40 JB 42759f |
0x426e46 IMUL %R13D,%R8D |
0x426e4a LEA (%R8,%RDX,1),%R9D |
0x426e4e LEA (%R13,%R9,1),%R10D |
0x426e53 MOV %R10D,0x54(%RSP) |
0x426e58 CMP %R10D,%R9D |
0x426e5b JAE 42756b |
0x426e61 MOV %R9D,%EAX |
0x426e64 XOR %EDX,%EDX |
0x426e66 MOV 0x58(%RSP),%R11D |
0x426e6b MOV (%R12),%RCX |
0x426e6f DIVL 0x78(%RSP) |
0x426e73 MOV 0x10(%R12),%RDI |
0x426e78 MOV 0x18(%R12),%RBX |
0x426e7d MOV %RCX,0x48(%RSP) |
0x426e82 MOV %RDI,0x40(%RSP) |
0x426e87 MOV %RBX,0x30(%RSP) |
0x426e8c MOV %R14D,%R10D |
0x426e8f MOV 0x8(%R12),%R14 |
0x426e94 MOV 0x20(%R12),%R12 |
0x426e99 MOV %R14,0x38(%RSP) |
0x426e9e MOV %R12,0x28(%RSP) |
0x426ea3 ADD %EDX,%R11D |
0x426ea6 LEA (%RAX,%R15,1),%R15D |
0x426eaa MOV %R11D,0xa0(%RSP) |
0x426eb2 SUB %R11D,%R10D |
0x426eb5 MOVSXD %R15D,%RCX |
0x426eb8 NOPL (%RAX,%RAX,1) |
(114) 0x426ec0 CMP %R10D,%R13D |
(114) 0x426ec3 CMOVBE %R13D,%R10D |
(114) 0x426ec7 LEA (%R9,%R10,1),%ESI |
(114) 0x426ecb MOV %R10D,%EDX |
(114) 0x426ece MOV %ESI,0x7c(%RSP) |
(114) 0x426ed2 CMP %ESI,%R9D |
(114) 0x426ed5 JAE 427580 |
(114) 0x426edb MOV 0x40(%RSP),%R10 |
(114) 0x426ee0 MOV 0x48(%RSP),%R8 |
(114) 0x426ee5 LEA 0x1(%RCX),%RSI |
(114) 0x426ee9 MOV 0x38(%RSP),%R11 |
(114) 0x426eee MOV 0x30(%RSP),%R12 |
(114) 0x426ef3 MOV %RSI,0x60(%RSP) |
(114) 0x426ef8 MOV (%R10),%RAX |
(114) 0x426efb MOV 0x10(%R8),%R15 |
(114) 0x426eff MOV (%R8),%R14 |
(114) 0x426f02 MOV 0x10(%R12),%R13 |
(114) 0x426f07 IMUL %RAX,%RSI |
(114) 0x426f0b MOV 0x10(%R10),%RDI |
(114) 0x426f0f MOV 0x10(%R11),%R8 |
(114) 0x426f13 MOV %R15,0x90(%RSP) |
(114) 0x426f1b MOV 0x28(%RSP),%R10 |
(114) 0x426f20 MOV (%R11),%R11 |
(114) 0x426f23 IMUL %RCX,%R14 |
(114) 0x426f27 MOV %R13,0xa8(%RSP) |
(114) 0x426f2f MOV (%R12),%R12 |
(114) 0x426f33 IMUL %RCX,%R11 |
(114) 0x426f37 MOV %RSI,%RBX |
(114) 0x426f3a MOV %RSI,0x68(%RSP) |
(114) 0x426f3f IMUL %RCX,%R12 |
(114) 0x426f43 SUB %RAX,%RBX |
(114) 0x426f46 MOV 0x10(%R10),%RAX |
(114) 0x426f4a MOV %R14,0x88(%RSP) |
(114) 0x426f52 IMUL (%R10),%RCX |
(114) 0x426f56 MOV %RBX,0x98(%RSP) |
(114) 0x426f5e MOV %R11,0x70(%RSP) |
(114) 0x426f63 MOV %R12,0x80(%RSP) |
(114) 0x426f6b MOV %RCX,0xb8(%RSP) |
(114) 0x426f73 LEA -0x1(%RDX),%ECX |
(114) 0x426f76 MOV %RAX,0xb0(%RSP) |
(114) 0x426f7e CMP $0x6,%ECX |
(114) 0x426f81 JBE 427590 |
(114) 0x426f87 MOVSXD 0xa0(%RSP),%RAX |
(114) 0x426f8f LEA (%RBX,%RAX,1),%RBX |
(114) 0x426f93 LEA 0x1(%R11,%RAX,1),%R11 |
(114) 0x426f98 LEA (%RSI,%RAX,1),%R10 |
(114) 0x426f9c LEA (%R14,%RAX,1),%R14 |
(114) 0x426fa0 SAL $0x3,%R11 |
(114) 0x426fa4 LEA (%RDI,%RBX,8),%RSI |
(114) 0x426fa8 MOV 0xb8(%RSP),%RBX |
(114) 0x426fb0 LEA (%R15,%R14,8),%R15 |
(114) 0x426fb4 LEA (%R8,%R11,1),%R13 |
(114) 0x426fb8 LEA -0x8(%R8,%R11,1),%R14 |
(114) 0x426fbd MOV 0xb0(%RSP),%R11 |
(114) 0x426fc5 LEA (%R12,%RAX,1),%R12 |
(114) 0x426fc9 ADD %RBX,%RAX |
(114) 0x426fcc LEA (%RDI,%R10,8),%RCX |
(114) 0x426fd0 MOV 0xa8(%RSP),%R10 |
(114) 0x426fd8 LEA (%R11,%RAX,8),%RBX |
(114) 0x426fdc MOV %EDX,%R11D |
(114) 0x426fdf XOR %EAX,%EAX |
(114) 0x426fe1 SHR $0x3,%R11D |
(114) 0x426fe5 LEA (%R10,%R12,8),%R12 |
(114) 0x426fe9 SAL $0x6,%R11 |
(114) 0x426fed LEA -0x40(%R11),%R10 |
(114) 0x426ff1 SHR $0x6,%R10 |
(114) 0x426ff5 INC %R10 |
(114) 0x426ff8 AND $0x3,%R10D |
(114) 0x426ffc JE 427104 |
(114) 0x427002 CMP $0x1,%R10 |
(114) 0x427006 JE 4270ab |
(114) 0x42700c CMP $0x2,%R10 |
(114) 0x427010 JE 42705b |
(114) 0x427012 VMOVUPD (%RCX),%ZMM3 |
(114) 0x427018 VMOVUPD (%R14),%ZMM6 |
(114) 0x42701e MOV $0x40,%EAX |
(114) 0x427023 VADDPD (%R15),%ZMM3,%ZMM0 |
(114) 0x427029 VADDPD (%RSI),%ZMM6,%ZMM1 |
(114) 0x42702f VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(114) 0x427035 VADDPD (%R13),%ZMM2,%ZMM4 |
(114) 0x42703c VMOVUPD %ZMM4,(%R12) |
(114) 0x427043 VMOVUPD (%RSI),%ZMM7 |
(114) 0x427049 VSUBPD (%RCX),%ZMM7,%ZMM5 |
(114) 0x42704f VADDPD %ZMM4,%ZMM5,%ZMM8 |
(114) 0x427055 VMOVUPD %ZMM8,(%RBX) |
(114) 0x42705b VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(114) 0x427062 VMOVUPD (%R14,%RAX,1),%ZMM11 |
(114) 0x427069 VADDPD (%R15,%RAX,1),%ZMM9,%ZMM10 |
(114) 0x427070 VADDPD (%RSI,%RAX,1),%ZMM11,%ZMM12 |
(114) 0x427077 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(114) 0x42707d VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(114) 0x427085 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(114) 0x42708c VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(114) 0x427093 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM3 |
(114) 0x42709a VADDPD %ZMM14,%ZMM3,%ZMM0 |
(114) 0x4270a0 VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(114) 0x4270a7 ADD $0x40,%RAX |
(114) 0x4270ab VMOVUPD (%RCX,%RAX,1),%ZMM6 |
(114) 0x4270b2 VMOVUPD (%R14,%RAX,1),%ZMM1 |
(114) 0x4270b9 VADDPD (%R15,%RAX,1),%ZMM6,%ZMM2 |
(114) 0x4270c0 VADDPD (%RSI,%RAX,1),%ZMM1,%ZMM4 |
(114) 0x4270c7 VSUBPD %ZMM4,%ZMM2,%ZMM7 |
(114) 0x4270cd VADDPD (%R13,%RAX,1),%ZMM7,%ZMM5 |
(114) 0x4270d5 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(114) 0x4270dc VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(114) 0x4270e3 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(114) 0x4270ea VADDPD %ZMM5,%ZMM9,%ZMM10 |
(114) 0x4270f0 VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(114) 0x4270f7 ADD $0x40,%RAX |
(114) 0x4270fb CMP %RAX,%R11 |
(114) 0x4270fe JE 42725b |
(115) 0x427104 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(115) 0x42710b VMOVUPD (%R14,%RAX,1),%ZMM13 |
(115) 0x427112 VADDPD (%R15,%RAX,1),%ZMM11,%ZMM12 |
(115) 0x427119 VADDPD (%RSI,%RAX,1),%ZMM13,%ZMM14 |
(115) 0x427120 VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(115) 0x427126 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM3 |
(115) 0x42712e VMOVUPD %ZMM3,(%R12,%RAX,1) |
(115) 0x427135 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(115) 0x42713c VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM6 |
(115) 0x427143 VADDPD %ZMM3,%ZMM6,%ZMM2 |
(115) 0x427149 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(115) 0x427150 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM1 |
(115) 0x427158 VMOVUPD 0x40(%R14,%RAX,1),%ZMM4 |
(115) 0x427160 VADDPD 0x40(%R15,%RAX,1),%ZMM1,%ZMM7 |
(115) 0x427168 VADDPD 0x40(%RSI,%RAX,1),%ZMM4,%ZMM5 |
(115) 0x427170 VSUBPD %ZMM5,%ZMM7,%ZMM8 |
(115) 0x427176 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(115) 0x42717e VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(115) 0x427186 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(115) 0x42718e VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(115) 0x427196 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(115) 0x42719c VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(115) 0x4271a4 VMOVUPD 0x80(%RCX,%RAX,1),%ZMM13 |
(115) 0x4271ac VMOVUPD 0x80(%R14,%RAX,1),%ZMM15 |
(115) 0x4271b4 VADDPD 0x80(%R15,%RAX,1),%ZMM13,%ZMM14 |
(115) 0x4271bc VADDPD 0x80(%RSI,%RAX,1),%ZMM15,%ZMM3 |
(115) 0x4271c4 VSUBPD %ZMM3,%ZMM14,%ZMM0 |
(115) 0x4271ca VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM6 |
(115) 0x4271d2 VMOVUPD %ZMM6,0x80(%R12,%RAX,1) |
(115) 0x4271da VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(115) 0x4271e2 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(115) 0x4271ea VADDPD %ZMM6,%ZMM1,%ZMM7 |
(115) 0x4271f0 VMOVUPD %ZMM7,0x80(%RBX,%RAX,1) |
(115) 0x4271f8 VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM4 |
(115) 0x427200 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM8 |
(115) 0x427208 VADDPD 0xc0(%R15,%RAX,1),%ZMM4,%ZMM5 |
(115) 0x427210 VADDPD 0xc0(%RSI,%RAX,1),%ZMM8,%ZMM9 |
(115) 0x427218 VSUBPD %ZMM9,%ZMM5,%ZMM10 |
(115) 0x42721e VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(115) 0x427226 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(115) 0x42722e VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(115) 0x427236 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(115) 0x42723e VADDPD %ZMM11,%ZMM13,%ZMM14 |
(115) 0x427244 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(115) 0x42724c ADD $0x100,%RAX |
(115) 0x427252 CMP %RAX,%R11 |
(115) 0x427255 JNE 427104 |
(114) 0x42725b MOV 0xa0(%RSP),%R15D |
(114) 0x427263 MOV %EDX,%R13D |
(114) 0x427266 AND $-0x8,%R13D |
(114) 0x42726a ADD %R13D,%R9D |
(114) 0x42726d LEA (%R13,%R15,1),%ESI |
(114) 0x427272 TEST $0x7,%DL |
(114) 0x427275 JE 427536 |
(114) 0x42727b SUB %R13D,%EDX |
(114) 0x42727e LEA -0x1(%RDX),%ECX |
(114) 0x427281 CMP $0x2,%ECX |
(114) 0x427284 JBE 427352 |
(114) 0x42728a MOVSXD 0xa0(%RSP),%RAX |
(114) 0x427292 MOV 0x98(%RSP),%RBX |
(114) 0x42729a MOV 0x68(%RSP),%R14 |
(114) 0x42729f MOV 0x70(%RSP),%R15 |
(114) 0x4272a4 LEA (%RBX,%RAX,1),%R10 |
(114) 0x4272a8 MOV 0x88(%RSP),%RBX |
(114) 0x4272b0 LEA (%R14,%RAX,1),%R12 |
(114) 0x4272b4 ADD %R13,%R10 |
(114) 0x4272b7 LEA (%R15,%RAX,1),%R14 |
(114) 0x4272bb MOV 0x90(%RSP),%R15 |
(114) 0x4272c3 ADD %R13,%R12 |
(114) 0x4272c6 LEA (%RDI,%R10,8),%RCX |
(114) 0x4272ca LEA (%RBX,%RAX,1),%R10 |
(114) 0x4272ce MOV 0xa8(%RSP),%RBX |
(114) 0x4272d6 LEA (%RDI,%R12,8),%R11 |
(114) 0x4272da ADD %R13,%R10 |
(114) 0x4272dd LEA 0x1(%R13,%R14,1),%R12 |
(114) 0x4272e2 MOV 0x80(%RSP),%R14 |
(114) 0x4272ea VMOVUPD (%R8,%R12,8),%YMM3 |
(114) 0x4272f0 VMOVUPD (%R15,%R10,8),%YMM15 |
(114) 0x4272f6 VSUBPD (%RCX),%YMM3,%YMM6 |
(114) 0x4272fa VADDPD (%R11),%YMM15,%YMM0 |
(114) 0x4272ff VADDPD %YMM6,%YMM0,%YMM2 |
(114) 0x427303 VSUBPD -0x8(%R8,%R12,8),%YMM2,%YMM7 |
(114) 0x42730a LEA (%R14,%RAX,1),%R12 |
(114) 0x42730e ADD %R13,%R12 |
(114) 0x427311 VMOVUPD %YMM7,(%RBX,%R12,8) |
(114) 0x427317 VMOVUPD (%RCX),%YMM1 |
(114) 0x42731b VSUBPD (%R11),%YMM1,%YMM4 |
(114) 0x427320 MOV 0xb8(%RSP),%R11 |
(114) 0x427328 ADD %R11,%RAX |
(114) 0x42732b VADDPD %YMM7,%YMM4,%YMM5 |
(114) 0x42732f ADD %R13,%RAX |
(114) 0x427332 MOV 0xb0(%RSP),%R13 |
(114) 0x42733a VMOVUPD %YMM5,(%R13,%RAX,8) |
(114) 0x427341 TEST $0x3,%DL |
(114) 0x427344 JE 427536 |
(114) 0x42734a AND $-0x4,%EDX |
(114) 0x42734d ADD %EDX,%R9D |
(114) 0x427350 ADD %EDX,%ESI |
(114) 0x427352 MOV 0x68(%RSP),%R15 |
(114) 0x427357 MOVSXD %ESI,%RDX |
(114) 0x42735a MOV 0x70(%RSP),%R14 |
(114) 0x42735f MOV 0x98(%RSP),%R13 |
(114) 0x427367 LEA (%R15,%RDX,1),%RAX |
(114) 0x42736b LEA (%RDI,%RAX,8),%R10 |
(114) 0x42736f LEA 0x1(%RSI),%EAX |
(114) 0x427372 CLTQ |
(114) 0x427374 LEA (%R13,%RDX,1),%RCX |
(114) 0x427379 LEA (%R14,%RAX,1),%R12 |
(114) 0x42737d LEA (%RDI,%RCX,8),%R11 |
(114) 0x427381 MOV 0x90(%RSP),%RCX |
(114) 0x427389 LEA (%R8,%R12,8),%RBX |
(114) 0x42738d MOV 0x88(%RSP),%R12 |
(114) 0x427395 MOV %RBX,0xa0(%RSP) |
(114) 0x42739d LEA (%R12,%RDX,1),%RBX |
(114) 0x4273a1 VMOVSD (%RCX,%RBX,8),%XMM8 |
(114) 0x4273a6 LEA (%R14,%RDX,1),%RCX |
(114) 0x4273aa MOV 0xa0(%RSP),%RBX |
(114) 0x4273b2 VADDSD (%R10),%XMM8,%XMM9 |
(114) 0x4273b7 VMOVSD (%RBX),%XMM10 |
(114) 0x4273bb MOV 0x80(%RSP),%RBX |
(114) 0x4273c3 VSUBSD (%R11),%XMM10,%XMM11 |
(114) 0x4273c8 ADD %RDX,%RBX |
(114) 0x4273cb VADDSD %XMM11,%XMM9,%XMM12 |
(114) 0x4273d0 VSUBSD (%R8,%RCX,8),%XMM12,%XMM13 |
(114) 0x4273d6 MOV 0xa8(%RSP),%RCX |
(114) 0x4273de VMOVSD %XMM13,(%RCX,%RBX,8) |
(114) 0x4273e3 MOV 0xb8(%RSP),%RBX |
(114) 0x4273eb VMOVSD (%R11),%XMM14 |
(114) 0x4273f0 MOV 0x7c(%RSP),%R11D |
(114) 0x4273f5 ADD %RBX,%RDX |
(114) 0x4273f8 VSUBSD (%R10),%XMM14,%XMM15 |
(114) 0x4273fd MOV 0xb0(%RSP),%R10 |
(114) 0x427405 VADDSD %XMM13,%XMM15,%XMM0 |
(114) 0x42740a VMOVSD %XMM0,(%R10,%RDX,8) |
(114) 0x427410 LEA 0x1(%R9),%EDX |
(114) 0x427414 CMP %R11D,%EDX |
(114) 0x427417 JAE 427536 |
(114) 0x42741d LEA (%RAX,%R13,1),%R13 |
(114) 0x427421 ADD %RAX,%R12 |
(114) 0x427424 LEA (%RAX,%R15,1),%RCX |
(114) 0x427428 ADD $0x2,%R9D |
(114) 0x42742c LEA (%RDI,%R13,8),%R11 |
(114) 0x427430 MOV 0x90(%RSP),%R13 |
(114) 0x427438 LEA (%RDI,%RCX,8),%R10 |
(114) 0x42743c LEA 0x2(%RSI),%EBX |
(114) 0x42743f VMOVSD (%R13,%R12,8),%XMM3 |
(114) 0x427446 MOV 0xa0(%RSP),%R12 |
(114) 0x42744e MOVSXD %EBX,%RDX |
(114) 0x427451 LEA (%R14,%RDX,1),%RCX |
(114) 0x427455 MOV 0xa8(%RSP),%R13 |
(114) 0x42745d VMOVSD (%R12),%XMM2 |
(114) 0x427463 VADDSD (%R10),%XMM3,%XMM6 |
(114) 0x427468 LEA (%R8,%RCX,8),%RBX |
(114) 0x42746c MOV 0x80(%RSP),%R12 |
(114) 0x427474 VADDSD (%R11),%XMM2,%XMM7 |
(114) 0x427479 MOV %R12,%RCX |
(114) 0x42747c ADD %RAX,%RCX |
(114) 0x42747f VSUBSD %XMM7,%XMM6,%XMM1 |
(114) 0x427483 VADDSD (%RBX),%XMM1,%XMM4 |
(114) 0x427487 VMOVSD %XMM4,(%R13,%RCX,8) |
(114) 0x42748e MOV 0xb8(%RSP),%RCX |
(114) 0x427496 VMOVSD (%R11),%XMM5 |
(114) 0x42749b MOV 0xb0(%RSP),%R11 |
(114) 0x4274a3 ADD %RCX,%RAX |
(114) 0x4274a6 VSUBSD (%R10),%XMM5,%XMM8 |
(114) 0x4274ab VADDSD %XMM4,%XMM8,%XMM9 |
(114) 0x4274af VMOVSD %XMM9,(%R11,%RAX,8) |
(114) 0x4274b5 MOV 0x7c(%RSP),%EAX |
(114) 0x4274b9 CMP %EAX,%R9D |
(114) 0x4274bc JAE 427536 |
(114) 0x4274be MOV 0x98(%RSP),%R9 |
(114) 0x4274c6 ADD %RDX,%R15 |
(114) 0x4274c9 MOV 0x90(%RSP),%RAX |
(114) 0x4274d1 ADD $0x3,%ESI |
(114) 0x4274d4 LEA (%RDI,%R15,8),%R10 |
(114) 0x4274d8 MOVSXD %ESI,%RSI |
(114) 0x4274db ADD %RDX,%R12 |
(114) 0x4274de ADD %RDX,%R9 |
(114) 0x4274e1 ADD %R14,%RSI |
(114) 0x4274e4 LEA (%RDI,%R9,8),%RCX |
(114) 0x4274e8 MOV 0x88(%RSP),%RDI |
(114) 0x4274f0 VMOVSD (%RCX),%XMM12 |
(114) 0x4274f4 ADD %RDX,%RDI |
(114) 0x4274f7 VMOVSD (%RAX,%RDI,8),%XMM10 |
(114) 0x4274fc VADDSD (%RBX),%XMM12,%XMM13 |
(114) 0x427500 VADDSD (%R10),%XMM10,%XMM11 |
(114) 0x427505 VSUBSD %XMM13,%XMM11,%XMM14 |
(114) 0x42750a VADDSD (%R8,%RSI,8),%XMM14,%XMM15 |
(114) 0x427510 MOV 0xb8(%RSP),%R8 |
(114) 0x427518 ADD %RDX,%R8 |
(114) 0x42751b VMOVSD %XMM15,(%R13,%R12,8) |
(114) 0x427522 VMOVSD (%RCX),%XMM0 |
(114) 0x427526 VSUBSD (%R10),%XMM0,%XMM3 |
(114) 0x42752b VADDSD %XMM15,%XMM3,%XMM6 |
(114) 0x427530 VMOVSD %XMM6,(%R11,%R8,8) |
(114) 0x427536 MOV 0x7c(%RSP),%R9D |
(114) 0x42753b MOV 0x60(%RSP),%RCX |
(114) 0x427540 LEA (%RCX),%EDX |
(114) 0x427542 CMP %EDX,0x5c(%RSP) |
(114) 0x427546 JLE 427568 |
(114) 0x427548 MOV 0x54(%RSP),%R13D |
(114) 0x42754d MOV 0x58(%RSP),%EBX |
(114) 0x427551 MOV 0x78(%RSP),%R10D |
(114) 0x427556 MOV %EBX,0xa0(%RSP) |
(114) 0x42755d SUB %R9D,%R13D |
(114) 0x427560 JMP 426ec0 |
0x427565 NOPL (%RAX) |
0x427568 VZEROUPPER |
0x42756b LEA -0x28(%RBP),%RSP |
0x42756f POP %RBX |
0x427570 POP %R12 |
0x427572 POP %R13 |
0x427574 POP %R14 |
0x427576 POP %R15 |
0x427578 POP %RBP |
0x427579 RET |
0x42757a NOPW (%RAX,%RAX,1) |
(114) 0x427580 LEA 0x1(%RCX),%R13 |
(114) 0x427584 MOV %R13,0x60(%RSP) |
(114) 0x427589 JMP 42753b |
0x42758b NOPL (%RAX,%RAX,1) |
(114) 0x427590 MOV 0xa0(%RSP),%ESI |
(114) 0x427597 XOR %R13D,%R13D |
(114) 0x42759a JMP 42727b |
0x42759f INC %R13D |
0x4275a2 XOR %EDX,%EDX |
0x4275a4 JMP 426e46 |
0x4275a9 NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:136-140 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 305 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42756b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42756b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x78(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42759f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42756b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 426e46 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:136-140 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 305 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42756b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42756b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x78(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42759f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42756b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 426e46 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0– | 1.49 | 1.12 |
▼Loop 114 - advec_cell.cpp:136-140 - exec– | 0 | 0 |
○Loop 115 - advec_cell.cpp:139-140 - exec | 1.49 | 1.11 |