Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 3.07% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 3.07% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 95 - 100 |
-------------------------------------------------------------------------------- |
95: #pragma omp parallel for simd collapse(2) |
96: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
97: for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) { |
98: node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) + |
99: density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0)); |
100: node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42ad40 PUSH %RBP |
0x42ad41 MOV %RSP,%RBP |
0x42ad44 PUSH %R15 |
0x42ad46 PUSH %R14 |
0x42ad48 PUSH %R13 |
0x42ad4a PUSH %R12 |
0x42ad4c PUSH %RBX |
0x42ad4d MOV %RDI,%RBX |
0x42ad50 AND $-0x40,%RSP |
0x42ad54 SUB $0x100,%RSP |
0x42ad5b MOV 0x30(%RDI),%EAX |
0x42ad5e MOV 0x34(%RDI),%ECX |
0x42ad61 MOV 0x28(%RDI),%EDX |
0x42ad64 MOV 0x2c(%RDI),%EDI |
0x42ad67 ADD $0x3,%ECX |
0x42ad6a LEA 0x1(%RAX),%R12D |
0x42ad6e MOV %EDX,0x6c(%RSP) |
0x42ad72 MOV %ECX,0x70(%RSP) |
0x42ad76 CMP %ECX,%R12D |
0x42ad79 JGE 42b5db |
0x42ad7f MOV %ECX,%R14D |
0x42ad82 LEA 0x4(%RDI),%R15D |
0x42ad86 SUB %R12D,%R14D |
0x42ad89 CMP %R15D,%EDX |
0x42ad8c JGE 42b5db |
0x42ad92 MOV %R15D,%ESI |
0x42ad95 SUB %EDX,%ESI |
0x42ad97 MOV %ESI,0x74(%RSP) |
0x42ad9b CALL 4046c0 <omp_get_num_threads@plt> |
0x42ada0 MOV %EAX,%R13D |
0x42ada3 CALL 4045b0 <omp_get_thread_num@plt> |
0x42ada8 XOR %EDX,%EDX |
0x42adaa MOV %EAX,%R8D |
0x42adad MOV 0x74(%RSP),%EAX |
0x42adb1 IMUL %R14D,%EAX |
0x42adb5 DIV %R13D |
0x42adb8 MOV %EAX,%ECX |
0x42adba CMP %EDX,%R8D |
0x42adbd JB 42b5fe |
0x42adc3 IMUL %ECX,%R8D |
0x42adc7 LEA (%R8,%RDX,1),%R9D |
0x42adcb LEA (%RCX,%R9,1),%R10D |
0x42adcf MOV %R10D,0x68(%RSP) |
0x42add4 CMP %R10D,%R9D |
0x42add7 JAE 42b5db |
0x42addd MOV %R9D,%EAX |
0x42ade0 XOR %EDX,%EDX |
0x42ade2 MOV 0x6c(%RSP),%R11D |
0x42ade7 MOV (%RBX),%RDI |
0x42adea DIVL 0x74(%RSP) |
0x42adee MOV 0x10(%RBX),%R14 |
0x42adf2 MOV 0x8(%RBX),%RSI |
0x42adf6 MOV %R9D,0xfc(%RSP) |
0x42adfe VMOVSD 0x37ac2(%RIP),%XMM3 |
0x42ae06 MOV %RDI,0x40(%RSP) |
0x42ae0b MOV %R14,0x30(%RSP) |
0x42ae10 MOV %RSI,0x28(%RSP) |
0x42ae15 MOV %R15D,%R8D |
0x42ae18 MOV 0x20(%RBX),%R15 |
0x42ae1c MOV 0x18(%RBX),%RBX |
0x42ae20 VBROADCASTSD %XMM3,%YMM4 |
0x42ae25 VBROADCASTSD %XMM3,%ZMM2 |
0x42ae2b MOV %R15,0x38(%RSP) |
0x42ae30 MOV %RBX,0x20(%RSP) |
0x42ae35 ADD %R12D,%EAX |
0x42ae38 ADD %EDX,%R11D |
0x42ae3b MOVSXD %EAX,%R12 |
0x42ae3e MOV %R11D,0xf8(%RSP) |
0x42ae46 SUB %R11D,%R8D |
0x42ae49 MOV %EAX,0xb4(%RSP) |
0x42ae50 MOV %R12,0x98(%RSP) |
0x42ae58 NOPL (%RAX,%RAX,1) |
(134) 0x42ae60 CMP %R8D,%ECX |
(134) 0x42ae63 CMOVBE %ECX,%R8D |
(134) 0x42ae67 MOV 0xfc(%RSP),%ECX |
(134) 0x42ae6e LEA (%RCX,%R8,1),%R13D |
(134) 0x42ae72 MOV %R8D,%R9D |
(134) 0x42ae75 MOV %R13D,0xb0(%RSP) |
(134) 0x42ae7d CMP %R13D,%ECX |
(134) 0x42ae80 JAE 42b58f |
(134) 0x42ae86 MOV 0xb4(%RSP),%R8D |
(134) 0x42ae8e MOV 0x40(%RSP),%RAX |
(134) 0x42ae93 MOV 0x38(%RSP),%RDI |
(134) 0x42ae98 MOV 0x98(%RSP),%R15 |
(134) 0x42aea0 LEA -0x1(%R8),%R10D |
(134) 0x42aea4 MOV 0x30(%RSP),%RSI |
(134) 0x42aea9 MOV 0x10(%RAX),%R13 |
(134) 0x42aead MOV (%RDI),%RCX |
(134) 0x42aeb0 MOVSXD %R10D,%R11 |
(134) 0x42aeb3 MOV (%RAX),%R10 |
(134) 0x42aeb6 MOV %R15,%RAX |
(134) 0x42aeb9 MOV %R11,%R14 |
(134) 0x42aebc MOV 0x28(%RSP),%R8 |
(134) 0x42aec1 MOV 0x10(%RDI),%RDX |
(134) 0x42aec5 IMUL %R10,%R14 |
(134) 0x42aec9 MOV 0x10(%RSI),%RBX |
(134) 0x42aecd IMUL %RCX,%R11 |
(134) 0x42aed1 MOV (%R8),%RDI |
(134) 0x42aed4 IMUL %R15,%R10 |
(134) 0x42aed8 MOV %RBX,0xe0(%RSP) |
(134) 0x42aee0 LEA -0x1(%R9),%EBX |
(134) 0x42aee4 IMUL %R15,%RCX |
(134) 0x42aee8 MOV %R14,0xb8(%RSP) |
(134) 0x42aef0 IMUL (%RSI),%R15 |
(134) 0x42aef4 MOV %R11,0xc0(%RSP) |
(134) 0x42aefc IMUL %RAX,%RDI |
(134) 0x42af00 MOV %R10,0xc8(%RSP) |
(134) 0x42af08 MOV %RCX,0xd0(%RSP) |
(134) 0x42af10 MOV %R15,0xd8(%RSP) |
(134) 0x42af18 MOV 0x10(%R8),%R15 |
(134) 0x42af1c MOV 0x20(%RSP),%R8 |
(134) 0x42af21 MOV %RDI,0xf0(%RSP) |
(134) 0x42af29 MOV (%R8),%R12 |
(134) 0x42af2c MOV 0x10(%R8),%RSI |
(134) 0x42af30 IMUL %RAX,%R12 |
(134) 0x42af34 MOV %RSI,0xe8(%RSP) |
(134) 0x42af3c MOV %R12,0xa8(%RSP) |
(134) 0x42af44 CMP $0x6,%EBX |
(134) 0x42af47 JBE 42b5f0 |
(134) 0x42af4d MOVSXD 0xf8(%RSP),%RAX |
(134) 0x42af55 LEA (%R11,%RAX,1),%RDI |
(134) 0x42af59 ADD %RAX,%RCX |
(134) 0x42af5c LEA (%R14,%RAX,1),%R8 |
(134) 0x42af60 SAL $0x3,%RDI |
(134) 0x42af64 SAL $0x3,%RCX |
(134) 0x42af68 LEA (%R10,%RAX,1),%RBX |
(134) 0x42af6c LEA (%RDX,%RDI,1),%R11 |
(134) 0x42af70 SAL $0x3,%R8 |
(134) 0x42af74 LEA (%RDX,%RCX,1),%R10 |
(134) 0x42af78 SAL $0x3,%RBX |
(134) 0x42af7c MOV %R11,0x80(%RSP) |
(134) 0x42af84 LEA -0x8(%RDX,%RCX,1),%R11 |
(134) 0x42af89 MOV 0xd8(%RSP),%RCX |
(134) 0x42af91 LEA (%R13,%R8,1),%R14 |
(134) 0x42af96 LEA -0x8(%R13,%R8,1),%RSI |
(134) 0x42af9b MOV %R10,0x88(%RSP) |
(134) 0x42afa3 MOV 0xe0(%RSP),%R8 |
(134) 0x42afab LEA -0x8(%RDX,%RDI,1),%R10 |
(134) 0x42afb0 MOV 0xf0(%RSP),%RDI |
(134) 0x42afb8 ADD %RAX,%RCX |
(134) 0x42afbb MOV %RSI,0x90(%RSP) |
(134) 0x42afc3 MOV 0xe8(%RSP),%RSI |
(134) 0x42afcb LEA (%R8,%RCX,8),%R8 |
(134) 0x42afcf MOV %R14,0x78(%RSP) |
(134) 0x42afd4 LEA (%R13,%RBX,1),%R14 |
(134) 0x42afd9 LEA (%RDI,%RAX,1),%RCX |
(134) 0x42afdd ADD %R12,%RAX |
(134) 0x42afe0 LEA -0x8(%R13,%RBX,1),%RBX |
(134) 0x42afe5 LEA (%RSI,%RAX,8),%RSI |
(134) 0x42afe9 MOV %R9D,%EAX |
(134) 0x42afec SAL $0x3,%RCX |
(134) 0x42aff0 SHR $0x3,%EAX |
(134) 0x42aff3 LEA -0x8(%R15,%RCX,1),%RDI |
(134) 0x42aff8 ADD %R15,%RCX |
(134) 0x42affb MOV %RAX,%R12 |
(134) 0x42affe SAL $0x6,%RAX |
(134) 0x42b002 MOV %RAX,0xa0(%RSP) |
(134) 0x42b00a XOR %EAX,%EAX |
(134) 0x42b00c AND $0x1,%R12D |
(134) 0x42b010 JE 42b0a4 |
(134) 0x42b016 MOV 0x88(%RSP),%RAX |
(134) 0x42b01e VMOVUPD (%R11),%ZMM5 |
(134) 0x42b024 MOV 0x80(%RSP),%R12 |
(134) 0x42b02c VMOVUPD (%R10),%ZMM8 |
(134) 0x42b032 VMOVUPD (%RAX),%ZMM7 |
(134) 0x42b038 VMULPD (%RBX),%ZMM5,%ZMM1 |
(134) 0x42b03e VMOVUPD (%R12),%ZMM6 |
(134) 0x42b045 MOV 0x78(%RSP),%RAX |
(134) 0x42b04a VMULPD (%R14),%ZMM7,%ZMM0 |
(134) 0x42b050 MOV 0xa0(%RSP),%R12 |
(134) 0x42b058 VFMADD231PD (%RAX),%ZMM6,%ZMM0 |
(134) 0x42b05e MOV 0x90(%RSP),%RAX |
(134) 0x42b066 VFMADD231PD (%RAX),%ZMM8,%ZMM1 |
(134) 0x42b06c MOV $0x40,%EAX |
(134) 0x42b071 VADDPD %ZMM1,%ZMM0,%ZMM9 |
(134) 0x42b077 VMULPD %ZMM2,%ZMM9,%ZMM10 |
(134) 0x42b07d VMOVUPD %ZMM10,(%R8) |
(134) 0x42b083 VMOVUPD (%RCX),%ZMM11 |
(134) 0x42b089 VSUBPD (%RDI),%ZMM11,%ZMM12 |
(134) 0x42b08f VADDPD %ZMM10,%ZMM12,%ZMM13 |
(134) 0x42b095 VMOVUPD %ZMM13,(%RSI) |
(134) 0x42b09b CMP %R12,%RAX |
(134) 0x42b09e JE 42b1d7 |
(134) 0x42b0a4 MOV %R15,0x58(%RSP) |
(134) 0x42b0a9 MOV 0x80(%RSP),%R12 |
(134) 0x42b0b1 MOV %R9D,0x64(%RSP) |
(134) 0x42b0b6 MOV 0x88(%RSP),%R9 |
(134) 0x42b0be MOV %RDX,0x50(%RSP) |
(134) 0x42b0c3 MOV 0x90(%RSP),%RDX |
(134) 0x42b0cb MOV %R13,0x48(%RSP) |
(134) 0x42b0d0 MOV 0x78(%RSP),%R13 |
(135) 0x42b0d5 VMOVUPD (%R9,%RAX,1),%ZMM14 |
(135) 0x42b0dc VMOVUPD (%R11,%RAX,1),%ZMM0 |
(135) 0x42b0e3 VMOVUPD (%R12,%RAX,1),%ZMM7 |
(135) 0x42b0ea VMOVUPD (%R10,%RAX,1),%ZMM5 |
(135) 0x42b0f1 VMULPD (%R14,%RAX,1),%ZMM14,%ZMM15 |
(135) 0x42b0f8 MOV 0xa0(%RSP),%R15 |
(135) 0x42b100 VMULPD (%RBX,%RAX,1),%ZMM0,%ZMM6 |
(135) 0x42b107 VFMADD231PD (%R13,%RAX,1),%ZMM7,%ZMM15 |
(135) 0x42b10f VFMADD231PD (%RDX,%RAX,1),%ZMM5,%ZMM6 |
(135) 0x42b116 VADDPD %ZMM6,%ZMM15,%ZMM1 |
(135) 0x42b11c VMULPD %ZMM2,%ZMM1,%ZMM8 |
(135) 0x42b122 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(135) 0x42b129 VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(135) 0x42b130 VSUBPD (%RDI,%RAX,1),%ZMM9,%ZMM10 |
(135) 0x42b137 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(135) 0x42b13d VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(135) 0x42b144 VMOVUPD 0x40(%R9,%RAX,1),%ZMM12 |
(135) 0x42b14c VMOVUPD 0x40(%R11,%RAX,1),%ZMM15 |
(135) 0x42b154 VMOVUPD 0x40(%R12,%RAX,1),%ZMM14 |
(135) 0x42b15c VMOVUPD 0x40(%R10,%RAX,1),%ZMM7 |
(135) 0x42b164 VMULPD 0x40(%R14,%RAX,1),%ZMM12,%ZMM13 |
(135) 0x42b16c VMULPD 0x40(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(135) 0x42b174 VFMADD231PD 0x40(%R13,%RAX,1),%ZMM14,%ZMM13 |
(135) 0x42b17c VFMADD231PD 0x40(%RDX,%RAX,1),%ZMM7,%ZMM0 |
(135) 0x42b184 VADDPD %ZMM0,%ZMM13,%ZMM6 |
(135) 0x42b18a VMULPD %ZMM2,%ZMM6,%ZMM8 |
(135) 0x42b190 VMOVUPD %ZMM8,0x40(%R8,%RAX,1) |
(135) 0x42b198 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM5 |
(135) 0x42b1a0 VSUBPD 0x40(%RDI,%RAX,1),%ZMM5,%ZMM1 |
(135) 0x42b1a8 VADDPD %ZMM8,%ZMM1,%ZMM9 |
(135) 0x42b1ae VMOVUPD %ZMM9,0x40(%RSI,%RAX,1) |
(135) 0x42b1b6 SUB $-0x80,%RAX |
(135) 0x42b1ba CMP %R15,%RAX |
(135) 0x42b1bd JNE 42b0d5 |
(134) 0x42b1c3 MOV 0x64(%RSP),%R9D |
(134) 0x42b1c8 MOV 0x58(%RSP),%R15 |
(134) 0x42b1cd MOV 0x50(%RSP),%RDX |
(134) 0x42b1d2 MOV 0x48(%RSP),%R13 |
(134) 0x42b1d7 MOV 0xf8(%RSP),%EAX |
(134) 0x42b1de MOV %R9D,%ESI |
(134) 0x42b1e1 AND $-0x8,%ESI |
(134) 0x42b1e4 ADD %ESI,0xfc(%RSP) |
(134) 0x42b1eb ADD %ESI,%EAX |
(134) 0x42b1ed TEST $0x7,%R9B |
(134) 0x42b1f1 JE 42b57f |
(134) 0x42b1f7 MOV %R9D,%EDI |
(134) 0x42b1fa SUB %ESI,%EDI |
(134) 0x42b1fc LEA -0x1(%RDI),%R14D |
(134) 0x42b200 CMP $0x2,%R14D |
(134) 0x42b204 JBE 42b2f9 |
(134) 0x42b20a MOVSXD 0xf8(%RSP),%RCX |
(134) 0x42b212 MOV 0xc0(%RSP),%RBX |
(134) 0x42b21a MOV 0xc8(%RSP),%R11 |
(134) 0x42b222 MOV 0xb8(%RSP),%R10 |
(134) 0x42b22a LEA (%RBX,%RCX,1),%R9 |
(134) 0x42b22e MOV 0xd0(%RSP),%RBX |
(134) 0x42b236 MOV 0xd8(%RSP),%R8 |
(134) 0x42b23e LEA (%R11,%RCX,1),%R11 |
(134) 0x42b242 LEA (%R10,%RCX,1),%R10 |
(134) 0x42b246 ADD %RSI,%R9 |
(134) 0x42b249 MOV 0xf0(%RSP),%R14 |
(134) 0x42b251 ADD %RCX,%RBX |
(134) 0x42b254 ADD %RSI,%R11 |
(134) 0x42b257 LEA (%R8,%RCX,1),%R12 |
(134) 0x42b25b ADD %RSI,%R10 |
(134) 0x42b25e ADD %RSI,%RBX |
(134) 0x42b261 VMOVUPD (%R13,%R11,8),%YMM10 |
(134) 0x42b268 VMOVUPD (%R13,%R10,8),%YMM12 |
(134) 0x42b26f LEA (%R14,%RCX,1),%R8 |
(134) 0x42b273 VMOVUPD -0x8(%RDX,%RBX,8),%YMM13 |
(134) 0x42b279 VMOVUPD -0x8(%R13,%R10,8),%YMM15 |
(134) 0x42b280 ADD %RSI,%R8 |
(134) 0x42b283 ADD %RSI,%R12 |
(134) 0x42b286 VMULPD (%RDX,%RBX,8),%YMM10,%YMM11 |
(134) 0x42b28b MOV 0xa8(%RSP),%R14 |
(134) 0x42b293 VMULPD -0x8(%R13,%R11,8),%YMM13,%YMM14 |
(134) 0x42b29a MOV 0xe8(%RSP),%R10 |
(134) 0x42b2a2 ADD %R14,%RCX |
(134) 0x42b2a5 ADD %RSI,%RCX |
(134) 0x42b2a8 MOV 0xe0(%RSP),%RSI |
(134) 0x42b2b0 VFMADD231PD (%RDX,%R9,8),%YMM12,%YMM11 |
(134) 0x42b2b6 VFMADD231PD -0x8(%RDX,%R9,8),%YMM15,%YMM14 |
(134) 0x42b2bd VADDPD %YMM14,%YMM11,%YMM0 |
(134) 0x42b2c2 VMULPD %YMM4,%YMM0,%YMM6 |
(134) 0x42b2c6 VMOVUPD %YMM6,(%RSI,%R12,8) |
(134) 0x42b2cc VMOVUPD (%R15,%R8,8),%YMM7 |
(134) 0x42b2d2 VSUBPD -0x8(%R15,%R8,8),%YMM7,%YMM8 |
(134) 0x42b2d9 VADDPD %YMM6,%YMM8,%YMM5 |
(134) 0x42b2dd VMOVUPD %YMM5,(%R10,%RCX,8) |
(134) 0x42b2e3 TEST $0x3,%DIL |
(134) 0x42b2e7 JE 42b57f |
(134) 0x42b2ed AND $-0x4,%EDI |
(134) 0x42b2f0 ADD %EDI,0xfc(%RSP) |
(134) 0x42b2f7 ADD %EDI,%EAX |
(134) 0x42b2f9 MOV 0xc8(%RSP),%R12 |
(134) 0x42b301 MOVSXD %EAX,%RCX |
(134) 0x42b304 MOV 0xb8(%RSP),%RDI |
(134) 0x42b30c MOV 0xc0(%RSP),%RBX |
(134) 0x42b314 LEA (%R12,%RCX,1),%R14 |
(134) 0x42b318 LEA (%RDI,%RCX,1),%R9 |
(134) 0x42b31c LEA (%R13,%R14,8),%R10 |
(134) 0x42b321 MOV 0xd0(%RSP),%R14 |
(134) 0x42b329 LEA (%RBX,%RCX,1),%R11 |
(134) 0x42b32d LEA (%R13,%R9,8),%R8 |
(134) 0x42b332 LEA (%RDX,%R11,8),%R9 |
(134) 0x42b336 LEA (%R14,%RCX,1),%RSI |
(134) 0x42b33a VMOVSD (%R9),%XMM10 |
(134) 0x42b33f LEA (%RDX,%RSI,8),%R11 |
(134) 0x42b343 LEA -0x1(%RAX),%ESI |
(134) 0x42b346 MOVSXD %ESI,%RSI |
(134) 0x42b349 VMOVSD (%R11),%XMM1 |
(134) 0x42b34e ADD %RSI,%R14 |
(134) 0x42b351 ADD %RSI,%R12 |
(134) 0x42b354 ADD %RSI,%RBX |
(134) 0x42b357 ADD %RSI,%RDI |
(134) 0x42b35a VMOVSD (%RDX,%R14,8),%XMM11 |
(134) 0x42b360 VMULSD (%R10),%XMM1,%XMM9 |
(134) 0x42b365 VMOVSD (%RDX,%RBX,8),%XMM13 |
(134) 0x42b36a MOV 0xf0(%RSP),%R14 |
(134) 0x42b372 VMULSD (%R13,%R12,8),%XMM11,%XMM12 |
(134) 0x42b379 MOV 0xe0(%RSP),%RBX |
(134) 0x42b381 ADD %R14,%RSI |
(134) 0x42b384 VFMADD231SD (%R8),%XMM10,%XMM9 |
(134) 0x42b389 VFMADD231SD (%R13,%RDI,8),%XMM13,%XMM12 |
(134) 0x42b390 MOV 0xd8(%RSP),%RDI |
(134) 0x42b398 LEA (%RDI,%RCX,1),%R12 |
(134) 0x42b39c LEA (%R14,%RCX,1),%RDI |
(134) 0x42b3a0 MOV 0xb0(%RSP),%R14D |
(134) 0x42b3a8 LEA (%R15,%RDI,8),%RDI |
(134) 0x42b3ac VADDSD %XMM12,%XMM9,%XMM14 |
(134) 0x42b3b1 VMULSD %XMM3,%XMM14,%XMM15 |
(134) 0x42b3b5 VMOVSD %XMM15,(%RBX,%R12,8) |
(134) 0x42b3bb MOV 0xa8(%RSP),%R12 |
(134) 0x42b3c3 MOV 0xfc(%RSP),%EBX |
(134) 0x42b3ca VMOVSD (%RDI),%XMM0 |
(134) 0x42b3ce ADD %R12,%RCX |
(134) 0x42b3d1 INC %EBX |
(134) 0x42b3d3 VSUBSD (%R15,%RSI,8),%XMM0,%XMM6 |
(134) 0x42b3d9 MOV 0xe8(%RSP),%RSI |
(134) 0x42b3e1 VADDSD %XMM15,%XMM6,%XMM7 |
(134) 0x42b3e6 VMOVSD %XMM7,(%RSI,%RCX,8) |
(134) 0x42b3eb LEA 0x1(%RAX),%ECX |
(134) 0x42b3ee CMP %R14D,%EBX |
(134) 0x42b3f1 JAE 42b57f |
(134) 0x42b3f7 MOV 0xb8(%RSP),%R12 |
(134) 0x42b3ff MOVSXD %ECX,%RCX |
(134) 0x42b402 MOV 0xc0(%RSP),%R14 |
(134) 0x42b40a ADD $0x2,%EAX |
(134) 0x42b40d VMOVSD (%R11),%XMM9 |
(134) 0x42b412 VMOVSD (%R9),%XMM11 |
(134) 0x42b417 LEA (%R12,%RCX,1),%RSI |
(134) 0x42b41b MOV 0xc8(%RSP),%R12 |
(134) 0x42b423 ADD %RCX,%R14 |
(134) 0x42b426 MOV 0xf0(%RSP),%R11 |
(134) 0x42b42e LEA (%R13,%RSI,8),%RBX |
(134) 0x42b433 LEA (%RDX,%R14,8),%RSI |
(134) 0x42b437 VMULSD (%R10),%XMM9,%XMM10 |
(134) 0x42b43c MOV 0xe0(%RSP),%R10 |
(134) 0x42b444 ADD %RCX,%R12 |
(134) 0x42b447 VMOVSD (%RSI),%XMM1 |
(134) 0x42b44b LEA (%R13,%R12,8),%R14 |
(134) 0x42b450 MOV 0xd0(%RSP),%R12 |
(134) 0x42b458 ADD %RCX,%R12 |
(134) 0x42b45b LEA (%RDX,%R12,8),%R12 |
(134) 0x42b45f VFMADD231SD (%R8),%XMM11,%XMM10 |
(134) 0x42b464 MOV 0xd8(%RSP),%R8 |
(134) 0x42b46c VMOVSD (%R12),%XMM8 |
(134) 0x42b472 LEA (%R8,%RCX,1),%R9 |
(134) 0x42b476 LEA (%R11,%RCX,1),%R8 |
(134) 0x42b47a VMULSD (%R14),%XMM8,%XMM5 |
(134) 0x42b47f LEA (%R15,%R8,8),%R8 |
(134) 0x42b483 VFMADD132SD (%RBX),%XMM5,%XMM1 |
(134) 0x42b488 VADDSD %XMM1,%XMM10,%XMM12 |
(134) 0x42b48c VMULSD %XMM3,%XMM12,%XMM13 |
(134) 0x42b490 VMOVSD %XMM13,(%R10,%R9,8) |
(134) 0x42b496 MOV 0xa8(%RSP),%R9 |
(134) 0x42b49e MOV 0xb0(%RSP),%R10D |
(134) 0x42b4a6 VMOVSD (%R8),%XMM14 |
(134) 0x42b4ab ADD %R9,%RCX |
(134) 0x42b4ae VSUBSD (%RDI),%XMM14,%XMM15 |
(134) 0x42b4b2 MOV 0xe8(%RSP),%RDI |
(134) 0x42b4ba VADDSD %XMM13,%XMM15,%XMM0 |
(134) 0x42b4bf VMOVSD %XMM0,(%RDI,%RCX,8) |
(134) 0x42b4c4 MOV 0xfc(%RSP),%ECX |
(134) 0x42b4cb ADD $0x2,%ECX |
(134) 0x42b4ce CMP %R10D,%ECX |
(134) 0x42b4d1 JAE 42b57f |
(134) 0x42b4d7 MOV 0xd0(%RSP),%R9 |
(134) 0x42b4df CLTQ |
(134) 0x42b4e1 MOV 0xc8(%RSP),%R10 |
(134) 0x42b4e9 VMOVSD (%R14),%XMM5 |
(134) 0x42b4ee MOV 0xc0(%RSP),%RCX |
(134) 0x42b4f6 ADD %RAX,%R11 |
(134) 0x42b4f9 ADD %RAX,%R9 |
(134) 0x42b4fc ADD %RAX,%R10 |
(134) 0x42b4ff MOV 0xb8(%RSP),%RDI |
(134) 0x42b507 VMOVSD (%RBX),%XMM9 |
(134) 0x42b50b VMOVSD (%RDX,%R9,8),%XMM6 |
(134) 0x42b511 VMULSD (%R12),%XMM5,%XMM1 |
(134) 0x42b517 ADD %RAX,%RCX |
(134) 0x42b51a VMOVSD (%RDX,%RCX,8),%XMM7 |
(134) 0x42b51f ADD %RAX,%RDI |
(134) 0x42b522 MOV 0xd8(%RSP),%RDX |
(134) 0x42b52a VMULSD (%R13,%R10,8),%XMM6,%XMM8 |
(134) 0x42b531 MOV 0xa8(%RSP),%RBX |
(134) 0x42b539 ADD %RAX,%RDX |
(134) 0x42b53c ADD %RAX,%RBX |
(134) 0x42b53f MOV 0xe8(%RSP),%RAX |
(134) 0x42b547 VFMADD231SD (%RSI),%XMM9,%XMM1 |
(134) 0x42b54c VFMADD231SD (%R13,%RDI,8),%XMM7,%XMM8 |
(134) 0x42b553 MOV 0xe0(%RSP),%R13 |
(134) 0x42b55b VADDSD %XMM1,%XMM8,%XMM10 |
(134) 0x42b55f VMULSD %XMM3,%XMM10,%XMM11 |
(134) 0x42b563 VMOVSD %XMM11,(%R13,%RDX,8) |
(134) 0x42b56a VMOVSD (%R15,%R11,8),%XMM12 |
(134) 0x42b570 VSUBSD (%R8),%XMM12,%XMM13 |
(134) 0x42b575 VADDSD %XMM11,%XMM13,%XMM14 |
(134) 0x42b57a VMOVSD %XMM14,(%RAX,%RBX,8) |
(134) 0x42b57f MOV 0xb0(%RSP),%R15D |
(134) 0x42b587 MOV %R15D,0xfc(%RSP) |
(134) 0x42b58f INCL 0xb4(%RSP) |
(134) 0x42b596 INCQ 0x98(%RSP) |
(134) 0x42b59e MOV 0xb4(%RSP),%ESI |
(134) 0x42b5a5 CMP %ESI,0x70(%RSP) |
(134) 0x42b5a9 JLE 42b5d8 |
(134) 0x42b5ab MOV 0x68(%RSP),%ECX |
(134) 0x42b5af MOV 0xfc(%RSP),%R14D |
(134) 0x42b5b7 MOV 0x6c(%RSP),%R12D |
(134) 0x42b5bc MOV 0x74(%RSP),%R8D |
(134) 0x42b5c1 SUB %R14D,%ECX |
(134) 0x42b5c4 MOV %R12D,0xf8(%RSP) |
(134) 0x42b5cc JMP 42ae60 |
0x42b5d1 NOPL (%RAX) |
0x42b5d8 VZEROUPPER |
0x42b5db LEA -0x28(%RBP),%RSP |
0x42b5df POP %RBX |
0x42b5e0 POP %R12 |
0x42b5e2 POP %R13 |
0x42b5e4 POP %R14 |
0x42b5e6 POP %R15 |
0x42b5e8 POP %RBP |
0x42b5e9 RET |
0x42b5ea NOPW (%RAX,%RAX,1) |
(134) 0x42b5f0 MOV 0xf8(%RSP),%EAX |
(134) 0x42b5f7 XOR %ESI,%ESI |
(134) 0x42b5f9 JMP 42b1f7 |
0x42b5fe INC %ECX |
0x42b600 XOR %EDX,%EDX |
0x42b602 JMP 42adc3 |
0x42b607 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 337 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b5fe <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b5db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x37ac2(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42adc3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 337 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b5fe <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b5db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x37ac2(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42adc3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5– | 3.07 | 2.3 |
▼Loop 134 - advec_mom.cpp:97-100 - exec– | 0 | 0 |
○Loop 135 - advec_mom.cpp:98-100 - exec | 3.07 | 2.29 |