Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 3.07% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 3.07% |
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/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
48: pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-145-9336/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x428e60 PUSH %RBP |
0x428e61 MOV %RSP,%RBP |
0x428e64 PUSH %R15 |
0x428e66 PUSH %R14 |
0x428e68 PUSH %R13 |
0x428e6a PUSH %R12 |
0x428e6c MOV %RDI,%R12 |
0x428e6f PUSH %RBX |
0x428e70 AND $-0x40,%RSP |
0x428e74 SUB $0xc0,%RSP |
0x428e7b MOV 0x30(%RDI),%EAX |
0x428e7e MOV 0x34(%RDI),%EDX |
0x428e81 MOV 0x28(%RDI),%ESI |
0x428e84 MOV 0x2c(%R12),%ECX |
0x428e89 ADD $0x4,%EDX |
0x428e8c LEA -0x1(%RAX),%R15D |
0x428e90 LEA -0x1(%RSI),%EDI |
0x428e93 MOV %EDX,0x60(%RSP) |
0x428e97 MOV %EDI,0x5c(%RSP) |
0x428e9b CMP %EDX,%R15D |
0x428e9e JGE 4294fb |
0x428ea4 MOV %EDX,%EBX |
0x428ea6 LEA 0x4(%RCX),%R14D |
0x428eaa SUB %R15D,%EBX |
0x428ead CMP %R14D,%EDI |
0x428eb0 JGE 4294fb |
0x428eb6 MOV %R14D,%R8D |
0x428eb9 SUB %EDI,%R8D |
0x428ebc MOV %R8D,0x64(%RSP) |
0x428ec1 CALL 4046c0 <omp_get_num_threads@plt> |
0x428ec6 MOV %EAX,%R13D |
0x428ec9 CALL 4045b0 <omp_get_thread_num@plt> |
0x428ece XOR %EDX,%EDX |
0x428ed0 MOV %EAX,%R9D |
0x428ed3 MOV 0x64(%RSP),%EAX |
0x428ed7 IMUL %EBX,%EAX |
0x428eda DIV %R13D |
0x428edd MOV %EAX,%R13D |
0x428ee0 CMP %EDX,%R9D |
0x428ee3 JB 429530 |
0x428ee9 IMUL %R13D,%R9D |
0x428eed LEA (%R9,%RDX,1),%EDI |
0x428ef1 LEA (%R13,%RDI,1),%R10D |
0x428ef6 MOV %R10D,0x58(%RSP) |
0x428efb CMP %R10D,%EDI |
0x428efe JAE 4294fb |
0x428f04 MOV %EDI,%EAX |
0x428f06 XOR %EDX,%EDX |
0x428f08 MOV 0x5c(%RSP),%R11D |
0x428f0d MOV (%R12),%R8 |
0x428f11 DIVL 0x64(%RSP) |
0x428f15 MOV 0x10(%R12),%RSI |
0x428f1a MOV 0x20(%R12),%RBX |
0x428f1f MOV %R8,0x38(%RSP) |
0x428f24 MOV %RSI,0x50(%RSP) |
0x428f29 MOV %RBX,0x40(%RSP) |
0x428f2e ADD %EDX,%R11D |
0x428f31 MOV %R14D,%EDX |
0x428f34 MOV 0x8(%R12),%R14 |
0x428f39 MOV 0x18(%R12),%R12 |
0x428f3e MOV %R11D,0xb4(%RSP) |
0x428f46 LEA (%RAX,%R15,1),%R15D |
0x428f4a SUB %R11D,%EDX |
0x428f4d MOV %R14,0x48(%RSP) |
0x428f52 MOVSXD %R15D,%R8 |
0x428f55 MOV %R12,0x30(%RSP) |
0x428f5a NOPW (%RAX,%RAX,1) |
(124) 0x428f60 CMP %EDX,%R13D |
(124) 0x428f63 CMOVBE %R13D,%EDX |
(124) 0x428f67 LEA (%RDI,%RDX,1),%ECX |
(124) 0x428f6a MOV %ECX,0xb0(%RSP) |
(124) 0x428f71 CMP %ECX,%EDI |
(124) 0x428f73 JAE 429510 |
(124) 0x428f79 MOV 0x48(%RSP),%R10 |
(124) 0x428f7e LEA 0x1(%R8),%R14 |
(124) 0x428f82 MOV 0x50(%RSP),%R9 |
(124) 0x428f87 MOV %R14,0x68(%RSP) |
(124) 0x428f8c MOV 0x40(%RSP),%R11 |
(124) 0x428f91 MOV (%R10),%RAX |
(124) 0x428f94 MOV 0x10(%R9),%R13 |
(124) 0x428f98 MOV (%R9),%R15 |
(124) 0x428f9b MOV 0x10(%R10),%RCX |
(124) 0x428f9f IMUL %RAX,%R14 |
(124) 0x428fa3 MOV 0x38(%RSP),%R9 |
(124) 0x428fa8 MOV 0x10(%R11),%R12 |
(124) 0x428fac MOV %R13,0xa0(%RSP) |
(124) 0x428fb4 MOV (%R11),%R11 |
(124) 0x428fb7 IMUL %R8,%R15 |
(124) 0x428fbb MOV 0x10(%R9),%RSI |
(124) 0x428fbf MOV (%R9),%R9 |
(124) 0x428fc2 MOV %R12,0xa8(%RSP) |
(124) 0x428fca MOV %R14,%RBX |
(124) 0x428fcd IMUL %R8,%R11 |
(124) 0x428fd1 MOV %R14,0x78(%RSP) |
(124) 0x428fd6 SUB %RAX,%RBX |
(124) 0x428fd9 MOV 0x30(%RSP),%RAX |
(124) 0x428fde IMUL %R8,%R9 |
(124) 0x428fe2 MOV %R15,0x70(%RSP) |
(124) 0x428fe7 MOV %RBX,0x80(%RSP) |
(124) 0x428fef MOV 0x10(%RAX),%R10 |
(124) 0x428ff3 MOV %R11,0x88(%RSP) |
(124) 0x428ffb MOV %R9,0x90(%RSP) |
(124) 0x429003 MOV %R10,0xb8(%RSP) |
(124) 0x42900b MOV (%RAX),%R10 |
(124) 0x42900e IMUL %R8,%R10 |
(124) 0x429012 LEA -0x1(%RDX),%R8D |
(124) 0x429016 MOV %R10,0x98(%RSP) |
(124) 0x42901e CMP $0x6,%R8D |
(124) 0x429022 JBE 429520 |
(124) 0x429028 MOVSXD 0xb4(%RSP),%RAX |
(124) 0x429030 LEA 0x1(%R9,%RAX,1),%R8 |
(124) 0x429035 MOV %EDX,%R9D |
(124) 0x429038 LEA (%RBX,%RAX,1),%RBX |
(124) 0x42903c SHR $0x3,%R9D |
(124) 0x429040 LEA (%R11,%RAX,1),%R11 |
(124) 0x429044 SAL $0x3,%R8 |
(124) 0x429048 LEA (%R15,%RAX,1),%R15 |
(124) 0x42904c SAL $0x6,%R9 |
(124) 0x429050 LEA (%R13,%R15,8),%R15 |
(124) 0x429055 LEA (%R12,%R11,8),%R12 |
(124) 0x429059 LEA (%RCX,%RBX,8),%R13 |
(124) 0x42905d LEA -0x8(%RSI,%R8,1),%R11 |
(124) 0x429062 LEA (%RSI,%R8,1),%RBX |
(124) 0x429066 LEA -0x40(%R9),%R8 |
(124) 0x42906a LEA (%R14,%RAX,1),%R14 |
(124) 0x42906e SHR $0x6,%R8 |
(124) 0x429072 ADD %R10,%RAX |
(124) 0x429075 MOV 0xb8(%RSP),%R10 |
(124) 0x42907d INC %R8 |
(124) 0x429080 LEA (%RCX,%R14,8),%R14 |
(124) 0x429084 LEA (%R10,%RAX,8),%R10 |
(124) 0x429088 XOR %EAX,%EAX |
(124) 0x42908a AND $0x3,%R8D |
(124) 0x42908e JE 429158 |
(124) 0x429094 CMP $0x1,%R8 |
(124) 0x429098 JE 429113 |
(124) 0x42909a CMP $0x2,%R8 |
(124) 0x42909e JE 4290d7 |
(124) 0x4290a0 VMOVUPD (%R14),%ZMM7 |
(124) 0x4290a6 MOV $0x40,%EAX |
(124) 0x4290ab VADDPD (%R15),%ZMM7,%ZMM0 |
(124) 0x4290b1 VSUBPD (%R13),%ZMM0,%ZMM2 |
(124) 0x4290b8 VMOVUPD %ZMM2,(%R12) |
(124) 0x4290bf VMOVUPD (%RBX),%ZMM1 |
(124) 0x4290c5 VSUBPD (%R11),%ZMM1,%ZMM3 |
(124) 0x4290cb VADDPD %ZMM2,%ZMM3,%ZMM4 |
(124) 0x4290d1 VMOVUPD %ZMM4,(%R10) |
(124) 0x4290d7 VMOVUPD (%R14,%RAX,1),%ZMM5 |
(124) 0x4290de VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(124) 0x4290e5 VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(124) 0x4290ed VMOVUPD %ZMM8,(%R12,%RAX,1) |
(124) 0x4290f4 VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(124) 0x4290fb VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(124) 0x429102 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(124) 0x429108 VMOVUPD %ZMM11,(%R10,%RAX,1) |
(124) 0x42910f ADD $0x40,%RAX |
(124) 0x429113 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(124) 0x42911a VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(124) 0x429121 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(124) 0x429129 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(124) 0x429130 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(124) 0x429137 VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(124) 0x42913e VADDPD %ZMM14,%ZMM7,%ZMM0 |
(124) 0x429144 VMOVUPD %ZMM0,(%R10,%RAX,1) |
(124) 0x42914b ADD $0x40,%RAX |
(124) 0x42914f CMP %RAX,%R9 |
(124) 0x429152 JE 429259 |
(125) 0x429158 VMOVUPD (%R14,%RAX,1),%ZMM2 |
(125) 0x42915f VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(125) 0x429166 VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(125) 0x42916e VMOVUPD %ZMM3,(%R12,%RAX,1) |
(125) 0x429175 VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(125) 0x42917c VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(125) 0x429183 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(125) 0x429189 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(125) 0x429190 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(125) 0x429198 VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(125) 0x4291a0 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(125) 0x4291a8 VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(125) 0x4291b0 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(125) 0x4291b8 VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(125) 0x4291c0 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(125) 0x4291c6 VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(125) 0x4291ce VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(125) 0x4291d6 VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(125) 0x4291de VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(125) 0x4291e6 VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(125) 0x4291ee VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(125) 0x4291f6 VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(125) 0x4291fe VADDPD %ZMM7,%ZMM2,%ZMM1 |
(125) 0x429204 VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(125) 0x42920c VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(125) 0x429214 VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(125) 0x42921c VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(125) 0x429224 VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(125) 0x42922c VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(125) 0x429234 VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(125) 0x42923c VADDPD %ZMM6,%ZMM8,%ZMM9 |
(125) 0x429242 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(125) 0x42924a ADD $0x100,%RAX |
(125) 0x429250 CMP %RAX,%R9 |
(125) 0x429253 JNE 429158 |
(124) 0x429259 MOV 0xb4(%RSP),%R15D |
(124) 0x429261 MOV %EDX,%R13D |
(124) 0x429264 AND $-0x8,%R13D |
(124) 0x429268 ADD %R13D,%EDI |
(124) 0x42926b LEA (%R13,%R15,1),%R9D |
(124) 0x429270 TEST $0x7,%DL |
(124) 0x429273 JE 4294c0 |
(124) 0x429279 SUB %R13D,%EDX |
(124) 0x42927c LEA -0x1(%RDX),%R14D |
(124) 0x429280 CMP $0x2,%R14D |
(124) 0x429284 JBE 429340 |
(124) 0x42928a MOVSXD 0xb4(%RSP),%R12 |
(124) 0x429292 MOV 0x78(%RSP),%R15 |
(124) 0x429297 MOV 0x90(%RSP),%RBX |
(124) 0x42929f MOV 0x70(%RSP),%R10 |
(124) 0x4292a4 LEA (%R15,%R12,1),%R14 |
(124) 0x4292a8 ADD %R13,%R14 |
(124) 0x4292ab LEA (%RBX,%R12,1),%R11 |
(124) 0x4292af LEA (%R10,%R12,1),%RAX |
(124) 0x4292b3 MOV 0xa0(%RSP),%RBX |
(124) 0x4292bb VMOVUPD (%RCX,%R14,8),%YMM10 |
(124) 0x4292c1 LEA 0x1(%R13,%R11,1),%R8 |
(124) 0x4292c6 ADD %R13,%RAX |
(124) 0x4292c9 MOV 0x80(%RSP),%R11 |
(124) 0x4292d1 MOV 0xa8(%RSP),%R14 |
(124) 0x4292d9 VADDPD (%RBX,%RAX,8),%YMM10,%YMM11 |
(124) 0x4292de LEA (%R11,%R12,1),%R10 |
(124) 0x4292e2 MOV 0x88(%RSP),%RAX |
(124) 0x4292ea ADD %R13,%R10 |
(124) 0x4292ed LEA (%RAX,%R12,1),%R15 |
(124) 0x4292f1 VSUBPD (%RCX,%R10,8),%YMM11,%YMM12 |
(124) 0x4292f7 ADD %R13,%R15 |
(124) 0x4292fa VMOVUPD %YMM12,(%R14,%R15,8) |
(124) 0x429300 VMOVUPD (%RSI,%R8,8),%YMM13 |
(124) 0x429306 VSUBPD -0x8(%RSI,%R8,8),%YMM13,%YMM14 |
(124) 0x42930d MOV 0x98(%RSP),%R8 |
(124) 0x429315 ADD %R8,%R12 |
(124) 0x429318 VADDPD %YMM12,%YMM14,%YMM15 |
(124) 0x42931d ADD %R13,%R12 |
(124) 0x429320 MOV 0xb8(%RSP),%R13 |
(124) 0x429328 VMOVUPD %YMM15,(%R13,%R12,8) |
(124) 0x42932f TEST $0x3,%DL |
(124) 0x429332 JE 4294c0 |
(124) 0x429338 AND $-0x4,%EDX |
(124) 0x42933b ADD %EDX,%EDI |
(124) 0x42933d ADD %EDX,%R9D |
(124) 0x429340 MOV 0x78(%RSP),%R15 |
(124) 0x429345 MOVSXD %R9D,%RDX |
(124) 0x429348 MOV 0x70(%RSP),%R14 |
(124) 0x42934d MOV 0xa0(%RSP),%RBX |
(124) 0x429355 MOV 0x88(%RSP),%R13 |
(124) 0x42935d LEA (%R15,%RDX,1),%R12 |
(124) 0x429361 LEA (%R14,%RDX,1),%R11 |
(124) 0x429365 MOV 0xa8(%RSP),%R8 |
(124) 0x42936d VMOVSD (%RCX,%R12,8),%XMM7 |
(124) 0x429373 LEA (%R13,%RDX,1),%RAX |
(124) 0x429378 VADDSD (%RBX,%R11,8),%XMM7,%XMM0 |
(124) 0x42937e MOV 0x80(%RSP),%R11 |
(124) 0x429386 MOV 0x90(%RSP),%RBX |
(124) 0x42938e LEA (%R11,%RDX,1),%R10 |
(124) 0x429392 VSUBSD (%RCX,%R10,8),%XMM0,%XMM2 |
(124) 0x429398 VMOVSD %XMM2,(%R8,%RAX,8) |
(124) 0x42939e LEA 0x1(%R9),%EAX |
(124) 0x4293a2 CLTQ |
(124) 0x4293a4 LEA (%RBX,%RAX,1),%R12 |
(124) 0x4293a8 LEA (%RSI,%R12,8),%R8 |
(124) 0x4293ac MOV 0x98(%RSP),%R12 |
(124) 0x4293b4 VMOVSD (%R8),%XMM1 |
(124) 0x4293b9 LEA (%R12,%RDX,1),%R10 |
(124) 0x4293bd ADD %RBX,%RDX |
(124) 0x4293c0 VSUBSD (%RSI,%RDX,8),%XMM1,%XMM3 |
(124) 0x4293c5 MOV 0xb8(%RSP),%RDX |
(124) 0x4293cd VADDSD %XMM2,%XMM3,%XMM4 |
(124) 0x4293d1 VMOVSD %XMM4,(%RDX,%R10,8) |
(124) 0x4293d7 MOV 0xb0(%RSP),%R10D |
(124) 0x4293df LEA 0x1(%RDI),%EDX |
(124) 0x4293e2 CMP %R10D,%EDX |
(124) 0x4293e5 JAE 4294c0 |
(124) 0x4293eb LEA (%RAX,%R15,1),%R10 |
(124) 0x4293ef LEA (%RAX,%R14,1),%RDX |
(124) 0x4293f3 ADD $0x2,%EDI |
(124) 0x4293f6 VMOVSD (%RCX,%R10,8),%XMM6 |
(124) 0x4293fc MOV 0xa0(%RSP),%R10 |
(124) 0x429404 VADDSD (%R10,%RDX,8),%XMM6,%XMM5 |
(124) 0x42940a LEA (%RAX,%R11,1),%RDX |
(124) 0x42940e MOV 0xa8(%RSP),%R10 |
(124) 0x429416 VSUBSD (%RCX,%RDX,8),%XMM5,%XMM8 |
(124) 0x42941b LEA (%RAX,%R13,1),%RDX |
(124) 0x42941f ADD %R12,%RAX |
(124) 0x429422 VMOVSD %XMM8,(%R10,%RDX,8) |
(124) 0x429428 LEA 0x2(%R9),%EDX |
(124) 0x42942c MOVSXD %EDX,%RDX |
(124) 0x42942f LEA (%RBX,%RDX,1),%R10 |
(124) 0x429433 LEA (%RSI,%R10,8),%R10 |
(124) 0x429437 VMOVSD (%R10),%XMM9 |
(124) 0x42943c VSUBSD (%R8),%XMM9,%XMM10 |
(124) 0x429441 MOV 0xb8(%RSP),%R8 |
(124) 0x429449 VADDSD %XMM8,%XMM10,%XMM11 |
(124) 0x42944e VMOVSD %XMM11,(%R8,%RAX,8) |
(124) 0x429454 MOV 0xb0(%RSP),%EAX |
(124) 0x42945b CMP %EAX,%EDI |
(124) 0x42945d JAE 4294c0 |
(124) 0x42945f MOV %R15,%RDI |
(124) 0x429462 MOV 0xa0(%RSP),%R15 |
(124) 0x42946a ADD %RDX,%R14 |
(124) 0x42946d ADD %RDX,%R11 |
(124) 0x429470 ADD %RDX,%RDI |
(124) 0x429473 ADD $0x3,%R9D |
(124) 0x429477 ADD %RDX,%R13 |
(124) 0x42947a ADD %RDX,%R12 |
(124) 0x42947d VMOVSD (%R15,%R14,8),%XMM12 |
(124) 0x429483 MOVSXD %R9D,%R9 |
(124) 0x429486 ADD %RBX,%R9 |
(124) 0x429489 VADDSD (%RCX,%RDI,8),%XMM12,%XMM13 |
(124) 0x42948e VSUBSD (%RCX,%R11,8),%XMM13,%XMM14 |
(124) 0x429494 MOV 0xa8(%RSP),%RCX |
(124) 0x42949c VMOVSD %XMM14,(%RCX,%R13,8) |
(124) 0x4294a2 VMOVSD (%RSI,%R9,8),%XMM15 |
(124) 0x4294a8 MOV 0xb8(%RSP),%RSI |
(124) 0x4294b0 VSUBSD (%R10),%XMM15,%XMM7 |
(124) 0x4294b5 VADDSD %XMM14,%XMM7,%XMM0 |
(124) 0x4294ba VMOVSD %XMM0,(%RSI,%R12,8) |
(124) 0x4294c0 MOV 0xb0(%RSP),%EDI |
(124) 0x4294c7 MOV 0x68(%RSP),%R8 |
(124) 0x4294cc LEA (%R8),%EBX |
(124) 0x4294cf CMP %EBX,0x60(%RSP) |
(124) 0x4294d3 JLE 4294f8 |
(124) 0x4294d5 MOV 0x58(%RSP),%R13D |
(124) 0x4294da MOV 0x5c(%RSP),%R10D |
(124) 0x4294df MOV 0x64(%RSP),%EDX |
(124) 0x4294e3 MOV %R10D,0xb4(%RSP) |
(124) 0x4294eb SUB %EDI,%R13D |
(124) 0x4294ee JMP 428f60 |
0x4294f3 NOPL (%RAX,%RAX,1) |
0x4294f8 VZEROUPPER |
0x4294fb LEA -0x28(%RBP),%RSP |
0x4294ff POP %RBX |
0x429500 POP %R12 |
0x429502 POP %R13 |
0x429504 POP %R14 |
0x429506 POP %R15 |
0x429508 POP %RBP |
0x429509 RET |
0x42950a NOPW (%RAX,%RAX,1) |
(124) 0x429510 LEA 0x1(%R8),%R13 |
(124) 0x429514 MOV %R13,0x68(%RSP) |
(124) 0x429519 JMP 4294c7 |
0x42951b NOPL (%RAX,%RAX,1) |
(124) 0x429520 MOV 0xb4(%RSP),%R9D |
(124) 0x429528 XOR %R13D,%R13D |
(124) 0x42952b JMP 429279 |
0x429530 INC %R13D |
0x429533 XOR %EDX,%EDX |
0x429535 JMP 428ee9 |
0x42953a NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429530 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4294fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 428ee9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429530 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4294fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 428ee9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0– | 3.07 | 2.3 |
▼Loop 124 - advec_mom.cpp:44-48 - exec– | 0.01 | 0.01 |
○Loop 125 - advec_mom.cpp:47-48 - exec | 3.07 | 2.29 |