Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 2.74% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 2.74% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 95 - 100 |
-------------------------------------------------------------------------------- |
95: #pragma omp parallel for simd collapse(2) |
96: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
97: for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) { |
98: node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) + |
99: density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0)); |
100: node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41de50 PUSH %RBP |
0x41de51 MOV %RSP,%RBP |
0x41de54 PUSH %R15 |
0x41de56 PUSH %R14 |
0x41de58 PUSH %R13 |
0x41de5a PUSH %R12 |
0x41de5c PUSH %RBX |
0x41de5d MOV %RDI,%RBX |
0x41de60 AND $-0x40,%RSP |
0x41de64 SUB $0x100,%RSP |
0x41de6b MOV 0x30(%RDI),%EAX |
0x41de6e MOV 0x34(%RDI),%ECX |
0x41de71 MOV 0x28(%RDI),%EDX |
0x41de74 MOV 0x2c(%RDI),%EDI |
0x41de77 ADD $0x3,%ECX |
0x41de7a LEA 0x1(%RAX),%R12D |
0x41de7e MOV %EDX,0x6c(%RSP) |
0x41de82 MOV %ECX,0x70(%RSP) |
0x41de86 CMP %ECX,%R12D |
0x41de89 JGE 41e6eb |
0x41de8f MOV %ECX,%R14D |
0x41de92 LEA 0x4(%RDI),%R15D |
0x41de96 SUB %R12D,%R14D |
0x41de99 CMP %R15D,%EDX |
0x41de9c JGE 41e6eb |
0x41dea2 MOV %R15D,%ESI |
0x41dea5 SUB %EDX,%ESI |
0x41dea7 MOV %ESI,0x74(%RSP) |
0x41deab CALL 4046c0 <omp_get_num_threads@plt> |
0x41deb0 MOV %EAX,%R13D |
0x41deb3 CALL 4045b0 <omp_get_thread_num@plt> |
0x41deb8 XOR %EDX,%EDX |
0x41deba MOV %EAX,%R8D |
0x41debd MOV 0x74(%RSP),%EAX |
0x41dec1 IMUL %R14D,%EAX |
0x41dec5 DIV %R13D |
0x41dec8 MOV %EAX,%ECX |
0x41deca CMP %EDX,%R8D |
0x41decd JB 41e70e |
0x41ded3 IMUL %ECX,%R8D |
0x41ded7 LEA (%R8,%RDX,1),%R9D |
0x41dedb LEA (%RCX,%R9,1),%R10D |
0x41dedf MOV %R10D,0x68(%RSP) |
0x41dee4 CMP %R10D,%R9D |
0x41dee7 JAE 41e6eb |
0x41deed MOV %R9D,%EAX |
0x41def0 XOR %EDX,%EDX |
0x41def2 MOV 0x6c(%RSP),%R11D |
0x41def7 MOV (%RBX),%RDI |
0x41defa DIVL 0x74(%RSP) |
0x41defe MOV 0x10(%RBX),%R14 |
0x41df02 MOV 0x8(%RBX),%RSI |
0x41df06 MOV %R9D,0xfc(%RSP) |
0x41df0e VMOVSD 0x2e662(%RIP),%XMM3 |
0x41df16 MOV %RDI,0x40(%RSP) |
0x41df1b MOV %R14,0x30(%RSP) |
0x41df20 MOV %RSI,0x28(%RSP) |
0x41df25 MOV %R15D,%R8D |
0x41df28 MOV 0x20(%RBX),%R15 |
0x41df2c MOV 0x18(%RBX),%RBX |
0x41df30 VBROADCASTSD %XMM3,%YMM4 |
0x41df35 VBROADCASTSD %XMM3,%ZMM2 |
0x41df3b MOV %R15,0x38(%RSP) |
0x41df40 MOV %RBX,0x20(%RSP) |
0x41df45 ADD %R12D,%EAX |
0x41df48 ADD %EDX,%R11D |
0x41df4b MOVSXD %EAX,%R12 |
0x41df4e MOV %R11D,0xf8(%RSP) |
0x41df56 SUB %R11D,%R8D |
0x41df59 MOV %EAX,0xb4(%RSP) |
0x41df60 MOV %R12,0x98(%RSP) |
0x41df68 NOPL (%RAX,%RAX,1) |
(124) 0x41df70 CMP %R8D,%ECX |
(124) 0x41df73 CMOVBE %ECX,%R8D |
(124) 0x41df77 MOV 0xfc(%RSP),%ECX |
(124) 0x41df7e LEA (%RCX,%R8,1),%R13D |
(124) 0x41df82 MOV %R8D,%R9D |
(124) 0x41df85 MOV %R13D,0xb0(%RSP) |
(124) 0x41df8d CMP %R13D,%ECX |
(124) 0x41df90 JAE 41e6a0 |
(124) 0x41df96 MOV 0xb4(%RSP),%R8D |
(124) 0x41df9e MOV 0x40(%RSP),%RAX |
(124) 0x41dfa3 MOV 0x38(%RSP),%RDI |
(124) 0x41dfa8 MOV 0x98(%RSP),%R15 |
(124) 0x41dfb0 LEA -0x1(%R8),%R10D |
(124) 0x41dfb4 MOV 0x30(%RSP),%RSI |
(124) 0x41dfb9 MOV 0x10(%RAX),%R13 |
(124) 0x41dfbd MOV (%RDI),%RCX |
(124) 0x41dfc0 MOVSXD %R10D,%R11 |
(124) 0x41dfc3 MOV (%RAX),%R10 |
(124) 0x41dfc6 MOV %R15,%RAX |
(124) 0x41dfc9 MOV %R11,%R14 |
(124) 0x41dfcc MOV 0x28(%RSP),%R8 |
(124) 0x41dfd1 MOV 0x10(%RDI),%RDX |
(124) 0x41dfd5 IMUL %R10,%R14 |
(124) 0x41dfd9 MOV 0x10(%RSI),%RBX |
(124) 0x41dfdd IMUL %RCX,%R11 |
(124) 0x41dfe1 MOV (%R8),%RDI |
(124) 0x41dfe4 IMUL %R15,%R10 |
(124) 0x41dfe8 MOV %RBX,0xe0(%RSP) |
(124) 0x41dff0 LEA -0x1(%R9),%EBX |
(124) 0x41dff4 IMUL %R15,%RCX |
(124) 0x41dff8 MOV %R14,0xb8(%RSP) |
(124) 0x41e000 IMUL (%RSI),%R15 |
(124) 0x41e004 MOV %R11,0xc0(%RSP) |
(124) 0x41e00c IMUL %RAX,%RDI |
(124) 0x41e010 MOV %R10,0xc8(%RSP) |
(124) 0x41e018 MOV %RCX,0xd0(%RSP) |
(124) 0x41e020 MOV %R15,0xd8(%RSP) |
(124) 0x41e028 MOV 0x10(%R8),%R15 |
(124) 0x41e02c MOV 0x20(%RSP),%R8 |
(124) 0x41e031 MOV %RDI,0xf0(%RSP) |
(124) 0x41e039 MOV (%R8),%R12 |
(124) 0x41e03c MOV 0x10(%R8),%RSI |
(124) 0x41e040 IMUL %RAX,%R12 |
(124) 0x41e044 MOV %RSI,0xe8(%RSP) |
(124) 0x41e04c MOV %R12,0xa8(%RSP) |
(124) 0x41e054 CMP $0x6,%EBX |
(124) 0x41e057 JBE 41e700 |
(124) 0x41e05d MOVSXD 0xf8(%RSP),%RAX |
(124) 0x41e065 LEA (%R14,%RAX,1),%R8 |
(124) 0x41e069 LEA (%R11,%RAX,1),%RDI |
(124) 0x41e06d ADD %RAX,%RCX |
(124) 0x41e070 SAL $0x3,%R8 |
(124) 0x41e074 SAL $0x3,%RDI |
(124) 0x41e078 LEA (%R10,%RAX,1),%RBX |
(124) 0x41e07c SAL $0x3,%RBX |
(124) 0x41e080 SAL $0x3,%RCX |
(124) 0x41e084 LEA (%R13,%R8,1),%R14 |
(124) 0x41e089 LEA (%RDX,%RDI,1),%R11 |
(124) 0x41e08d LEA (%R13,%RBX,1),%R10 |
(124) 0x41e092 MOV %R14,0x80(%RSP) |
(124) 0x41e09a LEA (%RDX,%RCX,1),%R14 |
(124) 0x41e09e MOV %R11,0x88(%RSP) |
(124) 0x41e0a6 LEA -0x8(%R13,%RBX,1),%R11 |
(124) 0x41e0ab LEA -0x8(%RDX,%RCX,1),%RBX |
(124) 0x41e0b0 MOV 0xd8(%RSP),%RCX |
(124) 0x41e0b8 LEA -0x8(%RDX,%RDI,1),%RSI |
(124) 0x41e0bd MOV %R10,0x90(%RSP) |
(124) 0x41e0c5 MOV 0xf0(%RSP),%RDI |
(124) 0x41e0cd LEA -0x8(%R13,%R8,1),%R10 |
(124) 0x41e0d2 MOV 0xe0(%RSP),%R8 |
(124) 0x41e0da ADD %RAX,%RCX |
(124) 0x41e0dd MOV %RSI,0x78(%RSP) |
(124) 0x41e0e2 MOV 0xe8(%RSP),%RSI |
(124) 0x41e0ea LEA (%R8,%RCX,8),%R8 |
(124) 0x41e0ee LEA (%RDI,%RAX,1),%RCX |
(124) 0x41e0f2 ADD %R12,%RAX |
(124) 0x41e0f5 LEA (%RSI,%RAX,8),%RSI |
(124) 0x41e0f9 MOV %R9D,%EAX |
(124) 0x41e0fc SAL $0x3,%RCX |
(124) 0x41e100 SHR $0x3,%EAX |
(124) 0x41e103 LEA -0x8(%R15,%RCX,1),%RDI |
(124) 0x41e108 ADD %R15,%RCX |
(124) 0x41e10b MOV %RAX,%R12 |
(124) 0x41e10e SAL $0x6,%RAX |
(124) 0x41e112 MOV %RAX,0xa0(%RSP) |
(124) 0x41e11a XOR %EAX,%EAX |
(124) 0x41e11c AND $0x1,%R12D |
(124) 0x41e120 JE 41e1b4 |
(124) 0x41e126 MOV 0x90(%RSP),%RAX |
(124) 0x41e12e VMOVUPD (%R11),%ZMM5 |
(124) 0x41e134 MOV 0x88(%RSP),%R12 |
(124) 0x41e13c VMOVUPD (%R10),%ZMM8 |
(124) 0x41e142 VMOVUPD (%RAX),%ZMM7 |
(124) 0x41e148 VMULPD (%RBX),%ZMM5,%ZMM1 |
(124) 0x41e14e VMOVUPD (%R12),%ZMM6 |
(124) 0x41e155 MOV 0x80(%RSP),%RAX |
(124) 0x41e15d VMULPD (%R14),%ZMM7,%ZMM0 |
(124) 0x41e163 MOV 0xa0(%RSP),%R12 |
(124) 0x41e16b VFMADD231PD (%RAX),%ZMM6,%ZMM0 |
(124) 0x41e171 MOV 0x78(%RSP),%RAX |
(124) 0x41e176 VFMADD231PD (%RAX),%ZMM8,%ZMM1 |
(124) 0x41e17c MOV $0x40,%EAX |
(124) 0x41e181 VADDPD %ZMM1,%ZMM0,%ZMM9 |
(124) 0x41e187 VMULPD %ZMM2,%ZMM9,%ZMM10 |
(124) 0x41e18d VMOVUPD %ZMM10,(%R8) |
(124) 0x41e193 VMOVUPD (%RCX),%ZMM11 |
(124) 0x41e199 VSUBPD (%RDI),%ZMM11,%ZMM12 |
(124) 0x41e19f VADDPD %ZMM10,%ZMM12,%ZMM13 |
(124) 0x41e1a5 VMOVUPD %ZMM13,(%RSI) |
(124) 0x41e1ab CMP %R12,%RAX |
(124) 0x41e1ae JE 41e2e7 |
(124) 0x41e1b4 MOV %R15,0x58(%RSP) |
(124) 0x41e1b9 MOV 0x88(%RSP),%R12 |
(124) 0x41e1c1 MOV %R9D,0x64(%RSP) |
(124) 0x41e1c6 MOV 0x80(%RSP),%R9 |
(124) 0x41e1ce MOV %RDX,0x50(%RSP) |
(124) 0x41e1d3 MOV 0x90(%RSP),%RDX |
(124) 0x41e1db MOV %R13,0x48(%RSP) |
(124) 0x41e1e0 MOV 0x78(%RSP),%R13 |
(125) 0x41e1e5 VMOVUPD (%RDX,%RAX,1),%ZMM14 |
(125) 0x41e1ec VMOVUPD (%R11,%RAX,1),%ZMM0 |
(125) 0x41e1f3 VMOVUPD (%R12,%RAX,1),%ZMM7 |
(125) 0x41e1fa VMOVUPD (%R10,%RAX,1),%ZMM5 |
(125) 0x41e201 VMULPD (%R14,%RAX,1),%ZMM14,%ZMM15 |
(125) 0x41e208 MOV 0xa0(%RSP),%R15 |
(125) 0x41e210 VMULPD (%RBX,%RAX,1),%ZMM0,%ZMM6 |
(125) 0x41e217 VFMADD231PD (%R9,%RAX,1),%ZMM7,%ZMM15 |
(125) 0x41e21e VFMADD231PD (%R13,%RAX,1),%ZMM5,%ZMM6 |
(125) 0x41e226 VADDPD %ZMM6,%ZMM15,%ZMM1 |
(125) 0x41e22c VMULPD %ZMM2,%ZMM1,%ZMM8 |
(125) 0x41e232 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(125) 0x41e239 VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(125) 0x41e240 VSUBPD (%RDI,%RAX,1),%ZMM9,%ZMM10 |
(125) 0x41e247 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(125) 0x41e24d VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(125) 0x41e254 VMOVUPD 0x40(%RDX,%RAX,1),%ZMM12 |
(125) 0x41e25c VMOVUPD 0x40(%R11,%RAX,1),%ZMM15 |
(125) 0x41e264 VMOVUPD 0x40(%R12,%RAX,1),%ZMM14 |
(125) 0x41e26c VMOVUPD 0x40(%R10,%RAX,1),%ZMM7 |
(125) 0x41e274 VMULPD 0x40(%R14,%RAX,1),%ZMM12,%ZMM13 |
(125) 0x41e27c VMULPD 0x40(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(125) 0x41e284 VFMADD231PD 0x40(%R9,%RAX,1),%ZMM14,%ZMM13 |
(125) 0x41e28c VFMADD231PD 0x40(%R13,%RAX,1),%ZMM7,%ZMM0 |
(125) 0x41e294 VADDPD %ZMM0,%ZMM13,%ZMM6 |
(125) 0x41e29a VMULPD %ZMM2,%ZMM6,%ZMM8 |
(125) 0x41e2a0 VMOVUPD %ZMM8,0x40(%R8,%RAX,1) |
(125) 0x41e2a8 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM5 |
(125) 0x41e2b0 VSUBPD 0x40(%RDI,%RAX,1),%ZMM5,%ZMM1 |
(125) 0x41e2b8 VADDPD %ZMM8,%ZMM1,%ZMM9 |
(125) 0x41e2be VMOVUPD %ZMM9,0x40(%RSI,%RAX,1) |
(125) 0x41e2c6 SUB $-0x80,%RAX |
(125) 0x41e2ca CMP %R15,%RAX |
(125) 0x41e2cd JNE 41e1e5 |
(124) 0x41e2d3 MOV 0x64(%RSP),%R9D |
(124) 0x41e2d8 MOV 0x58(%RSP),%R15 |
(124) 0x41e2dd MOV 0x50(%RSP),%RDX |
(124) 0x41e2e2 MOV 0x48(%RSP),%R13 |
(124) 0x41e2e7 MOV 0xf8(%RSP),%EAX |
(124) 0x41e2ee MOV %R9D,%ESI |
(124) 0x41e2f1 AND $-0x8,%ESI |
(124) 0x41e2f4 ADD %ESI,0xfc(%RSP) |
(124) 0x41e2fb ADD %ESI,%EAX |
(124) 0x41e2fd TEST $0x7,%R9B |
(124) 0x41e301 JE 41e690 |
(124) 0x41e307 MOV %R9D,%EDI |
(124) 0x41e30a SUB %ESI,%EDI |
(124) 0x41e30c LEA -0x1(%RDI),%R14D |
(124) 0x41e310 CMP $0x2,%R14D |
(124) 0x41e314 JBE 41e409 |
(124) 0x41e31a MOVSXD 0xf8(%RSP),%RCX |
(124) 0x41e322 MOV 0xc0(%RSP),%R11 |
(124) 0x41e32a MOV 0xc8(%RSP),%RBX |
(124) 0x41e332 MOV 0xb8(%RSP),%R10 |
(124) 0x41e33a LEA (%R11,%RCX,1),%R9 |
(124) 0x41e33e MOV 0xd8(%RSP),%R8 |
(124) 0x41e346 MOV 0xf0(%RSP),%R14 |
(124) 0x41e34e LEA (%RBX,%RCX,1),%R11 |
(124) 0x41e352 MOV 0xd0(%RSP),%RBX |
(124) 0x41e35a LEA (%R10,%RCX,1),%R10 |
(124) 0x41e35e ADD %RSI,%R9 |
(124) 0x41e361 ADD %RSI,%R11 |
(124) 0x41e364 ADD %RSI,%R10 |
(124) 0x41e367 LEA (%R8,%RCX,1),%R12 |
(124) 0x41e36b ADD %RCX,%RBX |
(124) 0x41e36e VMOVUPD (%R13,%R11,8),%YMM10 |
(124) 0x41e375 VMOVUPD (%R13,%R10,8),%YMM12 |
(124) 0x41e37c LEA (%R14,%RCX,1),%R8 |
(124) 0x41e380 ADD %RSI,%RBX |
(124) 0x41e383 VMOVUPD -0x8(%R13,%R10,8),%YMM15 |
(124) 0x41e38a MOV 0xa8(%RSP),%R14 |
(124) 0x41e392 ADD %RSI,%R8 |
(124) 0x41e395 VMOVUPD -0x8(%RDX,%RBX,8),%YMM13 |
(124) 0x41e39b VMULPD (%RDX,%RBX,8),%YMM10,%YMM11 |
(124) 0x41e3a0 ADD %RSI,%R12 |
(124) 0x41e3a3 ADD %R14,%RCX |
(124) 0x41e3a6 MOV 0xe8(%RSP),%R10 |
(124) 0x41e3ae VMULPD -0x8(%R13,%R11,8),%YMM13,%YMM14 |
(124) 0x41e3b5 ADD %RSI,%RCX |
(124) 0x41e3b8 MOV 0xe0(%RSP),%RSI |
(124) 0x41e3c0 VFMADD231PD (%RDX,%R9,8),%YMM12,%YMM11 |
(124) 0x41e3c6 VFMADD231PD -0x8(%RDX,%R9,8),%YMM15,%YMM14 |
(124) 0x41e3cd VADDPD %YMM14,%YMM11,%YMM0 |
(124) 0x41e3d2 VMULPD %YMM4,%YMM0,%YMM6 |
(124) 0x41e3d6 VMOVUPD %YMM6,(%RSI,%R12,8) |
(124) 0x41e3dc VMOVUPD (%R15,%R8,8),%YMM7 |
(124) 0x41e3e2 VSUBPD -0x8(%R15,%R8,8),%YMM7,%YMM8 |
(124) 0x41e3e9 VADDPD %YMM6,%YMM8,%YMM5 |
(124) 0x41e3ed VMOVUPD %YMM5,(%R10,%RCX,8) |
(124) 0x41e3f3 TEST $0x3,%DIL |
(124) 0x41e3f7 JE 41e690 |
(124) 0x41e3fd AND $-0x4,%EDI |
(124) 0x41e400 ADD %EDI,0xfc(%RSP) |
(124) 0x41e407 ADD %EDI,%EAX |
(124) 0x41e409 MOV 0xc8(%RSP),%R12 |
(124) 0x41e411 MOVSXD %EAX,%RCX |
(124) 0x41e414 MOV 0xb8(%RSP),%RDI |
(124) 0x41e41c MOV 0xc0(%RSP),%RBX |
(124) 0x41e424 LEA (%R12,%RCX,1),%R14 |
(124) 0x41e428 LEA (%RDI,%RCX,1),%R9 |
(124) 0x41e42c LEA (%R13,%R14,8),%R10 |
(124) 0x41e431 MOV 0xd0(%RSP),%R14 |
(124) 0x41e439 LEA (%RBX,%RCX,1),%R11 |
(124) 0x41e43d LEA (%R13,%R9,8),%R8 |
(124) 0x41e442 LEA (%RDX,%R11,8),%R9 |
(124) 0x41e446 LEA (%R14,%RCX,1),%RSI |
(124) 0x41e44a VMOVSD (%R9),%XMM10 |
(124) 0x41e44f LEA (%RDX,%RSI,8),%R11 |
(124) 0x41e453 LEA -0x1(%RAX),%ESI |
(124) 0x41e456 MOVSXD %ESI,%RSI |
(124) 0x41e459 VMOVSD (%R11),%XMM1 |
(124) 0x41e45e ADD %RSI,%R14 |
(124) 0x41e461 ADD %RSI,%R12 |
(124) 0x41e464 ADD %RSI,%RBX |
(124) 0x41e467 ADD %RSI,%RDI |
(124) 0x41e46a VMOVSD (%RDX,%R14,8),%XMM11 |
(124) 0x41e470 VMULSD (%R10),%XMM1,%XMM9 |
(124) 0x41e475 VMOVSD (%RDX,%RBX,8),%XMM13 |
(124) 0x41e47a MOV 0xe0(%RSP),%RBX |
(124) 0x41e482 VMULSD (%R13,%R12,8),%XMM11,%XMM12 |
(124) 0x41e489 MOV 0xf0(%RSP),%R12 |
(124) 0x41e491 LEA (%R12,%RCX,1),%R14 |
(124) 0x41e495 ADD %R12,%RSI |
(124) 0x41e498 MOV 0xb0(%RSP),%R12D |
(124) 0x41e4a0 VFMADD231SD (%R8),%XMM10,%XMM9 |
(124) 0x41e4a5 VFMADD231SD (%R13,%RDI,8),%XMM13,%XMM12 |
(124) 0x41e4ac MOV 0xd8(%RSP),%RDI |
(124) 0x41e4b4 ADD %RCX,%RDI |
(124) 0x41e4b7 VADDSD %XMM12,%XMM9,%XMM14 |
(124) 0x41e4bc VMULSD %XMM3,%XMM14,%XMM15 |
(124) 0x41e4c0 VMOVSD %XMM15,(%RBX,%RDI,8) |
(124) 0x41e4c5 LEA (%R15,%R14,8),%RDI |
(124) 0x41e4c9 MOV 0xa8(%RSP),%RBX |
(124) 0x41e4d1 MOV 0xfc(%RSP),%R14D |
(124) 0x41e4d9 VMOVSD (%RDI),%XMM0 |
(124) 0x41e4dd ADD %RBX,%RCX |
(124) 0x41e4e0 INC %R14D |
(124) 0x41e4e3 VSUBSD (%R15,%RSI,8),%XMM0,%XMM6 |
(124) 0x41e4e9 MOV 0xe8(%RSP),%RSI |
(124) 0x41e4f1 VADDSD %XMM15,%XMM6,%XMM7 |
(124) 0x41e4f6 VMOVSD %XMM7,(%RSI,%RCX,8) |
(124) 0x41e4fb LEA 0x1(%RAX),%ECX |
(124) 0x41e4fe CMP %R12D,%R14D |
(124) 0x41e501 JAE 41e690 |
(124) 0x41e507 MOV 0xb8(%RSP),%RBX |
(124) 0x41e50f MOV 0xc0(%RSP),%R14 |
(124) 0x41e517 MOVSXD %ECX,%RCX |
(124) 0x41e51a ADD $0x2,%EAX |
(124) 0x41e51d MOV 0xc8(%RSP),%R12 |
(124) 0x41e525 VMOVSD (%R11),%XMM9 |
(124) 0x41e52a LEA (%RBX,%RCX,1),%RSI |
(124) 0x41e52e ADD %RCX,%R14 |
(124) 0x41e531 VMOVSD (%R9),%XMM11 |
(124) 0x41e536 MOV 0xf0(%RSP),%R11 |
(124) 0x41e53e LEA (%R13,%RSI,8),%RBX |
(124) 0x41e543 LEA (%RDX,%R14,8),%RSI |
(124) 0x41e547 VMULSD (%R10),%XMM9,%XMM10 |
(124) 0x41e54c ADD %RCX,%R12 |
(124) 0x41e54f LEA (%R13,%R12,8),%R14 |
(124) 0x41e554 MOV 0xd0(%RSP),%R12 |
(124) 0x41e55c VMOVSD (%RSI),%XMM1 |
(124) 0x41e560 MOV 0xe0(%RSP),%R10 |
(124) 0x41e568 ADD %RCX,%R12 |
(124) 0x41e56b LEA (%RDX,%R12,8),%R12 |
(124) 0x41e56f VMOVSD (%R12),%XMM8 |
(124) 0x41e575 VFMADD231SD (%R8),%XMM11,%XMM10 |
(124) 0x41e57a MOV 0xd8(%RSP),%R8 |
(124) 0x41e582 VMULSD (%R14),%XMM8,%XMM5 |
(124) 0x41e587 LEA (%R8,%RCX,1),%R9 |
(124) 0x41e58b LEA (%R11,%RCX,1),%R8 |
(124) 0x41e58f LEA (%R15,%R8,8),%R8 |
(124) 0x41e593 VFMADD132SD (%RBX),%XMM5,%XMM1 |
(124) 0x41e598 VADDSD %XMM1,%XMM10,%XMM12 |
(124) 0x41e59c VMULSD %XMM3,%XMM12,%XMM13 |
(124) 0x41e5a0 VMOVSD %XMM13,(%R10,%R9,8) |
(124) 0x41e5a6 MOV 0xa8(%RSP),%R9 |
(124) 0x41e5ae MOV 0xb0(%RSP),%R10D |
(124) 0x41e5b6 VMOVSD (%R8),%XMM14 |
(124) 0x41e5bb ADD %R9,%RCX |
(124) 0x41e5be VSUBSD (%RDI),%XMM14,%XMM15 |
(124) 0x41e5c2 MOV 0xe8(%RSP),%RDI |
(124) 0x41e5ca VADDSD %XMM13,%XMM15,%XMM0 |
(124) 0x41e5cf VMOVSD %XMM0,(%RDI,%RCX,8) |
(124) 0x41e5d4 MOV 0xfc(%RSP),%ECX |
(124) 0x41e5db ADD $0x2,%ECX |
(124) 0x41e5de CMP %R10D,%ECX |
(124) 0x41e5e1 JAE 41e690 |
(124) 0x41e5e7 MOV 0xc8(%RSP),%R9 |
(124) 0x41e5ef CLTQ |
(124) 0x41e5f1 MOV 0xd0(%RSP),%R10 |
(124) 0x41e5f9 VMOVSD (%R14),%XMM5 |
(124) 0x41e5fe MOV 0xb8(%RSP),%RCX |
(124) 0x41e606 ADD %RAX,%R11 |
(124) 0x41e609 ADD %RAX,%R9 |
(124) 0x41e60c ADD %RAX,%R10 |
(124) 0x41e60f MOV 0xc0(%RSP),%RDI |
(124) 0x41e617 VMOVSD (%RBX),%XMM9 |
(124) 0x41e61b VMOVSD (%R13,%R9,8),%XMM6 |
(124) 0x41e622 VMULSD (%R12),%XMM5,%XMM1 |
(124) 0x41e628 ADD %RAX,%RCX |
(124) 0x41e62b VMOVSD (%R13,%RCX,8),%XMM7 |
(124) 0x41e632 ADD %RAX,%RDI |
(124) 0x41e635 MOV 0xe0(%RSP),%R13 |
(124) 0x41e63d VMULSD (%RDX,%R10,8),%XMM6,%XMM8 |
(124) 0x41e643 MOV 0xa8(%RSP),%RBX |
(124) 0x41e64b ADD %RAX,%RBX |
(124) 0x41e64e VFMADD231SD (%RSI),%XMM9,%XMM1 |
(124) 0x41e653 VFMADD231SD (%RDX,%RDI,8),%XMM7,%XMM8 |
(124) 0x41e659 MOV 0xd8(%RSP),%RDX |
(124) 0x41e661 ADD %RAX,%RDX |
(124) 0x41e664 MOV 0xe8(%RSP),%RAX |
(124) 0x41e66c VADDSD %XMM1,%XMM8,%XMM10 |
(124) 0x41e670 VMULSD %XMM3,%XMM10,%XMM11 |
(124) 0x41e674 VMOVSD %XMM11,(%R13,%RDX,8) |
(124) 0x41e67b VMOVSD (%R15,%R11,8),%XMM12 |
(124) 0x41e681 VSUBSD (%R8),%XMM12,%XMM13 |
(124) 0x41e686 VADDSD %XMM11,%XMM13,%XMM14 |
(124) 0x41e68b VMOVSD %XMM14,(%RAX,%RBX,8) |
(124) 0x41e690 MOV 0xb0(%RSP),%R15D |
(124) 0x41e698 MOV %R15D,0xfc(%RSP) |
(124) 0x41e6a0 INCL 0xb4(%RSP) |
(124) 0x41e6a7 INCQ 0x98(%RSP) |
(124) 0x41e6af MOV 0xb4(%RSP),%ESI |
(124) 0x41e6b6 CMP %ESI,0x70(%RSP) |
(124) 0x41e6ba JLE 41e6e8 |
(124) 0x41e6bc MOV 0x68(%RSP),%ECX |
(124) 0x41e6c0 MOV 0xfc(%RSP),%R14D |
(124) 0x41e6c8 MOV 0x6c(%RSP),%R12D |
(124) 0x41e6cd MOV 0x74(%RSP),%R8D |
(124) 0x41e6d2 SUB %R14D,%ECX |
(124) 0x41e6d5 MOV %R12D,0xf8(%RSP) |
(124) 0x41e6dd JMP 41df70 |
0x41e6e2 NOPW (%RAX,%RAX,1) |
0x41e6e8 VZEROUPPER |
0x41e6eb LEA -0x28(%RBP),%RSP |
0x41e6ef POP %RBX |
0x41e6f0 POP %R12 |
0x41e6f2 POP %R13 |
0x41e6f4 POP %R14 |
0x41e6f6 POP %R15 |
0x41e6f8 POP %RBP |
0x41e6f9 RET |
0x41e6fa NOPW (%RAX,%RAX,1) |
(124) 0x41e700 MOV 0xf8(%RSP),%EAX |
(124) 0x41e707 XOR %ESI,%ESI |
(124) 0x41e709 JMP 41e307 |
0x41e70e INC %ECX |
0x41e710 XOR %EDX,%EDX |
0x41e712 JMP 41ded3 |
0x41e717 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 336 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41e6eb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41e6eb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41e70e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41e6eb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x2e662(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41ded3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 336 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41e6eb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41e6eb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41e70e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41e6eb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x2e662(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41ded3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 2.74 | 0.88 |
▼Loop 124 - advec_mom.cpp:97-100 - exec– | 0.01 | 0 |
○Loop 125 - advec_mom.cpp:98-100 - exec | 2.73 | 0.87 |