Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 3.41% |
---|
Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 3.41% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 146 - 149 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
148: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
149: vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41f0e0 PUSH %RBP |
0x41f0e1 MOV %RSP,%RBP |
0x41f0e4 PUSH %R15 |
0x41f0e6 PUSH %R14 |
0x41f0e8 PUSH %R13 |
0x41f0ea PUSH %R12 |
0x41f0ec PUSH %RBX |
0x41f0ed AND $-0x40,%RSP |
0x41f0f1 ADD $-0x80,%RSP |
0x41f0f5 MOV 0x28(%RDI),%EAX |
0x41f0f8 MOV 0x2c(%RDI),%EDX |
0x41f0fb MOV 0x20(%RDI),%EBX |
0x41f0fe MOV 0x24(%RDI),%ECX |
0x41f101 ADD $0x3,%EDX |
0x41f104 LEA 0x1(%RAX),%R15D |
0x41f108 LEA 0x1(%RBX),%ESI |
0x41f10b MOV %EDX,0x44(%RSP) |
0x41f10f MOV %ESI,0x40(%RSP) |
0x41f113 CMP %EDX,%R15D |
0x41f116 JGE 41f5c3 |
0x41f11c MOV %EDX,%EBX |
0x41f11e LEA 0x3(%RCX),%R14D |
0x41f122 SUB %R15D,%EBX |
0x41f125 CMP %R14D,%ESI |
0x41f128 JGE 41f5c3 |
0x41f12e MOV %RDI,%R13 |
0x41f131 MOV %R14D,%EDI |
0x41f134 SUB %ESI,%EDI |
0x41f136 MOV %EDI,0x68(%RSP) |
0x41f13a CALL 4046c0 <omp_get_num_threads@plt> |
0x41f13f MOV %EAX,%R12D |
0x41f142 CALL 4045b0 <omp_get_thread_num@plt> |
0x41f147 XOR %EDX,%EDX |
0x41f149 MOV %EAX,%R8D |
0x41f14c MOV 0x68(%RSP),%EAX |
0x41f150 IMUL %EBX,%EAX |
0x41f153 DIV %R12D |
0x41f156 MOV %EAX,%ECX |
0x41f158 CMP %EDX,%R8D |
0x41f15b JB 41f5e2 |
0x41f161 IMUL %ECX,%R8D |
0x41f165 LEA (%R8,%RDX,1),%EBX |
0x41f169 LEA (%RCX,%RBX,1),%R9D |
0x41f16d MOV %R9D,0x3c(%RSP) |
0x41f172 CMP %R9D,%EBX |
0x41f175 JAE 41f5c3 |
0x41f17b MOV %EBX,%EAX |
0x41f17d XOR %EDX,%EDX |
0x41f17f MOV 0x40(%RSP),%ESI |
0x41f183 MOV (%R13),%R10 |
0x41f187 DIVL 0x68(%RSP) |
0x41f18b MOV 0x10(%R13),%R11 |
0x41f18f MOV %R10,0x30(%RSP) |
0x41f194 MOV %R11,0x28(%RSP) |
0x41f199 ADD %EDX,%ESI |
0x41f19b ADD %R15D,%EAX |
0x41f19e MOV %R14D,%EDX |
0x41f1a1 MOV 0x18(%R13),%R15 |
0x41f1a5 MOV 0x8(%R13),%R14 |
0x41f1a9 SUB %ESI,%EDX |
0x41f1ab MOVSXD %EAX,%R12 |
0x41f1ae MOV %R15,0x20(%RSP) |
0x41f1b3 MOV %R14,0x18(%RSP) |
0x41f1b8 NOPL (%RAX,%RAX,1) |
(129) 0x41f1c0 CMP %EDX,%ECX |
(129) 0x41f1c2 CMOVBE %ECX,%EDX |
(129) 0x41f1c5 LEA (%RBX,%RDX,1),%ECX |
(129) 0x41f1c8 MOV %ECX,0x6c(%RSP) |
(129) 0x41f1cc CMP %ECX,%EBX |
(129) 0x41f1ce JAE 41f59b |
(129) 0x41f1d4 MOV 0x30(%RSP),%R13 |
(129) 0x41f1d9 MOV 0x28(%RSP),%RDI |
(129) 0x41f1de MOV 0x18(%RSP),%RAX |
(129) 0x41f1e3 MOV 0x20(%RSP),%R9 |
(129) 0x41f1e8 MOV 0x10(%R13),%R14 |
(129) 0x41f1ec MOV (%R13),%RCX |
(129) 0x41f1f0 MOV (%RAX),%R10 |
(129) 0x41f1f3 MOV (%RDI),%R13 |
(129) 0x41f1f6 IMUL %R12,%RCX |
(129) 0x41f1fa MOV 0x10(%RDI),%R15 |
(129) 0x41f1fe MOV (%R9),%R11 |
(129) 0x41f201 LEA -0x1(%RDX),%EDI |
(129) 0x41f204 IMUL %R12,%R13 |
(129) 0x41f208 MOV 0x10(%R9),%R8 |
(129) 0x41f20c MOV 0x10(%RAX),%R9 |
(129) 0x41f210 MOV %R14,0x50(%RSP) |
(129) 0x41f215 IMUL %R12,%R10 |
(129) 0x41f219 MOV %R15,0x70(%RSP) |
(129) 0x41f21e MOV %RCX,0x48(%RSP) |
(129) 0x41f223 IMUL %R12,%R11 |
(129) 0x41f227 MOV %R13,0x58(%RSP) |
(129) 0x41f22c MOV %R9,0x78(%RSP) |
(129) 0x41f231 MOV %R10,0x60(%RSP) |
(129) 0x41f236 CMP $0x6,%EDI |
(129) 0x41f239 JBE 41f5d8 |
(129) 0x41f23f MOVSXD %ESI,%RAX |
(129) 0x41f242 ADD %RAX,%R13 |
(129) 0x41f245 ADD %RAX,%RCX |
(129) 0x41f248 LEA (%R11,%RAX,1),%RDI |
(129) 0x41f24c ADD %R10,%RAX |
(129) 0x41f24f MOV %EDX,%R10D |
(129) 0x41f252 LEA (%R15,%R13,8),%R15 |
(129) 0x41f256 LEA (%R9,%RAX,8),%R13 |
(129) 0x41f25a SAL $0x3,%RDI |
(129) 0x41f25e SHR $0x3,%R10D |
(129) 0x41f262 LEA (%R14,%RCX,8),%RCX |
(129) 0x41f266 LEA -0x8(%R8,%RDI,1),%R14 |
(129) 0x41f26b XOR %EAX,%EAX |
(129) 0x41f26d SAL $0x6,%R10 |
(129) 0x41f271 ADD %R8,%RDI |
(129) 0x41f274 LEA -0x40(%R10),%R9 |
(129) 0x41f278 SHR $0x6,%R9 |
(129) 0x41f27c INC %R9 |
(129) 0x41f27f AND $0x3,%R9D |
(129) 0x41f283 JE 41f326 |
(129) 0x41f289 CMP $0x1,%R9 |
(129) 0x41f28d JE 41f2ee |
(129) 0x41f28f CMP $0x2,%R9 |
(129) 0x41f293 JE 41f2bf |
(129) 0x41f295 VMOVUPD (%RCX),%ZMM0 |
(129) 0x41f29b VMOVUPD (%RDI),%ZMM3 |
(129) 0x41f2a1 MOV $0x40,%EAX |
(129) 0x41f2a6 VFMSUB132PD (%R15),%ZMM3,%ZMM0 |
(129) 0x41f2ac VADDPD (%R14),%ZMM0,%ZMM1 |
(129) 0x41f2b2 VDIVPD (%R13),%ZMM1,%ZMM2 |
(129) 0x41f2b9 VMOVUPD %ZMM2,(%RCX) |
(129) 0x41f2bf VMOVUPD (%RCX,%RAX,1),%ZMM4 |
(129) 0x41f2c6 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(129) 0x41f2cd VFMSUB132PD (%R15,%RAX,1),%ZMM5,%ZMM4 |
(129) 0x41f2d4 VADDPD (%R14,%RAX,1),%ZMM4,%ZMM6 |
(129) 0x41f2db VDIVPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(129) 0x41f2e3 VMOVUPD %ZMM7,(%RCX,%RAX,1) |
(129) 0x41f2ea ADD $0x40,%RAX |
(129) 0x41f2ee VMOVUPD (%RCX,%RAX,1),%ZMM8 |
(129) 0x41f2f5 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(129) 0x41f2fc VFMSUB132PD (%R15,%RAX,1),%ZMM9,%ZMM8 |
(129) 0x41f303 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM10 |
(129) 0x41f30a VDIVPD (%R13,%RAX,1),%ZMM10,%ZMM11 |
(129) 0x41f312 VMOVUPD %ZMM11,(%RCX,%RAX,1) |
(129) 0x41f319 ADD $0x40,%RAX |
(129) 0x41f31d CMP %RAX,%R10 |
(129) 0x41f320 JE 41f3f0 |
(130) 0x41f326 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(130) 0x41f32d VMOVUPD (%RCX,%RAX,1),%ZMM12 |
(130) 0x41f334 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM0 |
(130) 0x41f33c VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(130) 0x41f344 VFMSUB132PD (%R15,%RAX,1),%ZMM13,%ZMM12 |
(130) 0x41f34b VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8 |
(130) 0x41f353 VADDPD (%R14,%RAX,1),%ZMM12,%ZMM14 |
(130) 0x41f35a VDIVPD (%R13,%RAX,1),%ZMM14,%ZMM15 |
(130) 0x41f362 VMOVUPD %ZMM15,(%RCX,%RAX,1) |
(130) 0x41f369 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM3 |
(130) 0x41f371 VFMSUB132PD 0x40(%R15,%RAX,1),%ZMM3,%ZMM0 |
(130) 0x41f379 VADDPD 0x40(%R14,%RAX,1),%ZMM0,%ZMM1 |
(130) 0x41f381 VDIVPD 0x40(%R13,%RAX,1),%ZMM1,%ZMM2 |
(130) 0x41f389 VMOVUPD %ZMM2,0x40(%RCX,%RAX,1) |
(130) 0x41f391 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM4 |
(130) 0x41f399 VFMSUB132PD 0x80(%R15,%RAX,1),%ZMM4,%ZMM5 |
(130) 0x41f3a1 VADDPD 0x80(%R14,%RAX,1),%ZMM5,%ZMM6 |
(130) 0x41f3a9 VDIVPD 0x80(%R13,%RAX,1),%ZMM6,%ZMM7 |
(130) 0x41f3b1 VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) |
(130) 0x41f3b9 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM9 |
(130) 0x41f3c1 VFMSUB132PD 0xc0(%R15,%RAX,1),%ZMM9,%ZMM8 |
(130) 0x41f3c9 VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM10 |
(130) 0x41f3d1 VDIVPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(130) 0x41f3d9 VMOVUPD %ZMM11,0xc0(%RCX,%RAX,1) |
(130) 0x41f3e1 ADD $0x100,%RAX |
(130) 0x41f3e7 CMP %RAX,%R10 |
(130) 0x41f3ea JNE 41f326 |
(129) 0x41f3f0 MOV %EDX,%R13D |
(129) 0x41f3f3 AND $-0x8,%R13D |
(129) 0x41f3f7 ADD %R13D,%EBX |
(129) 0x41f3fa LEA (%R13,%RSI,1),%ECX |
(129) 0x41f3ff TEST $0x7,%DL |
(129) 0x41f402 JE 41f597 |
(129) 0x41f408 SUB %R13D,%EDX |
(129) 0x41f40b LEA -0x1(%RDX),%R15D |
(129) 0x41f40f CMP $0x2,%R15D |
(129) 0x41f413 JBE 41f488 |
(129) 0x41f415 MOV 0x48(%RSP),%RDI |
(129) 0x41f41a MOVSXD %ESI,%RSI |
(129) 0x41f41d MOV 0x50(%RSP),%R14 |
(129) 0x41f422 MOV 0x60(%RSP),%R9 |
(129) 0x41f427 MOV 0x58(%RSP),%RAX |
(129) 0x41f42c ADD %RSI,%RDI |
(129) 0x41f42f ADD %R13,%RDI |
(129) 0x41f432 LEA (%R9,%RSI,1),%R15 |
(129) 0x41f436 LEA (%R14,%RDI,8),%R10 |
(129) 0x41f43a LEA (%R11,%RSI,1),%RDI |
(129) 0x41f43e ADD %RAX,%RSI |
(129) 0x41f441 ADD %R13,%R15 |
(129) 0x41f444 ADD %R13,%RDI |
(129) 0x41f447 ADD %R13,%RSI |
(129) 0x41f44a VMOVUPD (%R10),%YMM12 |
(129) 0x41f44f MOV 0x70(%RSP),%R13 |
(129) 0x41f454 VMOVUPD -0x8(%R8,%RDI,8),%YMM13 |
(129) 0x41f45b VFMADD132PD (%R13,%RSI,8),%YMM13,%YMM12 |
(129) 0x41f462 MOV 0x78(%RSP),%RSI |
(129) 0x41f467 VSUBPD (%R8,%RDI,8),%YMM12,%YMM14 |
(129) 0x41f46d VDIVPD (%RSI,%R15,8),%YMM14,%YMM15 |
(129) 0x41f473 VMOVUPD %YMM15,(%R10) |
(129) 0x41f478 TEST $0x3,%DL |
(129) 0x41f47b JE 41f597 |
(129) 0x41f481 AND $-0x4,%EDX |
(129) 0x41f484 ADD %EDX,%EBX |
(129) 0x41f486 ADD %EDX,%ECX |
(129) 0x41f488 MOV 0x48(%RSP),%R15 |
(129) 0x41f48d MOVSXD %ECX,%RAX |
(129) 0x41f490 MOV 0x50(%RSP),%R14 |
(129) 0x41f495 LEA -0x1(%RCX),%R10D |
(129) 0x41f499 MOV 0x58(%RSP),%R9 |
(129) 0x41f49e MOVSXD %R10D,%RSI |
(129) 0x41f4a1 MOV 0x60(%RSP),%R10 |
(129) 0x41f4a6 LEA (%R15,%RAX,1),%RDX |
(129) 0x41f4aa ADD %R11,%RSI |
(129) 0x41f4ad LEA (%R14,%RDX,8),%R13 |
(129) 0x41f4b1 MOV 0x70(%RSP),%RDX |
(129) 0x41f4b6 LEA (%R9,%RAX,1),%RDI |
(129) 0x41f4ba VMOVSD (%R8,%RSI,8),%XMM3 |
(129) 0x41f4c0 MOV 0x78(%RSP),%RSI |
(129) 0x41f4c5 VMOVSD (%RDX,%RDI,8),%XMM0 |
(129) 0x41f4ca LEA (%R11,%RAX,1),%RDI |
(129) 0x41f4ce ADD %R10,%RAX |
(129) 0x41f4d1 LEA (%R8,%RDI,8),%RDX |
(129) 0x41f4d5 LEA 0x1(%RBX),%EDI |
(129) 0x41f4d8 VFMADD132SD (%R13),%XMM3,%XMM0 |
(129) 0x41f4de VSUBSD (%RDX),%XMM0,%XMM1 |
(129) 0x41f4e2 VDIVSD (%RSI,%RAX,8),%XMM1,%XMM2 |
(129) 0x41f4e7 VMOVSD %XMM2,(%R13) |
(129) 0x41f4ed MOV 0x6c(%RSP),%R13D |
(129) 0x41f4f2 LEA 0x1(%RCX),%EAX |
(129) 0x41f4f5 CMP %R13D,%EDI |
(129) 0x41f4f8 JAE 41f597 |
(129) 0x41f4fe CLTQ |
(129) 0x41f500 MOV %R14,%R13 |
(129) 0x41f503 ADD $0x2,%EBX |
(129) 0x41f506 ADD $0x2,%ECX |
(129) 0x41f509 LEA (%R15,%RAX,1),%RSI |
(129) 0x41f50d LEA (%R14,%RSI,8),%RSI |
(129) 0x41f511 LEA (%R11,%RAX,1),%R14 |
(129) 0x41f515 LEA (%R8,%R14,8),%RDI |
(129) 0x41f519 MOV %R9,%R14 |
(129) 0x41f51c LEA (%R9,%RAX,1),%R9 |
(129) 0x41f520 ADD %R10,%RAX |
(129) 0x41f523 MOV %RDI,0x60(%RSP) |
(129) 0x41f528 MOV 0x70(%RSP),%RDI |
(129) 0x41f52d VMOVSD (%RDI,%R9,8),%XMM5 |
(129) 0x41f533 MOV 0x60(%RSP),%R9 |
(129) 0x41f538 VMOVSD (%R9),%XMM4 |
(129) 0x41f53d MOV %R10,%R9 |
(129) 0x41f540 MOV 0x78(%RSP),%R10 |
(129) 0x41f545 VFMSUB132SD (%RSI),%XMM4,%XMM5 |
(129) 0x41f54a VADDSD (%RDX),%XMM5,%XMM6 |
(129) 0x41f54e MOV 0x6c(%RSP),%EDX |
(129) 0x41f552 VDIVSD (%R10,%RAX,8),%XMM6,%XMM7 |
(129) 0x41f558 VMOVSD %XMM7,(%RSI) |
(129) 0x41f55c CMP %EDX,%EBX |
(129) 0x41f55e JAE 41f597 |
(129) 0x41f560 MOVSXD %ECX,%RCX |
(129) 0x41f563 MOV 0x60(%RSP),%RBX |
(129) 0x41f568 ADD %RCX,%R15 |
(129) 0x41f56b ADD %RCX,%R11 |
(129) 0x41f56e ADD %RCX,%R14 |
(129) 0x41f571 ADD %RCX,%R9 |
(129) 0x41f574 LEA (%R13,%R15,8),%RAX |
(129) 0x41f579 VMOVSD (%R8,%R11,8),%XMM9 |
(129) 0x41f57f VMOVSD (%RAX),%XMM8 |
(129) 0x41f583 VFMSUB132SD (%RDI,%R14,8),%XMM9,%XMM8 |
(129) 0x41f589 VADDSD (%RBX),%XMM8,%XMM10 |
(129) 0x41f58d VDIVSD (%R10,%R9,8),%XMM10,%XMM11 |
(129) 0x41f593 VMOVSD %XMM11,(%RAX) |
(129) 0x41f597 MOV 0x6c(%RSP),%EBX |
(129) 0x41f59b INC %R12 |
(129) 0x41f59e LEA (%R12),%R8D |
(129) 0x41f5a2 CMP %R8D,0x44(%RSP) |
(129) 0x41f5a7 JLE 41f5c0 |
(129) 0x41f5a9 MOV 0x3c(%RSP),%ECX |
(129) 0x41f5ad MOV 0x68(%RSP),%EDX |
(129) 0x41f5b1 MOV 0x40(%RSP),%ESI |
(129) 0x41f5b5 SUB %EBX,%ECX |
(129) 0x41f5b7 JMP 41f1c0 |
0x41f5bc NOPL (%RAX) |
0x41f5c0 VZEROUPPER |
0x41f5c3 LEA -0x28(%RBP),%RSP |
0x41f5c7 POP %RBX |
0x41f5c8 POP %R12 |
0x41f5ca POP %R13 |
0x41f5cc POP %R14 |
0x41f5ce POP %R15 |
0x41f5d0 POP %RBP |
0x41f5d1 RET |
0x41f5d2 NOPW (%RAX,%RAX,1) |
(129) 0x41f5d8 MOV %ESI,%ECX |
(129) 0x41f5da XOR %R13D,%R13D |
(129) 0x41f5dd JMP 41f408 |
0x41f5e2 INC %ECX |
0x41f5e4 XOR %EDX,%EDX |
0x41f5e6 JMP 41f161 |
0x41f5eb NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 266 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41f5c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41f5c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x68(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41f5e2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x502> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41f5c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x68(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41f161 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 266 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41f5c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41f5c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x68(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41f5e2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x502> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41f5c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x68(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41f161 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 3.41 | 1.09 |
▼Loop 129 - advec_mom.cpp:149-149 - exec– | 0.01 | 0 |
○Loop 130 - advec_mom.cpp:149-149 - exec | 3.41 | 1.08 |