Function: clover_unpack_message_left(global_variables&, int, int, int, int, clover::Buffer2D<double> ... | Module: exec | Source: pack_kernel.cpp:88-92 [...] | Coverage: 0.03% |
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Function: clover_unpack_message_left(global_variables&, int, int, int, int, clover::Buffer2D<double> ... | Module: exec | Source: pack_kernel.cpp:88-92 [...] | Coverage: 0.03% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/pack_kernel.cpp: 88 - 92 |
-------------------------------------------------------------------------------- |
88: #pragma omp parallel for simd |
89: for (int k = (y_min - depth + 1); k < (y_max + y_inc + depth + 2); k++) { |
90: for (int j = 0; j < depth; ++j) { |
91: int index = buffer_offset + j + k * depth; |
92: field(x_min - j, k) = left_rcv[index]; |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42cc80 PUSH %RBP |
0x42cc81 MOV %RSP,%RBP |
0x42cc84 PUSH %R15 |
0x42cc86 PUSH %R14 |
0x42cc88 PUSH %R13 |
0x42cc8a PUSH %R12 |
0x42cc8c MOV %RDI,%R12 |
0x42cc8f PUSH %RBX |
0x42cc90 SUB $0x8,%RSP |
0x42cc94 MOV 0x1c(%RDI),%EBX |
0x42cc97 MOV 0x14(%RDI),%R8D |
0x42cc9b SUB %EBX,%R8D |
0x42cc9e LEA 0x1(%R8),%R14D |
0x42cca2 CALL 4046c0 <omp_get_num_threads@plt> |
0x42cca7 MOV %EAX,%R13D |
0x42ccaa CALL 4045b0 <omp_get_thread_num@plt> |
0x42ccaf MOV %EAX,%ECX |
0x42ccb1 MOV 0x18(%R12),%EAX |
0x42ccb6 ADD 0x24(%R12),%EAX |
0x42ccbb LEA 0x2(%RBX,%RAX,1),%EAX |
0x42ccbf SUB %R14D,%EAX |
0x42ccc2 CLTD |
0x42ccc3 IDIV %R13D |
0x42ccc6 CMP %EDX,%ECX |
0x42ccc8 JL 42ce86 |
0x42ccce IMUL %EAX,%ECX |
0x42ccd1 ADD %ECX,%EDX |
0x42ccd3 ADD %EDX,%EAX |
0x42ccd5 CMP %EAX,%EDX |
0x42ccd7 JGE 42ce5e |
0x42ccdd ADD %R14D,%EDX |
0x42cce0 MOV %EBX,%R9D |
0x42cce3 MOVSXD %EBX,%R11 |
0x42cce6 MOV 0x8(%R12),%R15 |
0x42cceb IMUL %EDX,%R9D |
0x42ccef MOV (%R12),%R10 |
0x42ccf3 MOVSXD 0x10(%R12),%R13 |
0x42ccf8 LEA (%R14,%RAX,1),%R8D |
0x42ccfc SAL $0x3,%R11 |
0x42cd00 MOVSXD 0x20(%R12),%R14 |
0x42cd05 MOVSXD %EDX,%RDI |
0x42cd08 XOR %R12D,%R12D |
0x42cd0b NOPL (%RAX,%RAX,1) |
(187) 0x42cd10 TEST %EBX,%EBX |
(187) 0x42cd12 JLE 42ce4b |
(187) 0x42cd18 MOV 0x8(%R15),%RAX |
(187) 0x42cd1c MOVSXD %R9D,%RCX |
(187) 0x42cd1f MOV 0x10(%R10),%RSI |
(187) 0x42cd23 ADD %R14,%RCX |
(187) 0x42cd26 LEA (%RAX,%RCX,8),%RDX |
(187) 0x42cd2a MOV (%R10),%RCX |
(187) 0x42cd2d IMUL %RDI,%RCX |
(187) 0x42cd31 ADD %R13,%RCX |
(187) 0x42cd34 SAL $0x3,%RCX |
(187) 0x42cd38 LEA (%RSI,%RCX,1),%RAX |
(187) 0x42cd3c SUB %R11,%RSI |
(187) 0x42cd3f ADD %RCX,%RSI |
(187) 0x42cd42 MOV %RAX,%RCX |
(187) 0x42cd45 SUB %RSI,%RCX |
(187) 0x42cd48 SUB $0x8,%RCX |
(187) 0x42cd4c SHR $0x3,%RCX |
(187) 0x42cd50 INC %RCX |
(187) 0x42cd53 AND $0x7,%ECX |
(187) 0x42cd56 JE 42cdef |
(187) 0x42cd5c CMP $0x1,%RCX |
(187) 0x42cd60 JE 42cdd9 |
(187) 0x42cd62 CMP $0x2,%RCX |
(187) 0x42cd66 JE 42cdc8 |
(187) 0x42cd68 CMP $0x3,%RCX |
(187) 0x42cd6c JE 42cdb7 |
(187) 0x42cd6e CMP $0x4,%RCX |
(187) 0x42cd72 JE 42cda6 |
(187) 0x42cd74 CMP $0x5,%RCX |
(187) 0x42cd78 JE 42cd95 |
(187) 0x42cd7a CMP $0x6,%RCX |
(187) 0x42cd7e JNE 42ce70 |
(187) 0x42cd84 VMOVSD (%RDX),%XMM1 |
(187) 0x42cd88 SUB $0x8,%RAX |
(187) 0x42cd8c ADD $0x8,%RDX |
(187) 0x42cd90 VMOVSD %XMM1,0x8(%RAX) |
(187) 0x42cd95 VMOVSD (%RDX),%XMM2 |
(187) 0x42cd99 SUB $0x8,%RAX |
(187) 0x42cd9d ADD $0x8,%RDX |
(187) 0x42cda1 VMOVSD %XMM2,0x8(%RAX) |
(187) 0x42cda6 VMOVSD (%RDX),%XMM3 |
(187) 0x42cdaa SUB $0x8,%RAX |
(187) 0x42cdae ADD $0x8,%RDX |
(187) 0x42cdb2 VMOVSD %XMM3,0x8(%RAX) |
(187) 0x42cdb7 VMOVSD (%RDX),%XMM4 |
(187) 0x42cdbb SUB $0x8,%RAX |
(187) 0x42cdbf ADD $0x8,%RDX |
(187) 0x42cdc3 VMOVSD %XMM4,0x8(%RAX) |
(187) 0x42cdc8 VMOVSD (%RDX),%XMM5 |
(187) 0x42cdcc SUB $0x8,%RAX |
(187) 0x42cdd0 ADD $0x8,%RDX |
(187) 0x42cdd4 VMOVSD %XMM5,0x8(%RAX) |
(187) 0x42cdd9 VMOVSD (%RDX),%XMM6 |
(187) 0x42cddd SUB $0x8,%RAX |
(187) 0x42cde1 ADD $0x8,%RDX |
(187) 0x42cde5 VMOVSD %XMM6,0x8(%RAX) |
(187) 0x42cdea CMP %RSI,%RAX |
(187) 0x42cded JE 42ce4b |
(188) 0x42cdef VMOVSD (%RDX),%XMM7 |
(188) 0x42cdf3 SUB $0x40,%RAX |
(188) 0x42cdf7 ADD $0x40,%RDX |
(188) 0x42cdfb VMOVSD %XMM7,0x40(%RAX) |
(188) 0x42ce00 VMOVSD -0x38(%RDX),%XMM8 |
(188) 0x42ce05 VMOVSD %XMM8,0x38(%RAX) |
(188) 0x42ce0a VMOVSD -0x30(%RDX),%XMM9 |
(188) 0x42ce0f VMOVSD %XMM9,0x30(%RAX) |
(188) 0x42ce14 VMOVSD -0x28(%RDX),%XMM10 |
(188) 0x42ce19 VMOVSD %XMM10,0x28(%RAX) |
(188) 0x42ce1e VMOVSD -0x20(%RDX),%XMM11 |
(188) 0x42ce23 VMOVSD %XMM11,0x20(%RAX) |
(188) 0x42ce28 VMOVSD -0x18(%RDX),%XMM12 |
(188) 0x42ce2d VMOVSD %XMM12,0x18(%RAX) |
(188) 0x42ce32 VMOVSD -0x10(%RDX),%XMM13 |
(188) 0x42ce37 VMOVSD %XMM13,0x10(%RAX) |
(188) 0x42ce3c VMOVSD -0x8(%RDX),%XMM14 |
(188) 0x42ce41 VMOVSD %XMM14,0x8(%RAX) |
(188) 0x42ce46 CMP %RSI,%RAX |
(188) 0x42ce49 JNE 42cdef |
(187) 0x42ce4b INC %RDI |
(187) 0x42ce4e ADD %EBX,%R9D |
(187) 0x42ce51 LEA (%R12,%RDI,1),%ESI |
(187) 0x42ce55 CMP %ESI,%R8D |
(187) 0x42ce58 JG 42cd10 |
0x42ce5e ADD $0x8,%RSP |
0x42ce62 POP %RBX |
0x42ce63 POP %R12 |
0x42ce65 POP %R13 |
0x42ce67 POP %R14 |
0x42ce69 POP %R15 |
0x42ce6b POP %RBP |
0x42ce6c RET |
0x42ce6d NOPL (%RAX) |
(187) 0x42ce70 VMOVSD (%RDX),%XMM0 |
(187) 0x42ce74 SUB $0x8,%RAX |
(187) 0x42ce78 ADD $0x8,%RDX |
(187) 0x42ce7c VMOVSD %XMM0,0x8(%RAX) |
(187) 0x42ce81 JMP 42cd84 |
0x42ce86 INC %EAX |
0x42ce88 XOR %EDX,%EDX |
0x42ce8a JMP 42ccce |
0x42ce8f NOP |
Path / |
Source file and lines | pack_kernel.cpp:88-92 |
Module | exec |
nb instructions | 56 |
nb uops | 61 |
loop length | 172 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.50 | 6.00 | 5.00 | 5.00 | 4.00 | 4.60 | 4.50 | 4.00 | 4.00 | 4.00 | 4.40 | 5.00 |
cycles | 4.50 | 8.87 | 5.00 | 5.00 | 4.00 | 4.60 | 4.50 | 4.00 | 4.00 | 4.00 | 4.40 | 5.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 17.82-17.63 |
Stall cycles | 7.78-7.59 |
LM full (events) | 9.39-9.20 |
Front-end | 10.17 |
Dispatch | 8.87 |
DIV/SQRT | 6.00 |
Overall L1 | 10.17 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 9% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R12),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x24(%R12),%EAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x2(%RBX,%RAX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 42ce86 <_Z26clover_unpack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x206> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ce5e <_Z26clover_unpack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x1de> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R14D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD %EBX,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x8(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EDX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV (%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R14,%RAX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOVSXD 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ccce <_Z26clover_unpack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | pack_kernel.cpp:88-92 |
Module | exec |
nb instructions | 56 |
nb uops | 61 |
loop length | 172 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.50 | 6.00 | 5.00 | 5.00 | 4.00 | 4.60 | 4.50 | 4.00 | 4.00 | 4.00 | 4.40 | 5.00 |
cycles | 4.50 | 8.87 | 5.00 | 5.00 | 4.00 | 4.60 | 4.50 | 4.00 | 4.00 | 4.00 | 4.40 | 5.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 17.82-17.63 |
Stall cycles | 7.78-7.59 |
LM full (events) | 9.39-9.20 |
Front-end | 10.17 |
Dispatch | 8.87 |
DIV/SQRT | 6.00 |
Overall L1 | 10.17 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 9% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R12),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x24(%R12),%EAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x2(%RBX,%RAX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 42ce86 <_Z26clover_unpack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x206> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ce5e <_Z26clover_unpack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x1de> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R14D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD %EBX,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x8(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EDX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV (%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R14,%RAX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOVSXD 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ccce <_Z26clover_unpack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼clover_unpack_message_left(global_variables&, int, int, int, int, clover::Buffer2D | 0.03 | 0.01 |
▼Loop 187 - pack_kernel.cpp:90-92 - exec– | 0.03 | 0.02 |
○Loop 188 - pack_kernel.cpp:90-92 - exec | 0 | 0 |