Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.06% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.06% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 146 - 150 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
148: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
149: pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
150: post_vol(i, j) = volume(i, j); |
0x41a6c0 PUSH %RBP |
0x41a6c1 MOV %RSP,%RBP |
0x41a6c4 PUSH %R15 |
0x41a6c6 PUSH %R14 |
0x41a6c8 PUSH %R13 |
0x41a6ca PUSH %R12 |
0x41a6cc PUSH %RBX |
0x41a6cd AND $-0x40,%RSP |
0x41a6d1 ADD $-0x80,%RSP |
0x41a6d5 MOV 0x28(%RDI),%EAX |
0x41a6d8 MOV 0x2c(%RDI),%EDX |
0x41a6db MOV 0x20(%RDI),%EBX |
0x41a6de MOV 0x24(%RDI),%ECX |
0x41a6e1 ADD $0x4,%EDX |
0x41a6e4 LEA -0x1(%RAX),%R15D |
0x41a6e8 LEA -0x1(%RBX),%ESI |
0x41a6eb MOV %EDX,0x40(%RSP) |
0x41a6ef MOV %ESI,0x3c(%RSP) |
0x41a6f3 CMP %EDX,%R15D |
0x41a6f6 JGE 41abd3 |
0x41a6fc MOV %EDX,%EBX |
0x41a6fe LEA 0x4(%RCX),%R14D |
0x41a702 SUB %R15D,%EBX |
0x41a705 CMP %R14D,%ESI |
0x41a708 JGE 41abd3 |
0x41a70e MOV %RDI,%R13 |
0x41a711 MOV %R14D,%EDI |
0x41a714 SUB %ESI,%EDI |
0x41a716 MOV %EDI,0x44(%RSP) |
0x41a71a CALL 4046c0 <omp_get_num_threads@plt> |
0x41a71f MOV %EAX,%R12D |
0x41a722 CALL 4045b0 <omp_get_thread_num@plt> |
0x41a727 XOR %EDX,%EDX |
0x41a729 MOV %EAX,%R8D |
0x41a72c MOV 0x44(%RSP),%EAX |
0x41a730 IMUL %EBX,%EAX |
0x41a733 DIV %R12D |
0x41a736 MOV %EAX,%EDI |
0x41a738 CMP %EDX,%R8D |
0x41a73b JB 41abf4 |
0x41a741 IMUL %EDI,%R8D |
0x41a745 LEA (%R8,%RDX,1),%EBX |
0x41a749 LEA (%RDI,%RBX,1),%R9D |
0x41a74d MOV %R9D,0x38(%RSP) |
0x41a752 CMP %R9D,%EBX |
0x41a755 JAE 41abd3 |
0x41a75b XOR %EDX,%EDX |
0x41a75d MOV %EBX,%EAX |
0x41a75f MOV 0x3c(%RSP),%R10D |
0x41a764 MOV 0x8(%R13),%RCX |
0x41a768 DIVL 0x44(%RSP) |
0x41a76c MOV %RCX,0x28(%RSP) |
0x41a771 ADD %EDX,%R10D |
0x41a774 MOV %R14D,%EDX |
0x41a777 LEA (%RAX,%R15,1),%R11D |
0x41a77b MOV 0x10(%R13),%R14 |
0x41a77f SUB %R10D,%EDX |
0x41a782 MOV (%R13),%R15 |
0x41a786 MOV 0x18(%R13),%R13 |
0x41a78a MOV %R10D,0x74(%RSP) |
0x41a78f CMP %EDX,%EDI |
0x41a791 MOV %R14,0x20(%RSP) |
0x41a796 MOVSXD %R11D,%RCX |
0x41a799 CMOVBE %EDI,%EDX |
0x41a79c MOV %R15,0x30(%RSP) |
0x41a7a1 MOV %R13,0x18(%RSP) |
0x41a7a6 LEA (%RBX,%RDX,1),%ESI |
0x41a7a9 MOV %ESI,0x70(%RSP) |
0x41a7ad CMP %ESI,%EBX |
0x41a7af JAE 41abb3 |
0x41a7b5 NOPL (%RAX) |
(106) 0x41a7b8 MOV 0x28(%RSP),%R8 |
(106) 0x41a7bd MOV 0x30(%RSP),%R12 |
(106) 0x41a7c2 MOV 0x20(%RSP),%RAX |
(106) 0x41a7c7 MOV 0x18(%RSP),%R13 |
(106) 0x41a7cc MOV (%R8),%R9 |
(106) 0x41a7cf MOV 0x10(%R8),%RSI |
(106) 0x41a7d3 LEA 0x1(%RCX),%R8 |
(106) 0x41a7d7 MOV (%R12),%R11 |
(106) 0x41a7db MOV 0x10(%R13),%RDI |
(106) 0x41a7df MOV %R8,0x48(%RSP) |
(106) 0x41a7e4 IMUL %R9,%R8 |
(106) 0x41a7e8 MOV 0x10(%R12),%R15 |
(106) 0x41a7ed MOV 0x10(%RAX),%R14 |
(106) 0x41a7f1 IMUL %RCX,%R11 |
(106) 0x41a7f5 MOV %RDI,0x78(%RSP) |
(106) 0x41a7fa MOV %R8,%R10 |
(106) 0x41a7fd SUB %R9,%R10 |
(106) 0x41a800 MOV (%RAX),%R9 |
(106) 0x41a803 MOV %R11,0x50(%RSP) |
(106) 0x41a808 MOV %R10,0x58(%RSP) |
(106) 0x41a80d IMUL %RCX,%R9 |
(106) 0x41a811 IMUL (%R13),%RCX |
(106) 0x41a816 MOV %R9,0x60(%RSP) |
(106) 0x41a81b MOV %RCX,0x68(%RSP) |
(106) 0x41a820 LEA -0x1(%RDX),%ECX |
(106) 0x41a823 CMP $0x6,%ECX |
(106) 0x41a826 JBE 41abe8 |
(106) 0x41a82c MOVSXD 0x74(%RSP),%RAX |
(106) 0x41a831 MOV 0x68(%RSP),%RDI |
(106) 0x41a836 LEA (%R11,%RAX,1),%R11 |
(106) 0x41a83a LEA (%R9,%RAX,1),%R9 |
(106) 0x41a83e LEA (%R15,%R11,8),%RCX |
(106) 0x41a842 LEA (%R14,%R9,8),%R11 |
(106) 0x41a846 MOV %EDX,%R9D |
(106) 0x41a849 SHR $0x3,%R9D |
(106) 0x41a84d LEA (%R10,%RAX,1),%R10 |
(106) 0x41a851 LEA (%R8,%RAX,1),%R13 |
(106) 0x41a855 ADD %RDI,%RAX |
(106) 0x41a858 SAL $0x6,%R9 |
(106) 0x41a85c LEA (%RSI,%R10,8),%R12 |
(106) 0x41a860 MOV 0x78(%RSP),%R10 |
(106) 0x41a865 LEA (%RSI,%R13,8),%R13 |
(106) 0x41a869 LEA -0x40(%R9),%RDI |
(106) 0x41a86d SHR $0x6,%RDI |
(106) 0x41a871 LEA (%R10,%RAX,8),%R10 |
(106) 0x41a875 XOR %EAX,%EAX |
(106) 0x41a877 INC %RDI |
(106) 0x41a87a AND $0x3,%EDI |
(106) 0x41a87d JE 41a921 |
(106) 0x41a883 CMP $0x1,%RDI |
(106) 0x41a887 JE 41a8e9 |
(106) 0x41a889 CMP $0x2,%RDI |
(106) 0x41a88d JE 41a8ba |
(106) 0x41a88f VMOVUPD (%RCX),%ZMM6 |
(106) 0x41a895 MOV $0x40,%EAX |
(106) 0x41a89a VADDPD (%R13),%ZMM6,%ZMM0 |
(106) 0x41a8a1 VSUBPD (%R12),%ZMM0,%ZMM1 |
(106) 0x41a8a8 VMOVUPD %ZMM1,(%R11) |
(106) 0x41a8ae VMOVUPD (%RCX),%ZMM7 |
(106) 0x41a8b4 VMOVUPD %ZMM7,(%R10) |
(106) 0x41a8ba VMOVUPD (%RCX,%RAX,1),%ZMM2 |
(106) 0x41a8c1 VADDPD (%R13,%RAX,1),%ZMM2,%ZMM3 |
(106) 0x41a8c9 VSUBPD (%R12,%RAX,1),%ZMM3,%ZMM4 |
(106) 0x41a8d0 VMOVUPD %ZMM4,(%R11,%RAX,1) |
(106) 0x41a8d7 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(106) 0x41a8de VMOVUPD %ZMM5,(%R10,%RAX,1) |
(106) 0x41a8e5 ADD $0x40,%RAX |
(106) 0x41a8e9 VMOVUPD (%RCX,%RAX,1),%ZMM8 |
(106) 0x41a8f0 VADDPD (%R13,%RAX,1),%ZMM8,%ZMM9 |
(106) 0x41a8f8 VSUBPD (%R12,%RAX,1),%ZMM9,%ZMM10 |
(106) 0x41a8ff VMOVUPD %ZMM10,(%R11,%RAX,1) |
(106) 0x41a906 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(106) 0x41a90d VMOVUPD %ZMM11,(%R10,%RAX,1) |
(106) 0x41a914 ADD $0x40,%RAX |
(106) 0x41a918 CMP %RAX,%R9 |
(106) 0x41a91b JE 41a9eb |
(107) 0x41a921 VMOVUPD (%RCX,%RAX,1),%ZMM12 |
(107) 0x41a928 VADDPD (%R13,%RAX,1),%ZMM12,%ZMM13 |
(107) 0x41a930 VSUBPD (%R12,%RAX,1),%ZMM13,%ZMM14 |
(107) 0x41a937 VMOVUPD %ZMM14,(%R11,%RAX,1) |
(107) 0x41a93e VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(107) 0x41a945 VMOVUPD %ZMM15,(%R10,%RAX,1) |
(107) 0x41a94c VMOVUPD 0x40(%RCX,%RAX,1),%ZMM6 |
(107) 0x41a954 VADDPD 0x40(%R13,%RAX,1),%ZMM6,%ZMM0 |
(107) 0x41a95c VSUBPD 0x40(%R12,%RAX,1),%ZMM0,%ZMM1 |
(107) 0x41a964 VMOVUPD %ZMM1,0x40(%R11,%RAX,1) |
(107) 0x41a96c VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(107) 0x41a974 VMOVUPD %ZMM7,0x40(%R10,%RAX,1) |
(107) 0x41a97c VMOVUPD 0x80(%RCX,%RAX,1),%ZMM2 |
(107) 0x41a984 VADDPD 0x80(%R13,%RAX,1),%ZMM2,%ZMM3 |
(107) 0x41a98c VSUBPD 0x80(%R12,%RAX,1),%ZMM3,%ZMM4 |
(107) 0x41a994 VMOVUPD %ZMM4,0x80(%R11,%RAX,1) |
(107) 0x41a99c VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(107) 0x41a9a4 VMOVUPD %ZMM5,0x80(%R10,%RAX,1) |
(107) 0x41a9ac VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8 |
(107) 0x41a9b4 VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM9 |
(107) 0x41a9bc VSUBPD 0xc0(%R12,%RAX,1),%ZMM9,%ZMM10 |
(107) 0x41a9c4 VMOVUPD %ZMM10,0xc0(%R11,%RAX,1) |
(107) 0x41a9cc VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(107) 0x41a9d4 VMOVUPD %ZMM11,0xc0(%R10,%RAX,1) |
(107) 0x41a9dc ADD $0x100,%RAX |
(107) 0x41a9e2 CMP %RAX,%R9 |
(107) 0x41a9e5 JNE 41a921 |
(106) 0x41a9eb MOV 0x74(%RSP),%ECX |
(106) 0x41a9ef MOV %EDX,%R12D |
(106) 0x41a9f2 AND $-0x8,%R12D |
(106) 0x41a9f6 ADD %R12D,%EBX |
(106) 0x41a9f9 LEA (%R12,%RCX,1),%EDI |
(106) 0x41a9fd TEST $0x7,%DL |
(106) 0x41aa00 JE 41ab7a |
(106) 0x41aa06 SUB %R12D,%EDX |
(106) 0x41aa09 LEA -0x1(%RDX),%R13D |
(106) 0x41aa0d CMP $0x2,%R13D |
(106) 0x41aa11 JBE 41aa88 |
(106) 0x41aa13 MOVSXD 0x74(%RSP),%RAX |
(106) 0x41aa18 MOV 0x50(%RSP),%R11 |
(106) 0x41aa1d MOV 0x58(%RSP),%R13 |
(106) 0x41aa22 LEA (%R8,%RAX,1),%R9 |
(106) 0x41aa26 LEA (%R11,%RAX,1),%R10 |
(106) 0x41aa2a ADD %R12,%R9 |
(106) 0x41aa2d ADD %R12,%R10 |
(106) 0x41aa30 LEA (%R13,%RAX,1),%R11 |
(106) 0x41aa35 VMOVUPD (%RSI,%R9,8),%YMM12 |
(106) 0x41aa3b LEA (%R15,%R10,8),%RCX |
(106) 0x41aa3f ADD %R12,%R11 |
(106) 0x41aa42 MOV 0x60(%RSP),%R10 |
(106) 0x41aa47 VADDPD (%RCX),%YMM12,%YMM13 |
(106) 0x41aa4b LEA (%R10,%RAX,1),%R9 |
(106) 0x41aa4f ADD %R12,%R9 |
(106) 0x41aa52 VSUBPD (%RSI,%R11,8),%YMM13,%YMM14 |
(106) 0x41aa58 VMOVUPD %YMM14,(%R14,%R9,8) |
(106) 0x41aa5e VMOVUPD (%RCX),%YMM15 |
(106) 0x41aa62 MOV 0x68(%RSP),%RCX |
(106) 0x41aa67 ADD %RCX,%RAX |
(106) 0x41aa6a ADD %R12,%RAX |
(106) 0x41aa6d MOV 0x78(%RSP),%R12 |
(106) 0x41aa72 VMOVUPD %YMM15,(%R12,%RAX,8) |
(106) 0x41aa78 TEST $0x3,%DL |
(106) 0x41aa7b JE 41ab7a |
(106) 0x41aa81 AND $-0x4,%EDX |
(106) 0x41aa84 ADD %EDX,%EBX |
(106) 0x41aa86 ADD %EDX,%EDI |
(106) 0x41aa88 MOVSXD %EDI,%RAX |
(106) 0x41aa8b MOV 0x50(%RSP),%R10 |
(106) 0x41aa90 MOV 0x58(%RSP),%R12 |
(106) 0x41aa95 LEA (%R8,%RAX,1),%R9 |
(106) 0x41aa99 MOV 0x60(%RSP),%R11 |
(106) 0x41aa9e VMOVSD (%RSI,%R9,8),%XMM6 |
(106) 0x41aaa4 LEA (%R10,%RAX,1),%RDX |
(106) 0x41aaa8 LEA 0x1(%RBX),%R9D |
(106) 0x41aaac LEA (%R15,%RDX,8),%R13 |
(106) 0x41aab0 LEA (%R12,%RAX,1),%RDX |
(106) 0x41aab4 VADDSD (%R13),%XMM6,%XMM0 |
(106) 0x41aaba LEA (%R11,%RAX,1),%RCX |
(106) 0x41aabe VSUBSD (%RSI,%RDX,8),%XMM0,%XMM1 |
(106) 0x41aac3 MOV 0x70(%RSP),%EDX |
(106) 0x41aac7 VMOVSD %XMM1,(%R14,%RCX,8) |
(106) 0x41aacd MOV 0x78(%RSP),%RCX |
(106) 0x41aad2 VMOVSD (%R13),%XMM7 |
(106) 0x41aad8 MOV 0x68(%RSP),%R13 |
(106) 0x41aadd ADD %R13,%RAX |
(106) 0x41aae0 VMOVSD %XMM7,(%RCX,%RAX,8) |
(106) 0x41aae5 LEA 0x1(%RDI),%EAX |
(106) 0x41aae8 CMP %EDX,%R9D |
(106) 0x41aaeb JAE 41ab7a |
(106) 0x41aaf1 CLTQ |
(106) 0x41aaf3 ADD $0x2,%EBX |
(106) 0x41aaf6 ADD $0x2,%EDI |
(106) 0x41aaf9 LEA (%R8,%RAX,1),%R9 |
(106) 0x41aafd LEA (%R10,%RAX,1),%RCX |
(106) 0x41ab01 VMOVSD (%RSI,%R9,8),%XMM2 |
(106) 0x41ab07 LEA (%R15,%RCX,8),%RDX |
(106) 0x41ab0b LEA (%R12,%RAX,1),%R9 |
(106) 0x41ab0f LEA (%R11,%RAX,1),%RCX |
(106) 0x41ab13 ADD %R13,%RAX |
(106) 0x41ab16 VADDSD (%RDX),%XMM2,%XMM3 |
(106) 0x41ab1a VSUBSD (%RSI,%R9,8),%XMM3,%XMM4 |
(106) 0x41ab20 MOV %R13,%R9 |
(106) 0x41ab23 MOV 0x78(%RSP),%R13 |
(106) 0x41ab28 VMOVSD %XMM4,(%R14,%RCX,8) |
(106) 0x41ab2e VMOVSD (%RDX),%XMM5 |
(106) 0x41ab32 VMOVSD %XMM5,(%R13,%RAX,8) |
(106) 0x41ab39 MOV 0x70(%RSP),%EAX |
(106) 0x41ab3d CMP %EAX,%EBX |
(106) 0x41ab3f JAE 41ab7a |
(106) 0x41ab41 MOVSXD %EDI,%RBX |
(106) 0x41ab44 ADD %RBX,%R8 |
(106) 0x41ab47 ADD %RBX,%R10 |
(106) 0x41ab4a ADD %RBX,%R12 |
(106) 0x41ab4d ADD %RBX,%R11 |
(106) 0x41ab50 VMOVSD (%RSI,%R8,8),%XMM8 |
(106) 0x41ab56 LEA (%R15,%R10,8),%R15 |
(106) 0x41ab5a ADD %RBX,%R9 |
(106) 0x41ab5d VADDSD (%R15),%XMM8,%XMM9 |
(106) 0x41ab62 VSUBSD (%RSI,%R12,8),%XMM9,%XMM10 |
(106) 0x41ab68 VMOVSD %XMM10,(%R14,%R11,8) |
(106) 0x41ab6e VMOVSD (%R15),%XMM11 |
(106) 0x41ab73 VMOVSD %XMM11,(%R13,%R9,8) |
(106) 0x41ab7a MOV 0x48(%RSP),%RCX |
(106) 0x41ab7f MOV 0x70(%RSP),%EBX |
(106) 0x41ab83 LEA (%RCX),%ESI |
(106) 0x41ab85 CMP %ESI,0x40(%RSP) |
(106) 0x41ab89 JLE 41abd0 |
(106) 0x41ab8b MOV 0x38(%RSP),%EDI |
(106) 0x41ab8f MOV 0x44(%RSP),%EDX |
(106) 0x41ab93 MOV 0x3c(%RSP),%R8D |
(106) 0x41ab98 SUB %EBX,%EDI |
(106) 0x41ab9a CMP %EDX,%EDI |
(106) 0x41ab9c MOV %R8D,0x74(%RSP) |
(106) 0x41aba1 CMOVBE %EDI,%EDX |
(106) 0x41aba4 LEA (%RBX,%RDX,1),%ESI |
(106) 0x41aba7 MOV %ESI,0x70(%RSP) |
(106) 0x41abab CMP %ESI,%EBX |
(106) 0x41abad JB 41a7b8 |
(108) 0x41abb3 LEA 0x1(%RCX),%RDI |
(108) 0x41abb7 MOV %RDI,0x48(%RSP) |
(108) 0x41abbc MOV 0x48(%RSP),%RCX |
(108) 0x41abc1 LEA (%RCX),%ESI |
(108) 0x41abc3 CMP %ESI,0x40(%RSP) |
(108) 0x41abc7 JG 41ab8b |
0x41abc9 NOPL (%RAX) |
0x41abd0 VZEROUPPER |
0x41abd3 LEA -0x28(%RBP),%RSP |
0x41abd7 POP %RBX |
0x41abd8 POP %R12 |
0x41abda POP %R13 |
0x41abdc POP %R14 |
0x41abde POP %R15 |
0x41abe0 POP %RBP |
0x41abe1 RET |
0x41abe2 NOPW (%RAX,%RAX,1) |
(106) 0x41abe8 MOV 0x74(%RSP),%EDI |
(106) 0x41abec XOR %R12D,%R12D |
(106) 0x41abef JMP 41aa06 |
0x41abf4 INC %EDI |
0x41abf6 XOR %EDX,%EDX |
0x41abf8 JMP 41a741 |
0x41abfd NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 86 |
nb uops | 97 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
cycles | 7.20 | 12.33 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.54 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 12.33 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41abd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41abd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41abf4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x534> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41abd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RCX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMOVBE %EDI,%EDX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RDX,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ESI,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41abb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x4f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41a741 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 86 |
nb uops | 97 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
cycles | 7.20 | 12.33 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.54 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 12.33 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41abd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41abd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41abf4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x534> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41abd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RCX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMOVBE %EDI,%EDX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RDX,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ESI,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41abb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x4f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41a741 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.06 | 0.34 |
▼Loop 108 - advec_cell.cpp:149-150 - exec– | 0 | 0 |
▼Loop 106 - advec_cell.cpp:149-150 - exec– | 0 | 0 |
○Loop 107 - advec_cell.cpp:149-150 - exec | 1.05 | 0.34 |