Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 1.66% |
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Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 1.66% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density0(i, j) = density1(i, j); |
38: energy0(i, j) = energy1(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x431b30 PUSH %RBP |
0x431b31 MOV %RSP,%RBP |
0x431b34 PUSH %R15 |
0x431b36 PUSH %R14 |
0x431b38 PUSH %R13 |
0x431b3a PUSH %R12 |
0x431b3c PUSH %RBX |
0x431b3d AND $-0x40,%RSP |
0x431b41 ADD $-0x80,%RSP |
0x431b45 MOV 0x28(%RDI),%EAX |
0x431b48 MOV 0x2c(%RDI),%EDX |
0x431b4b MOV 0x20(%RDI),%EBX |
0x431b4e MOV 0x24(%RDI),%ECX |
0x431b51 ADD $0x2,%EDX |
0x431b54 LEA 0x1(%RAX),%R15D |
0x431b58 LEA 0x1(%RBX),%ESI |
0x431b5b MOV %EDX,0x50(%RSP) |
0x431b5f MOV %ESI,0x4c(%RSP) |
0x431b63 CMP %EDX,%R15D |
0x431b66 JGE 43205b |
0x431b6c MOV %EDX,%EBX |
0x431b6e LEA 0x2(%RCX),%R14D |
0x431b72 SUB %R15D,%EBX |
0x431b75 CMP %R14D,%ESI |
0x431b78 JGE 43205b |
0x431b7e MOV %RDI,%R13 |
0x431b81 MOV %R14D,%EDI |
0x431b84 SUB %ESI,%EDI |
0x431b86 MOV %EDI,0x54(%RSP) |
0x431b8a CALL 4046c0 <omp_get_num_threads@plt> |
0x431b8f MOV %EAX,%R12D |
0x431b92 CALL 4045b0 <omp_get_thread_num@plt> |
0x431b97 XOR %EDX,%EDX |
0x431b99 MOV %EAX,%R8D |
0x431b9c MOV 0x54(%RSP),%EAX |
0x431ba0 IMUL %EBX,%EAX |
0x431ba3 DIV %R12D |
0x431ba6 MOV %EAX,%R12D |
0x431ba9 CMP %EDX,%R8D |
0x431bac JB 43207c |
0x431bb2 IMUL %R12D,%R8D |
0x431bb6 LEA (%R8,%RDX,1),%R9D |
0x431bba LEA (%R12,%R9,1),%R10D |
0x431bbe MOV %R10D,0x48(%RSP) |
0x431bc3 CMP %R10D,%R9D |
0x431bc6 JAE 43205b |
0x431bcc MOV %R9D,%EAX |
0x431bcf XOR %EDX,%EDX |
0x431bd1 MOV 0x4c(%RSP),%R11D |
0x431bd6 MOV (%R13),%RSI |
0x431bda DIVL 0x54(%RSP) |
0x431bde MOV 0x10(%R13),%RBX |
0x431be2 MOV %RSI,0x38(%RSP) |
0x431be7 MOV %RBX,0x28(%RSP) |
0x431bec ADD %EDX,%R11D |
0x431bef ADD %R15D,%EAX |
0x431bf2 MOV %R14D,%EDX |
0x431bf5 MOV 0x8(%R13),%R15 |
0x431bf9 MOV 0x18(%R13),%R14 |
0x431bfd MOV %R11D,0x7c(%RSP) |
0x431c02 SUB %R11D,%EDX |
0x431c05 MOVSXD %EAX,%RBX |
0x431c08 MOV %R15,0x40(%RSP) |
0x431c0d MOV %R14,0x30(%RSP) |
0x431c12 NOPW (%RAX,%RAX,1) |
(211) 0x431c18 CMP %EDX,%R12D |
(211) 0x431c1b CMOVBE %R12D,%EDX |
(211) 0x431c1f LEA (%R9,%RDX,1),%ECX |
(211) 0x431c23 MOV %ECX,0x78(%RSP) |
(211) 0x431c27 CMP %ECX,%R9D |
(211) 0x431c2a JAE 43202d |
(211) 0x431c30 MOV 0x30(%RSP),%R12 |
(211) 0x431c35 MOV 0x38(%RSP),%RDI |
(211) 0x431c3a LEA -0x1(%RDX),%EAX |
(211) 0x431c3d MOV 0x28(%RSP),%RCX |
(211) 0x431c42 MOV 0x40(%RSP),%R13 |
(211) 0x431c47 MOV (%R12),%RSI |
(211) 0x431c4b MOV (%RDI),%R8 |
(211) 0x431c4e MOV (%RCX),%R10 |
(211) 0x431c51 MOV (%R13),%R11 |
(211) 0x431c55 IMUL %RBX,%R8 |
(211) 0x431c59 MOV 0x10(%R13),%R15 |
(211) 0x431c5d MOV 0x10(%RDI),%R14 |
(211) 0x431c61 IMUL %RBX,%RSI |
(211) 0x431c65 MOV 0x10(%R12),%R13 |
(211) 0x431c6a MOV 0x10(%RCX),%R12 |
(211) 0x431c6e IMUL %RBX,%R10 |
(211) 0x431c72 IMUL %RBX,%R11 |
(211) 0x431c76 MOV %R8,0x60(%RSP) |
(211) 0x431c7b MOV %RSI,0x68(%RSP) |
(211) 0x431c80 MOV %R10,0x70(%RSP) |
(211) 0x431c85 CMP $0x6,%EAX |
(211) 0x431c88 JBE 432070 |
(211) 0x431c8e MOVSXD 0x7c(%RSP),%RAX |
(211) 0x431c93 LEA (%R8,%RAX,1),%RCX |
(211) 0x431c97 LEA (%R11,%RAX,1),%RDI |
(211) 0x431c9b LEA (%R14,%RCX,8),%R8 |
(211) 0x431c9f MOV 0x70(%RSP),%RCX |
(211) 0x431ca4 LEA (%RSI,%RAX,1),%RSI |
(211) 0x431ca8 LEA (%R15,%RDI,8),%R10 |
(211) 0x431cac LEA (%R13,%RSI,8),%RDI |
(211) 0x431cb1 ADD %RCX,%RAX |
(211) 0x431cb4 MOV %EDX,%ECX |
(211) 0x431cb6 SHR $0x3,%ECX |
(211) 0x431cb9 LEA (%R12,%RAX,8),%RSI |
(211) 0x431cbd XOR %EAX,%EAX |
(211) 0x431cbf SAL $0x6,%RCX |
(211) 0x431cc3 MOV %RCX,0x58(%RSP) |
(211) 0x431cc8 SUB $0x40,%RCX |
(211) 0x431ccc SHR $0x6,%RCX |
(211) 0x431cd0 INC %RCX |
(211) 0x431cd3 AND $0x7,%ECX |
(211) 0x431cd6 JE 431df4 |
(211) 0x431cdc CMP $0x1,%RCX |
(211) 0x431ce0 JE 431dc9 |
(211) 0x431ce6 CMP $0x2,%RCX |
(211) 0x431cea JE 431da9 |
(211) 0x431cf0 CMP $0x3,%RCX |
(211) 0x431cf4 JE 431d89 |
(211) 0x431cfa CMP $0x4,%RCX |
(211) 0x431cfe JE 431d69 |
(211) 0x431d00 CMP $0x5,%RCX |
(211) 0x431d04 JE 431d49 |
(211) 0x431d06 CMP $0x6,%RCX |
(211) 0x431d0a JE 431d29 |
(211) 0x431d0c VMOVUPD (%R10),%ZMM3 |
(211) 0x431d12 MOV $0x40,%EAX |
(211) 0x431d17 VMOVUPD %ZMM3,(%R8) |
(211) 0x431d1d VMOVUPD (%RDI),%ZMM4 |
(211) 0x431d23 VMOVUPD %ZMM4,(%RSI) |
(211) 0x431d29 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(211) 0x431d30 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(211) 0x431d37 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(211) 0x431d3e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(211) 0x431d45 ADD $0x40,%RAX |
(211) 0x431d49 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(211) 0x431d50 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(211) 0x431d57 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(211) 0x431d5e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(211) 0x431d65 ADD $0x40,%RAX |
(211) 0x431d69 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(211) 0x431d70 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(211) 0x431d77 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(211) 0x431d7e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(211) 0x431d85 ADD $0x40,%RAX |
(211) 0x431d89 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(211) 0x431d90 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(211) 0x431d97 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(211) 0x431d9e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(211) 0x431da5 ADD $0x40,%RAX |
(211) 0x431da9 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(211) 0x431db0 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(211) 0x431db7 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(211) 0x431dbe VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(211) 0x431dc5 ADD $0x40,%RAX |
(211) 0x431dc9 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(211) 0x431dd0 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(211) 0x431dd7 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(211) 0x431dde VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(211) 0x431de5 ADD $0x40,%RAX |
(211) 0x431de9 CMP %RAX,0x58(%RSP) |
(211) 0x431dee JE 431f01 |
(212) 0x431df4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(212) 0x431dfb VMOVUPD %ZMM14,(%R8,%RAX,1) |
(212) 0x431e02 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(212) 0x431e09 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(212) 0x431e10 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(212) 0x431e18 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(212) 0x431e20 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(212) 0x431e28 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(212) 0x431e30 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(212) 0x431e38 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(212) 0x431e40 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(212) 0x431e48 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(212) 0x431e50 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(212) 0x431e58 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(212) 0x431e60 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(212) 0x431e68 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(212) 0x431e70 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(212) 0x431e78 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(212) 0x431e80 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(212) 0x431e88 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(212) 0x431e90 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(212) 0x431e98 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(212) 0x431ea0 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(212) 0x431ea8 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(212) 0x431eb0 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(212) 0x431eb8 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(212) 0x431ec0 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(212) 0x431ec8 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(212) 0x431ed0 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(212) 0x431ed8 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(212) 0x431ee0 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(212) 0x431ee8 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(212) 0x431ef0 ADD $0x200,%RAX |
(212) 0x431ef6 CMP %RAX,0x58(%RSP) |
(212) 0x431efb JNE 431df4 |
(211) 0x431f01 MOV 0x7c(%RSP),%R10D |
(211) 0x431f06 MOV %EDX,%R8D |
(211) 0x431f09 AND $-0x8,%R8D |
(211) 0x431f0d ADD %R8D,%R9D |
(211) 0x431f10 LEA (%R8,%R10,1),%ESI |
(211) 0x431f14 TEST $0x7,%DL |
(211) 0x431f17 JE 432028 |
(211) 0x431f1d SUB %R8D,%EDX |
(211) 0x431f20 LEA -0x1(%RDX),%EDI |
(211) 0x431f23 CMP $0x2,%EDI |
(211) 0x431f26 JBE 431f7f |
(211) 0x431f28 MOVSXD 0x7c(%RSP),%RCX |
(211) 0x431f2d MOV 0x60(%RSP),%R10 |
(211) 0x431f32 MOV 0x68(%RSP),%RDI |
(211) 0x431f37 LEA (%R11,%RCX,1),%RAX |
(211) 0x431f3b ADD %RCX,%R10 |
(211) 0x431f3e ADD %R8,%RAX |
(211) 0x431f41 ADD %RCX,%RDI |
(211) 0x431f44 ADD %R8,%R10 |
(211) 0x431f47 VMOVUPD (%R15,%RAX,8),%YMM14 |
(211) 0x431f4d MOV 0x70(%RSP),%RAX |
(211) 0x431f52 ADD %R8,%RDI |
(211) 0x431f55 VMOVUPD %YMM14,(%R14,%R10,8) |
(211) 0x431f5b ADD %RAX,%RCX |
(211) 0x431f5e VMOVUPD (%R13,%RDI,8),%YMM15 |
(211) 0x431f65 ADD %R8,%RCX |
(211) 0x431f68 VMOVUPD %YMM15,(%R12,%RCX,8) |
(211) 0x431f6e TEST $0x3,%DL |
(211) 0x431f71 JE 432028 |
(211) 0x431f77 AND $-0x4,%EDX |
(211) 0x431f7a ADD %EDX,%R9D |
(211) 0x431f7d ADD %EDX,%ESI |
(211) 0x431f7f MOVSXD %ESI,%R10 |
(211) 0x431f82 MOV 0x60(%RSP),%RCX |
(211) 0x431f87 MOV 0x68(%RSP),%RDI |
(211) 0x431f8c LEA (%R11,%R10,1),%RDX |
(211) 0x431f90 VMOVSD (%R15,%RDX,8),%XMM3 |
(211) 0x431f96 LEA (%RCX,%R10,1),%R8 |
(211) 0x431f9a LEA (%RDI,%R10,1),%RAX |
(211) 0x431f9e LEA 0x1(%R9),%EDX |
(211) 0x431fa2 VMOVSD %XMM3,(%R14,%R8,8) |
(211) 0x431fa8 MOV 0x70(%RSP),%R8 |
(211) 0x431fad VMOVSD (%R13,%RAX,8),%XMM4 |
(211) 0x431fb4 LEA 0x1(%RSI),%EAX |
(211) 0x431fb7 ADD %R8,%R10 |
(211) 0x431fba VMOVSD %XMM4,(%R12,%R10,8) |
(211) 0x431fc0 MOV 0x78(%RSP),%R10D |
(211) 0x431fc5 CMP %R10D,%EDX |
(211) 0x431fc8 JAE 432028 |
(211) 0x431fca CLTQ |
(211) 0x431fcc ADD $0x2,%R9D |
(211) 0x431fd0 ADD $0x2,%ESI |
(211) 0x431fd3 LEA (%R11,%RAX,1),%RDX |
(211) 0x431fd7 VMOVSD (%R15,%RDX,8),%XMM1 |
(211) 0x431fdd LEA (%RCX,%RAX,1),%RDX |
(211) 0x431fe1 VMOVSD %XMM1,(%R14,%RDX,8) |
(211) 0x431fe7 LEA (%RDI,%RAX,1),%RDX |
(211) 0x431feb ADD %R8,%RAX |
(211) 0x431fee VMOVSD (%R13,%RDX,8),%XMM2 |
(211) 0x431ff5 VMOVSD %XMM2,(%R12,%RAX,8) |
(211) 0x431ffb CMP %R10D,%R9D |
(211) 0x431ffe JAE 432028 |
(211) 0x432000 MOVSXD %ESI,%R9 |
(211) 0x432003 ADD %R9,%R11 |
(211) 0x432006 ADD %R9,%RCX |
(211) 0x432009 ADD %R9,%RDI |
(211) 0x43200c ADD %R9,%R8 |
(211) 0x43200f VMOVSD (%R15,%R11,8),%XMM0 |
(211) 0x432015 VMOVSD %XMM0,(%R14,%RCX,8) |
(211) 0x43201b VMOVSD (%R13,%RDI,8),%XMM5 |
(211) 0x432022 VMOVSD %XMM5,(%R12,%R8,8) |
(211) 0x432028 MOV 0x78(%RSP),%R9D |
(211) 0x43202d INC %RBX |
(211) 0x432030 LEA (%RBX),%R15D |
(211) 0x432033 CMP %R15D,0x50(%RSP) |
(211) 0x432038 JLE 432058 |
(211) 0x43203a MOV 0x48(%RSP),%R12D |
(211) 0x43203f MOV 0x4c(%RSP),%R11D |
(211) 0x432044 MOV 0x54(%RSP),%EDX |
(211) 0x432048 MOV %R11D,0x7c(%RSP) |
(211) 0x43204d SUB %R9D,%R12D |
(211) 0x432050 JMP 431c18 |
0x432055 NOPL (%RAX) |
0x432058 VZEROUPPER |
0x43205b LEA -0x28(%RBP),%RSP |
0x43205f POP %RBX |
0x432060 POP %R12 |
0x432062 POP %R13 |
0x432064 POP %R14 |
0x432066 POP %R15 |
0x432068 POP %RBP |
0x432069 RET |
0x43206a NOPW (%RAX,%RAX,1) |
(211) 0x432070 MOV 0x7c(%RSP),%ESI |
(211) 0x432074 XOR %R8D,%R8D |
(211) 0x432077 JMP 431f1d |
0x43207c INC %R12D |
0x43207f XOR %EDX,%EDX |
0x432081 JMP 431bb2 |
0x432086 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43205b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43205b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43207c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43205b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 431bb2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43205b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43205b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43207c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43205b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 431bb2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼reset_field_kernel(int, int, int, int, clover::Buffer2D | 1.66 | 0.53 |
▼Loop 211 - reset_field.cpp:37-38 - exec– | 0 | 0.01 |
○Loop 212 - reset_field.cpp:37-38 - exec | 1.65 | 0.53 |