Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 1.91% |
---|
Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 1.91% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
46: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
47: xvel0(i, j) = xvel1(i, j); |
48: yvel0(i, j) = yvel1(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x432090 PUSH %RBP |
0x432091 MOV %RSP,%RBP |
0x432094 PUSH %R15 |
0x432096 PUSH %R14 |
0x432098 PUSH %R13 |
0x43209a PUSH %R12 |
0x43209c PUSH %RBX |
0x43209d AND $-0x40,%RSP |
0x4320a1 ADD $-0x80,%RSP |
0x4320a5 MOV 0x28(%RDI),%EAX |
0x4320a8 MOV 0x2c(%RDI),%EDX |
0x4320ab MOV 0x20(%RDI),%EBX |
0x4320ae MOV 0x24(%RDI),%ECX |
0x4320b1 ADD $0x3,%EDX |
0x4320b4 LEA 0x1(%RAX),%R15D |
0x4320b8 LEA 0x1(%RBX),%ESI |
0x4320bb MOV %EDX,0x50(%RSP) |
0x4320bf MOV %ESI,0x4c(%RSP) |
0x4320c3 CMP %EDX,%R15D |
0x4320c6 JGE 4325bb |
0x4320cc MOV %EDX,%EBX |
0x4320ce LEA 0x3(%RCX),%R14D |
0x4320d2 SUB %R15D,%EBX |
0x4320d5 CMP %R14D,%ESI |
0x4320d8 JGE 4325bb |
0x4320de MOV %RDI,%R13 |
0x4320e1 MOV %R14D,%EDI |
0x4320e4 SUB %ESI,%EDI |
0x4320e6 MOV %EDI,0x54(%RSP) |
0x4320ea CALL 4046c0 <omp_get_num_threads@plt> |
0x4320ef MOV %EAX,%R12D |
0x4320f2 CALL 4045b0 <omp_get_thread_num@plt> |
0x4320f7 XOR %EDX,%EDX |
0x4320f9 MOV %EAX,%R8D |
0x4320fc MOV 0x54(%RSP),%EAX |
0x432100 IMUL %EBX,%EAX |
0x432103 DIV %R12D |
0x432106 MOV %EAX,%R12D |
0x432109 CMP %EDX,%R8D |
0x43210c JB 4325dc |
0x432112 IMUL %R12D,%R8D |
0x432116 LEA (%R8,%RDX,1),%R9D |
0x43211a LEA (%R12,%R9,1),%R10D |
0x43211e MOV %R10D,0x48(%RSP) |
0x432123 CMP %R10D,%R9D |
0x432126 JAE 4325bb |
0x43212c MOV %R9D,%EAX |
0x43212f XOR %EDX,%EDX |
0x432131 MOV 0x4c(%RSP),%R11D |
0x432136 MOV (%R13),%RSI |
0x43213a DIVL 0x54(%RSP) |
0x43213e MOV 0x10(%R13),%RBX |
0x432142 MOV %RSI,0x38(%RSP) |
0x432147 MOV %RBX,0x28(%RSP) |
0x43214c ADD %EDX,%R11D |
0x43214f ADD %R15D,%EAX |
0x432152 MOV %R14D,%EDX |
0x432155 MOV 0x8(%R13),%R15 |
0x432159 MOV 0x18(%R13),%R14 |
0x43215d MOV %R11D,0x7c(%RSP) |
0x432162 SUB %R11D,%EDX |
0x432165 MOVSXD %EAX,%RBX |
0x432168 MOV %R15,0x40(%RSP) |
0x43216d MOV %R14,0x30(%RSP) |
0x432172 NOPW (%RAX,%RAX,1) |
(213) 0x432178 CMP %EDX,%R12D |
(213) 0x43217b CMOVBE %R12D,%EDX |
(213) 0x43217f LEA (%R9,%RDX,1),%ECX |
(213) 0x432183 MOV %ECX,0x78(%RSP) |
(213) 0x432187 CMP %ECX,%R9D |
(213) 0x43218a JAE 43258d |
(213) 0x432190 MOV 0x30(%RSP),%R12 |
(213) 0x432195 MOV 0x38(%RSP),%RDI |
(213) 0x43219a LEA -0x1(%RDX),%EAX |
(213) 0x43219d MOV 0x28(%RSP),%RCX |
(213) 0x4321a2 MOV 0x40(%RSP),%R13 |
(213) 0x4321a7 MOV (%R12),%RSI |
(213) 0x4321ab MOV (%RDI),%R8 |
(213) 0x4321ae MOV (%RCX),%R10 |
(213) 0x4321b1 MOV (%R13),%R11 |
(213) 0x4321b5 IMUL %RBX,%R8 |
(213) 0x4321b9 MOV 0x10(%R13),%R15 |
(213) 0x4321bd MOV 0x10(%RDI),%R14 |
(213) 0x4321c1 IMUL %RBX,%RSI |
(213) 0x4321c5 MOV 0x10(%R12),%R13 |
(213) 0x4321ca MOV 0x10(%RCX),%R12 |
(213) 0x4321ce IMUL %RBX,%R10 |
(213) 0x4321d2 IMUL %RBX,%R11 |
(213) 0x4321d6 MOV %R8,0x60(%RSP) |
(213) 0x4321db MOV %RSI,0x68(%RSP) |
(213) 0x4321e0 MOV %R10,0x70(%RSP) |
(213) 0x4321e5 CMP $0x6,%EAX |
(213) 0x4321e8 JBE 4325d0 |
(213) 0x4321ee MOVSXD 0x7c(%RSP),%RAX |
(213) 0x4321f3 LEA (%R8,%RAX,1),%RCX |
(213) 0x4321f7 LEA (%R11,%RAX,1),%RDI |
(213) 0x4321fb LEA (%R14,%RCX,8),%R8 |
(213) 0x4321ff MOV 0x70(%RSP),%RCX |
(213) 0x432204 LEA (%RSI,%RAX,1),%RSI |
(213) 0x432208 LEA (%R15,%RDI,8),%R10 |
(213) 0x43220c LEA (%R13,%RSI,8),%RDI |
(213) 0x432211 ADD %RCX,%RAX |
(213) 0x432214 MOV %EDX,%ECX |
(213) 0x432216 SHR $0x3,%ECX |
(213) 0x432219 LEA (%R12,%RAX,8),%RSI |
(213) 0x43221d XOR %EAX,%EAX |
(213) 0x43221f SAL $0x6,%RCX |
(213) 0x432223 MOV %RCX,0x58(%RSP) |
(213) 0x432228 SUB $0x40,%RCX |
(213) 0x43222c SHR $0x6,%RCX |
(213) 0x432230 INC %RCX |
(213) 0x432233 AND $0x7,%ECX |
(213) 0x432236 JE 432354 |
(213) 0x43223c CMP $0x1,%RCX |
(213) 0x432240 JE 432329 |
(213) 0x432246 CMP $0x2,%RCX |
(213) 0x43224a JE 432309 |
(213) 0x432250 CMP $0x3,%RCX |
(213) 0x432254 JE 4322e9 |
(213) 0x43225a CMP $0x4,%RCX |
(213) 0x43225e JE 4322c9 |
(213) 0x432260 CMP $0x5,%RCX |
(213) 0x432264 JE 4322a9 |
(213) 0x432266 CMP $0x6,%RCX |
(213) 0x43226a JE 432289 |
(213) 0x43226c VMOVUPD (%R10),%ZMM3 |
(213) 0x432272 MOV $0x40,%EAX |
(213) 0x432277 VMOVUPD %ZMM3,(%R8) |
(213) 0x43227d VMOVUPD (%RDI),%ZMM4 |
(213) 0x432283 VMOVUPD %ZMM4,(%RSI) |
(213) 0x432289 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(213) 0x432290 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(213) 0x432297 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(213) 0x43229e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(213) 0x4322a5 ADD $0x40,%RAX |
(213) 0x4322a9 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(213) 0x4322b0 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(213) 0x4322b7 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(213) 0x4322be VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(213) 0x4322c5 ADD $0x40,%RAX |
(213) 0x4322c9 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(213) 0x4322d0 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(213) 0x4322d7 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(213) 0x4322de VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(213) 0x4322e5 ADD $0x40,%RAX |
(213) 0x4322e9 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(213) 0x4322f0 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(213) 0x4322f7 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(213) 0x4322fe VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(213) 0x432305 ADD $0x40,%RAX |
(213) 0x432309 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(213) 0x432310 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(213) 0x432317 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(213) 0x43231e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(213) 0x432325 ADD $0x40,%RAX |
(213) 0x432329 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(213) 0x432330 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(213) 0x432337 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(213) 0x43233e VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(213) 0x432345 ADD $0x40,%RAX |
(213) 0x432349 CMP %RAX,0x58(%RSP) |
(213) 0x43234e JE 432461 |
(214) 0x432354 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(214) 0x43235b VMOVUPD %ZMM14,(%R8,%RAX,1) |
(214) 0x432362 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(214) 0x432369 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(214) 0x432370 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(214) 0x432378 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(214) 0x432380 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(214) 0x432388 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(214) 0x432390 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(214) 0x432398 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(214) 0x4323a0 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(214) 0x4323a8 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(214) 0x4323b0 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(214) 0x4323b8 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(214) 0x4323c0 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(214) 0x4323c8 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(214) 0x4323d0 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(214) 0x4323d8 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(214) 0x4323e0 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(214) 0x4323e8 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(214) 0x4323f0 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(214) 0x4323f8 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(214) 0x432400 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(214) 0x432408 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(214) 0x432410 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(214) 0x432418 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(214) 0x432420 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(214) 0x432428 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(214) 0x432430 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(214) 0x432438 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(214) 0x432440 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(214) 0x432448 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(214) 0x432450 ADD $0x200,%RAX |
(214) 0x432456 CMP %RAX,0x58(%RSP) |
(214) 0x43245b JNE 432354 |
(213) 0x432461 MOV 0x7c(%RSP),%R10D |
(213) 0x432466 MOV %EDX,%R8D |
(213) 0x432469 AND $-0x8,%R8D |
(213) 0x43246d ADD %R8D,%R9D |
(213) 0x432470 LEA (%R8,%R10,1),%ESI |
(213) 0x432474 TEST $0x7,%DL |
(213) 0x432477 JE 432588 |
(213) 0x43247d SUB %R8D,%EDX |
(213) 0x432480 LEA -0x1(%RDX),%EDI |
(213) 0x432483 CMP $0x2,%EDI |
(213) 0x432486 JBE 4324df |
(213) 0x432488 MOVSXD 0x7c(%RSP),%RCX |
(213) 0x43248d MOV 0x60(%RSP),%R10 |
(213) 0x432492 MOV 0x68(%RSP),%RDI |
(213) 0x432497 LEA (%R11,%RCX,1),%RAX |
(213) 0x43249b ADD %RCX,%R10 |
(213) 0x43249e ADD %R8,%RAX |
(213) 0x4324a1 ADD %RCX,%RDI |
(213) 0x4324a4 ADD %R8,%R10 |
(213) 0x4324a7 VMOVUPD (%R15,%RAX,8),%YMM14 |
(213) 0x4324ad MOV 0x70(%RSP),%RAX |
(213) 0x4324b2 ADD %R8,%RDI |
(213) 0x4324b5 VMOVUPD %YMM14,(%R14,%R10,8) |
(213) 0x4324bb ADD %RAX,%RCX |
(213) 0x4324be VMOVUPD (%R13,%RDI,8),%YMM15 |
(213) 0x4324c5 ADD %R8,%RCX |
(213) 0x4324c8 VMOVUPD %YMM15,(%R12,%RCX,8) |
(213) 0x4324ce TEST $0x3,%DL |
(213) 0x4324d1 JE 432588 |
(213) 0x4324d7 AND $-0x4,%EDX |
(213) 0x4324da ADD %EDX,%R9D |
(213) 0x4324dd ADD %EDX,%ESI |
(213) 0x4324df MOVSXD %ESI,%R10 |
(213) 0x4324e2 MOV 0x60(%RSP),%RCX |
(213) 0x4324e7 MOV 0x68(%RSP),%RDI |
(213) 0x4324ec LEA (%R11,%R10,1),%RDX |
(213) 0x4324f0 VMOVSD (%R15,%RDX,8),%XMM3 |
(213) 0x4324f6 LEA (%RCX,%R10,1),%R8 |
(213) 0x4324fa LEA (%RDI,%R10,1),%RAX |
(213) 0x4324fe LEA 0x1(%R9),%EDX |
(213) 0x432502 VMOVSD %XMM3,(%R14,%R8,8) |
(213) 0x432508 MOV 0x70(%RSP),%R8 |
(213) 0x43250d VMOVSD (%R13,%RAX,8),%XMM4 |
(213) 0x432514 LEA 0x1(%RSI),%EAX |
(213) 0x432517 ADD %R8,%R10 |
(213) 0x43251a VMOVSD %XMM4,(%R12,%R10,8) |
(213) 0x432520 MOV 0x78(%RSP),%R10D |
(213) 0x432525 CMP %R10D,%EDX |
(213) 0x432528 JAE 432588 |
(213) 0x43252a CLTQ |
(213) 0x43252c ADD $0x2,%R9D |
(213) 0x432530 ADD $0x2,%ESI |
(213) 0x432533 LEA (%R11,%RAX,1),%RDX |
(213) 0x432537 VMOVSD (%R15,%RDX,8),%XMM1 |
(213) 0x43253d LEA (%RCX,%RAX,1),%RDX |
(213) 0x432541 VMOVSD %XMM1,(%R14,%RDX,8) |
(213) 0x432547 LEA (%RDI,%RAX,1),%RDX |
(213) 0x43254b ADD %R8,%RAX |
(213) 0x43254e VMOVSD (%R13,%RDX,8),%XMM2 |
(213) 0x432555 VMOVSD %XMM2,(%R12,%RAX,8) |
(213) 0x43255b CMP %R10D,%R9D |
(213) 0x43255e JAE 432588 |
(213) 0x432560 MOVSXD %ESI,%R9 |
(213) 0x432563 ADD %R9,%R11 |
(213) 0x432566 ADD %R9,%RCX |
(213) 0x432569 ADD %R9,%RDI |
(213) 0x43256c ADD %R9,%R8 |
(213) 0x43256f VMOVSD (%R15,%R11,8),%XMM0 |
(213) 0x432575 VMOVSD %XMM0,(%R14,%RCX,8) |
(213) 0x43257b VMOVSD (%R13,%RDI,8),%XMM5 |
(213) 0x432582 VMOVSD %XMM5,(%R12,%R8,8) |
(213) 0x432588 MOV 0x78(%RSP),%R9D |
(213) 0x43258d INC %RBX |
(213) 0x432590 LEA (%RBX),%R15D |
(213) 0x432593 CMP %R15D,0x50(%RSP) |
(213) 0x432598 JLE 4325b8 |
(213) 0x43259a MOV 0x48(%RSP),%R12D |
(213) 0x43259f MOV 0x4c(%RSP),%R11D |
(213) 0x4325a4 MOV 0x54(%RSP),%EDX |
(213) 0x4325a8 MOV %R11D,0x7c(%RSP) |
(213) 0x4325ad SUB %R9D,%R12D |
(213) 0x4325b0 JMP 432178 |
0x4325b5 NOPL (%RAX) |
0x4325b8 VZEROUPPER |
0x4325bb LEA -0x28(%RBP),%RSP |
0x4325bf POP %RBX |
0x4325c0 POP %R12 |
0x4325c2 POP %R13 |
0x4325c4 POP %R14 |
0x4325c6 POP %R15 |
0x4325c8 POP %RBP |
0x4325c9 RET |
0x4325ca NOPW (%RAX,%RAX,1) |
(213) 0x4325d0 MOV 0x7c(%RSP),%ESI |
(213) 0x4325d4 XOR %R8D,%R8D |
(213) 0x4325d7 JMP 43247d |
0x4325dc INC %R12D |
0x4325df XOR %EDX,%EDX |
0x4325e1 JMP 432112 |
0x4325e6 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4325bb <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4325bb <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4325dc <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4325bb <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 432112 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4325bb <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4325bb <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4325dc <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4325bb <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 432112 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼reset_field_kernel(int, int, int, int, clover::Buffer2D | 1.91 | 0.61 |
▼Loop 213 - reset_field.cpp:47-48 - exec– | 0.01 | 0.01 |
○Loop 214 - reset_field.cpp:47-48 - exec | 1.91 | 0.61 |