Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:62-66 [...] | Coverage: 2.04% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:62-66 [...] | Coverage: 2.04% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 62 - 66 |
-------------------------------------------------------------------------------- |
62: #pragma omp parallel for simd collapse(2) |
63: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
64: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
65: post_vol(i, j) = volume(i, j); |
66: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41cd30 PUSH %RBP |
0x41cd31 MOV %RSP,%RBP |
0x41cd34 PUSH %R15 |
0x41cd36 PUSH %R14 |
0x41cd38 PUSH %R13 |
0x41cd3a MOV %RDI,%R13 |
0x41cd3d PUSH %R12 |
0x41cd3f PUSH %RBX |
0x41cd40 AND $-0x40,%RSP |
0x41cd44 ADD $-0x80,%RSP |
0x41cd48 MOV 0x28(%RDI),%EAX |
0x41cd4b MOV 0x2c(%RDI),%EDX |
0x41cd4e MOV 0x20(%RDI),%EBX |
0x41cd51 MOV 0x24(%R13),%ECX |
0x41cd55 ADD $0x4,%EDX |
0x41cd58 LEA -0x1(%RAX),%R15D |
0x41cd5c LEA -0x1(%RBX),%EDI |
0x41cd5f MOV %EDX,0x40(%RSP) |
0x41cd63 MOV %EDI,0x3c(%RSP) |
0x41cd67 CMP %EDX,%R15D |
0x41cd6a JGE 41d31b |
0x41cd70 MOV %EDX,%EBX |
0x41cd72 LEA 0x4(%RCX),%R14D |
0x41cd76 SUB %R15D,%EBX |
0x41cd79 CMP %R14D,%EDI |
0x41cd7c JGE 41d31b |
0x41cd82 MOV %R14D,%ESI |
0x41cd85 SUB %EDI,%ESI |
0x41cd87 MOV %ESI,0x44(%RSP) |
0x41cd8b CALL 4046c0 <omp_get_num_threads@plt> |
0x41cd90 MOV %EAX,%R12D |
0x41cd93 CALL 4045b0 <omp_get_thread_num@plt> |
0x41cd98 XOR %EDX,%EDX |
0x41cd9a MOV %EAX,%R8D |
0x41cd9d MOV 0x44(%RSP),%EAX |
0x41cda1 IMUL %EBX,%EAX |
0x41cda4 DIV %R12D |
0x41cda7 MOV %EAX,%R12D |
0x41cdaa CMP %EDX,%R8D |
0x41cdad JB 41d34c |
0x41cdb3 IMUL %R12D,%R8D |
0x41cdb7 LEA (%R8,%RDX,1),%EBX |
0x41cdbb LEA (%R12,%RBX,1),%R9D |
0x41cdbf MOV %R9D,0x38(%RSP) |
0x41cdc4 CMP %R9D,%EBX |
0x41cdc7 JAE 41d31b |
0x41cdcd MOV %EBX,%EAX |
0x41cdcf XOR %EDX,%EDX |
0x41cdd1 MOV 0x3c(%RSP),%R10D |
0x41cdd6 MOV 0x18(%R13),%RDI |
0x41cdda DIVL 0x44(%RSP) |
0x41cdde MOV %RDI,0x28(%RSP) |
0x41cde3 ADD %EDX,%R10D |
0x41cde6 LEA (%RAX,%R15,1),%R11D |
0x41cdea MOV %R14D,%EDX |
0x41cded MOV 0x8(%R13),%R15 |
0x41cdf1 MOV (%R13),%R14 |
0x41cdf5 MOV 0x10(%R13),%R13 |
0x41cdf9 MOV %R10D,0x7c(%RSP) |
0x41cdfe SUB %R10D,%EDX |
0x41ce01 MOV %R15,0x30(%RSP) |
0x41ce06 MOVSXD %R11D,%RSI |
0x41ce09 MOV %R14,0x20(%RSP) |
0x41ce0e MOV %R13,0x18(%RSP) |
0x41ce13 NOPL (%RAX,%RAX,1) |
(118) 0x41ce18 CMP %EDX,%R12D |
(118) 0x41ce1b CMOVBE %R12D,%EDX |
(118) 0x41ce1f LEA (%RBX,%RDX,1),%ECX |
(118) 0x41ce22 MOV %ECX,0x78(%RSP) |
(118) 0x41ce26 CMP %ECX,%EBX |
(118) 0x41ce28 JAE 41d330 |
(118) 0x41ce2e MOV 0x20(%RSP),%RAX |
(118) 0x41ce33 MOV 0x30(%RSP),%R12 |
(118) 0x41ce38 MOV 0x28(%RSP),%R8 |
(118) 0x41ce3d MOV 0x18(%RSP),%RCX |
(118) 0x41ce42 MOV (%RAX),%R11 |
(118) 0x41ce45 MOV (%R12),%R9 |
(118) 0x41ce49 MOV 0x10(%R12),%R15 |
(118) 0x41ce4e LEA 0x1(%RSI),%R12 |
(118) 0x41ce52 MOV (%R8),%R10 |
(118) 0x41ce55 IMUL %RSI,%R9 |
(118) 0x41ce59 MOV 0x10(%R8),%R14 |
(118) 0x41ce5d MOV 0x10(%RCX),%R13 |
(118) 0x41ce61 MOV %R12,0x48(%RSP) |
(118) 0x41ce66 IMUL %R11,%R12 |
(118) 0x41ce6a MOV 0x10(%RAX),%RDI |
(118) 0x41ce6e LEA -0x1(%RDX),%EAX |
(118) 0x41ce71 IMUL %RSI,%R10 |
(118) 0x41ce75 MOV %R13,0x68(%RSP) |
(118) 0x41ce7a IMUL (%RCX),%RSI |
(118) 0x41ce7e MOV %R9,0x50(%RSP) |
(118) 0x41ce83 MOV %R12,%R8 |
(118) 0x41ce86 SUB %R11,%R8 |
(118) 0x41ce89 MOV %R10,0x58(%RSP) |
(118) 0x41ce8e MOV %R8,0x60(%RSP) |
(118) 0x41ce93 MOV %RSI,0x70(%RSP) |
(118) 0x41ce98 CMP $0x6,%EAX |
(118) 0x41ce9b JBE 41d340 |
(118) 0x41cea1 MOVSXD 0x7c(%RSP),%RAX |
(118) 0x41cea6 LEA (%R9,%RAX,1),%R9 |
(118) 0x41ceaa LEA (%R10,%RAX,1),%RCX |
(118) 0x41ceae LEA (%R8,%RAX,1),%R8 |
(118) 0x41ceb2 LEA (%R15,%R9,8),%R11 |
(118) 0x41ceb6 LEA (%R12,%RAX,1),%R9 |
(118) 0x41ceba ADD %RSI,%RAX |
(118) 0x41cebd LEA (%R14,%RCX,8),%R10 |
(118) 0x41cec1 LEA (%R13,%RAX,8),%RSI |
(118) 0x41cec6 MOV %EDX,%R13D |
(118) 0x41cec9 LEA (%RDI,%R9,8),%R9 |
(118) 0x41cecd XOR %EAX,%EAX |
(118) 0x41cecf SHR $0x3,%R13D |
(118) 0x41ced3 LEA (%RDI,%R8,8),%R8 |
(118) 0x41ced7 SAL $0x6,%R13 |
(118) 0x41cedb LEA -0x40(%R13),%RCX |
(118) 0x41cedf SHR $0x6,%RCX |
(118) 0x41cee3 INC %RCX |
(118) 0x41cee6 AND $0x7,%ECX |
(118) 0x41cee9 JE 41d035 |
(118) 0x41ceef CMP $0x1,%RCX |
(118) 0x41cef3 JE 41d005 |
(118) 0x41cef9 CMP $0x2,%RCX |
(118) 0x41cefd JE 41cfde |
(118) 0x41cf03 CMP $0x3,%RCX |
(118) 0x41cf07 JE 41cfb7 |
(118) 0x41cf0d CMP $0x4,%RCX |
(118) 0x41cf11 JE 41cf90 |
(118) 0x41cf13 CMP $0x5,%RCX |
(118) 0x41cf17 JE 41cf69 |
(118) 0x41cf19 CMP $0x6,%RCX |
(118) 0x41cf1d JE 41cf42 |
(118) 0x41cf1f VMOVUPD (%R11),%ZMM0 |
(118) 0x41cf25 MOV $0x40,%EAX |
(118) 0x41cf2a VMOVUPD %ZMM0,(%R10) |
(118) 0x41cf30 VADDPD (%R9),%ZMM0,%ZMM1 |
(118) 0x41cf36 VSUBPD (%R8),%ZMM1,%ZMM2 |
(118) 0x41cf3c VMOVUPD %ZMM2,(%RSI) |
(118) 0x41cf42 VMOVUPD (%R11,%RAX,1),%ZMM3 |
(118) 0x41cf49 VMOVUPD %ZMM3,(%R10,%RAX,1) |
(118) 0x41cf50 VADDPD (%R9,%RAX,1),%ZMM3,%ZMM4 |
(118) 0x41cf57 VSUBPD (%R8,%RAX,1),%ZMM4,%ZMM5 |
(118) 0x41cf5e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(118) 0x41cf65 ADD $0x40,%RAX |
(118) 0x41cf69 VMOVUPD (%R11,%RAX,1),%ZMM6 |
(118) 0x41cf70 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(118) 0x41cf77 VADDPD (%R9,%RAX,1),%ZMM6,%ZMM7 |
(118) 0x41cf7e VSUBPD (%R8,%RAX,1),%ZMM7,%ZMM8 |
(118) 0x41cf85 VMOVUPD %ZMM8,(%RSI,%RAX,1) |
(118) 0x41cf8c ADD $0x40,%RAX |
(118) 0x41cf90 VMOVUPD (%R11,%RAX,1),%ZMM9 |
(118) 0x41cf97 VMOVUPD %ZMM9,(%R10,%RAX,1) |
(118) 0x41cf9e VADDPD (%R9,%RAX,1),%ZMM9,%ZMM10 |
(118) 0x41cfa5 VSUBPD (%R8,%RAX,1),%ZMM10,%ZMM11 |
(118) 0x41cfac VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(118) 0x41cfb3 ADD $0x40,%RAX |
(118) 0x41cfb7 VMOVUPD (%R11,%RAX,1),%ZMM12 |
(118) 0x41cfbe VMOVUPD %ZMM12,(%R10,%RAX,1) |
(118) 0x41cfc5 VADDPD (%R9,%RAX,1),%ZMM12,%ZMM13 |
(118) 0x41cfcc VSUBPD (%R8,%RAX,1),%ZMM13,%ZMM14 |
(118) 0x41cfd3 VMOVUPD %ZMM14,(%RSI,%RAX,1) |
(118) 0x41cfda ADD $0x40,%RAX |
(118) 0x41cfde VMOVUPD (%R11,%RAX,1),%ZMM15 |
(118) 0x41cfe5 VMOVUPD %ZMM15,(%R10,%RAX,1) |
(118) 0x41cfec VADDPD (%R9,%RAX,1),%ZMM15,%ZMM0 |
(118) 0x41cff3 VSUBPD (%R8,%RAX,1),%ZMM0,%ZMM1 |
(118) 0x41cffa VMOVUPD %ZMM1,(%RSI,%RAX,1) |
(118) 0x41d001 ADD $0x40,%RAX |
(118) 0x41d005 VMOVUPD (%R11,%RAX,1),%ZMM2 |
(118) 0x41d00c VMOVUPD %ZMM2,(%R10,%RAX,1) |
(118) 0x41d013 VADDPD (%R9,%RAX,1),%ZMM2,%ZMM3 |
(118) 0x41d01a VSUBPD (%R8,%RAX,1),%ZMM3,%ZMM4 |
(118) 0x41d021 VMOVUPD %ZMM4,(%RSI,%RAX,1) |
(118) 0x41d028 ADD $0x40,%RAX |
(118) 0x41d02c CMP %R13,%RAX |
(118) 0x41d02f JE 41d17f |
(119) 0x41d035 VMOVUPD (%R11,%RAX,1),%ZMM5 |
(119) 0x41d03c VMOVUPD %ZMM5,(%R10,%RAX,1) |
(119) 0x41d043 VADDPD (%R9,%RAX,1),%ZMM5,%ZMM6 |
(119) 0x41d04a VSUBPD (%R8,%RAX,1),%ZMM6,%ZMM7 |
(119) 0x41d051 VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(119) 0x41d058 VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(119) 0x41d060 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) |
(119) 0x41d068 VADDPD 0x40(%R9,%RAX,1),%ZMM8,%ZMM9 |
(119) 0x41d070 VSUBPD 0x40(%R8,%RAX,1),%ZMM9,%ZMM10 |
(119) 0x41d078 VMOVUPD %ZMM10,0x40(%RSI,%RAX,1) |
(119) 0x41d080 VMOVUPD 0x80(%R11,%RAX,1),%ZMM11 |
(119) 0x41d088 VMOVUPD %ZMM11,0x80(%R10,%RAX,1) |
(119) 0x41d090 VADDPD 0x80(%R9,%RAX,1),%ZMM11,%ZMM12 |
(119) 0x41d098 VSUBPD 0x80(%R8,%RAX,1),%ZMM12,%ZMM13 |
(119) 0x41d0a0 VMOVUPD %ZMM13,0x80(%RSI,%RAX,1) |
(119) 0x41d0a8 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM14 |
(119) 0x41d0b0 VMOVUPD %ZMM14,0xc0(%R10,%RAX,1) |
(119) 0x41d0b8 VADDPD 0xc0(%R9,%RAX,1),%ZMM14,%ZMM15 |
(119) 0x41d0c0 VSUBPD 0xc0(%R8,%RAX,1),%ZMM15,%ZMM0 |
(119) 0x41d0c8 VMOVUPD %ZMM0,0xc0(%RSI,%RAX,1) |
(119) 0x41d0d0 VMOVUPD 0x100(%R11,%RAX,1),%ZMM1 |
(119) 0x41d0d8 VMOVUPD %ZMM1,0x100(%R10,%RAX,1) |
(119) 0x41d0e0 VADDPD 0x100(%R9,%RAX,1),%ZMM1,%ZMM2 |
(119) 0x41d0e8 VSUBPD 0x100(%R8,%RAX,1),%ZMM2,%ZMM3 |
(119) 0x41d0f0 VMOVUPD %ZMM3,0x100(%RSI,%RAX,1) |
(119) 0x41d0f8 VMOVUPD 0x140(%R11,%RAX,1),%ZMM4 |
(119) 0x41d100 VMOVUPD %ZMM4,0x140(%R10,%RAX,1) |
(119) 0x41d108 VADDPD 0x140(%R9,%RAX,1),%ZMM4,%ZMM5 |
(119) 0x41d110 VSUBPD 0x140(%R8,%RAX,1),%ZMM5,%ZMM6 |
(119) 0x41d118 VMOVUPD %ZMM6,0x140(%RSI,%RAX,1) |
(119) 0x41d120 VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 |
(119) 0x41d128 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) |
(119) 0x41d130 VADDPD 0x180(%R9,%RAX,1),%ZMM7,%ZMM8 |
(119) 0x41d138 VSUBPD 0x180(%R8,%RAX,1),%ZMM8,%ZMM9 |
(119) 0x41d140 VMOVUPD %ZMM9,0x180(%RSI,%RAX,1) |
(119) 0x41d148 VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM10 |
(119) 0x41d150 VMOVUPD %ZMM10,0x1c0(%R10,%RAX,1) |
(119) 0x41d158 VADDPD 0x1c0(%R9,%RAX,1),%ZMM10,%ZMM11 |
(119) 0x41d160 VSUBPD 0x1c0(%R8,%RAX,1),%ZMM11,%ZMM12 |
(119) 0x41d168 VMOVUPD %ZMM12,0x1c0(%RSI,%RAX,1) |
(119) 0x41d170 ADD $0x200,%RAX |
(119) 0x41d176 CMP %R13,%RAX |
(119) 0x41d179 JNE 41d035 |
(118) 0x41d17f MOV 0x7c(%RSP),%R11D |
(118) 0x41d184 MOV %EDX,%R10D |
(118) 0x41d187 AND $-0x8,%R10D |
(118) 0x41d18b ADD %R10D,%EBX |
(118) 0x41d18e LEA (%R10,%R11,1),%ESI |
(118) 0x41d192 TEST $0x7,%DL |
(118) 0x41d195 JE 41d2e6 |
(118) 0x41d19b SUB %R10D,%EDX |
(118) 0x41d19e LEA -0x1(%RDX),%R9D |
(118) 0x41d1a2 CMP $0x2,%R9D |
(118) 0x41d1a6 JBE 41d215 |
(118) 0x41d1a8 MOVSXD 0x7c(%RSP),%R13 |
(118) 0x41d1ad MOV 0x50(%RSP),%R8 |
(118) 0x41d1b2 MOV 0x58(%RSP),%RAX |
(118) 0x41d1b7 LEA (%R8,%R13,1),%RCX |
(118) 0x41d1bb LEA (%R12,%R13,1),%R9 |
(118) 0x41d1bf MOV 0x60(%RSP),%R8 |
(118) 0x41d1c4 ADD %R10,%RCX |
(118) 0x41d1c7 LEA (%RAX,%R13,1),%R11 |
(118) 0x41d1cb ADD %R10,%R9 |
(118) 0x41d1ce MOV 0x70(%RSP),%RAX |
(118) 0x41d1d3 VMOVUPD (%R15,%RCX,8),%YMM13 |
(118) 0x41d1d9 ADD %R10,%R11 |
(118) 0x41d1dc LEA (%R8,%R13,1),%RCX |
(118) 0x41d1e0 ADD %R10,%RCX |
(118) 0x41d1e3 ADD %RAX,%R13 |
(118) 0x41d1e6 VMOVUPD %YMM13,(%R14,%R11,8) |
(118) 0x41d1ec ADD %R10,%R13 |
(118) 0x41d1ef MOV 0x68(%RSP),%R10 |
(118) 0x41d1f4 VADDPD (%RDI,%R9,8),%YMM13,%YMM14 |
(118) 0x41d1fa VSUBPD (%RDI,%RCX,8),%YMM14,%YMM15 |
(118) 0x41d1ff VMOVUPD %YMM15,(%R10,%R13,8) |
(118) 0x41d205 TEST $0x3,%DL |
(118) 0x41d208 JE 41d2e6 |
(118) 0x41d20e AND $-0x4,%EDX |
(118) 0x41d211 ADD %EDX,%EBX |
(118) 0x41d213 ADD %EDX,%ESI |
(118) 0x41d215 MOV 0x50(%RSP),%R10 |
(118) 0x41d21a MOVSXD %ESI,%R13 |
(118) 0x41d21d MOV 0x58(%RSP),%R11 |
(118) 0x41d222 LEA (%R12,%R13,1),%R8 |
(118) 0x41d226 MOV 0x78(%RSP),%ECX |
(118) 0x41d22a LEA (%R10,%R13,1),%RDX |
(118) 0x41d22e LEA (%R11,%R13,1),%R9 |
(118) 0x41d232 VMOVSD (%R15,%RDX,8),%XMM0 |
(118) 0x41d238 LEA 0x1(%RBX),%EDX |
(118) 0x41d23b VMOVSD %XMM0,(%R14,%R9,8) |
(118) 0x41d241 MOV 0x70(%RSP),%R9 |
(118) 0x41d246 VADDSD (%RDI,%R8,8),%XMM0,%XMM1 |
(118) 0x41d24c MOV 0x60(%RSP),%R8 |
(118) 0x41d251 LEA (%R9,%R13,1),%RAX |
(118) 0x41d255 ADD %R8,%R13 |
(118) 0x41d258 VSUBSD (%RDI,%R13,8),%XMM1,%XMM2 |
(118) 0x41d25e MOV 0x68(%RSP),%R13 |
(118) 0x41d263 VMOVSD %XMM2,(%R13,%RAX,8) |
(118) 0x41d26a LEA 0x1(%RSI),%EAX |
(118) 0x41d26d CMP %ECX,%EDX |
(118) 0x41d26f JAE 41d2e6 |
(118) 0x41d271 CLTQ |
(118) 0x41d273 ADD $0x2,%EBX |
(118) 0x41d276 ADD $0x2,%ESI |
(118) 0x41d279 LEA (%R10,%RAX,1),%RDX |
(118) 0x41d27d LEA (%R11,%RAX,1),%RCX |
(118) 0x41d281 VMOVSD (%R15,%RDX,8),%XMM3 |
(118) 0x41d287 LEA (%R9,%RAX,1),%RDX |
(118) 0x41d28b VMOVSD %XMM3,(%R14,%RCX,8) |
(118) 0x41d291 LEA (%R12,%RAX,1),%RCX |
(118) 0x41d295 ADD %R8,%RAX |
(118) 0x41d298 VADDSD (%RDI,%RCX,8),%XMM3,%XMM4 |
(118) 0x41d29d MOV %R8,%RCX |
(118) 0x41d2a0 MOV 0x78(%RSP),%R8D |
(118) 0x41d2a5 VSUBSD (%RDI,%RAX,8),%XMM4,%XMM5 |
(118) 0x41d2aa VMOVSD %XMM5,(%R13,%RDX,8) |
(118) 0x41d2b1 CMP %R8D,%EBX |
(118) 0x41d2b4 JAE 41d2e6 |
(118) 0x41d2b6 MOVSXD %ESI,%RBX |
(118) 0x41d2b9 ADD %RBX,%R10 |
(118) 0x41d2bc ADD %RBX,%R11 |
(118) 0x41d2bf ADD %RBX,%R12 |
(118) 0x41d2c2 ADD %RBX,%RCX |
(118) 0x41d2c5 VMOVSD (%R15,%R10,8),%XMM6 |
(118) 0x41d2cb ADD %RBX,%R9 |
(118) 0x41d2ce VMOVSD %XMM6,(%R14,%R11,8) |
(118) 0x41d2d4 VADDSD (%RDI,%R12,8),%XMM6,%XMM7 |
(118) 0x41d2da VSUBSD (%RDI,%RCX,8),%XMM7,%XMM8 |
(118) 0x41d2df VMOVSD %XMM8,(%R13,%R9,8) |
(118) 0x41d2e6 MOV 0x78(%RSP),%EBX |
(118) 0x41d2ea MOV 0x48(%RSP),%RSI |
(118) 0x41d2ef LEA (%RSI),%R15D |
(118) 0x41d2f2 CMP %R15D,0x40(%RSP) |
(118) 0x41d2f7 JLE 41d318 |
(118) 0x41d2f9 MOV 0x38(%RSP),%R12D |
(118) 0x41d2fe MOV 0x3c(%RSP),%R14D |
(118) 0x41d303 MOV 0x44(%RSP),%EDX |
(118) 0x41d307 MOV %R14D,0x7c(%RSP) |
(118) 0x41d30c SUB %EBX,%R12D |
(118) 0x41d30f JMP 41ce18 |
0x41d314 NOPL (%RAX) |
0x41d318 VZEROUPPER |
0x41d31b LEA -0x28(%RBP),%RSP |
0x41d31f POP %RBX |
0x41d320 POP %R12 |
0x41d322 POP %R13 |
0x41d324 POP %R14 |
0x41d326 POP %R15 |
0x41d328 POP %RBP |
0x41d329 RET |
0x41d32a NOPW (%RAX,%RAX,1) |
(118) 0x41d330 LEA 0x1(%RSI),%RSI |
(118) 0x41d334 MOV %RSI,0x48(%RSP) |
(118) 0x41d339 JMP 41d2ea |
0x41d33b NOPL (%RAX,%RAX,1) |
(118) 0x41d340 MOV 0x7c(%RSP),%ESI |
(118) 0x41d344 XOR %R10D,%R10D |
(118) 0x41d347 JMP 41d19b |
0x41d34c INC %R12D |
0x41d34f XOR %EDX,%EDX |
0x41d351 JMP 41cdb3 |
0x41d356 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:62-66 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 285 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.41-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 8% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41d31b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41d31b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41d34c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x61c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41d31b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41cdb3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:62-66 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 285 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.41-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 8% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41d31b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41d31b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41d34c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x61c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41d31b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41cdb3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 2.04 | 0.65 |
▼Loop 118 - advec_mom.cpp:62-66 - exec– | 0.01 | 0 |
○Loop 119 - advec_mom.cpp:65-66 - exec | 2.04 | 0.65 |