Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0] [clone .lto_priv.0] | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.04% |
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Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0] [clone .lto_priv.0] | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.04% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 74 - 80 |
-------------------------------------------------------------------------------- |
74: #pragma omp parallel for simd collapse(2) |
75: for (int j = (0); j < (yrange); j++) { |
76: for (int i = (0); i < (xrange); i++) { |
77: field.energy0(i, j) = state_energy[0]; |
78: field.density0(i, j) = state_density[0]; |
79: field.xvel0(i, j) = state_xvel[0]; |
80: field.yvel0(i, j) = state_yvel[0]; |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42d8e0 PUSH %RBP |
0x42d8e1 MOV %RSP,%RBP |
0x42d8e4 PUSH %R15 |
0x42d8e6 PUSH %R14 |
0x42d8e8 PUSH %R13 |
0x42d8ea PUSH %R12 |
0x42d8ec PUSH %RBX |
0x42d8ed AND $-0x40,%RSP |
0x42d8f1 ADD $-0x80,%RSP |
0x42d8f5 MOV 0x2c(%RDI),%R14D |
0x42d8f9 MOV 0x28(%RDI),%R15D |
0x42d8fd MOV %R14D,0x48(%RSP) |
0x42d902 MOV %R15D,0x2c(%RSP) |
0x42d907 TEST %R14D,%R14D |
0x42d90a JLE 42de7b |
0x42d910 TEST %R15D,%R15D |
0x42d913 JLE 42de7b |
0x42d919 MOV %RDI,%RBX |
0x42d91c CALL 4046c0 <omp_get_num_threads@plt> |
0x42d921 MOV %EAX,%R12D |
0x42d924 CALL 4045b0 <omp_get_thread_num@plt> |
0x42d929 XOR %EDX,%EDX |
0x42d92b MOV %EAX,%ESI |
0x42d92d MOV %R14D,%EAX |
0x42d930 IMUL %R15D,%EAX |
0x42d934 DIV %R12D |
0x42d937 MOV %EAX,%R12D |
0x42d93a CMP %EDX,%ESI |
0x42d93c JB 42de9d |
0x42d942 IMUL %R12D,%ESI |
0x42d946 LEA (%RSI,%RDX,1),%R14D |
0x42d94a LEA (%R12,%R14,1),%EDI |
0x42d94e MOV %EDI,0x28(%RSP) |
0x42d952 CMP %EDI,%R14D |
0x42d955 JAE 42de7b |
0x42d95b MOV 0x2c(%RSP),%R8D |
0x42d960 MOV %R14D,%EAX |
0x42d963 XOR %EDX,%EDX |
0x42d965 MOV 0x8(%RBX),%R9 |
0x42d969 MOV (%RBX),%R10 |
0x42d96c MOV 0x10(%RBX),%R11 |
0x42d970 DIV %R8D |
0x42d973 MOV 0x18(%RBX),%R15 |
0x42d977 MOV 0x20(%RBX),%R13 |
0x42d97b MOV %R9,0x20(%RSP) |
0x42d980 MOV %R10,0x18(%RSP) |
0x42d985 MOV %R11,0x10(%RSP) |
0x42d98a MOV %R15,0x8(%RSP) |
0x42d98f MOV %EDX,0x60(%RSP) |
0x42d993 SUB %EDX,%R8D |
0x42d996 MOVSXD %EAX,%RBX |
0x42d999 NOPL (%RAX) |
(191) 0x42d9a0 CMP %R8D,%R12D |
(191) 0x42d9a3 CMOVBE %R12D,%R8D |
(191) 0x42d9a7 LEA (%R14,%R8,1),%ECX |
(191) 0x42d9ab MOV %R8D,0x64(%RSP) |
(191) 0x42d9b0 MOV %ECX,0x4c(%RSP) |
(191) 0x42d9b4 CMP %ECX,%R14D |
(191) 0x42d9b7 JAE 42de4f |
(191) 0x42d9bd MOV 0x18(%RSP),%RSI |
(191) 0x42d9c2 MOV 0x10(%RSP),%R9 |
(191) 0x42d9c7 MOV 0xb8(%R13),%R11 |
(191) 0x42d9ce MOV 0x10(%R13),%RAX |
(191) 0x42d9d2 MOV 0x8(%RSP),%R15 |
(191) 0x42d9d7 MOV 0x30(%R13),%RDX |
(191) 0x42d9db MOV 0x8(%RSI),%RDI |
(191) 0x42d9df MOV (%R13),%R10 |
(191) 0x42d9e3 MOV %R11,0x70(%RSP) |
(191) 0x42d9e8 MOV 0x8(%R9),%RSI |
(191) 0x42d9ec MOV 0xa8(%R13),%R11 |
(191) 0x42d9f3 IMUL %RBX,%RDX |
(191) 0x42d9f7 MOV %RAX,0x68(%RSP) |
(191) 0x42d9fc MOV 0xd8(%R13),%R9 |
(191) 0x42da03 MOV 0x20(%RSP),%R12 |
(191) 0x42da08 IMUL %RBX,%R10 |
(191) 0x42da0c MOV 0xe8(%R13),%RAX |
(191) 0x42da13 IMUL %RBX,%R11 |
(191) 0x42da17 MOV 0x8(%R15),%RCX |
(191) 0x42da1b IMUL %RBX,%R9 |
(191) 0x42da1f MOV 0x64(%RSP),%R15D |
(191) 0x42da24 MOV 0x8(%R12),%R8 |
(191) 0x42da29 MOV %RDX,0x30(%RSP) |
(191) 0x42da2e MOV 0x40(%R13),%R12 |
(191) 0x42da32 MOV %RAX,0x78(%RSP) |
(191) 0x42da37 LEA -0x1(%R15),%EAX |
(191) 0x42da3b MOV %R10,0x38(%RSP) |
(191) 0x42da40 MOV %R12,0x50(%RSP) |
(191) 0x42da45 MOV %R11,0x40(%RSP) |
(191) 0x42da4a MOV %R9,0x58(%RSP) |
(191) 0x42da4f CMP $0x6,%EAX |
(191) 0x42da52 JBE 42de90 |
(191) 0x42da58 MOVSXD 0x60(%RSP),%RAX |
(191) 0x42da5d LEA (%R10,%RAX,1),%R9 |
(191) 0x42da61 MOV 0x68(%RSP),%R10 |
(191) 0x42da66 LEA (%RDX,%RAX,1),%RDX |
(191) 0x42da6a LEA (%R12,%RDX,8),%R15 |
(191) 0x42da6e MOV 0x70(%RSP),%RDX |
(191) 0x42da73 LEA (%R11,%RAX,1),%R11 |
(191) 0x42da77 LEA (%R10,%R9,8),%R12 |
(191) 0x42da7b MOV 0x58(%RSP),%R9 |
(191) 0x42da80 MOV 0x78(%RSP),%R10 |
(191) 0x42da85 LEA (%RDX,%R11,8),%RDX |
(191) 0x42da89 ADD %R9,%RAX |
(191) 0x42da8c LEA (%R10,%RAX,8),%R11 |
(191) 0x42da90 MOV 0x64(%RSP),%R10D |
(191) 0x42da95 XOR %EAX,%EAX |
(191) 0x42da97 SHR $0x3,%R10D |
(191) 0x42da9b SAL $0x6,%R10 |
(191) 0x42da9f LEA -0x40(%R10),%R9 |
(191) 0x42daa3 SHR $0x6,%R9 |
(191) 0x42daa7 INC %R9 |
(191) 0x42daaa AND $0x3,%R9D |
(191) 0x42daae JE 42db6f |
(191) 0x42dab4 CMP $0x1,%R9 |
(191) 0x42dab8 JE 42db2e |
(191) 0x42daba CMP $0x2,%R9 |
(191) 0x42dabe JE 42daf6 |
(191) 0x42dac0 VBROADCASTSD (%R8),%ZMM0 |
(191) 0x42dac6 MOV $0x40,%EAX |
(191) 0x42dacb VMOVUPD %ZMM0,(%R15) |
(191) 0x42dad1 VBROADCASTSD (%RDI),%ZMM1 |
(191) 0x42dad7 VMOVUPD %ZMM1,(%R12) |
(191) 0x42dade VBROADCASTSD (%RSI),%ZMM2 |
(191) 0x42dae4 VMOVUPD %ZMM2,(%RDX) |
(191) 0x42daea VBROADCASTSD (%RCX),%ZMM3 |
(191) 0x42daf0 VMOVUPD %ZMM3,(%R11) |
(191) 0x42daf6 VBROADCASTSD (%R8),%ZMM4 |
(191) 0x42dafc VMOVUPD %ZMM4,(%R15,%RAX,1) |
(191) 0x42db03 VBROADCASTSD (%RDI),%ZMM5 |
(191) 0x42db09 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(191) 0x42db10 VBROADCASTSD (%RSI),%ZMM6 |
(191) 0x42db16 VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(191) 0x42db1d VBROADCASTSD (%RCX),%ZMM7 |
(191) 0x42db23 VMOVUPD %ZMM7,(%R11,%RAX,1) |
(191) 0x42db2a ADD $0x40,%RAX |
(191) 0x42db2e VBROADCASTSD (%R8),%ZMM8 |
(191) 0x42db34 VMOVUPD %ZMM8,(%R15,%RAX,1) |
(191) 0x42db3b VBROADCASTSD (%RDI),%ZMM9 |
(191) 0x42db41 VMOVUPD %ZMM9,(%R12,%RAX,1) |
(191) 0x42db48 VBROADCASTSD (%RSI),%ZMM10 |
(191) 0x42db4e VMOVUPD %ZMM10,(%RDX,%RAX,1) |
(191) 0x42db55 VBROADCASTSD (%RCX),%ZMM11 |
(191) 0x42db5b VMOVUPD %ZMM11,(%R11,%RAX,1) |
(191) 0x42db62 ADD $0x40,%RAX |
(191) 0x42db66 CMP %RAX,%R10 |
(191) 0x42db69 JE 42dc5a |
(192) 0x42db6f VBROADCASTSD (%R8),%ZMM12 |
(192) 0x42db75 VMOVUPD %ZMM12,(%R15,%RAX,1) |
(192) 0x42db7c VBROADCASTSD (%RDI),%ZMM13 |
(192) 0x42db82 VMOVUPD %ZMM13,(%R12,%RAX,1) |
(192) 0x42db89 VBROADCASTSD (%RSI),%ZMM14 |
(192) 0x42db8f VMOVUPD %ZMM14,(%RDX,%RAX,1) |
(192) 0x42db96 VBROADCASTSD (%RCX),%ZMM15 |
(192) 0x42db9c VMOVUPD %ZMM15,(%R11,%RAX,1) |
(192) 0x42dba3 VBROADCASTSD (%R8),%ZMM0 |
(192) 0x42dba9 VMOVUPD %ZMM0,0x40(%R15,%RAX,1) |
(192) 0x42dbb1 VBROADCASTSD (%RDI),%ZMM1 |
(192) 0x42dbb7 VMOVUPD %ZMM1,0x40(%R12,%RAX,1) |
(192) 0x42dbbf VBROADCASTSD (%RSI),%ZMM2 |
(192) 0x42dbc5 VMOVUPD %ZMM2,0x40(%RDX,%RAX,1) |
(192) 0x42dbcd VBROADCASTSD (%RCX),%ZMM3 |
(192) 0x42dbd3 VMOVUPD %ZMM3,0x40(%R11,%RAX,1) |
(192) 0x42dbdb VBROADCASTSD (%R8),%ZMM4 |
(192) 0x42dbe1 VMOVUPD %ZMM4,0x80(%R15,%RAX,1) |
(192) 0x42dbe9 VBROADCASTSD (%RDI),%ZMM5 |
(192) 0x42dbef VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(192) 0x42dbf7 VBROADCASTSD (%RSI),%ZMM6 |
(192) 0x42dbfd VMOVUPD %ZMM6,0x80(%RDX,%RAX,1) |
(192) 0x42dc05 VBROADCASTSD (%RCX),%ZMM7 |
(192) 0x42dc0b VMOVUPD %ZMM7,0x80(%R11,%RAX,1) |
(192) 0x42dc13 VBROADCASTSD (%R8),%ZMM8 |
(192) 0x42dc19 VMOVUPD %ZMM8,0xc0(%R15,%RAX,1) |
(192) 0x42dc21 VBROADCASTSD (%RDI),%ZMM9 |
(192) 0x42dc27 VMOVUPD %ZMM9,0xc0(%R12,%RAX,1) |
(192) 0x42dc2f VBROADCASTSD (%RSI),%ZMM10 |
(192) 0x42dc35 VMOVUPD %ZMM10,0xc0(%RDX,%RAX,1) |
(192) 0x42dc3d VBROADCASTSD (%RCX),%ZMM11 |
(192) 0x42dc43 VMOVUPD %ZMM11,0xc0(%R11,%RAX,1) |
(192) 0x42dc4b ADD $0x100,%RAX |
(192) 0x42dc51 CMP %RAX,%R10 |
(192) 0x42dc54 JNE 42db6f |
(191) 0x42dc5a MOV 0x64(%RSP),%R15D |
(191) 0x42dc5f MOV 0x60(%RSP),%EDX |
(191) 0x42dc63 MOV %R15D,%R12D |
(191) 0x42dc66 AND $-0x8,%R12D |
(191) 0x42dc6a ADD %R12D,%R14D |
(191) 0x42dc6d LEA (%R12,%RDX,1),%R10D |
(191) 0x42dc71 TEST $0x7,%R15B |
(191) 0x42dc75 JE 42de4a |
(191) 0x42dc7b MOV 0x64(%RSP),%EDX |
(191) 0x42dc7f SUB %R12D,%EDX |
(191) 0x42dc82 LEA -0x1(%RDX),%R11D |
(191) 0x42dc86 CMP $0x2,%R11D |
(191) 0x42dc8a JBE 42dd22 |
(191) 0x42dc90 MOVSXD 0x60(%RSP),%RAX |
(191) 0x42dc95 MOV 0x30(%RSP),%R9 |
(191) 0x42dc9a VBROADCASTSD (%R8),%YMM15 |
(191) 0x42dc9f MOV 0x50(%RSP),%R15 |
(191) 0x42dca4 LEA (%R9,%RAX,1),%R11 |
(191) 0x42dca8 MOV 0x38(%RSP),%R9 |
(191) 0x42dcad VMOVSD (%RDI),%XMM12 |
(191) 0x42dcb1 ADD %R12,%R11 |
(191) 0x42dcb4 VMOVSD (%RSI),%XMM13 |
(191) 0x42dcb8 VMOVSD (%RCX),%XMM14 |
(191) 0x42dcbc VMOVUPD %YMM15,(%R15,%R11,8) |
(191) 0x42dcc2 LEA (%R9,%RAX,1),%R11 |
(191) 0x42dcc6 MOV 0x68(%RSP),%R15 |
(191) 0x42dccb MOV 0x40(%RSP),%R9 |
(191) 0x42dcd0 VBROADCASTSD %XMM12,%YMM0 |
(191) 0x42dcd5 VBROADCASTSD %XMM13,%YMM1 |
(191) 0x42dcda VBROADCASTSD %XMM14,%YMM2 |
(191) 0x42dcdf ADD %R12,%R11 |
(191) 0x42dce2 VMOVUPD %YMM0,(%R15,%R11,8) |
(191) 0x42dce8 LEA (%R9,%RAX,1),%R11 |
(191) 0x42dcec MOV 0x58(%RSP),%R9 |
(191) 0x42dcf1 MOV 0x70(%RSP),%R15 |
(191) 0x42dcf6 ADD %R12,%R11 |
(191) 0x42dcf9 ADD %R9,%RAX |
(191) 0x42dcfc VMOVUPD %YMM1,(%R15,%R11,8) |
(191) 0x42dd02 ADD %R12,%RAX |
(191) 0x42dd05 MOV 0x78(%RSP),%R12 |
(191) 0x42dd0a VMOVUPD %YMM2,(%R12,%RAX,8) |
(191) 0x42dd10 TEST $0x3,%DL |
(191) 0x42dd13 JE 42de4a |
(191) 0x42dd19 AND $-0x4,%EDX |
(191) 0x42dd1c ADD %EDX,%R14D |
(191) 0x42dd1f ADD %EDX,%R10D |
(191) 0x42dd22 MOV 0x30(%RSP),%R9 |
(191) 0x42dd27 VMOVSD (%R8),%XMM3 |
(191) 0x42dd2c MOVSXD %R10D,%RAX |
(191) 0x42dd2f MOV 0x50(%RSP),%R11 |
(191) 0x42dd34 MOV 0x38(%RSP),%R15 |
(191) 0x42dd39 LEA (%R9,%RAX,1),%RDX |
(191) 0x42dd3d VMOVSD %XMM3,(%R11,%RDX,8) |
(191) 0x42dd43 MOV 0x68(%RSP),%RDX |
(191) 0x42dd48 LEA (%R15,%RAX,1),%R12 |
(191) 0x42dd4c MOV 0x40(%RSP),%R11 |
(191) 0x42dd51 VMOVSD (%RDI),%XMM4 |
(191) 0x42dd55 VMOVSD %XMM4,(%RDX,%R12,8) |
(191) 0x42dd5b MOV 0x70(%RSP),%R12 |
(191) 0x42dd60 LEA (%R11,%RAX,1),%RDX |
(191) 0x42dd64 VMOVSD (%RSI),%XMM5 |
(191) 0x42dd68 VMOVSD %XMM5,(%R12,%RDX,8) |
(191) 0x42dd6e MOV 0x58(%RSP),%RDX |
(191) 0x42dd73 MOV 0x78(%RSP),%R12 |
(191) 0x42dd78 VMOVSD (%RCX),%XMM6 |
(191) 0x42dd7c ADD %RDX,%RAX |
(191) 0x42dd7f LEA 0x1(%R14),%EDX |
(191) 0x42dd83 VMOVSD %XMM6,(%R12,%RAX,8) |
(191) 0x42dd89 MOV 0x4c(%RSP),%R12D |
(191) 0x42dd8e LEA 0x1(%R10),%EAX |
(191) 0x42dd92 CMP %R12D,%EDX |
(191) 0x42dd95 JAE 42de4a |
(191) 0x42dd9b VMOVSD (%R8),%XMM7 |
(191) 0x42dda0 CLTQ |
(191) 0x42dda2 MOV 0x50(%RSP),%R12 |
(191) 0x42dda7 ADD $0x2,%R14D |
(191) 0x42ddab LEA (%RAX,%R9,1),%RDX |
(191) 0x42ddaf ADD $0x2,%R10D |
(191) 0x42ddb3 VMOVSD %XMM7,(%R12,%RDX,8) |
(191) 0x42ddb9 MOV 0x68(%RSP),%R12 |
(191) 0x42ddbe LEA (%RAX,%R15,1),%RDX |
(191) 0x42ddc2 VMOVSD (%RDI),%XMM8 |
(191) 0x42ddc6 VMOVSD %XMM8,(%R12,%RDX,8) |
(191) 0x42ddcc MOV 0x70(%RSP),%R12 |
(191) 0x42ddd1 LEA (%RAX,%R11,1),%RDX |
(191) 0x42ddd5 VMOVSD (%RSI),%XMM9 |
(191) 0x42ddd9 VMOVSD %XMM9,(%R12,%RDX,8) |
(191) 0x42dddf MOV 0x58(%RSP),%RDX |
(191) 0x42dde4 MOV 0x78(%RSP),%R12 |
(191) 0x42dde9 VMOVSD (%RCX),%XMM10 |
(191) 0x42dded ADD %RDX,%RAX |
(191) 0x42ddf0 VMOVSD %XMM10,(%R12,%RAX,8) |
(191) 0x42ddf6 MOV 0x4c(%RSP),%EAX |
(191) 0x42ddfa CMP %EAX,%R14D |
(191) 0x42ddfd JAE 42de4a |
(191) 0x42ddff VMOVSD (%R8),%XMM11 |
(191) 0x42de04 MOVSXD %R10D,%R14 |
(191) 0x42de07 MOV 0x50(%RSP),%R8 |
(191) 0x42de0c ADD %R14,%R9 |
(191) 0x42de0f ADD %R14,%R15 |
(191) 0x42de12 ADD %R14,%R11 |
(191) 0x42de15 ADD %R14,%RDX |
(191) 0x42de18 VMOVSD %XMM11,(%R8,%R9,8) |
(191) 0x42de1e VMOVSD (%RDI),%XMM12 |
(191) 0x42de22 MOV 0x68(%RSP),%RDI |
(191) 0x42de27 VMOVSD %XMM12,(%RDI,%R15,8) |
(191) 0x42de2d VMOVSD (%RSI),%XMM13 |
(191) 0x42de31 MOV 0x70(%RSP),%RSI |
(191) 0x42de36 VMOVSD %XMM13,(%RSI,%R11,8) |
(191) 0x42de3c VMOVSD (%RCX),%XMM14 |
(191) 0x42de40 MOV 0x78(%RSP),%RCX |
(191) 0x42de45 VMOVSD %XMM14,(%RCX,%RDX,8) |
(191) 0x42de4a MOV 0x4c(%RSP),%R14D |
(191) 0x42de4f INC %RBX |
(191) 0x42de52 CMP %EBX,0x48(%RSP) |
(191) 0x42de56 JLE 42de78 |
(191) 0x42de58 MOV 0x28(%RSP),%R12D |
(191) 0x42de5d MOV 0x2c(%RSP),%R8D |
(191) 0x42de62 MOVL $0,0x60(%RSP) |
(191) 0x42de6a SUB %R14D,%R12D |
(191) 0x42de6d JMP 42d9a0 |
0x42de72 NOPW (%RAX,%RAX,1) |
0x42de78 VZEROUPPER |
0x42de7b LEA -0x28(%RBP),%RSP |
0x42de7f POP %RBX |
0x42de80 POP %R12 |
0x42de82 POP %R13 |
0x42de84 POP %R14 |
0x42de86 POP %R15 |
0x42de88 POP %RBP |
0x42de89 RET |
0x42de8a NOPW (%RAX,%RAX,1) |
(191) 0x42de90 MOV 0x60(%RSP),%R10D |
(191) 0x42de95 XOR %R12D,%R12D |
(191) 0x42de98 JMP 42dc7b |
0x42de9d INC %R12D |
0x42dea0 XOR %EDX,%EDX |
0x42dea2 JMP 42d942 |
0x42dea7 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42de7b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42de7b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42de9d <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42de7b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42d942 <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42de7b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42de7b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42de9d <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42de7b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42d942 <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0] [clone .lto_priv.0]– | 0.04 | 0.01 |
▼Loop 191 - generate_chunk.cpp:74-80 - exec– | 0 | 0 |
○Loop 192 - generate_chunk.cpp:77-80 - exec | 0.04 | 0.01 |