Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:157-202 [...] | Coverage: 1.48% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:157-202 [...] | Coverage: 1.48% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 157 - 202 |
-------------------------------------------------------------------------------- |
157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 2); i++) |
160: ({ |
161: int upwind, donor, downwind, dif; |
162: double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind; |
163: if (vol_flux_y(i, j) > 0.0) { |
164: upwind = j - 2; |
165: donor = j - 1; |
166: downwind = j; |
167: dif = donor; |
168: } else { |
169: upwind = std::min(j + 1, y_max + 2); |
170: donor = j; |
171: downwind = j - 1; |
172: dif = upwind; |
173: } |
174: sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor); |
175: sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]); |
176: sigma4 = 2.0 - sigmat; |
177: sigmav = sigmat; |
178: diffuw = density1(i, donor) - density1(i, upwind); |
179: diffdw = density1(i, downwind) - density1(i, donor); |
180: wind = 1.0; |
181: if (diffdw <= 0.0) wind = -1.0; |
182: if (diffuw * diffdw > 0.0) { |
183: limiter = (1.0 - sigmav) * wind * |
184: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
185: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
186: } else { |
187: limiter = 0.0; |
188: } |
189: mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter); |
190: sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor)); |
191: diffuw = energy1(i, donor) - energy1(i, upwind); |
192: diffdw = energy1(i, downwind) - energy1(i, donor); |
193: wind = 1.0; |
194: if (diffdw <= 0.0) wind = -1.0; |
195: if (diffuw * diffdw > 0.0) { |
196: limiter = (1.0 - sigmam) * wind * |
197: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
198: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
199: } else { |
200: limiter = 0.0; |
201: } |
202: ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter); |
0x41e730 PUSH %RBP |
0x41e731 MOV %RSP,%RBP |
0x41e734 PUSH %R15 |
0x41e736 PUSH %R14 |
0x41e738 PUSH %R13 |
0x41e73a PUSH %R12 |
0x41e73c PUSH %RBX |
0x41e73d AND $-0x20,%RSP |
0x41e741 SUB $0x260,%RSP |
0x41e748 MOV %R8,%R12 |
0x41e74b MOV 0x50(%RBP),%RAX |
0x41e74f MOV 0x40(%RBP),%R10 |
0x41e753 MOV 0x38(%RBP),%RSI |
0x41e757 MOV 0x28(%RBP),%R15 |
0x41e75b MOV 0x20(%RBP),%R14 |
0x41e75f MOV 0x18(%RBP),%R13 |
0x41e763 MOV 0x10(%RBP),%RBX |
0x41e767 MOV 0x30(%RBP),%R8D |
0x41e76b MOV %R8D,0x1c(%RSP) |
0x41e770 MOVL $0,0x5c(%RSP) |
0x41e778 TEST %RAX,%RAX |
0x41e77b JS 41f0e3 |
0x41e781 MOV %RCX,0xc0(%RSP) |
0x41e789 MOV %R9,0x30(%RSP) |
0x41e78e MOV %RSI,0x20(%RSP) |
0x41e793 MOV %R10,0x28(%RSP) |
0x41e798 MOV %RDX,0x38(%RSP) |
0x41e79d MOV (%RDI),%ESI |
0x41e79f MOVQ $0,0x88(%RSP) |
0x41e7ab MOV %RAX,0x80(%RSP) |
0x41e7b3 MOVQ $0x1,0xb8(%RSP) |
0x41e7bf SUB $0x8,%RSP |
0x41e7c3 LEA 0xc0(%RSP),%RAX |
0x41e7cb LEA 0x64(%RSP),%RCX |
0x41e7d0 LEA 0x90(%RSP),%R8 |
0x41e7d8 LEA 0x88(%RSP),%R9 |
0x41e7e0 MOV $0x682450,%EDI |
0x41e7e5 MOV %ESI,0x60(%RSP) |
0x41e7e9 MOV $0x22,%EDX |
0x41e7ee PUSH $0x1 |
0x41e7f0 PUSH $0x1 |
0x41e7f2 PUSH %RAX |
0x41e7f3 CALL 403020 <__kmpc_for_static_init_8@plt> |
0x41e7f8 ADD $0x20,%RSP |
0x41e7fc MOV 0x88(%RSP),%RSI |
0x41e804 MOV 0x80(%RSP),%RAX |
0x41e80c MOV %RAX,0x78(%RSP) |
0x41e811 CMP %RAX,%RSI |
0x41e814 JA 41f0c4 |
0x41e81a MOV 0x28(%RSP),%RDX |
0x41e81f SUB 0x20(%RSP),%EDX |
0x41e823 MOV (%R13),%RAX |
0x41e827 MOV %RAX,0x70(%RSP) |
0x41e82c MOV 0x10(%R13),%R11 |
0x41e830 MOV (%R14),%RAX |
0x41e833 MOV %RAX,0x40(%RSP) |
0x41e838 MOV 0x10(%R14),%RAX |
0x41e83c MOV %RAX,0x50(%RSP) |
0x41e841 MOV 0xc0(%RSP),%RAX |
0x41e849 MOV 0x8(%RAX),%R13 |
0x41e84d MOV (%R12),%RAX |
0x41e851 MOV %RAX,0x48(%RSP) |
0x41e856 MOV 0x10(%R12),%R12 |
0x41e85b MOV (%RBX),%RAX |
0x41e85e MOV %RAX,0x68(%RSP) |
0x41e863 MOV 0x10(%RBX),%RBX |
0x41e867 MOV 0x38(%RSP),%RCX |
0x41e86c ADD $0x2,%ECX |
0x41e86f LEA 0x1(%RSI),%RAX |
0x41e873 MOV 0x78(%RSP),%R9 |
0x41e878 LEA 0x1(%R9),%R8 |
0x41e87c CMP %R8,%RAX |
0x41e87f CMOVG %RAX,%R8 |
0x41e883 MOV 0x30(%RSP),%RAX |
0x41e888 MOV (%RAX),%R9 |
0x41e88b MOV 0x10(%RAX),%R14 |
0x41e88f MOV (%R15),%R10 |
0x41e892 MOV 0x10(%R15),%RDI |
0x41e896 MOV 0x48(%RSP),%R15 |
0x41e89b SUB %RSI,%R8 |
0x41e89e MOV $-0x8,%EAX |
0x41e8a3 MOV %R8,0x98(%RSP) |
0x41e8ab AND %R8,%RAX |
0x41e8ae MOV %RCX,0x38(%RSP) |
0x41e8b3 MOV %RDX,0x28(%RSP) |
0x41e8b8 MOV %R11,0x30(%RSP) |
0x41e8bd MOV %R9,0xa8(%RSP) |
0x41e8c5 MOV %R10,0xa0(%RSP) |
0x41e8cd MOV %RBX,0xb0(%RSP) |
0x41e8d5 JE 41f0f2 |
0x41e8db MOV %RAX,%R8 |
0x41e8de VPBROADCASTQ %RDX,%YMM0 |
0x41e8e4 VMOVDQU %YMM0,0x200(%RSP) |
0x41e8ed MOV %RDI,0x60(%RSP) |
0x41e8f2 MOV 0x1c(%RSP),%EAX |
0x41e8f6 VPBROADCASTD %EAX,%YMM0 |
0x41e8fc VMOVDQU %YMM0,0x1e0(%RSP) |
0x41e905 MOV 0x20(%RSP),%RAX |
0x41e90a VPBROADCASTQ %RAX,%YMM0 |
0x41e910 VMOVDQU %YMM0,0x1c0(%RSP) |
0x41e919 MOV 0x70(%RSP),%RAX |
0x41e91e VPBROADCASTQ %RAX,%YMM0 |
0x41e924 VMOVDQU %YMM0,0x1a0(%RSP) |
0x41e92d VPBROADCASTD %ECX,%YMM0 |
0x41e933 VMOVDQU %YMM0,0x180(%RSP) |
0x41e93c MOV 0x40(%RSP),%RAX |
0x41e941 VPBROADCASTQ %RAX,%YMM0 |
0x41e947 VMOVDQU %YMM0,0x160(%RSP) |
0x41e950 VPBROADCASTQ %R15,%YMM0 |
0x41e956 VMOVDQU %YMM0,0x100(%RSP) |
0x41e95f MOV 0x68(%RSP),%RAX |
0x41e964 VPBROADCASTQ %RAX,%YMM0 |
0x41e96a VMOVDQU %YMM0,0x140(%RSP) |
0x41e973 VPBROADCASTQ %R9,%YMM0 |
0x41e979 VMOVDQU %YMM0,0xe0(%RSP) |
0x41e982 VPBROADCASTQ %R10,%YMM0 |
0x41e988 VMOVDQU %YMM0,0x120(%RSP) |
0x41e991 MOV %RSI,0x90(%RSP) |
0x41e999 VPBROADCASTQ %RSI,%YMM0 |
0x41e99f VPADDQ 0x478d7(%RIP),%YMM0,%YMM17 |
0x41e9a9 VPADDQ 0x4774f(%RIP),%YMM0,%YMM10 |
0x41e9b1 XOR %R15D,%R15D |
0x41e9b4 NOPW %CS:(%RAX,%RAX,1) |
(105) 0x41e9c0 VMOVDQA %YMM10,%YMM0 |
(105) 0x41e9c4 VMOVDQU 0x200(%RSP),%YMM8 |
(105) 0x41e9cd VMOVDQA %YMM8,%YMM1 |
(105) 0x41e9d1 MOV %R13,%RDI |
(105) 0x41e9d4 MOV %RBX,%R13 |
(105) 0x41e9d7 MOV %R8,%RBX |
(105) 0x41e9da MOV $0x454690,%RSI |
(105) 0x41e9e1 CALL %RSI |
(105) 0x41e9e3 VMOVDQA %YMM0,%YMM11 |
(105) 0x41e9e7 VMOVDQA64 %YMM17,%YMM0 |
(105) 0x41e9ed VMOVDQA %YMM8,%YMM1 |
(105) 0x41e9f1 CALL %RSI |
(105) 0x41e9f3 VPMOVQD %YMM11,%XMM1 |
(105) 0x41e9f9 VPMOVQD %YMM0,%XMM0 |
(105) 0x41e9ff VINSERTI128 $0x1,%XMM0,%YMM1,%YMM0 |
(105) 0x41ea05 VPADDD 0x1e0(%RSP),%YMM0,%YMM12 |
(105) 0x41ea0e VMOVDQA %YMM10,%YMM0 |
(105) 0x41ea12 VMOVDQA %YMM8,%YMM1 |
(105) 0x41ea16 MOV $0x454460,%RSI |
(105) 0x41ea1d CALL %RSI |
(105) 0x41ea1f VMOVDQA %YMM0,%YMM11 |
(105) 0x41ea23 VMOVDQA64 %YMM17,%YMM0 |
(105) 0x41ea29 VMOVDQA %YMM8,%YMM1 |
(105) 0x41ea2d CALL %RSI |
(105) 0x41ea2f MOV %RBX,%R8 |
(105) 0x41ea32 MOV %R13,%RBX |
(105) 0x41ea35 MOV %RDI,%R13 |
(105) 0x41ea38 MOV 0x30(%RSP),%R11 |
(105) 0x41ea3d VEXTRACTI128 $0x1,%YMM12,%XMM14 |
(105) 0x41ea43 VPMOVSXDQ %XMM14,%YMM1 |
(105) 0x41ea48 VMOVDQU 0x1a0(%RSP),%YMM5 |
(105) 0x41ea51 VXORPS %XMM4,%XMM4,%XMM4 |
(105) 0x41ea55 VPMULLQ %YMM1,%YMM5,%YMM4 |
(105) 0x41ea5b VMOVDQA %YMM1,%YMM2 |
(105) 0x41ea5f VMOVDQU 0x1c0(%RSP),%YMM6 |
(105) 0x41ea68 VPADDQ %YMM6,%YMM11,%YMM3 |
(105) 0x41ea6c VPMOVSXDQ %XMM12,%YMM1 |
(105) 0x41ea71 VPMULLQ %YMM1,%YMM5,%YMM5 |
(105) 0x41ea77 VMOVDQA %YMM1,%YMM9 |
(105) 0x41ea7b VPADDQ %YMM6,%YMM0,%YMM0 |
(105) 0x41ea7f VPSLLQ $0x20,%YMM3,%YMM3 |
(105) 0x41ea84 VPSRAQ $0x20,%YMM3,%YMM3 |
(105) 0x41ea8b VPADDQ %YMM3,%YMM5,%YMM5 |
(105) 0x41ea8f VXORPD %XMM7,%XMM7,%XMM7 |
(105) 0x41ea93 KXNORW %K0,%K0,%K1 |
(105) 0x41ea97 VGATHERQPD (%R11,%YMM5,8),%YMM7{%K1} |
(105) 0x41ea9e VPSLLQ $0x20,%YMM0,%YMM0 |
(105) 0x41eaa3 VPSRAQ $0x20,%YMM0,%YMM0 |
(105) 0x41eaaa VPADDQ %YMM0,%YMM4,%YMM4 |
(105) 0x41eaae VPXOR %XMM6,%XMM6,%XMM6 |
(105) 0x41eab2 KXNORW %K0,%K0,%K1 |
(105) 0x41eab6 VGATHERQPD (%R11,%YMM4,8),%YMM6{%K1} |
(105) 0x41eabd VPXOR %XMM1,%XMM1,%XMM1 |
(105) 0x41eac1 VCMPPD $0x1,%YMM7,%YMM1,%K2 |
(105) 0x41eac8 VCMPPD $0x1,%YMM6,%YMM1,%K1 |
(105) 0x41eacf VXORPD %XMM24,%XMM24,%XMM24 |
(105) 0x41ead5 VPCMPEQD %YMM8,%YMM8,%YMM8 |
(105) 0x41eada VPADDD %YMM8,%YMM12,%YMM4 |
(105) 0x41eadf VPMOVSXDQ %XMM4,%YMM18 |
(105) 0x41eae5 VEXTRACTI128 $0x1,%YMM4,%XMM4 |
(105) 0x41eaeb VPMOVSXDQ %XMM4,%YMM13 |
(105) 0x41eaf0 VPBLENDMQ %YMM18,%YMM9,%YMM11{%K2} |
(105) 0x41eaf6 VPBLENDMQ %YMM13,%YMM2,%YMM30{%K1} |
(105) 0x41eafc VMOVDQU 0x160(%RSP),%YMM5 |
(105) 0x41eb05 VXORPS %XMM4,%XMM4,%XMM4 |
(105) 0x41eb09 VPMULLQ %YMM11,%YMM5,%YMM4 |
(105) 0x41eb0f VPMULLQ %YMM30,%YMM5,%YMM15 |
(105) 0x41eb15 VPADDQ %YMM3,%YMM4,%YMM1 |
(105) 0x41eb19 VMOVDQU %YMM1,0x220(%RSP) |
(105) 0x41eb22 VXORPD %XMM16,%XMM16,%XMM16 |
(105) 0x41eb28 KXNORW %K0,%K0,%K3 |
(105) 0x41eb2c MOV 0x50(%RSP),%RAX |
(105) 0x41eb31 VGATHERQPD (%RAX,%YMM1,8),%YMM16{%K3} |
(105) 0x41eb38 VPADDQ %YMM0,%YMM15,%YMM1 |
(105) 0x41eb3c VMOVDQU %YMM1,0xc0(%RSP) |
(105) 0x41eb45 VXORPD %XMM20,%XMM20,%XMM20 |
(105) 0x41eb4b KXNORW %K0,%K0,%K3 |
(105) 0x41eb4f VGATHERQPD (%RAX,%YMM1,8),%YMM20{%K3} |
(105) 0x41eb56 VXORPD %XMM26,%XMM26,%XMM26 |
(105) 0x41eb5c KXNORW %K0,%K0,%K3 |
(105) 0x41eb60 VGATHERDPD (%RDI,%XMM12,8),%YMM26{%K3} |
(105) 0x41eb67 VPSUBD %YMM8,%YMM12,%YMM15 |
(105) 0x41eb6c VXORPD %XMM23,%XMM23,%XMM23 |
(105) 0x41eb72 KXNORW %K0,%K0,%K3 |
(105) 0x41eb76 VGATHERDPD (%RDI,%XMM14,8),%YMM23{%K3} |
(105) 0x41eb7d VPMINSD 0x180(%RSP),%YMM15,%YMM14 |
(105) 0x41eb87 VPMOVSXDQ %XMM14,%YMM15 |
(105) 0x41eb8c VMOVDQA64 %YMM15,%YMM22 |
(105) 0x41eb92 VMOVDQA64 %YMM18,%YMM15{%K2} |
(105) 0x41eb98 VXORPD %XMM25,%XMM25,%XMM25 |
(105) 0x41eb9e KXNORW %K0,%K0,%K3 |
(105) 0x41eba2 VGATHERQPD (%RDI,%YMM15,8),%YMM25{%K3} |
(105) 0x41eba9 VEXTRACTI128 $0x1,%YMM14,%XMM14 |
(105) 0x41ebaf VPMOVSXDQ %XMM14,%YMM14 |
(105) 0x41ebb4 VPADDD 0x47702(%RIP){1to8},%YMM12,%YMM27 |
(105) 0x41ebbe VMOVDQA %YMM14,%YMM15 |
(105) 0x41ebc3 VMOVDQA64 %YMM13,%YMM14{%K1} |
(105) 0x41ebc9 VXORPD %XMM29,%XMM29,%XMM29 |
(105) 0x41ebcf KXNORW %K0,%K0,%K3 |
(105) 0x41ebd3 VMOVDQU64 0x100(%RSP),%YMM19 |
(105) 0x41ebdb VPMULLQ %YMM11,%YMM19,%YMM31 |
(105) 0x41ebe1 VGATHERQPD (%RDI,%YMM14,8),%YMM29{%K3} |
(105) 0x41ebe8 VPMOVSXDQ %XMM27,%YMM22{%K2} |
(105) 0x41ebee VPBLENDMQ %YMM9,%YMM18,%YMM12{%K2} |
(105) 0x41ebf4 VMOVDQA %YMM9,%YMM5 |
(105) 0x41ebf8 VPMULLQ %YMM22,%YMM19,%YMM28 |
(105) 0x41ebfe VPADDQ %YMM3,%YMM31,%YMM31 |
(105) 0x41ec04 VPXORD %XMM18,%XMM18,%XMM18 |
(105) 0x41ec0a KXNORW %K0,%K0,%K2 |
(105) 0x41ec0e VXORPS %XMM14,%XMM14,%XMM14 |
(105) 0x41ec13 VPMULLQ %YMM12,%YMM19,%YMM14 |
(105) 0x41ec19 VGATHERQPD (%R12,%YMM31,8),%YMM18{%K2} |
(105) 0x41ec20 VEXTRACTI32X4 $0x1,%YMM27,%XMM27 |
(105) 0x41ec27 VPADDQ %YMM3,%YMM14,%YMM14 |
(105) 0x41ec2b VPXOR %XMM8,%XMM8,%XMM8 |
(105) 0x41ec30 KXNORW %K0,%K0,%K2 |
(105) 0x41ec34 VGATHERQPD (%R12,%YMM14,8),%YMM8{%K2} |
(105) 0x41ec3b VPMOVSXDQ %XMM27,%YMM15{%K1} |
(105) 0x41ec41 VPBLENDMQ %YMM2,%YMM13,%YMM14{%K1} |
(105) 0x41ec47 VMOVDQA %YMM2,%YMM4 |
(105) 0x41ec4b VXORPS %XMM13,%XMM13,%XMM13 |
(105) 0x41ec50 VPMULLQ %YMM15,%YMM19,%YMM13 |
(105) 0x41ec56 VPADDQ %YMM3,%YMM28,%YMM27 |
(105) 0x41ec5c VPXORD %XMM28,%XMM28,%XMM28 |
(105) 0x41ec62 KXNORW %K0,%K0,%K1 |
(105) 0x41ec66 VPMULLQ %YMM14,%YMM19,%YMM21 |
(105) 0x41ec6c VGATHERQPD (%R12,%YMM27,8),%YMM28{%K1} |
(105) 0x41ec73 VPADDQ %YMM0,%YMM21,%YMM21 |
(105) 0x41ec79 VXORPD %XMM27,%XMM27,%XMM27 |
(105) 0x41ec7f KXNORW %K0,%K0,%K1 |
(105) 0x41ec83 VGATHERQPD (%R12,%YMM21,8),%YMM27{%K1} |
(105) 0x41ec8a VPADDQ %YMM0,%YMM13,%YMM13 |
(105) 0x41ec8e VXORPD %XMM21,%XMM21,%XMM21 |
(105) 0x41ec94 KXNORW %K0,%K0,%K1 |
(105) 0x41ec98 VGATHERQPD (%R12,%YMM13,8),%YMM21{%K1} |
(105) 0x41ec9f VBROADCASTSD 0x46a40(%RIP),%YMM1 |
(105) 0x41eca8 VANDPD %YMM1,%YMM7,%YMM13 |
(105) 0x41ecac VDIVPD %YMM16,%YMM13,%YMM13 |
(105) 0x41ecb2 VANDPD %YMM1,%YMM6,%YMM16 |
(105) 0x41ecb8 VDIVPD %YMM20,%YMM16,%YMM20 |
(105) 0x41ecbe VFMADD213PD %YMM26,%YMM13,%YMM26 |
(105) 0x41ecc4 VSUBPD %YMM28,%YMM18,%YMM28 |
(105) 0x41ecca VSUBPD %YMM18,%YMM8,%YMM8 |
(105) 0x41ecd0 VMULPD %YMM28,%YMM8,%YMM16 |
(105) 0x41ecd6 VCMPPD $0x1,%YMM16,%YMM24,%K1 |
(105) 0x41ecdd VCMPPD $0x1,%YMM8,%YMM24,%K2 |
(105) 0x41ece4 VDIVPD %YMM25,%YMM26,%YMM26 |
(105) 0x41ecea VBROADCASTSD 0x469dd(%RIP),%YMM9 |
(105) 0x41ecf3 VSUBPD %YMM13,%YMM9,%YMM16 |
(105) 0x41ecf9 VBROADCASTSD 0x475ae(%RIP),%YMM2 |
(105) 0x41ed02 VXORPD %YMM2,%YMM16,%YMM25 |
(105) 0x41ed08 VMOVAPD %YMM16,%YMM25{%K2} |
(105) 0x41ed0e VPXORD %XMM16,%XMM16,%XMM16 |
(105) 0x41ed14 VPMULLQ %YMM30,%YMM19,%YMM16 |
(105) 0x41ed1a VFMADD213PD %YMM23,%YMM20,%YMM23 |
(105) 0x41ed20 VBROADCASTSD 0x4757e(%RIP),%YMM19 |
(105) 0x41ed2a VSUBPD %YMM13,%YMM19,%YMM13 |
(105) 0x41ed30 VPADDQ %YMM0,%YMM16,%YMM16 |
(105) 0x41ed36 VANDPD %YMM1,%YMM28,%YMM28 |
(105) 0x41ed3c VANDPD %YMM1,%YMM8,%YMM8 |
(105) 0x41ed40 VDIVPD %YMM29,%YMM23,%YMM23 |
(105) 0x41ed46 VMINPD %YMM8,%YMM28,%YMM29 |
(105) 0x41ed4c VMULPD %YMM26,%YMM28,%YMM28 |
(105) 0x41ed52 VFMADD231PD %YMM8,%YMM13,%YMM28 |
(105) 0x41ed58 VXORPD %XMM8,%XMM8,%XMM8 |
(105) 0x41ed5d KXNORW %K0,%K0,%K2 |
(105) 0x41ed61 VGATHERQPD (%R12,%YMM16,8),%YMM8{%K2} |
(105) 0x41ed68 VBROADCASTSD 0x47546(%RIP),%YMM24 |
(105) 0x41ed72 VMULPD %YMM24,%YMM28,%YMM28 |
(105) 0x41ed78 VMINPD %YMM28,%YMM29,%YMM28 |
(105) 0x41ed7e VSUBPD %YMM21,%YMM8,%YMM21 |
(105) 0x41ed84 VSUBPD %YMM8,%YMM27,%YMM27 |
(105) 0x41ed8a VFMADD231PD %YMM25,%YMM28,%YMM18{%K1} |
(105) 0x41ed90 VSUBPD %YMM20,%YMM19,%YMM29 |
(105) 0x41ed96 VMULPD %YMM21,%YMM27,%YMM25 |
(105) 0x41ed9c VXORPD %XMM19,%XMM19,%XMM19 |
(105) 0x41eda2 VCMPPD $0x1,%YMM25,%YMM19,%K1 |
(105) 0x41eda9 VCMPPD $0x1,%YMM27,%YMM19,%K2 |
(105) 0x41edb0 VXORPD %XMM28,%XMM28,%XMM28 |
(105) 0x41edb6 VSUBPD %YMM20,%YMM9,%YMM20 |
(105) 0x41edbc VXORPD %YMM2,%YMM20,%YMM25 |
(105) 0x41edc2 VMOVAPD %YMM20,%YMM25{%K2} |
(105) 0x41edc8 VANDPD %YMM1,%YMM21,%YMM20 |
(105) 0x41edce VANDPD %YMM1,%YMM27,%YMM21 |
(105) 0x41edd4 VMINPD %YMM21,%YMM20,%YMM27 |
(105) 0x41edda VMULPD %YMM23,%YMM20,%YMM20 |
(105) 0x41ede0 VFMADD231PD %YMM21,%YMM29,%YMM20 |
(105) 0x41ede6 VMULPD %YMM24,%YMM20,%YMM20 |
(105) 0x41edec VMINPD %YMM20,%YMM27,%YMM20 |
(105) 0x41edf2 VMULPD %YMM7,%YMM18,%YMM7 |
(105) 0x41edf8 VMOVDQU64 0x140(%RSP),%YMM21 |
(105) 0x41ee00 VMOVDQA %YMM5,%YMM9 |
(105) 0x41ee04 VPXORD %XMM18,%XMM18,%XMM18 |
(105) 0x41ee0a VPMULLQ %YMM5,%YMM21,%YMM18 |
(105) 0x41ee10 VPADDQ %YMM3,%YMM18,%YMM18 |
(105) 0x41ee16 KXNORW %K0,%K0,%K2 |
(105) 0x41ee1a VSCATTERQPD %YMM7,(%RBX,%YMM18,8){%K2} |
(105) 0x41ee21 VMOVDQA64 %YMM4,%YMM27 |
(105) 0x41ee27 VPXORD %XMM18,%XMM18,%XMM18 |
(105) 0x41ee2d VPMULLQ %YMM4,%YMM21,%YMM18 |
(105) 0x41ee33 VMOVDQU64 0xe0(%RSP),%YMM19 |
(105) 0x41ee3b VPXORD %XMM21,%XMM21,%XMM21 |
(105) 0x41ee41 VPMULLQ %YMM30,%YMM19,%YMM21 |
(105) 0x41ee47 VFMADD231PD %YMM25,%YMM20,%YMM8{%K1} |
(105) 0x41ee4d VMULPD %YMM6,%YMM8,%YMM6 |
(105) 0x41ee51 VXORPS %XMM8,%XMM8,%XMM8 |
(105) 0x41ee56 VPMULLQ %YMM11,%YMM19,%YMM8 |
(105) 0x41ee5c VPADDQ %YMM0,%YMM18,%YMM11 |
(105) 0x41ee62 KXNORW %K0,%K0,%K1 |
(105) 0x41ee66 VSCATTERQPD %YMM6,(%RBX,%YMM11,8){%K1} |
(105) 0x41ee6d VPADDQ %YMM0,%YMM21,%YMM18 |
(105) 0x41ee73 VXORPD %XMM11,%XMM11,%XMM11 |
(105) 0x41ee78 KXNORW %K0,%K0,%K1 |
(105) 0x41ee7c VGATHERQPD (%R14,%YMM18,8),%YMM11{%K1} |
(105) 0x41ee83 VXORPD %XMM18,%XMM18,%XMM18 |
(105) 0x41ee89 KXNORW %K0,%K0,%K1 |
(105) 0x41ee8d VPXORD %XMM20,%XMM20,%XMM20 |
(105) 0x41ee93 VPMULLQ %YMM22,%YMM19,%YMM20 |
(105) 0x41ee99 VPADDQ %YMM3,%YMM8,%YMM8 |
(105) 0x41ee9d VPMULLQ %YMM15,%YMM19,%YMM15 |
(105) 0x41eea3 VPADDQ %YMM0,%YMM15,%YMM15 |
(105) 0x41eea7 VPADDQ %YMM3,%YMM20,%YMM20 |
(105) 0x41eead VGATHERQPD (%R14,%YMM8,8),%YMM18{%K1} |
(105) 0x41eeb4 VXORPD %XMM8,%XMM8,%XMM8 |
(105) 0x41eeb9 KXNORW %K0,%K0,%K1 |
(105) 0x41eebd VPMULLQ %YMM12,%YMM19,%YMM12 |
(105) 0x41eec3 VGATHERQPD (%R14,%YMM20,8),%YMM8{%K1} |
(105) 0x41eeca VXORPD %XMM20,%XMM20,%XMM20 |
(105) 0x41eed0 KXNORW %K0,%K0,%K1 |
(105) 0x41eed4 VPMULLQ %YMM14,%YMM19,%YMM14 |
(105) 0x41eeda VGATHERQPD (%R14,%YMM15,8),%YMM20{%K1} |
(105) 0x41eee1 VPADDQ %YMM3,%YMM12,%YMM12 |
(105) 0x41eee5 VXORPD %XMM15,%XMM15,%XMM15 |
(105) 0x41eeea KXNORW %K0,%K0,%K1 |
(105) 0x41eeee VGATHERQPD (%R14,%YMM12,8),%YMM15{%K1} |
(105) 0x41eef5 VPADDQ %YMM0,%YMM14,%YMM12 |
(105) 0x41eef9 VPXORD %XMM21,%XMM21,%XMM21 |
(105) 0x41eeff KXNORW %K0,%K0,%K1 |
(105) 0x41ef03 VGATHERQPD (%R14,%YMM12,8),%YMM21{%K1} |
(105) 0x41ef0a VSUBPD %YMM8,%YMM18,%YMM8 |
(105) 0x41ef10 VSUBPD %YMM18,%YMM15,%YMM15 |
(105) 0x41ef16 VMULPD %YMM8,%YMM15,%YMM12 |
(105) 0x41ef1b VCMPPD $0x1,%YMM12,%YMM28,%K2 |
(105) 0x41ef22 VPXORD %XMM22,%XMM22,%XMM22 |
(105) 0x41ef28 KMOVQ %K2,%K1 |
(105) 0x41ef2d VGATHERQPD (%R12,%YMM31,8),%YMM22{%K1} |
(105) 0x41ef34 VSUBPD %YMM20,%YMM11,%YMM14 |
(105) 0x41ef3a VSUBPD %YMM11,%YMM21,%YMM12 |
(105) 0x41ef40 VMULPD %YMM14,%YMM12,%YMM20 |
(105) 0x41ef46 VCMPPD $0x1,%YMM20,%YMM28,%K1 |
(105) 0x41ef4d VXORPD %XMM20,%XMM20,%XMM20 |
(105) 0x41ef53 KMOVQ %K1,%K3 |
(105) 0x41ef58 VGATHERQPD (%R12,%YMM16,8),%YMM20{%K3} |
(105) 0x41ef5f VXORPD %XMM16,%XMM16,%XMM16 |
(105) 0x41ef65 KMOVQ %K2,%K3 |
(105) 0x41ef6a VMOVUPD 0x220(%RSP),%YMM2 |
(105) 0x41ef73 VGATHERQPD (%RAX,%YMM2,8),%YMM16{%K3} |
(105) 0x41ef7a VPXOR %XMM5,%XMM5,%XMM5 |
(105) 0x41ef7e KMOVQ %K1,%K3 |
(105) 0x41ef83 VMOVUPD 0xc0(%RSP),%YMM2 |
(105) 0x41ef8c VGATHERQPD (%RAX,%YMM2,8),%YMM5{%K3} |
(105) 0x41ef93 VMULPD %YMM22,%YMM16,%YMM4 |
(105) 0x41ef99 VCMPPD $0x1,%YMM15,%YMM28,%K3 |
(105) 0x41efa0 VANDPD %YMM1,%YMM8,%YMM8 |
(105) 0x41efa4 VANDPD %YMM1,%YMM15,%YMM15 |
(105) 0x41efa8 VMULPD %YMM26,%YMM8,%YMM16 |
(105) 0x41efae VFMADD231PD %YMM13,%YMM15,%YMM16 |
(105) 0x41efb4 VANDPD %YMM1,%YMM7,%YMM13 |
(105) 0x41efb8 VDIVPD %YMM4,%YMM13,%YMM4 |
(105) 0x41efbc VMINPD %YMM15,%YMM8,%YMM8 |
(105) 0x41efc1 VBROADCASTSD 0x46705(%RIP),%YMM19 |
(105) 0x41efcb VSUBPD %YMM4,%YMM19,%YMM4 |
(105) 0x41efd1 VMULPD %YMM24,%YMM16,%YMM13 |
(105) 0x41efd7 VMINPD %YMM13,%YMM8,%YMM8 |
(105) 0x41efdc VBROADCASTSD 0x472cb(%RIP),%YMM15 |
(105) 0x41efe5 VXORPD %YMM4,%YMM15,%YMM13 |
(105) 0x41efe9 VMOVAPD %YMM4,%YMM13{%K3} |
(105) 0x41efef VFMADD231PD %YMM8,%YMM13,%YMM18{%K2} |
(105) 0x41eff5 VMOVDQU 0x120(%RSP),%YMM8 |
(105) 0x41effe VXORPS %XMM2,%XMM2,%XMM2 |
(105) 0x41f002 VPMULLQ %YMM9,%YMM8,%YMM2 |
(105) 0x41f008 VPADDQ %YMM3,%YMM2,%YMM2 |
(105) 0x41f00c VMULPD %YMM7,%YMM18,%YMM3 |
(105) 0x41f012 KXNORW %K0,%K0,%K2 |
(105) 0x41f016 MOV 0x60(%RSP),%RAX |
(105) 0x41f01b VSCATTERQPD %YMM3,(%RAX,%YMM2,8){%K2} |
(105) 0x41f022 VMULPD %YMM20,%YMM5,%YMM2 |
(105) 0x41f028 VANDPD %YMM1,%YMM6,%YMM3 |
(105) 0x41f02c VDIVPD %YMM2,%YMM3,%YMM2 |
(105) 0x41f030 VANDPD %YMM1,%YMM14,%YMM3 |
(105) 0x41f034 VANDPD %YMM1,%YMM12,%YMM4 |
(105) 0x41f038 VMULPD %YMM23,%YMM3,%YMM5 |
(105) 0x41f03e VFMADD231PD %YMM29,%YMM4,%YMM5 |
(105) 0x41f044 VCMPPD $0x1,%YMM12,%YMM28,%K2 |
(105) 0x41f04b VMINPD %YMM4,%YMM3,%YMM3 |
(105) 0x41f04f VSUBPD %YMM2,%YMM19,%YMM2 |
(105) 0x41f055 VMULPD %YMM24,%YMM5,%YMM4 |
(105) 0x41f05b VMINPD %YMM4,%YMM3,%YMM3 |
(105) 0x41f05f VXORPD %YMM2,%YMM15,%YMM4 |
(105) 0x41f063 VMOVAPD %YMM2,%YMM4{%K2} |
(105) 0x41f069 VFMADD231PD %YMM3,%YMM4,%YMM11{%K1} |
(105) 0x41f06f VMULPD %YMM6,%YMM11,%YMM2 |
(105) 0x41f073 VPMULLQ %YMM27,%YMM8,%YMM1 |
(105) 0x41f079 VPADDQ %YMM0,%YMM1,%YMM0 |
(105) 0x41f07d KXNORW %K0,%K0,%K1 |
(105) 0x41f081 VSCATTERQPD %YMM2,(%RAX,%YMM0,8){%K1} |
(105) 0x41f088 VPBROADCASTQ 0x4720f(%RIP),%YMM0 |
(105) 0x41f091 VPADDQ %YMM0,%YMM10,%YMM10 |
(105) 0x41f095 VPADDQ %YMM0,%YMM17,%YMM17 |
(105) 0x41f09b ADD $0x8,%R15 |
(105) 0x41f09f CMP %R8,%R15 |
(105) 0x41f0a2 JB 41e9c0 |
0x41f0a8 CMP %R8,0x98(%RSP) |
0x41f0b0 MOV 0x48(%RSP),%RBX |
0x41f0b5 MOV 0x60(%RSP),%RDI |
0x41f0ba MOV 0x90(%RSP),%RSI |
0x41f0c2 JNE 41f0f7 |
0x41f0c4 MOV $0x682470,%EDI |
0x41f0c9 MOV 0x58(%RSP),%ESI |
0x41f0cd LEA -0x28(%RBP),%RSP |
0x41f0d1 POP %RBX |
0x41f0d2 POP %R12 |
0x41f0d4 POP %R13 |
0x41f0d6 POP %R14 |
0x41f0d8 POP %R15 |
0x41f0da POP %RBP |
0x41f0db VZEROUPPER |
0x41f0de JMP 402e90 |
0x41f0e3 LEA -0x28(%RBP),%RSP |
0x41f0e7 POP %RBX |
0x41f0e8 POP %R12 |
0x41f0ea POP %R13 |
0x41f0ec POP %R14 |
0x41f0ee POP %R15 |
0x41f0f0 POP %RBP |
0x41f0f1 RET |
0x41f0f2 MOV %R15,%RBX |
0x41f0f5 JMP 41f0fa |
0x41f0f7 ADD %R8,%RSI |
0x41f0fa VPXOR %XMM0,%XMM0,%XMM0 |
0x41f0fe VMOVDDUP 0x465e2(%RIP),%XMM1 |
0x41f106 VMOVSD 0x4719a(%RIP),%XMM2 |
0x41f10e VMOVSD 0x465ba(%RIP),%XMM3 |
0x41f116 VMOVDDUP 0x47192(%RIP),%XMM4 |
0x41f11e VMOVDDUP 0x465c2(%RIP),%XMM5 |
0x41f126 VMOVSD 0x4718a(%RIP),%XMM6 |
0x41f12e JMP 41f162 |
(104) 0x41f130 VADDSD %XMM11,%XMM10,%XMM8 |
(104) 0x41f135 VMULSD %XMM7,%XMM8,%XMM7 |
(104) 0x41f139 IMUL 0xa0(%RSP),%RDX |
(104) 0x41f142 ADD %RAX,%RDX |
(104) 0x41f145 VMOVSD %XMM7,(%RDI,%RDX,8) |
(104) 0x41f14a INC %RSI |
(104) 0x41f14d CMP 0x78(%RSP),%RSI |
(104) 0x41f152 MOV 0x30(%RSP),%R11 |
(104) 0x41f157 MOV 0x48(%RSP),%RBX |
(104) 0x41f15c JG 41f0c4 |
(104) 0x41f162 MOV %RSI,%R8 |
(104) 0x41f165 SHR $0x20,%R8 |
(104) 0x41f169 JE 41f190 |
(104) 0x41f16b MOV %RSI,%RAX |
(104) 0x41f16e XOR %EDX,%EDX |
(104) 0x41f170 MOV 0x28(%RSP),%R9 |
(104) 0x41f175 DIV %R9 |
(104) 0x41f178 MOV %RAX,%RCX |
(104) 0x41f17b TEST %R8,%R8 |
(104) 0x41f17e MOV 0x70(%RSP),%R8 |
(104) 0x41f183 JE 41f1a8 |
(104) 0x41f185 MOV %RSI,%RAX |
(104) 0x41f188 CQTO |
(104) 0x41f18a IDIV %R9 |
(104) 0x41f18d JMP 41f1af |
0x41f18f NOP |
(104) 0x41f190 MOV %ESI,%EAX |
(104) 0x41f192 XOR %EDX,%EDX |
(104) 0x41f194 MOV 0x28(%RSP),%R9 |
(104) 0x41f199 DIV %R9D |
(104) 0x41f19c MOV %EAX,%ECX |
(104) 0x41f19e TEST %R8,%R8 |
(104) 0x41f1a1 MOV 0x70(%RSP),%R8 |
(104) 0x41f1a6 JNE 41f185 |
(104) 0x41f1a8 MOV %ESI,%EAX |
(104) 0x41f1aa XOR %EDX,%EDX |
(104) 0x41f1ac DIV %R9D |
(104) 0x41f1af MOV 0x20(%RSP),%RAX |
(104) 0x41f1b4 ADD 0x1c(%RSP),%ECX |
(104) 0x41f1b8 ADD %EAX,%EDX |
(104) 0x41f1ba MOVSXD %EDX,%RAX |
(104) 0x41f1bd MOVSXD %ECX,%RDX |
(104) 0x41f1c0 IMUL %RDX,%R8 |
(104) 0x41f1c4 ADD %RAX,%R8 |
(104) 0x41f1c7 VMOVSD (%R11,%R8,8),%XMM7 |
(104) 0x41f1cd LEA -0x1(%RDX),%R8D |
(104) 0x41f1d1 VUCOMISD %XMM7,%XMM0 |
(104) 0x41f1d5 JAE 41f1f0 |
(104) 0x41f1d7 ADD $-0x2,%ECX |
(104) 0x41f1da MOVSXD %R8D,%R10 |
(104) 0x41f1dd MOVSXD %ECX,%RCX |
(104) 0x41f1e0 MOV %RDX,%R8 |
(104) 0x41f1e3 MOV %R10,%R11 |
(104) 0x41f1e6 JMP 41f20a |
0x41f1e8 NOPL (%RAX,%RAX,1) |
(104) 0x41f1f0 MOVSXD %R8D,%R8 |
(104) 0x41f1f3 INC %ECX |
(104) 0x41f1f5 MOV 0x38(%RSP),%R9 |
(104) 0x41f1fa CMP %ECX,%R9D |
(104) 0x41f1fd CMOVL %R9D,%ECX |
(104) 0x41f201 MOVSXD %ECX,%RCX |
(104) 0x41f204 MOV %RCX,%R10 |
(104) 0x41f207 MOV %RDX,%R11 |
(104) 0x41f20a MOV 0x40(%RSP),%R9 |
(104) 0x41f20f VANDPD %XMM1,%XMM7,%XMM8 |
(104) 0x41f213 IMUL %R11,%R9 |
(104) 0x41f217 ADD %RAX,%R9 |
(104) 0x41f21a MOV 0x50(%RSP),%R15 |
(104) 0x41f21f VDIVSD (%R15,%R9,8),%XMM8,%XMM12 |
(104) 0x41f225 VMOVSD (%R13,%RDX,8),%XMM8 |
(104) 0x41f22c VFMADD213SD %XMM8,%XMM12,%XMM8 |
(104) 0x41f231 VDIVSD (%R13,%R10,8),%XMM8,%XMM9 |
(104) 0x41f238 VSUBSD %XMM12,%XMM2,%XMM8 |
(104) 0x41f23d MOV %RBX,%R10 |
(104) 0x41f240 IMUL %R11,%R10 |
(104) 0x41f244 ADD %RAX,%R10 |
(104) 0x41f247 VMOVSD (%R12,%R10,8),%XMM11 |
(104) 0x41f24d MOV %RBX,%R15 |
(104) 0x41f250 IMUL %RCX,%R15 |
(104) 0x41f254 ADD %RAX,%R15 |
(104) 0x41f257 VSUBSD (%R12,%R15,8),%XMM11,%XMM13 |
(104) 0x41f25d IMUL %R8,%RBX |
(104) 0x41f261 ADD %RAX,%RBX |
(104) 0x41f264 VMOVSD (%R12,%RBX,8),%XMM10 |
(104) 0x41f26a VSUBSD %XMM11,%XMM10,%XMM14 |
(104) 0x41f26f VMULSD %XMM13,%XMM14,%XMM15 |
(104) 0x41f274 VXORPD %XMM10,%XMM10,%XMM10 |
(104) 0x41f279 VUCOMISD %XMM10,%XMM15 |
(104) 0x41f27e VXORPD %XMM15,%XMM15,%XMM15 |
(104) 0x41f283 JBE 41f2c0 |
(104) 0x41f285 VSUBSD %XMM12,%XMM3,%XMM12 |
(104) 0x41f28a VXORPD %XMM4,%XMM12,%XMM15 |
(104) 0x41f28e VCMPSD $0x1,%XMM14,%XMM0,%K1 |
(104) 0x41f295 VMOVSD %XMM12,%XMM15,%XMM15{%K1} |
(104) 0x41f29b VANDPD %XMM5,%XMM13,%XMM12 |
(104) 0x41f29f VANDPD %XMM5,%XMM14,%XMM13 |
(104) 0x41f2a3 VMINSD %XMM13,%XMM12,%XMM14 |
(104) 0x41f2a8 VMULSD %XMM9,%XMM12,%XMM12 |
(104) 0x41f2ad VFMADD231SD %XMM13,%XMM8,%XMM12 |
(104) 0x41f2b2 VMULSD %XMM6,%XMM12,%XMM12 |
(104) 0x41f2b6 VMINSD %XMM12,%XMM14,%XMM12 |
(104) 0x41f2bb VMULSD %XMM15,%XMM12,%XMM15 |
(104) 0x41f2c0 VADDSD %XMM11,%XMM15,%XMM11 |
(104) 0x41f2c5 VMULSD %XMM7,%XMM11,%XMM7 |
(104) 0x41f2c9 MOV 0x68(%RSP),%R15 |
(104) 0x41f2ce IMUL %RDX,%R15 |
(104) 0x41f2d2 ADD %RAX,%R15 |
(104) 0x41f2d5 MOV 0xb0(%RSP),%RBX |
(104) 0x41f2dd VMOVSD %XMM7,(%RBX,%R15,8) |
(104) 0x41f2e3 MOV 0xa8(%RSP),%RBX |
(104) 0x41f2eb IMUL %RBX,%R11 |
(104) 0x41f2ef ADD %RAX,%R11 |
(104) 0x41f2f2 VMOVSD (%R14,%R11,8),%XMM11 |
(104) 0x41f2f8 IMUL %RBX,%RCX |
(104) 0x41f2fc ADD %RAX,%RCX |
(104) 0x41f2ff VSUBSD (%R14,%RCX,8),%XMM11,%XMM12 |
(104) 0x41f305 IMUL %RBX,%R8 |
(104) 0x41f309 ADD %RAX,%R8 |
(104) 0x41f30c VMOVSD (%R14,%R8,8),%XMM13 |
(104) 0x41f312 VSUBSD %XMM11,%XMM13,%XMM13 |
(104) 0x41f317 VMULSD %XMM12,%XMM13,%XMM14 |
(104) 0x41f31c VUCOMISD %XMM10,%XMM14 |
(104) 0x41f321 JBE 41f130 |
(104) 0x41f327 VANDPD %XMM5,%XMM7,%XMM10 |
(104) 0x41f32b MOV 0x50(%RSP),%RCX |
(104) 0x41f330 VMOVSD (%RCX,%R9,8),%XMM14 |
(104) 0x41f336 VMULSD (%R12,%R10,8),%XMM14,%XMM14 |
(104) 0x41f33c VDIVSD %XMM14,%XMM10,%XMM10 |
(104) 0x41f341 VSUBSD %XMM10,%XMM3,%XMM10 |
(104) 0x41f346 VXORPD %XMM4,%XMM10,%XMM14 |
(104) 0x41f34a VCMPSD $0x1,%XMM13,%XMM0,%K1 |
(104) 0x41f351 VMOVSD %XMM10,%XMM14,%XMM14{%K1} |
(104) 0x41f357 VANDPD %XMM5,%XMM12,%XMM10 |
(104) 0x41f35b VANDPD %XMM5,%XMM13,%XMM12 |
(104) 0x41f35f VMINSD %XMM12,%XMM10,%XMM13 |
(104) 0x41f364 VMULSD %XMM9,%XMM10,%XMM9 |
(104) 0x41f369 VFMADD213SD %XMM9,%XMM12,%XMM8 |
(104) 0x41f36e VMULSD %XMM6,%XMM8,%XMM8 |
(104) 0x41f372 VMINSD %XMM8,%XMM13,%XMM8 |
(104) 0x41f377 VMULSD %XMM8,%XMM14,%XMM10 |
(104) 0x41f37c JMP 41f130 |
0x41f381 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_cell.cpp:157-202 |
Module | exec |
nb instructions | 161 |
nb uops | 163 |
loop length | 816 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 3 |
used zmm registers | 0 |
nb stack references | 43 |
micro-operation queue | 27.17 cycles |
front end | 27.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.80 | 5.80 | 20.67 | 20.67 | 23.00 | 11.00 | 5.80 | 23.00 | 23.00 | 23.00 | 5.60 | 20.67 |
cycles | 5.80 | 5.80 | 20.67 | 20.67 | 23.00 | 11.00 | 5.80 | 23.00 | 23.00 | 23.00 | 5.60 | 20.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 26.97 |
Stall cycles | 0.00 |
Front-end | 27.17 |
Dispatch | 23.00 |
Overall L1 | 27.17 |
all | 22% |
load | 22% |
store | 27% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 20% |
load | 13% |
store | 27% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 19% |
load | 20% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 18% |
load | 17% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x260,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8D,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 41f0e3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0x1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x64(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x88(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x682450,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403020 <__kmpc_for_static_init_8@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JA 41f0c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x994> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x28(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB 0x20(%RSP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV (%R13),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RSI),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R9),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x8,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 41f0f2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPBROADCASTQ %RDX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x1c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTD %EAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x1e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x20(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTD %ECX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x180(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x40(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTQ %R15,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTQ %R9,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTQ %R10,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %RSI,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ 0x478d7(%RIP),%YMM0,%YMM17 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VPADDQ 0x4774f(%RIP),%YMM0,%YMM10 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R8,0x98(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 41f0f7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x682470,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x58(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402e90 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV %R15,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 41f0fa <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9ca> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPXOR %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0x465e2(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x4719a(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x465ba(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x47192(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x465c2(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x4718a(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 41f162 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xa32> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:157-202 |
Module | exec |
nb instructions | 161 |
nb uops | 163 |
loop length | 816 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 3 |
used zmm registers | 0 |
nb stack references | 43 |
micro-operation queue | 27.17 cycles |
front end | 27.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.80 | 5.80 | 20.67 | 20.67 | 23.00 | 11.00 | 5.80 | 23.00 | 23.00 | 23.00 | 5.60 | 20.67 |
cycles | 5.80 | 5.80 | 20.67 | 20.67 | 23.00 | 11.00 | 5.80 | 23.00 | 23.00 | 23.00 | 5.60 | 20.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 26.97 |
Stall cycles | 0.00 |
Front-end | 27.17 |
Dispatch | 23.00 |
Overall L1 | 27.17 |
all | 22% |
load | 22% |
store | 27% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 20% |
load | 13% |
store | 27% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 19% |
load | 20% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 18% |
load | 17% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 28% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x260,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8D,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JS 41f0e3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0x1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x64(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x88(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x682450,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403020 <__kmpc_for_static_init_8@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JA 41f0c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x994> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x28(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB 0x20(%RSP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV (%R13),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RSI),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R9),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x8,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 41f0f2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPBROADCASTQ %RDX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x1c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTD %EAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x1e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x20(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTD %ECX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x180(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x40(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTQ %R15,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RAX,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTQ %R9,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VPBROADCASTQ %R10,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU %YMM0,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %RSI,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ 0x478d7(%RIP),%YMM0,%YMM17 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VPADDQ 0x4774f(%RIP),%YMM0,%YMM10 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R8,0x98(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 41f0f7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x682470,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x58(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402e90 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV %R15,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 41f0fa <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x9ca> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPXOR %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP 0x465e2(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x4719a(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x465ba(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x47192(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x465c2(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x4718a(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 41f162 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xa32> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.48 | 2.35 |
○Loop 105 - advec_cell.cpp:158-202 - exec | 1.48 | 2.35 |
○Loop 104 - advec_cell.cpp:158-202 - exec | 0 | 0 |