Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.05% |
---|
Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.05% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 54 - 58 |
-------------------------------------------------------------------------------- |
54: #pragma omp parallel for simd collapse(2) |
55: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
56: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
57: pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
58: post_vol(i, j) = volume(i, j); |
0x418850 PUSH %RBP |
0x418851 MOV %RSP,%RBP |
0x418854 PUSH %R15 |
0x418856 PUSH %R14 |
0x418858 PUSH %R13 |
0x41885a PUSH %R12 |
0x41885c PUSH %RBX |
0x41885d AND $-0x40,%RSP |
0x418861 ADD $-0x80,%RSP |
0x418865 MOV 0x28(%RDI),%EAX |
0x418868 MOV 0x2c(%RDI),%ECX |
0x41886b MOV 0x20(%RDI),%ESI |
0x41886e MOV 0x24(%RDI),%EDX |
0x418871 ADD $0x4,%ECX |
0x418874 LEA -0x1(%RAX),%R15D |
0x418878 DEC %ESI |
0x41887a MOV %ECX,0x48(%RSP) |
0x41887e MOV %ESI,0x44(%RSP) |
0x418882 CMP %ECX,%R15D |
0x418885 JGE 418d33 |
0x41888b MOV %ECX,%EBX |
0x41888d LEA 0x4(%RDX),%R14D |
0x418891 SUB %R15D,%EBX |
0x418894 CMP %R14D,%ESI |
0x418897 JGE 418d33 |
0x41889d MOV %RDI,%R13 |
0x4188a0 MOV %R14D,%EDI |
0x4188a3 SUB %ESI,%EDI |
0x4188a5 MOV %EDI,0x4c(%RSP) |
0x4188a9 CALL 4046c0 <omp_get_num_threads@plt> |
0x4188ae MOV %EAX,%R12D |
0x4188b1 CALL 4045b0 <omp_get_thread_num@plt> |
0x4188b6 XOR %EDX,%EDX |
0x4188b8 MOV %EAX,%R8D |
0x4188bb MOV 0x4c(%RSP),%EAX |
0x4188bf IMUL %EBX,%EAX |
0x4188c2 DIV %R12D |
0x4188c5 MOV %EAX,%ECX |
0x4188c7 CMP %EDX,%R8D |
0x4188ca JB 418d53 |
0x4188d0 IMUL %ECX,%R8D |
0x4188d4 LEA (%R8,%RDX,1),%R11D |
0x4188d8 LEA (%RCX,%R11,1),%R9D |
0x4188dc MOV %R9D,0x40(%RSP) |
0x4188e1 CMP %R9D,%R11D |
0x4188e4 JAE 418d33 |
0x4188ea MOV %R11D,%EAX |
0x4188ed XOR %EDX,%EDX |
0x4188ef MOV 0x44(%RSP),%R10D |
0x4188f4 MOV 0x8(%R13),%RSI |
0x4188f8 DIVL 0x4c(%RSP) |
0x4188fc MOV 0x18(%R13),%RBX |
0x418900 MOV %RSI,0x30(%RSP) |
0x418905 MOV %RBX,0x20(%RSP) |
0x41890a ADD %EDX,%R10D |
0x41890d ADD %R15D,%EAX |
0x418910 MOV %R14D,%EDX |
0x418913 MOV (%R13),%R15 |
0x418917 MOV 0x10(%R13),%R14 |
0x41891b MOV %R10D,0x74(%RSP) |
0x418920 SUB %R10D,%EDX |
0x418923 MOVSXD %EAX,%R12 |
0x418926 MOV %R15,0x38(%RSP) |
0x41892b MOV %R14,0x28(%RSP) |
(97) 0x418930 CMP %EDX,%ECX |
(97) 0x418932 CMOVBE %ECX,%EDX |
(97) 0x418935 LEA (%R11,%RDX,1),%ECX |
(97) 0x418939 MOV %ECX,0x70(%RSP) |
(97) 0x41893d CMP %ECX,%R11D |
(97) 0x418940 JAE 418d02 |
(97) 0x418946 MOV 0x38(%RSP),%R13 |
(97) 0x41894b MOV 0x28(%RSP),%R9 |
(97) 0x418950 MOV 0x20(%RSP),%RAX |
(97) 0x418955 MOV 0x30(%RSP),%RDI |
(97) 0x41895a MOV (%R13),%RBX |
(97) 0x41895e MOV 0x10(%R9),%R8 |
(97) 0x418962 MOV (%R9),%R10 |
(97) 0x418965 MOV (%RAX),%R9 |
(97) 0x418968 IMUL %R12,%RBX |
(97) 0x41896c MOV (%RDI),%R14 |
(97) 0x41896f MOV 0x10(%RAX),%RCX |
(97) 0x418973 MOV %R8,0x60(%RSP) |
(97) 0x418978 IMUL %R12,%R10 |
(97) 0x41897c MOV 0x10(%R13),%R15 |
(97) 0x418980 LEA -0x1(%RDX),%R13D |
(97) 0x418984 MOV 0x10(%RDI),%RSI |
(97) 0x418988 IMUL %R12,%R9 |
(97) 0x41898c MOV %RCX,0x78(%RSP) |
(97) 0x418991 MOV %RBX,0x50(%RSP) |
(97) 0x418996 IMUL %R12,%R14 |
(97) 0x41899a MOV %R10,0x58(%RSP) |
(97) 0x41899f MOV %R9,0x68(%RSP) |
(97) 0x4189a4 CMP $0x6,%R13D |
(97) 0x4189a8 JBE 418d48 |
(97) 0x4189ae MOVSXD 0x74(%RSP),%RAX |
(97) 0x4189b3 LEA (%R10,%RAX,1),%R10 |
(97) 0x4189b7 LEA (%RBX,%RAX,1),%RBX |
(97) 0x4189bb LEA (%R8,%R10,8),%R10 |
(97) 0x4189bf MOV 0x78(%RSP),%R8 |
(97) 0x4189c4 LEA 0x1(%R14,%RAX,1),%RDI |
(97) 0x4189c9 ADD %R9,%RAX |
(97) 0x4189cc SAL $0x3,%RDI |
(97) 0x4189d0 LEA (%R15,%RBX,8),%RCX |
(97) 0x4189d4 LEA (%R8,%RAX,8),%R9 |
(97) 0x4189d8 MOV %EDX,%R8D |
(97) 0x4189db LEA (%RSI,%RDI,1),%R13 |
(97) 0x4189df XOR %EAX,%EAX |
(97) 0x4189e1 SHR $0x3,%R8D |
(97) 0x4189e5 LEA -0x8(%RSI,%RDI,1),%RBX |
(97) 0x4189ea SAL $0x6,%R8 |
(97) 0x4189ee LEA -0x40(%R8),%RDI |
(97) 0x4189f2 SHR $0x6,%RDI |
(97) 0x4189f6 INC %RDI |
(97) 0x4189f9 AND $0x3,%EDI |
(97) 0x4189fc JE 418a9f |
(97) 0x418a02 CMP $0x1,%RDI |
(97) 0x418a06 JE 418a67 |
(97) 0x418a08 CMP $0x2,%RDI |
(97) 0x418a0c JE 418a38 |
(97) 0x418a0e VMOVUPD (%RCX),%ZMM6 |
(97) 0x418a14 MOV $0x40,%EAX |
(97) 0x418a19 VADDPD (%R13),%ZMM6,%ZMM0 |
(97) 0x418a20 VSUBPD (%RBX),%ZMM0,%ZMM1 |
(97) 0x418a26 VMOVUPD %ZMM1,(%R10) |
(97) 0x418a2c VMOVUPD (%RCX),%ZMM7 |
(97) 0x418a32 VMOVUPD %ZMM7,(%R9) |
(97) 0x418a38 VMOVUPD (%RCX,%RAX,1),%ZMM2 |
(97) 0x418a3f VADDPD (%R13,%RAX,1),%ZMM2,%ZMM3 |
(97) 0x418a47 VSUBPD (%RBX,%RAX,1),%ZMM3,%ZMM4 |
(97) 0x418a4e VMOVUPD %ZMM4,(%R10,%RAX,1) |
(97) 0x418a55 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(97) 0x418a5c VMOVUPD %ZMM5,(%R9,%RAX,1) |
(97) 0x418a63 ADD $0x40,%RAX |
(97) 0x418a67 VMOVUPD (%RCX,%RAX,1),%ZMM8 |
(97) 0x418a6e VADDPD (%R13,%RAX,1),%ZMM8,%ZMM9 |
(97) 0x418a76 VSUBPD (%RBX,%RAX,1),%ZMM9,%ZMM10 |
(97) 0x418a7d VMOVUPD %ZMM10,(%R10,%RAX,1) |
(97) 0x418a84 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(97) 0x418a8b VMOVUPD %ZMM11,(%R9,%RAX,1) |
(97) 0x418a92 ADD $0x40,%RAX |
(97) 0x418a96 CMP %RAX,%R8 |
(97) 0x418a99 JE 418b69 |
(98) 0x418a9f VMOVUPD (%RCX,%RAX,1),%ZMM12 |
(98) 0x418aa6 VADDPD (%R13,%RAX,1),%ZMM12,%ZMM13 |
(98) 0x418aae VSUBPD (%RBX,%RAX,1),%ZMM13,%ZMM14 |
(98) 0x418ab5 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(98) 0x418abc VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(98) 0x418ac3 VMOVUPD %ZMM15,(%R9,%RAX,1) |
(98) 0x418aca VMOVUPD 0x40(%RCX,%RAX,1),%ZMM6 |
(98) 0x418ad2 VADDPD 0x40(%R13,%RAX,1),%ZMM6,%ZMM0 |
(98) 0x418ada VSUBPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM1 |
(98) 0x418ae2 VMOVUPD %ZMM1,0x40(%R10,%RAX,1) |
(98) 0x418aea VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(98) 0x418af2 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(98) 0x418afa VMOVUPD 0x80(%RCX,%RAX,1),%ZMM2 |
(98) 0x418b02 VADDPD 0x80(%R13,%RAX,1),%ZMM2,%ZMM3 |
(98) 0x418b0a VSUBPD 0x80(%RBX,%RAX,1),%ZMM3,%ZMM4 |
(98) 0x418b12 VMOVUPD %ZMM4,0x80(%R10,%RAX,1) |
(98) 0x418b1a VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(98) 0x418b22 VMOVUPD %ZMM5,0x80(%R9,%RAX,1) |
(98) 0x418b2a VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8 |
(98) 0x418b32 VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM9 |
(98) 0x418b3a VSUBPD 0xc0(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(98) 0x418b42 VMOVUPD %ZMM10,0xc0(%R10,%RAX,1) |
(98) 0x418b4a VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(98) 0x418b52 VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(98) 0x418b5a ADD $0x100,%RAX |
(98) 0x418b60 CMP %RAX,%R8 |
(98) 0x418b63 JNE 418a9f |
(97) 0x418b69 MOV 0x74(%RSP),%EAX |
(97) 0x418b6d MOV %EDX,%EDI |
(97) 0x418b6f AND $-0x8,%EDI |
(97) 0x418b72 ADD %EDI,%R11D |
(97) 0x418b75 ADD %EDI,%EAX |
(97) 0x418b77 TEST $0x7,%DL |
(97) 0x418b7a JE 418cfd |
(97) 0x418b80 SUB %EDI,%EDX |
(97) 0x418b82 LEA -0x1(%RDX),%ECX |
(97) 0x418b85 CMP $0x2,%ECX |
(97) 0x418b88 JBE 418bfb |
(97) 0x418b8a MOVSXD 0x74(%RSP),%R13 |
(97) 0x418b8f MOV 0x50(%RSP),%RBX |
(97) 0x418b94 LEA (%R14,%R13,1),%R8 |
(97) 0x418b98 LEA (%RBX,%R13,1),%R10 |
(97) 0x418b9c MOV 0x58(%RSP),%RBX |
(97) 0x418ba1 LEA 0x1(%RDI,%R8,1),%RCX |
(97) 0x418ba6 ADD %RDI,%R10 |
(97) 0x418ba9 MOV 0x60(%RSP),%R8 |
(97) 0x418bae VMOVUPD (%RSI,%RCX,8),%YMM12 |
(97) 0x418bb3 LEA (%R15,%R10,8),%R9 |
(97) 0x418bb7 LEA (%RBX,%R13,1),%R10 |
(97) 0x418bbb ADD %RDI,%R10 |
(97) 0x418bbe VSUBPD -0x8(%RSI,%RCX,8),%YMM12,%YMM13 |
(97) 0x418bc4 VADDPD (%R9),%YMM13,%YMM14 |
(97) 0x418bc9 VMOVUPD %YMM14,(%R8,%R10,8) |
(97) 0x418bcf VMOVUPD (%R9),%YMM15 |
(97) 0x418bd4 MOV 0x68(%RSP),%R9 |
(97) 0x418bd9 ADD %R9,%R13 |
(97) 0x418bdc ADD %RDI,%R13 |
(97) 0x418bdf MOV 0x78(%RSP),%RDI |
(97) 0x418be4 VMOVUPD %YMM15,(%RDI,%R13,8) |
(97) 0x418bea TEST $0x3,%DL |
(97) 0x418bed JE 418cfd |
(97) 0x418bf3 AND $-0x4,%EDX |
(97) 0x418bf6 ADD %EDX,%R11D |
(97) 0x418bf9 ADD %EDX,%EAX |
(97) 0x418bfb MOV 0x50(%RSP),%RBX |
(97) 0x418c00 MOVSXD %EAX,%RCX |
(97) 0x418c03 LEA 0x1(%RAX),%R13D |
(97) 0x418c07 LEA (%RBX,%RCX,1),%RDX |
(97) 0x418c0b LEA (%R15,%RDX,8),%RDI |
(97) 0x418c0f MOVSXD %R13D,%RDX |
(97) 0x418c12 MOV 0x58(%RSP),%R13 |
(97) 0x418c17 LEA (%R14,%RDX,1),%R10 |
(97) 0x418c1b LEA (%RSI,%R10,8),%R8 |
(97) 0x418c1f LEA (%R14,%RCX,1),%R10 |
(97) 0x418c23 VMOVSD (%R8),%XMM6 |
(97) 0x418c28 LEA (%R13,%RCX,1),%R9 |
(97) 0x418c2d VSUBSD (%RSI,%R10,8),%XMM6,%XMM0 |
(97) 0x418c33 MOV 0x60(%RSP),%R10 |
(97) 0x418c38 VADDSD (%RDI),%XMM0,%XMM1 |
(97) 0x418c3c VMOVSD %XMM1,(%R10,%R9,8) |
(97) 0x418c42 MOV 0x78(%RSP),%R9 |
(97) 0x418c47 MOV 0x70(%RSP),%R10D |
(97) 0x418c4c VMOVSD (%RDI),%XMM7 |
(97) 0x418c50 MOV 0x68(%RSP),%RDI |
(97) 0x418c55 ADD %RDI,%RCX |
(97) 0x418c58 VMOVSD %XMM7,(%R9,%RCX,8) |
(97) 0x418c5e LEA 0x1(%R11),%ECX |
(97) 0x418c62 CMP %R10D,%ECX |
(97) 0x418c65 JAE 418cfd |
(97) 0x418c6b LEA 0x2(%RAX),%R9D |
(97) 0x418c6f LEA (%RDX,%RBX,1),%RDI |
(97) 0x418c73 ADD $0x2,%R11D |
(97) 0x418c77 MOVSXD %R9D,%RCX |
(97) 0x418c7a LEA (%R15,%RDI,8),%RDI |
(97) 0x418c7e LEA (%R14,%RCX,1),%R10 |
(97) 0x418c82 LEA (%RSI,%R10,8),%R9 |
(97) 0x418c86 LEA (%R13,%RDX,1),%R10 |
(97) 0x418c8b VMOVSD (%R9),%XMM2 |
(97) 0x418c90 VADDSD (%RDI),%XMM2,%XMM3 |
(97) 0x418c94 VSUBSD (%R8),%XMM3,%XMM4 |
(97) 0x418c99 MOV 0x60(%RSP),%R8 |
(97) 0x418c9e VMOVSD %XMM4,(%R8,%R10,8) |
(97) 0x418ca4 MOV 0x68(%RSP),%R10 |
(97) 0x418ca9 VMOVSD (%RDI),%XMM5 |
(97) 0x418cad MOV 0x78(%RSP),%RDI |
(97) 0x418cb2 ADD %R10,%RDX |
(97) 0x418cb5 VMOVSD %XMM5,(%RDI,%RDX,8) |
(97) 0x418cba MOV 0x70(%RSP),%EDX |
(97) 0x418cbe CMP %EDX,%R11D |
(97) 0x418cc1 JAE 418cfd |
(97) 0x418cc3 ADD $0x3,%EAX |
(97) 0x418cc6 ADD %RCX,%RBX |
(97) 0x418cc9 ADD %RCX,%R13 |
(97) 0x418ccc ADD %RCX,%R10 |
(97) 0x418ccf CLTQ |
(97) 0x418cd1 LEA (%R15,%RBX,8),%R11 |
(97) 0x418cd5 MOV 0x78(%RSP),%R15 |
(97) 0x418cda ADD %R14,%RAX |
(97) 0x418cdd VMOVSD (%RSI,%RAX,8),%XMM8 |
(97) 0x418ce2 VADDSD (%R11),%XMM8,%XMM9 |
(97) 0x418ce7 VSUBSD (%R9),%XMM9,%XMM10 |
(97) 0x418cec VMOVSD %XMM10,(%R8,%R13,8) |
(97) 0x418cf2 VMOVSD (%R11),%XMM11 |
(97) 0x418cf7 VMOVSD %XMM11,(%R15,%R10,8) |
(97) 0x418cfd MOV 0x70(%RSP),%R11D |
(97) 0x418d02 INC %R12 |
(97) 0x418d05 LEA (%R12),%ESI |
(97) 0x418d09 CMP %ESI,0x48(%RSP) |
(97) 0x418d0d JLE 418d30 |
(97) 0x418d0f MOV 0x40(%RSP),%ECX |
(97) 0x418d13 MOV 0x44(%RSP),%R14D |
(97) 0x418d18 MOV 0x4c(%RSP),%EDX |
(97) 0x418d1c MOV %R14D,0x74(%RSP) |
(97) 0x418d21 SUB %R11D,%ECX |
(97) 0x418d24 JMP 418930 |
0x418d29 NOPL (%RAX) |
0x418d30 VZEROUPPER |
0x418d33 LEA -0x28(%RBP),%RSP |
0x418d37 POP %RBX |
0x418d38 POP %R12 |
0x418d3a POP %R13 |
0x418d3c POP %R14 |
0x418d3e POP %R15 |
0x418d40 POP %RBP |
0x418d41 RET |
0x418d42 NOPW (%RAX,%RAX,1) |
(97) 0x418d48 MOV 0x74(%RSP),%EAX |
(97) 0x418d4c XOR %EDI,%EDI |
(97) 0x418d4e JMP 418b80 |
0x418d53 INC %ECX |
0x418d55 XOR %EDX,%EDX |
0x418d57 JMP 4188d0 |
0x418d5c NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418d33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418d33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 418d53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 418d33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4188d0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418d33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418d33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 418d53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 418d33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4188d0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.05 | 0.33 |
▼Loop 97 - advec_cell.cpp:57-58 - exec– | 0 | 0 |
○Loop 98 - advec_cell.cpp:57-58 - exec | 1.04 | 0.33 |