Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 2.66% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 2.66% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
48: pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41bf60 PUSH %RBP |
0x41bf61 MOV %RSP,%RBP |
0x41bf64 PUSH %R15 |
0x41bf66 PUSH %R14 |
0x41bf68 PUSH %R13 |
0x41bf6a PUSH %R12 |
0x41bf6c MOV %RDI,%R12 |
0x41bf6f PUSH %RBX |
0x41bf70 AND $-0x40,%RSP |
0x41bf74 SUB $0xc0,%RSP |
0x41bf7b MOV 0x30(%RDI),%EAX |
0x41bf7e MOV 0x34(%RDI),%EDX |
0x41bf81 MOV 0x28(%RDI),%ESI |
0x41bf84 MOV 0x2c(%R12),%ECX |
0x41bf89 ADD $0x4,%EDX |
0x41bf8c LEA -0x1(%RAX),%R15D |
0x41bf90 LEA -0x1(%RSI),%EDI |
0x41bf93 MOV %EDX,0x60(%RSP) |
0x41bf97 MOV %EDI,0x5c(%RSP) |
0x41bf9b CMP %EDX,%R15D |
0x41bf9e JGE 41c5fb |
0x41bfa4 MOV %EDX,%EBX |
0x41bfa6 LEA 0x4(%RCX),%R14D |
0x41bfaa SUB %R15D,%EBX |
0x41bfad CMP %R14D,%EDI |
0x41bfb0 JGE 41c5fb |
0x41bfb6 MOV %R14D,%R8D |
0x41bfb9 SUB %EDI,%R8D |
0x41bfbc MOV %R8D,0x64(%RSP) |
0x41bfc1 CALL 4046c0 <omp_get_num_threads@plt> |
0x41bfc6 MOV %EAX,%R13D |
0x41bfc9 CALL 4045b0 <omp_get_thread_num@plt> |
0x41bfce XOR %EDX,%EDX |
0x41bfd0 MOV %EAX,%R9D |
0x41bfd3 MOV 0x64(%RSP),%EAX |
0x41bfd7 IMUL %EBX,%EAX |
0x41bfda DIV %R13D |
0x41bfdd MOV %EAX,%R13D |
0x41bfe0 CMP %EDX,%R9D |
0x41bfe3 JB 41c630 |
0x41bfe9 IMUL %R13D,%R9D |
0x41bfed LEA (%R9,%RDX,1),%EDI |
0x41bff1 LEA (%R13,%RDI,1),%R10D |
0x41bff6 MOV %R10D,0x58(%RSP) |
0x41bffb CMP %R10D,%EDI |
0x41bffe JAE 41c5fb |
0x41c004 MOV %EDI,%EAX |
0x41c006 XOR %EDX,%EDX |
0x41c008 MOV 0x5c(%RSP),%R11D |
0x41c00d MOV (%R12),%R8 |
0x41c011 DIVL 0x64(%RSP) |
0x41c015 MOV 0x10(%R12),%RSI |
0x41c01a MOV 0x20(%R12),%RBX |
0x41c01f MOV %R8,0x38(%RSP) |
0x41c024 MOV %RSI,0x50(%RSP) |
0x41c029 MOV %RBX,0x40(%RSP) |
0x41c02e ADD %EDX,%R11D |
0x41c031 MOV %R14D,%EDX |
0x41c034 MOV 0x8(%R12),%R14 |
0x41c039 MOV 0x18(%R12),%R12 |
0x41c03e MOV %R11D,0xb4(%RSP) |
0x41c046 LEA (%RAX,%R15,1),%R15D |
0x41c04a SUB %R11D,%EDX |
0x41c04d MOV %R14,0x48(%RSP) |
0x41c052 MOVSXD %R15D,%R8 |
0x41c055 MOV %R12,0x30(%RSP) |
0x41c05a NOPW (%RAX,%RAX,1) |
(114) 0x41c060 CMP %EDX,%R13D |
(114) 0x41c063 CMOVBE %R13D,%EDX |
(114) 0x41c067 LEA (%RDI,%RDX,1),%ECX |
(114) 0x41c06a MOV %ECX,0xb0(%RSP) |
(114) 0x41c071 CMP %ECX,%EDI |
(114) 0x41c073 JAE 41c610 |
(114) 0x41c079 MOV 0x48(%RSP),%R10 |
(114) 0x41c07e LEA 0x1(%R8),%R15 |
(114) 0x41c082 MOV 0x50(%RSP),%R9 |
(114) 0x41c087 MOV %R15,0x68(%RSP) |
(114) 0x41c08c MOV 0x40(%RSP),%R11 |
(114) 0x41c091 MOV (%R10),%RAX |
(114) 0x41c094 MOV 0x10(%R9),%R13 |
(114) 0x41c098 MOV (%R9),%R14 |
(114) 0x41c09b MOV 0x10(%R10),%RCX |
(114) 0x41c09f IMUL %RAX,%R15 |
(114) 0x41c0a3 MOV 0x38(%RSP),%R9 |
(114) 0x41c0a8 MOV 0x10(%R11),%R12 |
(114) 0x41c0ac MOV %R13,0xa0(%RSP) |
(114) 0x41c0b4 MOV (%R11),%R11 |
(114) 0x41c0b7 IMUL %R8,%R14 |
(114) 0x41c0bb MOV 0x10(%R9),%RSI |
(114) 0x41c0bf MOV (%R9),%R9 |
(114) 0x41c0c2 MOV %R12,0xa8(%RSP) |
(114) 0x41c0ca MOV %R15,%RBX |
(114) 0x41c0cd IMUL %R8,%R11 |
(114) 0x41c0d1 MOV %R15,0x78(%RSP) |
(114) 0x41c0d6 SUB %RAX,%RBX |
(114) 0x41c0d9 MOV 0x30(%RSP),%RAX |
(114) 0x41c0de IMUL %R8,%R9 |
(114) 0x41c0e2 MOV %R14,0x70(%RSP) |
(114) 0x41c0e7 MOV %RBX,0x80(%RSP) |
(114) 0x41c0ef MOV 0x10(%RAX),%R10 |
(114) 0x41c0f3 MOV %R11,0x88(%RSP) |
(114) 0x41c0fb MOV %R9,0x90(%RSP) |
(114) 0x41c103 MOV %R10,0xb8(%RSP) |
(114) 0x41c10b MOV (%RAX),%R10 |
(114) 0x41c10e IMUL %R8,%R10 |
(114) 0x41c112 LEA -0x1(%RDX),%R8D |
(114) 0x41c116 MOV %R10,0x98(%RSP) |
(114) 0x41c11e CMP $0x6,%R8D |
(114) 0x41c122 JBE 41c620 |
(114) 0x41c128 MOVSXD 0xb4(%RSP),%RAX |
(114) 0x41c130 LEA 0x1(%R9,%RAX,1),%R8 |
(114) 0x41c135 MOV %EDX,%R9D |
(114) 0x41c138 LEA (%RBX,%RAX,1),%RBX |
(114) 0x41c13c SHR $0x3,%R9D |
(114) 0x41c140 LEA (%R11,%RAX,1),%R11 |
(114) 0x41c144 SAL $0x3,%R8 |
(114) 0x41c148 LEA (%R14,%RAX,1),%R14 |
(114) 0x41c14c SAL $0x6,%R9 |
(114) 0x41c150 LEA (%R13,%R14,8),%R14 |
(114) 0x41c155 LEA (%R12,%R11,8),%R12 |
(114) 0x41c159 LEA (%RCX,%RBX,8),%R13 |
(114) 0x41c15d LEA -0x8(%RSI,%R8,1),%R11 |
(114) 0x41c162 LEA (%RSI,%R8,1),%RBX |
(114) 0x41c166 LEA -0x40(%R9),%R8 |
(114) 0x41c16a LEA (%R15,%RAX,1),%R15 |
(114) 0x41c16e SHR $0x6,%R8 |
(114) 0x41c172 ADD %R10,%RAX |
(114) 0x41c175 MOV 0xb8(%RSP),%R10 |
(114) 0x41c17d INC %R8 |
(114) 0x41c180 LEA (%RCX,%R15,8),%R15 |
(114) 0x41c184 LEA (%R10,%RAX,8),%R10 |
(114) 0x41c188 XOR %EAX,%EAX |
(114) 0x41c18a AND $0x3,%R8D |
(114) 0x41c18e JE 41c258 |
(114) 0x41c194 CMP $0x1,%R8 |
(114) 0x41c198 JE 41c213 |
(114) 0x41c19a CMP $0x2,%R8 |
(114) 0x41c19e JE 41c1d7 |
(114) 0x41c1a0 VMOVUPD (%R14),%ZMM7 |
(114) 0x41c1a6 MOV $0x40,%EAX |
(114) 0x41c1ab VADDPD (%R15),%ZMM7,%ZMM0 |
(114) 0x41c1b1 VSUBPD (%R13),%ZMM0,%ZMM2 |
(114) 0x41c1b8 VMOVUPD %ZMM2,(%R12) |
(114) 0x41c1bf VMOVUPD (%RBX),%ZMM1 |
(114) 0x41c1c5 VSUBPD (%R11),%ZMM1,%ZMM3 |
(114) 0x41c1cb VADDPD %ZMM2,%ZMM3,%ZMM4 |
(114) 0x41c1d1 VMOVUPD %ZMM4,(%R10) |
(114) 0x41c1d7 VMOVUPD (%R14,%RAX,1),%ZMM5 |
(114) 0x41c1de VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(114) 0x41c1e5 VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(114) 0x41c1ed VMOVUPD %ZMM8,(%R12,%RAX,1) |
(114) 0x41c1f4 VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(114) 0x41c1fb VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(114) 0x41c202 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(114) 0x41c208 VMOVUPD %ZMM11,(%R10,%RAX,1) |
(114) 0x41c20f ADD $0x40,%RAX |
(114) 0x41c213 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(114) 0x41c21a VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(114) 0x41c221 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(114) 0x41c229 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(114) 0x41c230 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(114) 0x41c237 VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(114) 0x41c23e VADDPD %ZMM14,%ZMM7,%ZMM0 |
(114) 0x41c244 VMOVUPD %ZMM0,(%R10,%RAX,1) |
(114) 0x41c24b ADD $0x40,%RAX |
(114) 0x41c24f CMP %RAX,%R9 |
(114) 0x41c252 JE 41c359 |
(115) 0x41c258 VMOVUPD (%R14,%RAX,1),%ZMM2 |
(115) 0x41c25f VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(115) 0x41c266 VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(115) 0x41c26e VMOVUPD %ZMM3,(%R12,%RAX,1) |
(115) 0x41c275 VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(115) 0x41c27c VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(115) 0x41c283 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(115) 0x41c289 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(115) 0x41c290 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(115) 0x41c298 VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(115) 0x41c2a0 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(115) 0x41c2a8 VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(115) 0x41c2b0 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(115) 0x41c2b8 VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(115) 0x41c2c0 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(115) 0x41c2c6 VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(115) 0x41c2ce VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(115) 0x41c2d6 VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(115) 0x41c2de VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(115) 0x41c2e6 VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(115) 0x41c2ee VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(115) 0x41c2f6 VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(115) 0x41c2fe VADDPD %ZMM7,%ZMM2,%ZMM1 |
(115) 0x41c304 VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(115) 0x41c30c VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(115) 0x41c314 VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(115) 0x41c31c VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(115) 0x41c324 VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(115) 0x41c32c VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(115) 0x41c334 VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(115) 0x41c33c VADDPD %ZMM6,%ZMM8,%ZMM9 |
(115) 0x41c342 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(115) 0x41c34a ADD $0x100,%RAX |
(115) 0x41c350 CMP %RAX,%R9 |
(115) 0x41c353 JNE 41c258 |
(114) 0x41c359 MOV 0xb4(%RSP),%R14D |
(114) 0x41c361 MOV %EDX,%R13D |
(114) 0x41c364 AND $-0x8,%R13D |
(114) 0x41c368 ADD %R13D,%EDI |
(114) 0x41c36b LEA (%R13,%R14,1),%R9D |
(114) 0x41c370 TEST $0x7,%DL |
(114) 0x41c373 JE 41c5c0 |
(114) 0x41c379 SUB %R13D,%EDX |
(114) 0x41c37c LEA -0x1(%RDX),%R15D |
(114) 0x41c380 CMP $0x2,%R15D |
(114) 0x41c384 JBE 41c440 |
(114) 0x41c38a MOVSXD 0xb4(%RSP),%R12 |
(114) 0x41c392 MOV 0x78(%RSP),%R14 |
(114) 0x41c397 MOV 0x90(%RSP),%RBX |
(114) 0x41c39f MOV 0x70(%RSP),%R10 |
(114) 0x41c3a4 LEA (%R14,%R12,1),%R15 |
(114) 0x41c3a8 ADD %R13,%R15 |
(114) 0x41c3ab LEA (%RBX,%R12,1),%R11 |
(114) 0x41c3af LEA (%R10,%R12,1),%RAX |
(114) 0x41c3b3 MOV 0xa0(%RSP),%RBX |
(114) 0x41c3bb VMOVUPD (%RCX,%R15,8),%YMM10 |
(114) 0x41c3c1 LEA 0x1(%R13,%R11,1),%R8 |
(114) 0x41c3c6 ADD %R13,%RAX |
(114) 0x41c3c9 MOV 0x80(%RSP),%R11 |
(114) 0x41c3d1 MOV 0xa8(%RSP),%R15 |
(114) 0x41c3d9 VADDPD (%RBX,%RAX,8),%YMM10,%YMM11 |
(114) 0x41c3de LEA (%R11,%R12,1),%R10 |
(114) 0x41c3e2 MOV 0x88(%RSP),%RAX |
(114) 0x41c3ea ADD %R13,%R10 |
(114) 0x41c3ed LEA (%RAX,%R12,1),%R14 |
(114) 0x41c3f1 VSUBPD (%RCX,%R10,8),%YMM11,%YMM12 |
(114) 0x41c3f7 ADD %R13,%R14 |
(114) 0x41c3fa VMOVUPD %YMM12,(%R15,%R14,8) |
(114) 0x41c400 VMOVUPD (%RSI,%R8,8),%YMM13 |
(114) 0x41c406 VSUBPD -0x8(%RSI,%R8,8),%YMM13,%YMM14 |
(114) 0x41c40d MOV 0x98(%RSP),%R8 |
(114) 0x41c415 ADD %R8,%R12 |
(114) 0x41c418 VADDPD %YMM12,%YMM14,%YMM15 |
(114) 0x41c41d ADD %R13,%R12 |
(114) 0x41c420 MOV 0xb8(%RSP),%R13 |
(114) 0x41c428 VMOVUPD %YMM15,(%R13,%R12,8) |
(114) 0x41c42f TEST $0x3,%DL |
(114) 0x41c432 JE 41c5c0 |
(114) 0x41c438 AND $-0x4,%EDX |
(114) 0x41c43b ADD %EDX,%EDI |
(114) 0x41c43d ADD %EDX,%R9D |
(114) 0x41c440 MOV 0x78(%RSP),%R14 |
(114) 0x41c445 MOVSXD %R9D,%RDX |
(114) 0x41c448 MOV 0x70(%RSP),%R15 |
(114) 0x41c44d MOV 0xa0(%RSP),%RBX |
(114) 0x41c455 MOV 0x88(%RSP),%R13 |
(114) 0x41c45d LEA (%R14,%RDX,1),%R12 |
(114) 0x41c461 LEA (%R15,%RDX,1),%R11 |
(114) 0x41c465 MOV 0xa8(%RSP),%R8 |
(114) 0x41c46d VMOVSD (%RCX,%R12,8),%XMM7 |
(114) 0x41c473 LEA (%R13,%RDX,1),%RAX |
(114) 0x41c478 VADDSD (%RBX,%R11,8),%XMM7,%XMM0 |
(114) 0x41c47e MOV 0x80(%RSP),%R11 |
(114) 0x41c486 MOV 0x90(%RSP),%RBX |
(114) 0x41c48e LEA (%R11,%RDX,1),%R10 |
(114) 0x41c492 VSUBSD (%RCX,%R10,8),%XMM0,%XMM2 |
(114) 0x41c498 VMOVSD %XMM2,(%R8,%RAX,8) |
(114) 0x41c49e LEA 0x1(%R9),%EAX |
(114) 0x41c4a2 CLTQ |
(114) 0x41c4a4 LEA (%RBX,%RAX,1),%R12 |
(114) 0x41c4a8 LEA (%RSI,%R12,8),%R8 |
(114) 0x41c4ac MOV 0x98(%RSP),%R12 |
(114) 0x41c4b4 VMOVSD (%R8),%XMM1 |
(114) 0x41c4b9 LEA (%R12,%RDX,1),%R10 |
(114) 0x41c4bd ADD %RBX,%RDX |
(114) 0x41c4c0 VSUBSD (%RSI,%RDX,8),%XMM1,%XMM3 |
(114) 0x41c4c5 MOV 0xb8(%RSP),%RDX |
(114) 0x41c4cd VADDSD %XMM2,%XMM3,%XMM4 |
(114) 0x41c4d1 VMOVSD %XMM4,(%RDX,%R10,8) |
(114) 0x41c4d7 MOV 0xb0(%RSP),%R10D |
(114) 0x41c4df LEA 0x1(%RDI),%EDX |
(114) 0x41c4e2 CMP %R10D,%EDX |
(114) 0x41c4e5 JAE 41c5c0 |
(114) 0x41c4eb LEA (%RAX,%R14,1),%R10 |
(114) 0x41c4ef LEA (%RAX,%R15,1),%RDX |
(114) 0x41c4f3 ADD $0x2,%EDI |
(114) 0x41c4f6 VMOVSD (%RCX,%R10,8),%XMM6 |
(114) 0x41c4fc MOV 0xa0(%RSP),%R10 |
(114) 0x41c504 VADDSD (%R10,%RDX,8),%XMM6,%XMM5 |
(114) 0x41c50a LEA (%RAX,%R11,1),%RDX |
(114) 0x41c50e MOV 0xa8(%RSP),%R10 |
(114) 0x41c516 VSUBSD (%RCX,%RDX,8),%XMM5,%XMM8 |
(114) 0x41c51b LEA (%RAX,%R13,1),%RDX |
(114) 0x41c51f ADD %R12,%RAX |
(114) 0x41c522 VMOVSD %XMM8,(%R10,%RDX,8) |
(114) 0x41c528 LEA 0x2(%R9),%EDX |
(114) 0x41c52c MOVSXD %EDX,%RDX |
(114) 0x41c52f LEA (%RBX,%RDX,1),%R10 |
(114) 0x41c533 LEA (%RSI,%R10,8),%R10 |
(114) 0x41c537 VMOVSD (%R10),%XMM9 |
(114) 0x41c53c VSUBSD (%R8),%XMM9,%XMM10 |
(114) 0x41c541 MOV 0xb8(%RSP),%R8 |
(114) 0x41c549 VADDSD %XMM8,%XMM10,%XMM11 |
(114) 0x41c54e VMOVSD %XMM11,(%R8,%RAX,8) |
(114) 0x41c554 MOV 0xb0(%RSP),%EAX |
(114) 0x41c55b CMP %EAX,%EDI |
(114) 0x41c55d JAE 41c5c0 |
(114) 0x41c55f MOV %R14,%RDI |
(114) 0x41c562 MOV 0xa0(%RSP),%R14 |
(114) 0x41c56a ADD %RDX,%R15 |
(114) 0x41c56d ADD %RDX,%R11 |
(114) 0x41c570 ADD %RDX,%RDI |
(114) 0x41c573 ADD $0x3,%R9D |
(114) 0x41c577 ADD %RDX,%R13 |
(114) 0x41c57a ADD %RDX,%R12 |
(114) 0x41c57d VMOVSD (%R14,%R15,8),%XMM12 |
(114) 0x41c583 MOVSXD %R9D,%R9 |
(114) 0x41c586 ADD %RBX,%R9 |
(114) 0x41c589 VADDSD (%RCX,%RDI,8),%XMM12,%XMM13 |
(114) 0x41c58e VSUBSD (%RCX,%R11,8),%XMM13,%XMM14 |
(114) 0x41c594 MOV 0xa8(%RSP),%RCX |
(114) 0x41c59c VMOVSD %XMM14,(%RCX,%R13,8) |
(114) 0x41c5a2 VMOVSD (%RSI,%R9,8),%XMM15 |
(114) 0x41c5a8 MOV 0xb8(%RSP),%RSI |
(114) 0x41c5b0 VSUBSD (%R10),%XMM15,%XMM7 |
(114) 0x41c5b5 VADDSD %XMM14,%XMM7,%XMM0 |
(114) 0x41c5ba VMOVSD %XMM0,(%RSI,%R12,8) |
(114) 0x41c5c0 MOV 0xb0(%RSP),%EDI |
(114) 0x41c5c7 MOV 0x68(%RSP),%R8 |
(114) 0x41c5cc LEA (%R8),%EBX |
(114) 0x41c5cf CMP %EBX,0x60(%RSP) |
(114) 0x41c5d3 JLE 41c5f8 |
(114) 0x41c5d5 MOV 0x58(%RSP),%R13D |
(114) 0x41c5da MOV 0x5c(%RSP),%R10D |
(114) 0x41c5df MOV 0x64(%RSP),%EDX |
(114) 0x41c5e3 MOV %R10D,0xb4(%RSP) |
(114) 0x41c5eb SUB %EDI,%R13D |
(114) 0x41c5ee JMP 41c060 |
0x41c5f3 NOPL (%RAX,%RAX,1) |
0x41c5f8 VZEROUPPER |
0x41c5fb LEA -0x28(%RBP),%RSP |
0x41c5ff POP %RBX |
0x41c600 POP %R12 |
0x41c602 POP %R13 |
0x41c604 POP %R14 |
0x41c606 POP %R15 |
0x41c608 POP %RBP |
0x41c609 RET |
0x41c60a NOPW (%RAX,%RAX,1) |
(114) 0x41c610 LEA 0x1(%R8),%R13 |
(114) 0x41c614 MOV %R13,0x68(%RSP) |
(114) 0x41c619 JMP 41c5c7 |
0x41c61b NOPL (%RAX,%RAX,1) |
(114) 0x41c620 MOV 0xb4(%RSP),%R9D |
(114) 0x41c628 XOR %R13D,%R13D |
(114) 0x41c62b JMP 41c379 |
0x41c630 INC %R13D |
0x41c633 XOR %EDX,%EDX |
0x41c635 JMP 41bfe9 |
0x41c63a NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41c5fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41c5fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41c630 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41c5fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41bfe9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41c5fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41c5fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41c630 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41c5fb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41bfe9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 2.66 | 0.85 |
▼Loop 114 - advec_mom.cpp:44-48 - exec– | 0.01 | 0 |
○Loop 115 - advec_mom.cpp:47-48 - exec | 2.65 | 0.84 |