Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 2.6% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 2.6% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 53 - 57 |
-------------------------------------------------------------------------------- |
53: #pragma omp parallel for simd collapse(2) |
54: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
55: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
56: post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
57: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41c640 PUSH %RBP |
0x41c641 MOV %RSP,%RBP |
0x41c644 PUSH %R15 |
0x41c646 PUSH %R14 |
0x41c648 PUSH %R13 |
0x41c64a PUSH %R12 |
0x41c64c PUSH %RBX |
0x41c64d AND $-0x40,%RSP |
0x41c651 SUB $0xc0,%RSP |
0x41c658 MOV 0x30(%RDI),%EAX |
0x41c65b MOV 0x34(%RDI),%EDX |
0x41c65e MOV 0x28(%RDI),%ECX |
0x41c661 MOV 0x2c(%RDI),%EBX |
0x41c664 ADD $0x4,%EDX |
0x41c667 LEA -0x1(%RAX),%R15D |
0x41c66b LEA -0x1(%RCX),%ESI |
0x41c66e MOV %EDX,0x5c(%RSP) |
0x41c672 MOV %ESI,0x58(%RSP) |
0x41c676 CMP %EDX,%R15D |
0x41c679 JGE 41ccf3 |
0x41c67f LEA 0x4(%RBX),%R14D |
0x41c683 MOV %EDX,%EBX |
0x41c685 SUB %R15D,%EBX |
0x41c688 CMP %R14D,%ESI |
0x41c68b JGE 41ccf3 |
0x41c691 MOV %RDI,%R12 |
0x41c694 MOV %R14D,%EDI |
0x41c697 SUB %ESI,%EDI |
0x41c699 MOV %EDI,0x90(%RSP) |
0x41c6a0 CALL 4046c0 <omp_get_num_threads@plt> |
0x41c6a5 MOV %EAX,%R13D |
0x41c6a8 CALL 4045b0 <omp_get_thread_num@plt> |
0x41c6ad XOR %EDX,%EDX |
0x41c6af MOV %EAX,%R8D |
0x41c6b2 MOV 0x90(%RSP),%EAX |
0x41c6b9 IMUL %EBX,%EAX |
0x41c6bc DIV %R13D |
0x41c6bf MOV %EAX,%EDI |
0x41c6c1 CMP %EDX,%R8D |
0x41c6c4 JB 41cd27 |
0x41c6ca IMUL %EDI,%R8D |
0x41c6ce LEA (%R8,%RDX,1),%R8D |
0x41c6d2 LEA (%RDI,%R8,1),%R9D |
0x41c6d6 MOV %R9D,0x54(%RSP) |
0x41c6db CMP %R9D,%R8D |
0x41c6de JAE 41ccf3 |
0x41c6e4 MOV %R8D,%EAX |
0x41c6e7 XOR %EDX,%EDX |
0x41c6e9 MOV 0x58(%RSP),%R10D |
0x41c6ee MOV (%R12),%RSI |
0x41c6f2 DIVL 0x90(%RSP) |
0x41c6f9 MOV 0x8(%R12),%RBX |
0x41c6fe MOV %RSI,0x40(%RSP) |
0x41c703 MOV %RBX,0x30(%RSP) |
0x41c708 ADD %EDX,%R10D |
0x41c70b LEA (%RAX,%R15,1),%R11D |
0x41c70f MOV %R14D,%EDX |
0x41c712 MOV 0x10(%R12),%R15 |
0x41c717 MOV 0x20(%R12),%R14 |
0x41c71c MOV 0x18(%R12),%R12 |
0x41c721 MOV %R10D,0xb0(%RSP) |
0x41c729 SUB %R10D,%EDX |
0x41c72c MOV %R15,0x48(%RSP) |
0x41c731 MOVSXD %R11D,%R9 |
0x41c734 MOV %R14,0x38(%RSP) |
0x41c739 MOV %R12,0x28(%RSP) |
0x41c73e XCHG %AX,%AX |
(116) 0x41c740 CMP %EDX,%EDI |
(116) 0x41c742 CMOVBE %EDI,%EDX |
(116) 0x41c745 LEA (%R8,%RDX,1),%ECX |
(116) 0x41c749 MOV %ECX,0x94(%RSP) |
(116) 0x41c750 CMP %ECX,%R8D |
(116) 0x41c753 JAE 41cd08 |
(116) 0x41c759 MOV 0x48(%RSP),%R13 |
(116) 0x41c75e MOV 0x30(%RSP),%R11 |
(116) 0x41c763 LEA 0x1(%R9),%RBX |
(116) 0x41c767 MOV 0x40(%RSP),%RAX |
(116) 0x41c76c MOV 0x38(%RSP),%R10 |
(116) 0x41c771 MOV %RBX,0x60(%RSP) |
(116) 0x41c776 MOV 0x10(%R13),%R14 |
(116) 0x41c77a MOV (%R13),%RDI |
(116) 0x41c77e MOV (%R11),%R13 |
(116) 0x41c781 MOV (%RAX),%R15 |
(116) 0x41c784 MOV 0x10(%R10),%R12 |
(116) 0x41c788 MOV 0x10(%RAX),%RSI |
(116) 0x41c78c IMUL %R9,%RDI |
(116) 0x41c790 MOV %R14,0xa0(%RSP) |
(116) 0x41c798 IMUL %R13,%RBX |
(116) 0x41c79c MOV 0x28(%RSP),%RAX |
(116) 0x41c7a1 MOV (%R10),%R10 |
(116) 0x41c7a4 IMUL %R9,%R15 |
(116) 0x41c7a8 MOV 0x10(%R11),%RCX |
(116) 0x41c7ac MOV %R12,0xa8(%RSP) |
(116) 0x41c7b4 IMUL %R9,%R10 |
(116) 0x41c7b8 MOV %RDI,0x68(%RSP) |
(116) 0x41c7bd IMUL (%RAX),%R9 |
(116) 0x41c7c1 MOV %RBX,%R11 |
(116) 0x41c7c4 MOV %RBX,0x80(%RSP) |
(116) 0x41c7cc SUB %R13,%R11 |
(116) 0x41c7cf MOV 0x10(%RAX),%R13 |
(116) 0x41c7d3 LEA -0x1(%RDX),%EAX |
(116) 0x41c7d6 MOV %R15,0x70(%RSP) |
(116) 0x41c7db MOV %R10,0x78(%RSP) |
(116) 0x41c7e0 MOV %R11,0x98(%RSP) |
(116) 0x41c7e8 MOV %R13,0xb8(%RSP) |
(116) 0x41c7f0 MOV %R9,0x88(%RSP) |
(116) 0x41c7f8 CMP $0x6,%EAX |
(116) 0x41c7fb JBE 41cd18 |
(116) 0x41c801 MOVSXD 0xb0(%RSP),%RAX |
(116) 0x41c809 ADD %RAX,%RDI |
(116) 0x41c80c LEA (%R10,%RAX,1),%R10 |
(116) 0x41c810 LEA (%RBX,%RAX,1),%RBX |
(116) 0x41c814 LEA (%R11,%RAX,1),%R11 |
(116) 0x41c818 LEA (%R14,%RDI,8),%R14 |
(116) 0x41c81c LEA 0x1(%R15,%RAX,1),%RDI |
(116) 0x41c821 ADD %R9,%RAX |
(116) 0x41c824 MOV 0xb8(%RSP),%R9 |
(116) 0x41c82c LEA (%R12,%R10,8),%R12 |
(116) 0x41c830 SAL $0x3,%RDI |
(116) 0x41c834 LEA (%RCX,%RBX,8),%RBX |
(116) 0x41c838 LEA (%RCX,%R11,8),%R11 |
(116) 0x41c83c LEA (%R9,%RAX,8),%R10 |
(116) 0x41c840 MOV %EDX,%R9D |
(116) 0x41c843 LEA (%RSI,%RDI,1),%R15 |
(116) 0x41c847 XOR %EAX,%EAX |
(116) 0x41c849 SHR $0x3,%R9D |
(116) 0x41c84d LEA -0x8(%RSI,%RDI,1),%R13 |
(116) 0x41c852 SAL $0x6,%R9 |
(116) 0x41c856 LEA -0x40(%R9),%RDI |
(116) 0x41c85a SHR $0x6,%RDI |
(116) 0x41c85e INC %RDI |
(116) 0x41c861 AND $0x3,%EDI |
(116) 0x41c864 JE 41c92e |
(116) 0x41c86a CMP $0x1,%RDI |
(116) 0x41c86e JE 41c8e9 |
(116) 0x41c870 CMP $0x2,%RDI |
(116) 0x41c874 JE 41c8ad |
(116) 0x41c876 VMOVUPD (%R14),%ZMM7 |
(116) 0x41c87c MOV $0x40,%EAX |
(116) 0x41c881 VADDPD (%R15),%ZMM7,%ZMM0 |
(116) 0x41c887 VSUBPD (%R13),%ZMM0,%ZMM2 |
(116) 0x41c88e VMOVUPD %ZMM2,(%R12) |
(116) 0x41c895 VMOVUPD (%RBX),%ZMM1 |
(116) 0x41c89b VSUBPD (%R11),%ZMM1,%ZMM3 |
(116) 0x41c8a1 VADDPD %ZMM2,%ZMM3,%ZMM4 |
(116) 0x41c8a7 VMOVUPD %ZMM4,(%R10) |
(116) 0x41c8ad VMOVUPD (%R14,%RAX,1),%ZMM5 |
(116) 0x41c8b4 VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(116) 0x41c8bb VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(116) 0x41c8c3 VMOVUPD %ZMM8,(%R12,%RAX,1) |
(116) 0x41c8ca VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(116) 0x41c8d1 VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(116) 0x41c8d8 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(116) 0x41c8de VMOVUPD %ZMM11,(%R10,%RAX,1) |
(116) 0x41c8e5 ADD $0x40,%RAX |
(116) 0x41c8e9 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(116) 0x41c8f0 VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(116) 0x41c8f7 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(116) 0x41c8ff VMOVUPD %ZMM14,(%R12,%RAX,1) |
(116) 0x41c906 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(116) 0x41c90d VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(116) 0x41c914 VADDPD %ZMM14,%ZMM7,%ZMM0 |
(116) 0x41c91a VMOVUPD %ZMM0,(%R10,%RAX,1) |
(116) 0x41c921 ADD $0x40,%RAX |
(116) 0x41c925 CMP %RAX,%R9 |
(116) 0x41c928 JE 41ca2f |
(117) 0x41c92e VMOVUPD (%R14,%RAX,1),%ZMM2 |
(117) 0x41c935 VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(117) 0x41c93c VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(117) 0x41c944 VMOVUPD %ZMM3,(%R12,%RAX,1) |
(117) 0x41c94b VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(117) 0x41c952 VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(117) 0x41c959 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(117) 0x41c95f VMOVUPD %ZMM6,(%R10,%RAX,1) |
(117) 0x41c966 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(117) 0x41c96e VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(117) 0x41c976 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(117) 0x41c97e VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(117) 0x41c986 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(117) 0x41c98e VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(117) 0x41c996 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(117) 0x41c99c VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(117) 0x41c9a4 VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(117) 0x41c9ac VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(117) 0x41c9b4 VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(117) 0x41c9bc VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(117) 0x41c9c4 VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(117) 0x41c9cc VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(117) 0x41c9d4 VADDPD %ZMM7,%ZMM2,%ZMM1 |
(117) 0x41c9da VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(117) 0x41c9e2 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(117) 0x41c9ea VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(117) 0x41c9f2 VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(117) 0x41c9fa VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(117) 0x41ca02 VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(117) 0x41ca0a VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(117) 0x41ca12 VADDPD %ZMM6,%ZMM8,%ZMM9 |
(117) 0x41ca18 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(117) 0x41ca20 ADD $0x100,%RAX |
(117) 0x41ca26 CMP %RAX,%R9 |
(117) 0x41ca29 JNE 41c92e |
(116) 0x41ca2f MOV 0xb0(%RSP),%EAX |
(116) 0x41ca36 MOV %EDX,%R9D |
(116) 0x41ca39 AND $-0x8,%R9D |
(116) 0x41ca3d ADD %R9D,%R8D |
(116) 0x41ca40 ADD %R9D,%EAX |
(116) 0x41ca43 TEST $0x7,%DL |
(116) 0x41ca46 JE 41ccb5 |
(116) 0x41ca4c SUB %R9D,%EDX |
(116) 0x41ca4f LEA -0x1(%RDX),%R14D |
(116) 0x41ca53 CMP $0x2,%R14D |
(116) 0x41ca57 JBE 41cb0e |
(116) 0x41ca5d MOVSXD 0xb0(%RSP),%R15 |
(116) 0x41ca65 MOV 0x70(%RSP),%R13 |
(116) 0x41ca6a MOV 0x68(%RSP),%R11 |
(116) 0x41ca6f MOV 0xa0(%RSP),%RDI |
(116) 0x41ca77 LEA (%R13,%R15,1),%R12 |
(116) 0x41ca7c MOV 0x78(%RSP),%R14 |
(116) 0x41ca81 LEA 0x1(%R9,%R12,1),%RBX |
(116) 0x41ca86 LEA (%R11,%R15,1),%R10 |
(116) 0x41ca8a MOV 0xa8(%RSP),%R12 |
(116) 0x41ca92 VMOVUPD (%RSI,%RBX,8),%YMM10 |
(116) 0x41ca97 ADD %R9,%R10 |
(116) 0x41ca9a LEA (%R14,%R15,1),%R13 |
(116) 0x41ca9e MOV 0x88(%RSP),%R14 |
(116) 0x41caa6 ADD %R9,%R13 |
(116) 0x41caa9 VSUBPD -0x8(%RSI,%RBX,8),%YMM10,%YMM11 |
(116) 0x41caaf MOV 0x80(%RSP),%RBX |
(116) 0x41cab7 LEA (%RBX,%R15,1),%R11 |
(116) 0x41cabb VADDPD (%RDI,%R10,8),%YMM11,%YMM12 |
(116) 0x41cac1 MOV 0x98(%RSP),%R10 |
(116) 0x41cac9 ADD %R9,%R11 |
(116) 0x41cacc LEA (%R10,%R15,1),%RDI |
(116) 0x41cad0 ADD %R14,%R15 |
(116) 0x41cad3 VMOVUPD %YMM12,(%R12,%R13,8) |
(116) 0x41cad9 ADD %R9,%RDI |
(116) 0x41cadc ADD %R9,%R15 |
(116) 0x41cadf MOV 0xb8(%RSP),%R9 |
(116) 0x41cae7 VMOVUPD (%RCX,%R11,8),%YMM13 |
(116) 0x41caed VSUBPD (%RCX,%RDI,8),%YMM13,%YMM14 |
(116) 0x41caf2 VADDPD %YMM12,%YMM14,%YMM15 |
(116) 0x41caf7 VMOVUPD %YMM15,(%R9,%R15,8) |
(116) 0x41cafd TEST $0x3,%DL |
(116) 0x41cb00 JE 41ccb5 |
(116) 0x41cb06 AND $-0x4,%EDX |
(116) 0x41cb09 ADD %EDX,%R8D |
(116) 0x41cb0c ADD %EDX,%EAX |
(116) 0x41cb0e MOV 0x70(%RSP),%RBX |
(116) 0x41cb13 LEA 0x1(%RAX),%R15D |
(116) 0x41cb17 MOVSXD %EAX,%RDX |
(116) 0x41cb1a MOV 0x68(%RSP),%R14 |
(116) 0x41cb1f MOVSXD %R15D,%RDI |
(116) 0x41cb22 MOV 0xa0(%RSP),%R9 |
(116) 0x41cb2a MOV 0x78(%RSP),%R15 |
(116) 0x41cb2f LEA (%RBX,%RDI,1),%R13 |
(116) 0x41cb33 LEA (%RBX,%RDX,1),%R11 |
(116) 0x41cb37 LEA (%RSI,%R13,8),%R12 |
(116) 0x41cb3b LEA (%R14,%RDX,1),%R10 |
(116) 0x41cb3f MOV 0xa8(%RSP),%R13 |
(116) 0x41cb47 VMOVSD (%R12),%XMM7 |
(116) 0x41cb4d MOV %R12,0xb0(%RSP) |
(116) 0x41cb55 LEA (%R15,%RDX,1),%R12 |
(116) 0x41cb59 VSUBSD (%RSI,%R11,8),%XMM7,%XMM0 |
(116) 0x41cb5f VADDSD (%R9,%R10,8),%XMM0,%XMM2 |
(116) 0x41cb65 MOV 0x98(%RSP),%R9 |
(116) 0x41cb6d VMOVSD %XMM2,(%R13,%R12,8) |
(116) 0x41cb74 MOV 0x80(%RSP),%R12 |
(116) 0x41cb7c MOV 0x88(%RSP),%R13 |
(116) 0x41cb84 LEA (%R12,%RDX,1),%R11 |
(116) 0x41cb88 LEA (%R13,%RDX,1),%R10 |
(116) 0x41cb8d ADD %R9,%RDX |
(116) 0x41cb90 VMOVSD (%RCX,%R11,8),%XMM1 |
(116) 0x41cb96 LEA 0x1(%R8),%R11D |
(116) 0x41cb9a VSUBSD (%RCX,%RDX,8),%XMM1,%XMM3 |
(116) 0x41cb9f MOV 0xb8(%RSP),%RDX |
(116) 0x41cba7 VADDSD %XMM2,%XMM3,%XMM4 |
(116) 0x41cbab VMOVSD %XMM4,(%RDX,%R10,8) |
(116) 0x41cbb1 MOV 0x94(%RSP),%R10D |
(116) 0x41cbb9 CMP %R10D,%R11D |
(116) 0x41cbbc JAE 41ccb5 |
(116) 0x41cbc2 LEA 0x2(%RAX),%R9D |
(116) 0x41cbc6 ADD $0x2,%R8D |
(116) 0x41cbca MOVSXD %R9D,%RDX |
(116) 0x41cbcd MOV 0xa0(%RSP),%R9 |
(116) 0x41cbd5 LEA (%RBX,%RDX,1),%R11 |
(116) 0x41cbd9 LEA (%RSI,%R11,8),%R10 |
(116) 0x41cbdd LEA (%RDI,%R14,1),%R11 |
(116) 0x41cbe1 VMOVSD (%R9,%R11,8),%XMM6 |
(116) 0x41cbe7 MOV 0xb0(%RSP),%R11 |
(116) 0x41cbef LEA (%R15,%RDI,1),%R9 |
(116) 0x41cbf3 VADDSD (%R10),%XMM6,%XMM5 |
(116) 0x41cbf8 VSUBSD (%R11),%XMM5,%XMM8 |
(116) 0x41cbfd MOV 0xa8(%RSP),%R11 |
(116) 0x41cc05 VMOVSD %XMM8,(%R11,%R9,8) |
(116) 0x41cc0b LEA (%R13,%RDI,1),%R9 |
(116) 0x41cc10 LEA (%R12,%RDI,1),%R11 |
(116) 0x41cc14 MOV %R9,0xb0(%RSP) |
(116) 0x41cc1c MOV 0x98(%RSP),%R9 |
(116) 0x41cc24 VMOVSD (%RCX,%R11,8),%XMM9 |
(116) 0x41cc2a ADD %R9,%RDI |
(116) 0x41cc2d VSUBSD (%RCX,%RDI,8),%XMM9,%XMM10 |
(116) 0x41cc32 MOV 0xb0(%RSP),%R11 |
(116) 0x41cc3a MOV 0xb8(%RSP),%RDI |
(116) 0x41cc42 VADDSD %XMM8,%XMM10,%XMM11 |
(116) 0x41cc47 VMOVSD %XMM11,(%RDI,%R11,8) |
(116) 0x41cc4d MOV 0x94(%RSP),%EDI |
(116) 0x41cc54 CMP %EDI,%R8D |
(116) 0x41cc57 JAE 41ccb5 |
(116) 0x41cc59 ADD $0x3,%EAX |
(116) 0x41cc5c MOV 0xa0(%RSP),%R8 |
(116) 0x41cc64 ADD %RDX,%R14 |
(116) 0x41cc67 ADD %RDX,%R15 |
(116) 0x41cc6a CLTQ |
(116) 0x41cc6c ADD %RDX,%R12 |
(116) 0x41cc6f ADD %RDX,%R9 |
(116) 0x41cc72 ADD %RDX,%R13 |
(116) 0x41cc75 ADD %RBX,%RAX |
(116) 0x41cc78 VMOVSD (%RSI,%RAX,8),%XMM12 |
(116) 0x41cc7d MOV 0xa8(%RSP),%RSI |
(116) 0x41cc85 VADDSD (%R8,%R14,8),%XMM12,%XMM13 |
(116) 0x41cc8b VSUBSD (%R10),%XMM13,%XMM14 |
(116) 0x41cc90 VMOVSD %XMM14,(%RSI,%R15,8) |
(116) 0x41cc96 VMOVSD (%RCX,%R12,8),%XMM15 |
(116) 0x41cc9c VSUBSD (%RCX,%R9,8),%XMM15,%XMM7 |
(116) 0x41cca2 MOV 0xb8(%RSP),%RCX |
(116) 0x41ccaa VADDSD %XMM14,%XMM7,%XMM0 |
(116) 0x41ccaf VMOVSD %XMM0,(%RCX,%R13,8) |
(116) 0x41ccb5 MOV 0x94(%RSP),%R8D |
(116) 0x41ccbd MOV 0x60(%RSP),%R9 |
(116) 0x41ccc2 LEA (%R9),%EAX |
(116) 0x41ccc5 CMP %EAX,0x5c(%RSP) |
(116) 0x41ccc9 JLE 41ccf0 |
(116) 0x41cccb MOV 0x54(%RSP),%EDI |
(116) 0x41cccf MOV 0x58(%RSP),%EBX |
(116) 0x41ccd3 MOV 0x90(%RSP),%EDX |
(116) 0x41ccda MOV %EBX,0xb0(%RSP) |
(116) 0x41cce1 SUB %R8D,%EDI |
(116) 0x41cce4 JMP 41c740 |
0x41cce9 NOPL (%RAX) |
0x41ccf0 VZEROUPPER |
0x41ccf3 LEA -0x28(%RBP),%RSP |
0x41ccf7 POP %RBX |
0x41ccf8 POP %R12 |
0x41ccfa POP %R13 |
0x41ccfc POP %R14 |
0x41ccfe POP %R15 |
0x41cd00 POP %RBP |
0x41cd01 RET |
0x41cd02 NOPW (%RAX,%RAX,1) |
(116) 0x41cd08 LEA 0x1(%R9),%RDI |
(116) 0x41cd0c MOV %RDI,0x60(%RSP) |
(116) 0x41cd11 JMP 41ccbd |
0x41cd13 NOPL (%RAX,%RAX,1) |
(116) 0x41cd18 MOV 0xb0(%RSP),%EAX |
(116) 0x41cd1f XOR %R9D,%R9D |
(116) 0x41cd22 JMP 41ca4c |
0x41cd27 INC %EDI |
0x41cd29 XOR %EDX,%EDX |
0x41cd2b JMP 41c6ca |
Path / |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 301 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.60-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RCX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41ccf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x4(%RBX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41ccf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41cd27 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41ccf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x90(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41c6ca <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 301 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.60-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RCX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41ccf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x4(%RBX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41ccf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41cd27 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41ccf3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x90(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41c6ca <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 2.6 | 0.83 |
▼Loop 116 - advec_mom.cpp:53-57 - exec– | 0.01 | 0 |
○Loop 117 - advec_mom.cpp:56-57 - exec | 2.59 | 0.82 |