Function: clover_unpack_message_right(global_variables&, int, int, int, int, clover::Buffer2D<double ... | Module: exec | Source: pack_kernel.cpp:156-160 [...] | Coverage: 0.03% |
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Function: clover_unpack_message_right(global_variables&, int, int, int, int, clover::Buffer2D<double ... | Module: exec | Source: pack_kernel.cpp:156-160 [...] | Coverage: 0.03% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/pack_kernel.cpp: 156 - 160 |
-------------------------------------------------------------------------------- |
156: #pragma omp parallel for simd |
157: for (int k = (y_min - depth + 1); k < (y_max + y_inc + depth + 2); k++) { |
158: for (int j = 0; j < depth; ++j) { |
159: int index = buffer_offset + j + k * depth; |
160: field(x_max + x_inc + j + 2, k) = right_rcv[index]; |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42ca80 PUSH %RBP |
0x42ca81 MOV %RSP,%RBP |
0x42ca84 PUSH %R15 |
0x42ca86 PUSH %R14 |
0x42ca88 PUSH %R13 |
0x42ca8a MOV %RDI,%R13 |
0x42ca8d PUSH %R12 |
0x42ca8f PUSH %RBX |
0x42ca90 SUB $0x8,%RSP |
0x42ca94 MOV 0x1c(%RDI),%EBX |
0x42ca97 MOV 0x14(%RDI),%R8D |
0x42ca9b SUB %EBX,%R8D |
0x42ca9e LEA 0x1(%R8),%R14D |
0x42caa2 CALL 4046c0 <omp_get_num_threads@plt> |
0x42caa7 MOV %EAX,%R12D |
0x42caaa CALL 4045b0 <omp_get_thread_num@plt> |
0x42caaf MOV %EAX,%ECX |
0x42cab1 MOV 0x18(%R13),%EAX |
0x42cab5 ADD 0x28(%R13),%EAX |
0x42cab9 LEA 0x2(%RBX,%RAX,1),%EAX |
0x42cabd SUB %R14D,%EAX |
0x42cac0 CLTD |
0x42cac1 IDIV %R12D |
0x42cac4 CMP %EDX,%ECX |
0x42cac6 JL 42cc73 |
0x42cacc IMUL %EAX,%ECX |
0x42cacf ADD %ECX,%EDX |
0x42cad1 ADD %EDX,%EAX |
0x42cad3 CMP %EAX,%EDX |
0x42cad5 JGE 42cc51 |
0x42cadb ADD %R14D,%EDX |
0x42cade MOV 0x10(%R13),%ESI |
0x42cae2 MOVSXD %EBX,%R10 |
0x42cae5 MOV 0x8(%R13),%R15 |
0x42cae9 MOV %EDX,%R9D |
0x42caec MOV (%R13),%R11 |
0x42caf0 LEA (%R14,%RAX,1),%R8D |
0x42caf4 SAL $0x3,%R10 |
0x42caf8 IMUL %EBX,%R9D |
0x42cafc ADD 0x24(%R13),%ESI |
0x42cb00 MOVSXD 0x20(%R13),%R14 |
0x42cb04 MOVSXD %EDX,%RDI |
0x42cb07 MOVSXD %ESI,%R12 |
0x42cb0a XOR %R13D,%R13D |
0x42cb0d NOPL (%RAX) |
(185) 0x42cb10 TEST %EBX,%EBX |
(185) 0x42cb12 JLE 42cc3d |
(185) 0x42cb18 MOV (%R11),%RSI |
(185) 0x42cb1b MOV 0x10(%R11),%RDX |
(185) 0x42cb1f MOVSXD %R9D,%RCX |
(185) 0x42cb22 MOV 0x8(%R15),%RAX |
(185) 0x42cb26 ADD %R14,%RCX |
(185) 0x42cb29 IMUL %RDI,%RSI |
(185) 0x42cb2d LEA (%RAX,%RCX,8),%RCX |
(185) 0x42cb31 XOR %EAX,%EAX |
(185) 0x42cb33 ADD %R12,%RSI |
(185) 0x42cb36 LEA (%RDX,%RSI,8),%RDX |
(185) 0x42cb3a LEA -0x8(%R10),%RSI |
(185) 0x42cb3e SHR $0x3,%RSI |
(185) 0x42cb42 INC %RSI |
(185) 0x42cb45 AND $0x7,%ESI |
(185) 0x42cb48 JE 42cbd5 |
(185) 0x42cb4e CMP $0x1,%RSI |
(185) 0x42cb52 JE 42cbc1 |
(185) 0x42cb54 CMP $0x2,%RSI |
(185) 0x42cb58 JE 42cbb2 |
(185) 0x42cb5a CMP $0x3,%RSI |
(185) 0x42cb5e JE 42cba3 |
(185) 0x42cb60 CMP $0x4,%RSI |
(185) 0x42cb64 JE 42cb94 |
(185) 0x42cb66 CMP $0x5,%RSI |
(185) 0x42cb6a JE 42cb85 |
(185) 0x42cb6c CMP $0x6,%RSI |
(185) 0x42cb70 JNE 42cc60 |
(185) 0x42cb76 VMOVSD (%RCX,%RAX,1),%XMM1 |
(185) 0x42cb7b VMOVSD %XMM1,0x10(%RDX,%RAX,1) |
(185) 0x42cb81 ADD $0x8,%RAX |
(185) 0x42cb85 VMOVSD (%RCX,%RAX,1),%XMM2 |
(185) 0x42cb8a VMOVSD %XMM2,0x10(%RDX,%RAX,1) |
(185) 0x42cb90 ADD $0x8,%RAX |
(185) 0x42cb94 VMOVSD (%RCX,%RAX,1),%XMM3 |
(185) 0x42cb99 VMOVSD %XMM3,0x10(%RDX,%RAX,1) |
(185) 0x42cb9f ADD $0x8,%RAX |
(185) 0x42cba3 VMOVSD (%RCX,%RAX,1),%XMM4 |
(185) 0x42cba8 VMOVSD %XMM4,0x10(%RDX,%RAX,1) |
(185) 0x42cbae ADD $0x8,%RAX |
(185) 0x42cbb2 VMOVSD (%RCX,%RAX,1),%XMM5 |
(185) 0x42cbb7 VMOVSD %XMM5,0x10(%RDX,%RAX,1) |
(185) 0x42cbbd ADD $0x8,%RAX |
(185) 0x42cbc1 VMOVSD (%RCX,%RAX,1),%XMM6 |
(185) 0x42cbc6 VMOVSD %XMM6,0x10(%RDX,%RAX,1) |
(185) 0x42cbcc ADD $0x8,%RAX |
(185) 0x42cbd0 CMP %RAX,%R10 |
(185) 0x42cbd3 JE 42cc3d |
(186) 0x42cbd5 VMOVSD (%RCX,%RAX,1),%XMM7 |
(186) 0x42cbda VMOVSD %XMM7,0x10(%RDX,%RAX,1) |
(186) 0x42cbe0 VMOVSD 0x8(%RCX,%RAX,1),%XMM8 |
(186) 0x42cbe6 VMOVSD %XMM8,0x18(%RDX,%RAX,1) |
(186) 0x42cbec VMOVSD 0x10(%RCX,%RAX,1),%XMM9 |
(186) 0x42cbf2 VMOVSD %XMM9,0x20(%RDX,%RAX,1) |
(186) 0x42cbf8 VMOVSD 0x18(%RCX,%RAX,1),%XMM10 |
(186) 0x42cbfe VMOVSD %XMM10,0x28(%RDX,%RAX,1) |
(186) 0x42cc04 VMOVSD 0x20(%RCX,%RAX,1),%XMM11 |
(186) 0x42cc0a VMOVSD %XMM11,0x30(%RDX,%RAX,1) |
(186) 0x42cc10 VMOVSD 0x28(%RCX,%RAX,1),%XMM12 |
(186) 0x42cc16 VMOVSD %XMM12,0x38(%RDX,%RAX,1) |
(186) 0x42cc1c VMOVSD 0x30(%RCX,%RAX,1),%XMM13 |
(186) 0x42cc22 VMOVSD %XMM13,0x40(%RDX,%RAX,1) |
(186) 0x42cc28 VMOVSD 0x38(%RCX,%RAX,1),%XMM14 |
(186) 0x42cc2e VMOVSD %XMM14,0x48(%RDX,%RAX,1) |
(186) 0x42cc34 ADD $0x40,%RAX |
(186) 0x42cc38 CMP %RAX,%R10 |
(186) 0x42cc3b JNE 42cbd5 |
(185) 0x42cc3d INC %RDI |
(185) 0x42cc40 ADD %EBX,%R9D |
(185) 0x42cc43 LEA (%R13,%RDI,1),%ECX |
(185) 0x42cc48 CMP %ECX,%R8D |
(185) 0x42cc4b JG 42cb10 |
0x42cc51 ADD $0x8,%RSP |
0x42cc55 POP %RBX |
0x42cc56 POP %R12 |
0x42cc58 POP %R13 |
0x42cc5a POP %R14 |
0x42cc5c POP %R15 |
0x42cc5e POP %RBP |
0x42cc5f RET |
(185) 0x42cc60 VMOVSD (%RCX),%XMM0 |
(185) 0x42cc64 MOV $0x8,%EAX |
(185) 0x42cc69 VMOVSD %XMM0,0x10(%RDX) |
(185) 0x42cc6e JMP 42cb76 |
0x42cc73 INC %EAX |
0x42cc75 XOR %EDX,%EDX |
0x42cc77 JMP 42cacc |
0x42cc7c NOPL (%RAX) |
Path / |
Source file and lines | pack_kernel.cpp:156-160 |
Module | exec |
nb instructions | 57 |
nb uops | 62 |
loop length | 172 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.33 cycles |
front end | 10.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 6.00 | 5.33 | 5.33 | 4.00 | 5.07 | 4.90 | 4.00 | 4.00 | 4.00 | 4.93 | 5.33 |
cycles | 5.10 | 9.40 | 5.33 | 5.33 | 4.00 | 5.07 | 4.90 | 4.00 | 4.00 | 4.00 | 4.93 | 5.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 18.15-17.99 |
Stall cycles | 7.96-7.80 |
LM full (events) | 8.77-8.61 |
Front-end | 10.33 |
Dispatch | 9.40 |
DIV/SQRT | 6.00 |
Overall L1 | 10.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 9% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 8% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x28(%R13),%EAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x2(%RBX,%RAX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 42cc73 <_Z27clover_unpack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42cc51 <_Z27clover_unpack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x1d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R14D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R13),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EBX,%R10 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R14,%RAX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x3,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %EBX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x24(%R13),%ESI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOVSXD 0x20(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOVSXD %ESI,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42cacc <_Z27clover_unpack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | pack_kernel.cpp:156-160 |
Module | exec |
nb instructions | 57 |
nb uops | 62 |
loop length | 172 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.33 cycles |
front end | 10.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 6.00 | 5.33 | 5.33 | 4.00 | 5.07 | 4.90 | 4.00 | 4.00 | 4.00 | 4.93 | 5.33 |
cycles | 5.10 | 9.40 | 5.33 | 5.33 | 4.00 | 5.07 | 4.90 | 4.00 | 4.00 | 4.00 | 4.93 | 5.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 18.15-17.99 |
Stall cycles | 7.96-7.80 |
LM full (events) | 8.77-8.61 |
Front-end | 10.33 |
Dispatch | 9.40 |
DIV/SQRT | 6.00 |
Overall L1 | 10.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 9% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 8% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x28(%R13),%EAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x2(%RBX,%RAX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 42cc73 <_Z27clover_unpack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x1f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42cc51 <_Z27clover_unpack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x1d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R14D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R13),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EBX,%R10 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R14,%RAX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x3,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %EBX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x24(%R13),%ESI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOVSXD 0x20(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOVSXD %ESI,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42cacc <_Z27clover_unpack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼clover_unpack_message_right(global_variables&, int, int, int, int, clover::Buffer2D | 0.03 | 0.01 |
▼Loop 185 - pack_kernel.cpp:158-160 - exec– | 0.03 | 0.02 |
○Loop 186 - pack_kernel.cpp:158-160 - exec | 0 | 0 |