Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:136-140 [...] | Coverage: 1.32% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:136-140 [...] | Coverage: 1.32% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 136 - 140 |
-------------------------------------------------------------------------------- |
136: #pragma omp parallel for simd collapse(2) |
137: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
138: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
139: pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
140: post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
0x419ed0 PUSH %RBP |
0x419ed1 MOV %RSP,%RBP |
0x419ed4 PUSH %R15 |
0x419ed6 PUSH %R14 |
0x419ed8 PUSH %R13 |
0x419eda PUSH %R12 |
0x419edc MOV %RDI,%R12 |
0x419edf PUSH %RBX |
0x419ee0 AND $-0x40,%RSP |
0x419ee4 SUB $0xc0,%RSP |
0x419eeb MOV 0x30(%RDI),%EAX |
0x419eee MOV 0x34(%RDI),%ECX |
0x419ef1 MOV 0x28(%RDI),%EDI |
0x419ef4 MOV 0x2c(%R12),%EDX |
0x419ef9 ADD $0x4,%ECX |
0x419efc LEA -0x1(%RAX),%R15D |
0x419f00 DEC %EDI |
0x419f02 MOV %ECX,0x5c(%RSP) |
0x419f06 MOV %EDI,0x58(%RSP) |
0x419f0a CMP %ECX,%R15D |
0x419f0d JGE 41a67b |
0x419f13 MOV %ECX,%EBX |
0x419f15 LEA 0x4(%RDX),%R14D |
0x419f19 SUB %R15D,%EBX |
0x419f1c CMP %R14D,%EDI |
0x419f1f JGE 41a67b |
0x419f25 MOV %R14D,%ESI |
0x419f28 SUB %EDI,%ESI |
0x419f2a MOV %ESI,0x78(%RSP) |
0x419f2e CALL 4046c0 <omp_get_num_threads@plt> |
0x419f33 MOV %EAX,%R13D |
0x419f36 CALL 4045b0 <omp_get_thread_num@plt> |
0x419f3b XOR %EDX,%EDX |
0x419f3d MOV %EAX,%R8D |
0x419f40 MOV 0x78(%RSP),%EAX |
0x419f44 IMUL %EBX,%EAX |
0x419f47 DIV %R13D |
0x419f4a MOV %EAX,%R13D |
0x419f4d CMP %EDX,%R8D |
0x419f50 JB 41a6af |
0x419f56 IMUL %R13D,%R8D |
0x419f5a LEA (%R8,%RDX,1),%R9D |
0x419f5e LEA (%R13,%R9,1),%R10D |
0x419f63 MOV %R10D,0x54(%RSP) |
0x419f68 CMP %R10D,%R9D |
0x419f6b JAE 41a67b |
0x419f71 MOV %R9D,%EAX |
0x419f74 XOR %EDX,%EDX |
0x419f76 MOV 0x58(%RSP),%R11D |
0x419f7b MOV (%R12),%RCX |
0x419f7f DIVL 0x78(%RSP) |
0x419f83 MOV 0x10(%R12),%RDI |
0x419f88 MOV 0x18(%R12),%RBX |
0x419f8d MOV %RCX,0x48(%RSP) |
0x419f92 MOV %RDI,0x40(%RSP) |
0x419f97 MOV %RBX,0x30(%RSP) |
0x419f9c MOV %R14D,%R10D |
0x419f9f MOV 0x8(%R12),%R14 |
0x419fa4 MOV 0x20(%R12),%R12 |
0x419fa9 MOV %R14,0x38(%RSP) |
0x419fae MOV %R12,0x28(%RSP) |
0x419fb3 ADD %EDX,%R11D |
0x419fb6 LEA (%RAX,%R15,1),%R15D |
0x419fba MOV %R11D,0xa0(%RSP) |
0x419fc2 SUB %R11D,%R10D |
0x419fc5 MOVSXD %R15D,%RCX |
0x419fc8 NOPL (%RAX,%RAX,1) |
(104) 0x419fd0 CMP %R10D,%R13D |
(104) 0x419fd3 CMOVBE %R13D,%R10D |
(104) 0x419fd7 LEA (%R9,%R10,1),%ESI |
(104) 0x419fdb MOV %R10D,%EDX |
(104) 0x419fde MOV %ESI,0x7c(%RSP) |
(104) 0x419fe2 CMP %ESI,%R9D |
(104) 0x419fe5 JAE 41a690 |
(104) 0x419feb MOV 0x40(%RSP),%R10 |
(104) 0x419ff0 MOV 0x48(%RSP),%R8 |
(104) 0x419ff5 LEA 0x1(%RCX),%RSI |
(104) 0x419ff9 MOV 0x38(%RSP),%R11 |
(104) 0x419ffe MOV 0x30(%RSP),%R12 |
(104) 0x41a003 MOV %RSI,0x60(%RSP) |
(104) 0x41a008 MOV (%R10),%RAX |
(104) 0x41a00b MOV 0x10(%R8),%R15 |
(104) 0x41a00f MOV (%R8),%R14 |
(104) 0x41a012 MOV 0x10(%R12),%R13 |
(104) 0x41a017 IMUL %RAX,%RSI |
(104) 0x41a01b MOV 0x10(%R10),%RDI |
(104) 0x41a01f MOV 0x10(%R11),%R8 |
(104) 0x41a023 MOV %R15,0x90(%RSP) |
(104) 0x41a02b MOV 0x28(%RSP),%R10 |
(104) 0x41a030 MOV (%R11),%R11 |
(104) 0x41a033 IMUL %RCX,%R14 |
(104) 0x41a037 MOV %R13,0xa8(%RSP) |
(104) 0x41a03f MOV (%R12),%R12 |
(104) 0x41a043 IMUL %RCX,%R11 |
(104) 0x41a047 MOV %RSI,%RBX |
(104) 0x41a04a MOV %RSI,0x68(%RSP) |
(104) 0x41a04f IMUL %RCX,%R12 |
(104) 0x41a053 SUB %RAX,%RBX |
(104) 0x41a056 MOV 0x10(%R10),%RAX |
(104) 0x41a05a MOV %R14,0x88(%RSP) |
(104) 0x41a062 IMUL (%R10),%RCX |
(104) 0x41a066 MOV %RBX,0x98(%RSP) |
(104) 0x41a06e MOV %R11,0x70(%RSP) |
(104) 0x41a073 MOV %R12,0x80(%RSP) |
(104) 0x41a07b MOV %RCX,0xb8(%RSP) |
(104) 0x41a083 LEA -0x1(%RDX),%ECX |
(104) 0x41a086 MOV %RAX,0xb0(%RSP) |
(104) 0x41a08e CMP $0x6,%ECX |
(104) 0x41a091 JBE 41a6a0 |
(104) 0x41a097 MOVSXD 0xa0(%RSP),%RAX |
(104) 0x41a09f LEA (%RAX,%RBX,1),%RBX |
(104) 0x41a0a3 LEA 0x1(%RAX,%R11,1),%R11 |
(104) 0x41a0a8 LEA (%RAX,%RSI,1),%R10 |
(104) 0x41a0ac LEA (%RAX,%R14,1),%R14 |
(104) 0x41a0b0 SAL $0x3,%R11 |
(104) 0x41a0b4 LEA (%RDI,%RBX,8),%RSI |
(104) 0x41a0b8 MOV 0xb8(%RSP),%RBX |
(104) 0x41a0c0 LEA (%R15,%R14,8),%R15 |
(104) 0x41a0c4 LEA (%R8,%R11,1),%R13 |
(104) 0x41a0c8 LEA -0x8(%R8,%R11,1),%R14 |
(104) 0x41a0cd MOV 0xb0(%RSP),%R11 |
(104) 0x41a0d5 LEA (%RAX,%R12,1),%R12 |
(104) 0x41a0d9 ADD %RBX,%RAX |
(104) 0x41a0dc LEA (%RDI,%R10,8),%RCX |
(104) 0x41a0e0 MOV 0xa8(%RSP),%R10 |
(104) 0x41a0e8 LEA (%R11,%RAX,8),%RBX |
(104) 0x41a0ec MOV %EDX,%R11D |
(104) 0x41a0ef XOR %EAX,%EAX |
(104) 0x41a0f1 SHR $0x3,%R11D |
(104) 0x41a0f5 LEA (%R10,%R12,8),%R12 |
(104) 0x41a0f9 SAL $0x6,%R11 |
(104) 0x41a0fd LEA -0x40(%R11),%R10 |
(104) 0x41a101 SHR $0x6,%R10 |
(104) 0x41a105 INC %R10 |
(104) 0x41a108 AND $0x3,%R10D |
(104) 0x41a10c JE 41a214 |
(104) 0x41a112 CMP $0x1,%R10 |
(104) 0x41a116 JE 41a1bb |
(104) 0x41a11c CMP $0x2,%R10 |
(104) 0x41a120 JE 41a16b |
(104) 0x41a122 VMOVUPD (%R15),%ZMM3 |
(104) 0x41a128 VMOVUPD (%RSI),%ZMM6 |
(104) 0x41a12e MOV $0x40,%EAX |
(104) 0x41a133 VADDPD (%RCX),%ZMM3,%ZMM0 |
(104) 0x41a139 VADDPD (%R14),%ZMM6,%ZMM1 |
(104) 0x41a13f VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(104) 0x41a145 VADDPD (%R13),%ZMM2,%ZMM4 |
(104) 0x41a14c VMOVUPD %ZMM4,(%R12) |
(104) 0x41a153 VMOVUPD (%RSI),%ZMM7 |
(104) 0x41a159 VSUBPD (%RCX),%ZMM7,%ZMM5 |
(104) 0x41a15f VADDPD %ZMM4,%ZMM5,%ZMM8 |
(104) 0x41a165 VMOVUPD %ZMM8,(%RBX) |
(104) 0x41a16b VMOVUPD (%R15,%RAX,1),%ZMM9 |
(104) 0x41a172 VMOVUPD (%RSI,%RAX,1),%ZMM11 |
(104) 0x41a179 VADDPD (%RCX,%RAX,1),%ZMM9,%ZMM10 |
(104) 0x41a180 VADDPD (%R14,%RAX,1),%ZMM11,%ZMM12 |
(104) 0x41a187 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(104) 0x41a18d VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(104) 0x41a195 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(104) 0x41a19c VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(104) 0x41a1a3 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM3 |
(104) 0x41a1aa VADDPD %ZMM14,%ZMM3,%ZMM0 |
(104) 0x41a1b0 VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(104) 0x41a1b7 ADD $0x40,%RAX |
(104) 0x41a1bb VMOVUPD (%R15,%RAX,1),%ZMM6 |
(104) 0x41a1c2 VMOVUPD (%RSI,%RAX,1),%ZMM1 |
(104) 0x41a1c9 VADDPD (%RCX,%RAX,1),%ZMM6,%ZMM2 |
(104) 0x41a1d0 VADDPD (%R14,%RAX,1),%ZMM1,%ZMM4 |
(104) 0x41a1d7 VSUBPD %ZMM4,%ZMM2,%ZMM7 |
(104) 0x41a1dd VADDPD (%R13,%RAX,1),%ZMM7,%ZMM5 |
(104) 0x41a1e5 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(104) 0x41a1ec VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(104) 0x41a1f3 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(104) 0x41a1fa VADDPD %ZMM5,%ZMM9,%ZMM10 |
(104) 0x41a200 VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(104) 0x41a207 ADD $0x40,%RAX |
(104) 0x41a20b CMP %RAX,%R11 |
(104) 0x41a20e JE 41a36b |
(105) 0x41a214 VMOVUPD (%R15,%RAX,1),%ZMM11 |
(105) 0x41a21b VMOVUPD (%RSI,%RAX,1),%ZMM13 |
(105) 0x41a222 VADDPD (%RCX,%RAX,1),%ZMM11,%ZMM12 |
(105) 0x41a229 VADDPD (%R14,%RAX,1),%ZMM13,%ZMM14 |
(105) 0x41a230 VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(105) 0x41a236 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM3 |
(105) 0x41a23e VMOVUPD %ZMM3,(%R12,%RAX,1) |
(105) 0x41a245 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(105) 0x41a24c VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM6 |
(105) 0x41a253 VADDPD %ZMM3,%ZMM6,%ZMM2 |
(105) 0x41a259 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(105) 0x41a260 VMOVUPD 0x40(%R15,%RAX,1),%ZMM1 |
(105) 0x41a268 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM4 |
(105) 0x41a270 VADDPD 0x40(%RCX,%RAX,1),%ZMM1,%ZMM7 |
(105) 0x41a278 VADDPD 0x40(%R14,%RAX,1),%ZMM4,%ZMM5 |
(105) 0x41a280 VSUBPD %ZMM5,%ZMM7,%ZMM8 |
(105) 0x41a286 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(105) 0x41a28e VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(105) 0x41a296 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(105) 0x41a29e VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(105) 0x41a2a6 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(105) 0x41a2ac VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(105) 0x41a2b4 VMOVUPD 0x80(%R15,%RAX,1),%ZMM13 |
(105) 0x41a2bc VMOVUPD 0x80(%RSI,%RAX,1),%ZMM15 |
(105) 0x41a2c4 VADDPD 0x80(%RCX,%RAX,1),%ZMM13,%ZMM14 |
(105) 0x41a2cc VADDPD 0x80(%R14,%RAX,1),%ZMM15,%ZMM3 |
(105) 0x41a2d4 VSUBPD %ZMM3,%ZMM14,%ZMM0 |
(105) 0x41a2da VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM6 |
(105) 0x41a2e2 VMOVUPD %ZMM6,0x80(%R12,%RAX,1) |
(105) 0x41a2ea VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(105) 0x41a2f2 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(105) 0x41a2fa VADDPD %ZMM6,%ZMM1,%ZMM7 |
(105) 0x41a300 VMOVUPD %ZMM7,0x80(%RBX,%RAX,1) |
(105) 0x41a308 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM4 |
(105) 0x41a310 VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM8 |
(105) 0x41a318 VADDPD 0xc0(%RCX,%RAX,1),%ZMM4,%ZMM5 |
(105) 0x41a320 VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM9 |
(105) 0x41a328 VSUBPD %ZMM9,%ZMM5,%ZMM10 |
(105) 0x41a32e VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(105) 0x41a336 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(105) 0x41a33e VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(105) 0x41a346 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(105) 0x41a34e VADDPD %ZMM11,%ZMM13,%ZMM14 |
(105) 0x41a354 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(105) 0x41a35c ADD $0x100,%RAX |
(105) 0x41a362 CMP %RAX,%R11 |
(105) 0x41a365 JNE 41a214 |
(104) 0x41a36b MOV 0xa0(%RSP),%R15D |
(104) 0x41a373 MOV %EDX,%R13D |
(104) 0x41a376 AND $-0x8,%R13D |
(104) 0x41a37a ADD %R13D,%R9D |
(104) 0x41a37d LEA (%R13,%R15,1),%ESI |
(104) 0x41a382 TEST $0x7,%DL |
(104) 0x41a385 JE 41a646 |
(104) 0x41a38b SUB %R13D,%EDX |
(104) 0x41a38e LEA -0x1(%RDX),%ECX |
(104) 0x41a391 CMP $0x2,%ECX |
(104) 0x41a394 JBE 41a462 |
(104) 0x41a39a MOVSXD 0xa0(%RSP),%RAX |
(104) 0x41a3a2 MOV 0x98(%RSP),%RBX |
(104) 0x41a3aa MOV 0x68(%RSP),%R14 |
(104) 0x41a3af MOV 0x70(%RSP),%R15 |
(104) 0x41a3b4 LEA (%RBX,%RAX,1),%R10 |
(104) 0x41a3b8 MOV 0x88(%RSP),%RBX |
(104) 0x41a3c0 LEA (%R14,%RAX,1),%R12 |
(104) 0x41a3c4 ADD %R13,%R10 |
(104) 0x41a3c7 LEA (%R15,%RAX,1),%R14 |
(104) 0x41a3cb MOV 0x90(%RSP),%R15 |
(104) 0x41a3d3 ADD %R13,%R12 |
(104) 0x41a3d6 LEA (%RDI,%R10,8),%RCX |
(104) 0x41a3da LEA (%RBX,%RAX,1),%R10 |
(104) 0x41a3de MOV 0xa8(%RSP),%RBX |
(104) 0x41a3e6 LEA (%RDI,%R12,8),%R11 |
(104) 0x41a3ea ADD %R13,%R10 |
(104) 0x41a3ed LEA 0x1(%R13,%R14,1),%R12 |
(104) 0x41a3f2 MOV 0x80(%RSP),%R14 |
(104) 0x41a3fa VMOVUPD (%R8,%R12,8),%YMM3 |
(104) 0x41a400 VMOVUPD (%R15,%R10,8),%YMM15 |
(104) 0x41a406 VSUBPD (%RCX),%YMM3,%YMM6 |
(104) 0x41a40a VADDPD (%R11),%YMM15,%YMM0 |
(104) 0x41a40f VADDPD %YMM6,%YMM0,%YMM2 |
(104) 0x41a413 VSUBPD -0x8(%R8,%R12,8),%YMM2,%YMM7 |
(104) 0x41a41a LEA (%R14,%RAX,1),%R12 |
(104) 0x41a41e ADD %R13,%R12 |
(104) 0x41a421 VMOVUPD %YMM7,(%RBX,%R12,8) |
(104) 0x41a427 VMOVUPD (%RCX),%YMM1 |
(104) 0x41a42b VSUBPD (%R11),%YMM1,%YMM4 |
(104) 0x41a430 MOV 0xb8(%RSP),%R11 |
(104) 0x41a438 ADD %R11,%RAX |
(104) 0x41a43b VADDPD %YMM7,%YMM4,%YMM5 |
(104) 0x41a43f ADD %R13,%RAX |
(104) 0x41a442 MOV 0xb0(%RSP),%R13 |
(104) 0x41a44a VMOVUPD %YMM5,(%R13,%RAX,8) |
(104) 0x41a451 TEST $0x3,%DL |
(104) 0x41a454 JE 41a646 |
(104) 0x41a45a AND $-0x4,%EDX |
(104) 0x41a45d ADD %EDX,%R9D |
(104) 0x41a460 ADD %EDX,%ESI |
(104) 0x41a462 MOV 0x68(%RSP),%R15 |
(104) 0x41a467 MOVSXD %ESI,%RDX |
(104) 0x41a46a MOV 0x70(%RSP),%R14 |
(104) 0x41a46f MOV 0x98(%RSP),%R13 |
(104) 0x41a477 LEA (%R15,%RDX,1),%RAX |
(104) 0x41a47b LEA (%RDI,%RAX,8),%R10 |
(104) 0x41a47f LEA 0x1(%RSI),%EAX |
(104) 0x41a482 CLTQ |
(104) 0x41a484 LEA (%R13,%RDX,1),%RCX |
(104) 0x41a489 LEA (%R14,%RAX,1),%R12 |
(104) 0x41a48d LEA (%RDI,%RCX,8),%R11 |
(104) 0x41a491 MOV 0x90(%RSP),%RCX |
(104) 0x41a499 LEA (%R8,%R12,8),%RBX |
(104) 0x41a49d MOV 0x88(%RSP),%R12 |
(104) 0x41a4a5 MOV %RBX,0xa0(%RSP) |
(104) 0x41a4ad LEA (%R12,%RDX,1),%RBX |
(104) 0x41a4b1 VMOVSD (%RCX,%RBX,8),%XMM8 |
(104) 0x41a4b6 LEA (%R14,%RDX,1),%RCX |
(104) 0x41a4ba MOV 0xa0(%RSP),%RBX |
(104) 0x41a4c2 VADDSD (%R10),%XMM8,%XMM9 |
(104) 0x41a4c7 VMOVSD (%RBX),%XMM10 |
(104) 0x41a4cb MOV 0x80(%RSP),%RBX |
(104) 0x41a4d3 VSUBSD (%R11),%XMM10,%XMM11 |
(104) 0x41a4d8 ADD %RDX,%RBX |
(104) 0x41a4db VADDSD %XMM11,%XMM9,%XMM12 |
(104) 0x41a4e0 VSUBSD (%R8,%RCX,8),%XMM12,%XMM13 |
(104) 0x41a4e6 MOV 0xa8(%RSP),%RCX |
(104) 0x41a4ee VMOVSD %XMM13,(%RCX,%RBX,8) |
(104) 0x41a4f3 MOV 0xb8(%RSP),%RBX |
(104) 0x41a4fb VMOVSD (%R11),%XMM14 |
(104) 0x41a500 MOV 0x7c(%RSP),%R11D |
(104) 0x41a505 ADD %RBX,%RDX |
(104) 0x41a508 VSUBSD (%R10),%XMM14,%XMM15 |
(104) 0x41a50d MOV 0xb0(%RSP),%R10 |
(104) 0x41a515 VADDSD %XMM13,%XMM15,%XMM0 |
(104) 0x41a51a VMOVSD %XMM0,(%R10,%RDX,8) |
(104) 0x41a520 LEA 0x1(%R9),%EDX |
(104) 0x41a524 CMP %R11D,%EDX |
(104) 0x41a527 JAE 41a646 |
(104) 0x41a52d LEA (%RAX,%R13,1),%R13 |
(104) 0x41a531 ADD %RAX,%R12 |
(104) 0x41a534 LEA (%RAX,%R15,1),%RCX |
(104) 0x41a538 ADD $0x2,%R9D |
(104) 0x41a53c LEA (%RDI,%R13,8),%R11 |
(104) 0x41a540 MOV 0x90(%RSP),%R13 |
(104) 0x41a548 LEA (%RDI,%RCX,8),%R10 |
(104) 0x41a54c LEA 0x2(%RSI),%EBX |
(104) 0x41a54f VMOVSD (%R13,%R12,8),%XMM3 |
(104) 0x41a556 MOV 0xa0(%RSP),%R12 |
(104) 0x41a55e MOVSXD %EBX,%RDX |
(104) 0x41a561 LEA (%R14,%RDX,1),%RCX |
(104) 0x41a565 MOV 0xa8(%RSP),%R13 |
(104) 0x41a56d VMOVSD (%R12),%XMM2 |
(104) 0x41a573 VADDSD (%R10),%XMM3,%XMM6 |
(104) 0x41a578 LEA (%R8,%RCX,8),%RBX |
(104) 0x41a57c MOV 0x80(%RSP),%R12 |
(104) 0x41a584 VADDSD (%R11),%XMM2,%XMM7 |
(104) 0x41a589 MOV %R12,%RCX |
(104) 0x41a58c ADD %RAX,%RCX |
(104) 0x41a58f VSUBSD %XMM7,%XMM6,%XMM1 |
(104) 0x41a593 VADDSD (%RBX),%XMM1,%XMM4 |
(104) 0x41a597 VMOVSD %XMM4,(%R13,%RCX,8) |
(104) 0x41a59e MOV 0xb8(%RSP),%RCX |
(104) 0x41a5a6 VMOVSD (%R11),%XMM5 |
(104) 0x41a5ab MOV 0xb0(%RSP),%R11 |
(104) 0x41a5b3 ADD %RCX,%RAX |
(104) 0x41a5b6 VSUBSD (%R10),%XMM5,%XMM8 |
(104) 0x41a5bb VADDSD %XMM4,%XMM8,%XMM9 |
(104) 0x41a5bf VMOVSD %XMM9,(%R11,%RAX,8) |
(104) 0x41a5c5 MOV 0x7c(%RSP),%EAX |
(104) 0x41a5c9 CMP %EAX,%R9D |
(104) 0x41a5cc JAE 41a646 |
(104) 0x41a5ce MOV 0x98(%RSP),%R9 |
(104) 0x41a5d6 ADD %RDX,%R15 |
(104) 0x41a5d9 MOV 0x90(%RSP),%RAX |
(104) 0x41a5e1 ADD $0x3,%ESI |
(104) 0x41a5e4 LEA (%RDI,%R15,8),%R10 |
(104) 0x41a5e8 MOVSXD %ESI,%RSI |
(104) 0x41a5eb ADD %RDX,%R12 |
(104) 0x41a5ee ADD %RDX,%R9 |
(104) 0x41a5f1 ADD %R14,%RSI |
(104) 0x41a5f4 LEA (%RDI,%R9,8),%RCX |
(104) 0x41a5f8 MOV 0x88(%RSP),%RDI |
(104) 0x41a600 VMOVSD (%RCX),%XMM12 |
(104) 0x41a604 ADD %RDX,%RDI |
(104) 0x41a607 VMOVSD (%RAX,%RDI,8),%XMM10 |
(104) 0x41a60c VADDSD (%RBX),%XMM12,%XMM13 |
(104) 0x41a610 VADDSD (%R10),%XMM10,%XMM11 |
(104) 0x41a615 VSUBSD %XMM13,%XMM11,%XMM14 |
(104) 0x41a61a VADDSD (%R8,%RSI,8),%XMM14,%XMM15 |
(104) 0x41a620 MOV 0xb8(%RSP),%R8 |
(104) 0x41a628 ADD %RDX,%R8 |
(104) 0x41a62b VMOVSD %XMM15,(%R13,%R12,8) |
(104) 0x41a632 VMOVSD (%RCX),%XMM0 |
(104) 0x41a636 VSUBSD (%R10),%XMM0,%XMM3 |
(104) 0x41a63b VADDSD %XMM15,%XMM3,%XMM6 |
(104) 0x41a640 VMOVSD %XMM6,(%R11,%R8,8) |
(104) 0x41a646 MOV 0x7c(%RSP),%R9D |
(104) 0x41a64b MOV 0x60(%RSP),%RCX |
(104) 0x41a650 LEA (%RCX),%EDX |
(104) 0x41a652 CMP %EDX,0x5c(%RSP) |
(104) 0x41a656 JLE 41a678 |
(104) 0x41a658 MOV 0x54(%RSP),%R13D |
(104) 0x41a65d MOV 0x58(%RSP),%EBX |
(104) 0x41a661 MOV 0x78(%RSP),%R10D |
(104) 0x41a666 MOV %EBX,0xa0(%RSP) |
(104) 0x41a66d SUB %R9D,%R13D |
(104) 0x41a670 JMP 419fd0 |
0x41a675 NOPL (%RAX) |
0x41a678 VZEROUPPER |
0x41a67b LEA -0x28(%RBP),%RSP |
0x41a67f POP %RBX |
0x41a680 POP %R12 |
0x41a682 POP %R13 |
0x41a684 POP %R14 |
0x41a686 POP %R15 |
0x41a688 POP %RBP |
0x41a689 RET |
0x41a68a NOPW (%RAX,%RAX,1) |
(104) 0x41a690 LEA 0x1(%RCX),%R13 |
(104) 0x41a694 MOV %R13,0x60(%RSP) |
(104) 0x41a699 JMP 41a64b |
0x41a69b NOPL (%RAX,%RAX,1) |
(104) 0x41a6a0 MOV 0xa0(%RSP),%ESI |
(104) 0x41a6a7 XOR %R13D,%R13D |
(104) 0x41a6aa JMP 41a38b |
0x41a6af INC %R13D |
0x41a6b2 XOR %EDX,%EDX |
0x41a6b4 JMP 419f56 |
0x41a6b9 NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:136-140 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 305 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41a67b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41a67b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x78(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41a6af <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41a67b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 419f56 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:136-140 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 305 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41a67b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41a67b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x78(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41a6af <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41a67b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 419f56 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4.lto_priv.0+0x86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.32 | 0.42 |
▼Loop 104 - advec_cell.cpp:136-140 - exec– | 0 | 0 |
○Loop 105 - advec_cell.cpp:139-140 - exec | 1.31 | 0.42 |