Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:208-216 [...] | Coverage: 2.73% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:208-216 [...] | Coverage: 2.73% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 208 - 216 |
-------------------------------------------------------------------------------- |
208: #pragma omp parallel for simd collapse(2) |
209: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
210: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
211: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
212: double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1); |
213: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s; |
214: double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1); |
215: density1(i, j) = post_mass_s / advec_vol_s; |
216: energy1(i, j) = post_ener_s; |
0x41b780 PUSH %RBP |
0x41b781 MOV %RSP,%RBP |
0x41b784 PUSH %R15 |
0x41b786 PUSH %R14 |
0x41b788 PUSH %R13 |
0x41b78a PUSH %R12 |
0x41b78c PUSH %RBX |
0x41b78d MOV %RDI,%RBX |
0x41b790 AND $-0x40,%RSP |
0x41b794 SUB $0x100,%RSP |
0x41b79b MOV 0x38(%RDI),%EAX |
0x41b79e MOV 0x3c(%RDI),%EDX |
0x41b7a1 MOV 0x30(%RDI),%EDI |
0x41b7a4 MOV 0x34(%RBX),%ESI |
0x41b7a7 ADD $0x2,%EDX |
0x41b7aa LEA 0x1(%RAX),%R15D |
0x41b7ae INC %EDI |
0x41b7b0 MOV %EDX,0x70(%RSP) |
0x41b7b4 MOV %EDI,0x6c(%RSP) |
0x41b7b8 CMP %EDX,%R15D |
0x41b7bb JGE 41bf33 |
0x41b7c1 MOV %EDX,%R13D |
0x41b7c4 LEA 0x2(%RSI),%R14D |
0x41b7c8 SUB %R15D,%R13D |
0x41b7cb CMP %R14D,%EDI |
0x41b7ce JGE 41bf33 |
0x41b7d4 MOV %R14D,%ECX |
0x41b7d7 SUB %EDI,%ECX |
0x41b7d9 MOV %ECX,0x74(%RSP) |
0x41b7dd CALL 4046c0 <omp_get_num_threads@plt> |
0x41b7e2 MOV %EAX,%R12D |
0x41b7e5 CALL 4045b0 <omp_get_thread_num@plt> |
0x41b7ea XOR %EDX,%EDX |
0x41b7ec MOV %EAX,%R8D |
0x41b7ef MOV 0x74(%RSP),%EAX |
0x41b7f3 IMUL %R13D,%EAX |
0x41b7f7 DIV %R12D |
0x41b7fa MOV %EAX,%ECX |
0x41b7fc CMP %EDX,%R8D |
0x41b7ff JB 41bf56 |
0x41b805 IMUL %ECX,%R8D |
0x41b809 LEA (%R8,%RDX,1),%R11D |
0x41b80d LEA (%RCX,%R11,1),%R9D |
0x41b811 MOV %R9D,0x68(%RSP) |
0x41b816 CMP %R9D,%R11D |
0x41b819 JAE 41bf33 |
0x41b81f MOV %R11D,%EAX |
0x41b822 XOR %EDX,%EDX |
0x41b824 MOV 0x6c(%RSP),%R10D |
0x41b829 MOV (%RBX),%RDI |
0x41b82c DIVL 0x74(%RSP) |
0x41b830 MOV 0x20(%RBX),%RSI |
0x41b834 MOV 0x8(%RBX),%R13 |
0x41b838 MOV 0x28(%RBX),%R12 |
0x41b83c MOV %RDI,0x60(%RSP) |
0x41b841 MOV %RSI,0x58(%RSP) |
0x41b846 MOV %R13,0x48(%RSP) |
0x41b84b MOV %R12,0x40(%RSP) |
0x41b850 LEA (%RAX,%R15,1),%R15D |
0x41b854 MOV %R14D,%EAX |
0x41b857 MOV 0x10(%RBX),%R14 |
0x41b85b MOV 0x18(%RBX),%RBX |
0x41b85f ADD %EDX,%R10D |
0x41b862 MOVSXD %R15D,%R8 |
0x41b865 MOV %R11D,%R15D |
0x41b868 MOV %R10D,0xd4(%RSP) |
0x41b870 SUB %R10D,%EAX |
0x41b873 MOV %R14,0x50(%RSP) |
0x41b878 MOV %RBX,0x38(%RSP) |
0x41b87d MOV %R8,0xc8(%RSP) |
0x41b885 NOPL (%RAX) |
(112) 0x41b888 CMP %EAX,%ECX |
(112) 0x41b88a CMOVBE %ECX,%EAX |
(112) 0x41b88d LEA (%R15,%RAX,1),%ECX |
(112) 0x41b891 MOV %EAX,%EDX |
(112) 0x41b893 MOV %ECX,0xd0(%RSP) |
(112) 0x41b89a CMP %ECX,%R15D |
(112) 0x41b89d JAE 41bef7 |
(112) 0x41b8a3 MOV 0x50(%RSP),%R10 |
(112) 0x41b8a8 MOV 0xc8(%RSP),%RSI |
(112) 0x41b8b0 MOV 0x58(%RSP),%R9 |
(112) 0x41b8b5 MOV 0x48(%RSP),%R12 |
(112) 0x41b8ba MOV (%R10),%R14 |
(112) 0x41b8bd MOV 0x40(%RSP),%RCX |
(112) 0x41b8c2 MOV 0x10(%R9),%RAX |
(112) 0x41b8c6 MOV 0x10(%R10),%RDI |
(112) 0x41b8ca MOV %RSI,%R10 |
(112) 0x41b8cd MOV 0x10(%R12),%R8 |
(112) 0x41b8d2 IMUL %R14,%R10 |
(112) 0x41b8d6 MOV 0x60(%RSP),%R11 |
(112) 0x41b8db MOV %RAX,0xe8(%RSP) |
(112) 0x41b8e3 MOV (%RCX),%RAX |
(112) 0x41b8e6 MOV 0x10(%R11),%R13 |
(112) 0x41b8ea MOV (%R11),%RBX |
(112) 0x41b8ed MOV %R8,0xf0(%RSP) |
(112) 0x41b8f5 MOV %RSI,%R8 |
(112) 0x41b8f8 IMUL %RAX,%R8 |
(112) 0x41b8fc ADD %R10,%R14 |
(112) 0x41b8ff MOV (%R9),%R11 |
(112) 0x41b902 MOV (%R12),%R9 |
(112) 0x41b906 MOV %R14,0xa8(%RSP) |
(112) 0x41b90e MOV 0x10(%RCX),%R14 |
(112) 0x41b912 IMUL %RSI,%RBX |
(112) 0x41b916 MOV 0x38(%RSP),%RCX |
(112) 0x41b91b IMUL %RSI,%R11 |
(112) 0x41b91f MOV %R13,0xb0(%RSP) |
(112) 0x41b927 IMUL %RSI,%R9 |
(112) 0x41b92b LEA (%RAX,%R8,1),%R12 |
(112) 0x41b92f MOV %R10,0x98(%RSP) |
(112) 0x41b937 MOV (%RCX),%RAX |
(112) 0x41b93a MOV %R12,0xf8(%RSP) |
(112) 0x41b942 MOV 0x10(%RCX),%R12 |
(112) 0x41b946 LEA -0x1(%RDX),%ECX |
(112) 0x41b949 MOV %RBX,0x88(%RSP) |
(112) 0x41b951 IMUL %RAX,%RSI |
(112) 0x41b955 MOV %R11,0x90(%RSP) |
(112) 0x41b95d MOV %R9,0xb8(%RSP) |
(112) 0x41b965 MOV %R8,0xc0(%RSP) |
(112) 0x41b96d MOV %RSI,0xd8(%RSP) |
(112) 0x41b975 LEA (%RAX,%RSI,1),%RSI |
(112) 0x41b979 MOV %RSI,0xe0(%RSP) |
(112) 0x41b981 CMP $0x6,%ECX |
(112) 0x41b984 JBE 41bf48 |
(112) 0x41b98a MOVSXD 0xd4(%RSP),%RAX |
(112) 0x41b992 MOV 0xa8(%RSP),%RCX |
(112) 0x41b99a LEA (%RBX,%RAX,1),%RBX |
(112) 0x41b99e LEA (%R10,%RAX,1),%R10 |
(112) 0x41b9a2 ADD %RAX,%RCX |
(112) 0x41b9a5 ADD %RAX,%R8 |
(112) 0x41b9a8 LEA (%R13,%RBX,8),%RSI |
(112) 0x41b9ad LEA (%R11,%RAX,1),%R13 |
(112) 0x41b9b1 MOV 0xe8(%RSP),%R11 |
(112) 0x41b9b9 LEA (%RDI,%R10,8),%RBX |
(112) 0x41b9bd MOV 0xf0(%RSP),%R10 |
(112) 0x41b9c5 LEA (%R9,%RAX,1),%R9 |
(112) 0x41b9c9 LEA (%R11,%R13,8),%R13 |
(112) 0x41b9cd LEA (%RDI,%RCX,8),%R11 |
(112) 0x41b9d1 MOV %R11,0x80(%RSP) |
(112) 0x41b9d9 LEA (%R14,%R8,8),%R11 |
(112) 0x41b9dd MOV 0xf8(%RSP),%R8 |
(112) 0x41b9e5 LEA (%R10,%R9,8),%RCX |
(112) 0x41b9e9 MOV 0xd8(%RSP),%R9 |
(112) 0x41b9f1 ADD %RAX,%R8 |
(112) 0x41b9f4 LEA (%R14,%R8,8),%R10 |
(112) 0x41b9f8 LEA (%R9,%RAX,1),%R8 |
(112) 0x41b9fc LEA (%R12,%R8,8),%R9 |
(112) 0x41ba00 MOV 0xe0(%RSP),%R8 |
(112) 0x41ba08 ADD %R8,%RAX |
(112) 0x41ba0b LEA (%R12,%RAX,8),%R8 |
(112) 0x41ba0f MOV %EDX,%EAX |
(112) 0x41ba11 SHR $0x3,%EAX |
(112) 0x41ba14 MOV %RAX,0x78(%RSP) |
(112) 0x41ba19 SAL $0x6,%RAX |
(112) 0x41ba1d MOV %RAX,0xa0(%RSP) |
(112) 0x41ba25 XOR %EAX,%EAX |
(112) 0x41ba27 TESTB $0x1,0x78(%RSP) |
(112) 0x41ba2c JE 41ba99 |
(112) 0x41ba2e VMOVUPD (%R13),%ZMM0 |
(112) 0x41ba35 VMOVUPD (%R11),%ZMM6 |
(112) 0x41ba3b MOV 0x80(%RSP),%RAX |
(112) 0x41ba43 CMPQ $0x40,0xa0(%RSP) |
(112) 0x41ba4c VMULPD (%RSI),%ZMM0,%ZMM1 |
(112) 0x41ba52 VSUBPD (%R10),%ZMM6,%ZMM3 |
(112) 0x41ba58 VADDPD (%R9),%ZMM0,%ZMM5 |
(112) 0x41ba5e VSUBPD (%R8),%ZMM5,%ZMM7 |
(112) 0x41ba64 VSUBPD (%RAX),%ZMM1,%ZMM2 |
(112) 0x41ba6a VFMADD132PD (%RCX),%ZMM3,%ZMM1 |
(112) 0x41ba70 MOV $0x40,%EAX |
(112) 0x41ba75 VADDPD (%RBX),%ZMM2,%ZMM4 |
(112) 0x41ba7b VDIVPD %ZMM7,%ZMM4,%ZMM8 |
(112) 0x41ba81 VDIVPD %ZMM4,%ZMM1,%ZMM9 |
(112) 0x41ba87 VMOVUPD %ZMM8,(%RSI) |
(112) 0x41ba8d VMOVUPD %ZMM9,(%RCX) |
(112) 0x41ba93 JE 41bb7b |
(112) 0x41ba99 MOV %R15D,0x78(%RSP) |
(112) 0x41ba9e MOV 0x80(%RSP),%R15 |
(113) 0x41baa6 VMOVUPD (%R13,%RAX,1),%ZMM10 |
(113) 0x41baae VMOVUPD (%R11,%RAX,1),%ZMM14 |
(113) 0x41bab5 VMULPD (%RSI,%RAX,1),%ZMM10,%ZMM11 |
(113) 0x41babc VSUBPD (%R10,%RAX,1),%ZMM14,%ZMM15 |
(113) 0x41bac3 VADDPD (%R9,%RAX,1),%ZMM10,%ZMM0 |
(113) 0x41baca VSUBPD (%R8,%RAX,1),%ZMM0,%ZMM1 |
(113) 0x41bad1 VSUBPD (%R15,%RAX,1),%ZMM11,%ZMM12 |
(113) 0x41bad8 VFMADD132PD (%RCX,%RAX,1),%ZMM15,%ZMM11 |
(113) 0x41badf VADDPD (%RBX,%RAX,1),%ZMM12,%ZMM13 |
(113) 0x41bae6 VDIVPD %ZMM13,%ZMM11,%ZMM4 |
(113) 0x41baec VDIVPD %ZMM1,%ZMM13,%ZMM2 |
(113) 0x41baf2 VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(113) 0x41baf9 VMOVUPD %ZMM4,(%RCX,%RAX,1) |
(113) 0x41bb00 VMOVUPD 0x40(%R13,%RAX,1),%ZMM6 |
(113) 0x41bb08 VMOVUPD 0x40(%R11,%RAX,1),%ZMM5 |
(113) 0x41bb10 VMULPD 0x40(%RSI,%RAX,1),%ZMM6,%ZMM7 |
(113) 0x41bb18 VSUBPD 0x40(%R10,%RAX,1),%ZMM5,%ZMM9 |
(113) 0x41bb20 VADDPD 0x40(%R9,%RAX,1),%ZMM6,%ZMM10 |
(113) 0x41bb28 VSUBPD 0x40(%R8,%RAX,1),%ZMM10,%ZMM11 |
(113) 0x41bb30 VSUBPD 0x40(%R15,%RAX,1),%ZMM7,%ZMM3 |
(113) 0x41bb38 VFMADD132PD 0x40(%RCX,%RAX,1),%ZMM9,%ZMM7 |
(113) 0x41bb40 VADDPD 0x40(%RBX,%RAX,1),%ZMM3,%ZMM8 |
(113) 0x41bb48 VDIVPD %ZMM11,%ZMM8,%ZMM12 |
(113) 0x41bb4e VDIVPD %ZMM8,%ZMM7,%ZMM13 |
(113) 0x41bb54 VMOVUPD %ZMM12,0x40(%RSI,%RAX,1) |
(113) 0x41bb5c VMOVUPD %ZMM13,0x40(%RCX,%RAX,1) |
(113) 0x41bb64 SUB $-0x80,%RAX |
(113) 0x41bb68 CMP %RAX,0xa0(%RSP) |
(113) 0x41bb70 JNE 41baa6 |
(112) 0x41bb76 MOV 0x78(%RSP),%R15D |
(112) 0x41bb7b MOV 0xd4(%RSP),%ESI |
(112) 0x41bb82 MOV %EDX,%ECX |
(112) 0x41bb84 AND $-0x8,%ECX |
(112) 0x41bb87 ADD %ECX,%R15D |
(112) 0x41bb8a LEA (%RCX,%RSI,1),%ESI |
(112) 0x41bb8d TEST $0x7,%DL |
(112) 0x41bb90 JE 41beef |
(112) 0x41bb96 SUB %ECX,%EDX |
(112) 0x41bb98 LEA -0x1(%RDX),%R13D |
(112) 0x41bb9c CMP $0x2,%R13D |
(112) 0x41bba0 JBE 41bca6 |
(112) 0x41bba6 MOVSXD 0xd4(%RSP),%RAX |
(112) 0x41bbae MOV 0x88(%RSP),%RBX |
(112) 0x41bbb6 MOV 0xb0(%RSP),%R10 |
(112) 0x41bbbe MOV 0xb8(%RSP),%R9 |
(112) 0x41bbc6 LEA (%RBX,%RAX,1),%R11 |
(112) 0x41bbca MOV 0xf0(%RSP),%R13 |
(112) 0x41bbd2 ADD %RCX,%R11 |
(112) 0x41bbd5 LEA (%R9,%RAX,1),%R8 |
(112) 0x41bbd9 MOV 0xd8(%RSP),%R9 |
(112) 0x41bbe1 LEA (%R10,%R11,8),%RBX |
(112) 0x41bbe5 MOV 0xe0(%RSP),%R10 |
(112) 0x41bbed ADD %RCX,%R8 |
(112) 0x41bbf0 LEA (%R13,%R8,8),%R11 |
(112) 0x41bbf5 MOV 0xe8(%RSP),%R13 |
(112) 0x41bbfd ADD %RAX,%R9 |
(112) 0x41bc00 LEA (%R10,%RAX,1),%R8 |
(112) 0x41bc04 MOV 0x90(%RSP),%R10 |
(112) 0x41bc0c ADD %RCX,%R9 |
(112) 0x41bc0f ADD %RCX,%R8 |
(112) 0x41bc12 ADD %RAX,%R10 |
(112) 0x41bc15 ADD %RCX,%R10 |
(112) 0x41bc18 VMOVUPD (%R13,%R10,8),%YMM14 |
(112) 0x41bc1f MOV 0xa8(%RSP),%R10 |
(112) 0x41bc27 MOV 0x98(%RSP),%R13 |
(112) 0x41bc2f VMULPD (%RBX),%YMM14,%YMM15 |
(112) 0x41bc33 ADD %RAX,%R10 |
(112) 0x41bc36 VADDPD (%R12,%R9,8),%YMM14,%YMM6 |
(112) 0x41bc3c ADD %RCX,%R10 |
(112) 0x41bc3f ADD %RAX,%R13 |
(112) 0x41bc42 ADD %RCX,%R13 |
(112) 0x41bc45 VSUBPD (%R12,%R8,8),%YMM6,%YMM7 |
(112) 0x41bc4b VSUBPD (%RDI,%R10,8),%YMM15,%YMM0 |
(112) 0x41bc51 MOV 0xc0(%RSP),%R10 |
(112) 0x41bc59 ADD %RAX,%R10 |
(112) 0x41bc5c VADDPD (%RDI,%R13,8),%YMM0,%YMM1 |
(112) 0x41bc62 MOV 0xf8(%RSP),%R13 |
(112) 0x41bc6a ADD %RCX,%R10 |
(112) 0x41bc6d VMOVUPD (%R14,%R10,8),%YMM2 |
(112) 0x41bc73 ADD %R13,%RAX |
(112) 0x41bc76 VDIVPD %YMM7,%YMM1,%YMM3 |
(112) 0x41bc7a ADD %RCX,%RAX |
(112) 0x41bc7d VSUBPD (%R14,%RAX,8),%YMM2,%YMM4 |
(112) 0x41bc83 VFMADD132PD (%R11),%YMM4,%YMM15 |
(112) 0x41bc88 VDIVPD %YMM1,%YMM15,%YMM8 |
(112) 0x41bc8c VMOVUPD %YMM3,(%RBX) |
(112) 0x41bc90 VMOVUPD %YMM8,(%R11) |
(112) 0x41bc95 TEST $0x3,%DL |
(112) 0x41bc98 JE 41beef |
(112) 0x41bc9e AND $-0x4,%EDX |
(112) 0x41bca1 ADD %EDX,%R15D |
(112) 0x41bca4 ADD %EDX,%ESI |
(112) 0x41bca6 MOV 0x90(%RSP),%R11 |
(112) 0x41bcae MOVSXD %ESI,%RAX |
(112) 0x41bcb1 MOV 0xe8(%RSP),%R9 |
(112) 0x41bcb9 MOV 0x88(%RSP),%RBX |
(112) 0x41bcc1 MOV 0xb0(%RSP),%RCX |
(112) 0x41bcc9 LEA (%R11,%RAX,1),%R8 |
(112) 0x41bccd MOV 0xa8(%RSP),%R10 |
(112) 0x41bcd5 VMOVSD (%R9,%R8,8),%XMM5 |
(112) 0x41bcdb LEA (%RBX,%RAX,1),%RDX |
(112) 0x41bcdf MOV 0xb8(%RSP),%R9 |
(112) 0x41bce7 LEA (%RCX,%RDX,8),%RCX |
(112) 0x41bceb LEA (%R10,%RAX,1),%R13 |
(112) 0x41bcef MOV 0xf0(%RSP),%R8 |
(112) 0x41bcf7 VMULSD (%RCX),%XMM5,%XMM9 |
(112) 0x41bcfb ADD %RAX,%R9 |
(112) 0x41bcfe VSUBSD (%RDI,%R13,8),%XMM9,%XMM10 |
(112) 0x41bd04 MOV 0x98(%RSP),%R13 |
(112) 0x41bd0c LEA (%R13,%RAX,1),%RDX |
(112) 0x41bd11 VADDSD (%RDI,%RDX,8),%XMM10,%XMM11 |
(112) 0x41bd16 LEA (%R8,%R9,8),%RDX |
(112) 0x41bd1a MOV 0xc0(%RSP),%R9 |
(112) 0x41bd22 MOV 0xf8(%RSP),%R8 |
(112) 0x41bd2a ADD %RAX,%R9 |
(112) 0x41bd2d VMOVSD (%R14,%R9,8),%XMM12 |
(112) 0x41bd33 MOV 0xd8(%RSP),%R9 |
(112) 0x41bd3b ADD %RAX,%R8 |
(112) 0x41bd3e VSUBSD (%R14,%R8,8),%XMM12,%XMM13 |
(112) 0x41bd44 LEA (%R9,%RAX,1),%R8 |
(112) 0x41bd48 MOV 0xe0(%RSP),%R9 |
(112) 0x41bd50 VADDSD (%R12,%R8,8),%XMM5,%XMM14 |
(112) 0x41bd56 ADD %R9,%RAX |
(112) 0x41bd59 VFMADD132SD (%RDX),%XMM13,%XMM9 |
(112) 0x41bd5e VSUBSD (%R12,%RAX,8),%XMM14,%XMM15 |
(112) 0x41bd64 LEA 0x1(%RSI),%EAX |
(112) 0x41bd67 VDIVSD %XMM15,%XMM11,%XMM0 |
(112) 0x41bd6c VDIVSD %XMM11,%XMM9,%XMM1 |
(112) 0x41bd71 VMOVSD %XMM0,(%RCX) |
(112) 0x41bd75 MOV 0xd0(%RSP),%ECX |
(112) 0x41bd7c VMOVSD %XMM1,(%RDX) |
(112) 0x41bd80 LEA 0x1(%R15),%EDX |
(112) 0x41bd84 CMP %ECX,%EDX |
(112) 0x41bd86 JAE 41beef |
(112) 0x41bd8c CLTQ |
(112) 0x41bd8e MOV 0xb0(%RSP),%R9 |
(112) 0x41bd96 ADD $0x2,%ESI |
(112) 0x41bd99 LEA (%RBX,%RAX,1),%R8 |
(112) 0x41bd9d LEA (%R11,%RAX,1),%RDX |
(112) 0x41bda1 LEA (%R9,%R8,8),%RCX |
(112) 0x41bda5 MOV 0xe8(%RSP),%R8 |
(112) 0x41bdad LEA (%R10,%RAX,1),%R9 |
(112) 0x41bdb1 VMOVSD (%R8,%RDX,8),%XMM4 |
(112) 0x41bdb7 MOV 0xf0(%RSP),%R8 |
(112) 0x41bdbf LEA (%R13,%RAX,1),%RDX |
(112) 0x41bdc4 VMULSD (%RCX),%XMM4,%XMM6 |
(112) 0x41bdc8 VSUBSD (%RDI,%R9,8),%XMM6,%XMM2 |
(112) 0x41bdce MOV 0xb8(%RSP),%R9 |
(112) 0x41bdd6 ADD %RAX,%R9 |
(112) 0x41bdd9 VADDSD (%RDI,%RDX,8),%XMM2,%XMM7 |
(112) 0x41bdde LEA (%R8,%R9,8),%RDX |
(112) 0x41bde2 MOV 0xc0(%RSP),%R9 |
(112) 0x41bdea MOV 0xf8(%RSP),%R8 |
(112) 0x41bdf2 ADD %RAX,%R9 |
(112) 0x41bdf5 VMOVSD (%R14,%R9,8),%XMM3 |
(112) 0x41bdfb ADD %RAX,%R8 |
(112) 0x41bdfe MOV 0xd8(%RSP),%R9 |
(112) 0x41be06 VSUBSD (%R14,%R8,8),%XMM3,%XMM8 |
(112) 0x41be0c LEA (%R9,%RAX,1),%R8 |
(112) 0x41be10 VADDSD (%R12,%R8,8),%XMM4,%XMM5 |
(112) 0x41be16 MOV 0xe0(%RSP),%R8 |
(112) 0x41be1e VFMADD132SD (%RDX),%XMM8,%XMM6 |
(112) 0x41be23 ADD %R8,%RAX |
(112) 0x41be26 VSUBSD (%R12,%RAX,8),%XMM5,%XMM9 |
(112) 0x41be2c LEA 0x2(%R15),%EAX |
(112) 0x41be30 MOV 0xd0(%RSP),%R15D |
(112) 0x41be38 VDIVSD %XMM9,%XMM7,%XMM10 |
(112) 0x41be3d VDIVSD %XMM7,%XMM6,%XMM11 |
(112) 0x41be41 VMOVSD %XMM10,(%RCX) |
(112) 0x41be45 VMOVSD %XMM11,(%RDX) |
(112) 0x41be49 CMP %R15D,%EAX |
(112) 0x41be4c JAE 41beef |
(112) 0x41be52 MOVSXD %ESI,%RSI |
(112) 0x41be55 MOV 0xe8(%RSP),%RDX |
(112) 0x41be5d MOV %RBX,%RCX |
(112) 0x41be60 MOV 0xb0(%RSP),%RBX |
(112) 0x41be68 ADD %RSI,%R11 |
(112) 0x41be6b ADD %RSI,%RCX |
(112) 0x41be6e ADD %RSI,%R10 |
(112) 0x41be71 ADD %RSI,%R13 |
(112) 0x41be74 VMOVSD (%RDX,%R11,8),%XMM12 |
(112) 0x41be7a LEA (%RBX,%RCX,8),%RAX |
(112) 0x41be7e MOV 0xc0(%RSP),%RCX |
(112) 0x41be86 ADD %RSI,%R9 |
(112) 0x41be89 MOV 0xf8(%RSP),%R11 |
(112) 0x41be91 MOV 0xf0(%RSP),%R15 |
(112) 0x41be99 ADD %RSI,%R8 |
(112) 0x41be9c VMULSD (%RAX),%XMM12,%XMM13 |
(112) 0x41bea0 ADD %RSI,%RCX |
(112) 0x41bea3 VADDSD (%R12,%R9,8),%XMM12,%XMM4 |
(112) 0x41bea9 VMOVSD (%R14,%RCX,8),%XMM0 |
(112) 0x41beaf ADD %RSI,%R11 |
(112) 0x41beb2 VSUBSD (%R14,%R11,8),%XMM0,%XMM1 |
(112) 0x41beb8 VSUBSD (%R12,%R8,8),%XMM4,%XMM6 |
(112) 0x41bebe VSUBSD (%RDI,%R10,8),%XMM13,%XMM14 |
(112) 0x41bec4 VADDSD (%RDI,%R13,8),%XMM14,%XMM15 |
(112) 0x41beca MOV 0xb8(%RSP),%RDI |
(112) 0x41bed2 ADD %RSI,%RDI |
(112) 0x41bed5 LEA (%R15,%RDI,8),%RBX |
(112) 0x41bed9 VDIVSD %XMM6,%XMM15,%XMM2 |
(112) 0x41bedd VFMADD132SD (%RBX),%XMM1,%XMM13 |
(112) 0x41bee2 VDIVSD %XMM15,%XMM13,%XMM7 |
(112) 0x41bee7 VMOVSD %XMM2,(%RAX) |
(112) 0x41beeb VMOVSD %XMM7,(%RBX) |
(112) 0x41beef MOV 0xd0(%RSP),%R15D |
(112) 0x41bef7 INCQ 0xc8(%RSP) |
(112) 0x41beff MOV 0xc8(%RSP),%R14 |
(112) 0x41bf07 ADD $0,%R14D |
(112) 0x41bf0b CMP %R14D,0x70(%RSP) |
(112) 0x41bf10 JLE 41bf30 |
(112) 0x41bf12 MOV 0x68(%RSP),%ECX |
(112) 0x41bf16 MOV 0x6c(%RSP),%R12D |
(112) 0x41bf1b MOV 0x74(%RSP),%EAX |
(112) 0x41bf1f MOV %R12D,0xd4(%RSP) |
(112) 0x41bf27 SUB %R15D,%ECX |
(112) 0x41bf2a JMP 41b888 |
0x41bf2f NOP |
0x41bf30 VZEROUPPER |
0x41bf33 LEA -0x28(%RBP),%RSP |
0x41bf37 POP %RBX |
0x41bf38 POP %R12 |
0x41bf3a POP %R13 |
0x41bf3c POP %R14 |
0x41bf3e POP %R15 |
0x41bf40 POP %RBP |
0x41bf41 RET |
0x41bf42 NOPW (%RAX,%RAX,1) |
(112) 0x41bf48 MOV 0xd4(%RSP),%ESI |
(112) 0x41bf4f XOR %ECX,%ECX |
(112) 0x41bf51 JMP 41bb96 |
0x41bf56 INC %ECX |
0x41bf58 XOR %EDX,%EDX |
0x41bf5a JMP 41b805 |
0x41bf5f NOP |
Path / |
Source file and lines | advec_cell.cpp:208-216 |
Module | exec |
nb instructions | 86 |
nb uops | 96 |
loop length | 299 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 16.00 cycles |
front end | 16.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.23-15.34 |
Stall cycles | 0.00 |
Front-end | 16.00 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 16.00 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41bf33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RSI),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41bf33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41bf56 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7d6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41bf33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x20(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10D,0xd4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41b805 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:208-216 |
Module | exec |
nb instructions | 86 |
nb uops | 96 |
loop length | 299 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 16.00 cycles |
front end | 16.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.23-15.34 |
Stall cycles | 0.00 |
Front-end | 16.00 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 16.00 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41bf33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RSI),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41bf33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41bf56 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7d6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41bf33 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x20(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10D,0xd4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41b805 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 2.73 | 0.87 |
▼Loop 112 - advec_cell.cpp:211-216 - exec– | 0.01 | 0 |
○Loop 113 - advec_cell.cpp:211-216 - exec | 2.73 | 0.87 |