Loop Id: 119 | Module: exec | Source: advec_mom.cpp:65-66 | Coverage: 2.04% |
---|
Loop Id: 119 | Module: exec | Source: advec_mom.cpp:65-66 | Coverage: 2.04% |
---|
0x41d035 VMOVUPD (%R11,%RAX,1),%ZMM5 [1] |
0x41d03c VMOVUPD %ZMM5,(%R10,%RAX,1) [4] |
0x41d043 VADDPD (%R9,%RAX,1),%ZMM5,%ZMM6 [2] |
0x41d04a VSUBPD (%R8,%RAX,1),%ZMM6,%ZMM7 [5] |
0x41d051 VMOVUPD %ZMM7,(%RSI,%RAX,1) [3] |
0x41d058 VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 [1] |
0x41d060 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) [4] |
0x41d068 VADDPD 0x40(%R9,%RAX,1),%ZMM8,%ZMM9 [2] |
0x41d070 VSUBPD 0x40(%R8,%RAX,1),%ZMM9,%ZMM10 [5] |
0x41d078 VMOVUPD %ZMM10,0x40(%RSI,%RAX,1) [3] |
0x41d080 VMOVUPD 0x80(%R11,%RAX,1),%ZMM11 [1] |
0x41d088 VMOVUPD %ZMM11,0x80(%R10,%RAX,1) [4] |
0x41d090 VADDPD 0x80(%R9,%RAX,1),%ZMM11,%ZMM12 [2] |
0x41d098 VSUBPD 0x80(%R8,%RAX,1),%ZMM12,%ZMM13 [5] |
0x41d0a0 VMOVUPD %ZMM13,0x80(%RSI,%RAX,1) [3] |
0x41d0a8 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM14 [1] |
0x41d0b0 VMOVUPD %ZMM14,0xc0(%R10,%RAX,1) [4] |
0x41d0b8 VADDPD 0xc0(%R9,%RAX,1),%ZMM14,%ZMM15 [2] |
0x41d0c0 VSUBPD 0xc0(%R8,%RAX,1),%ZMM15,%ZMM0 [5] |
0x41d0c8 VMOVUPD %ZMM0,0xc0(%RSI,%RAX,1) [3] |
0x41d0d0 VMOVUPD 0x100(%R11,%RAX,1),%ZMM1 [1] |
0x41d0d8 VMOVUPD %ZMM1,0x100(%R10,%RAX,1) [4] |
0x41d0e0 VADDPD 0x100(%R9,%RAX,1),%ZMM1,%ZMM2 [2] |
0x41d0e8 VSUBPD 0x100(%R8,%RAX,1),%ZMM2,%ZMM3 [5] |
0x41d0f0 VMOVUPD %ZMM3,0x100(%RSI,%RAX,1) [3] |
0x41d0f8 VMOVUPD 0x140(%R11,%RAX,1),%ZMM4 [1] |
0x41d100 VMOVUPD %ZMM4,0x140(%R10,%RAX,1) [4] |
0x41d108 VADDPD 0x140(%R9,%RAX,1),%ZMM4,%ZMM5 [2] |
0x41d110 VSUBPD 0x140(%R8,%RAX,1),%ZMM5,%ZMM6 [5] |
0x41d118 VMOVUPD %ZMM6,0x140(%RSI,%RAX,1) [3] |
0x41d120 VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 [1] |
0x41d128 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) [4] |
0x41d130 VADDPD 0x180(%R9,%RAX,1),%ZMM7,%ZMM8 [2] |
0x41d138 VSUBPD 0x180(%R8,%RAX,1),%ZMM8,%ZMM9 [5] |
0x41d140 VMOVUPD %ZMM9,0x180(%RSI,%RAX,1) [3] |
0x41d148 VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM10 [1] |
0x41d150 VMOVUPD %ZMM10,0x1c0(%R10,%RAX,1) [4] |
0x41d158 VADDPD 0x1c0(%R9,%RAX,1),%ZMM10,%ZMM11 [2] |
0x41d160 VSUBPD 0x1c0(%R8,%RAX,1),%ZMM11,%ZMM12 [5] |
0x41d168 VMOVUPD %ZMM12,0x1c0(%RSI,%RAX,1) [3] |
0x41d170 ADD $0x200,%RAX |
0x41d176 CMP %R13,%RAX |
0x41d179 JNE 41d035 |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 65 - 66 |
-------------------------------------------------------------------------------- |
65: post_vol(i, j) = volume(i, j); |
66: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel(int, int, int, int, clover::Buffer2D |
Source | advec_mom.cpp:65-66 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.67 |
CQA cycles if no scalar integer | 9.67 |
CQA cycles if FP arith vectorized | 9.67 |
CQA cycles if fully vectorized | 9.67 |
Front-end cycles | 9.67 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 8.00 |
P1 cycles | 8.00 |
P2 cycles | 8.00 |
P3 cycles | 8.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.40 |
P10 cycles | 8.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 9.86 |
Stall cycles (UFS) | 0.00 |
Nb insns | 43.00 |
Nb uops | 42.00 |
Nb loads | 24.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 13.24 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 264.83 |
Bytes prefetched | 0.00 |
Bytes loaded | 1536.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel(int, int, int, int, clover::Buffer2D |
Source | advec_mom.cpp:65-66 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.67 |
CQA cycles if no scalar integer | 9.67 |
CQA cycles if FP arith vectorized | 9.67 |
CQA cycles if fully vectorized | 9.67 |
Front-end cycles | 9.67 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 8.00 |
P1 cycles | 8.00 |
P2 cycles | 8.00 |
P3 cycles | 8.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.40 |
P10 cycles | 8.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 9.86 |
Stall cycles (UFS) | 0.00 |
Nb insns | 43.00 |
Nb uops | 42.00 |
Nb loads | 24.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 13.24 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 264.83 |
Bytes prefetched | 0.00 |
Bytes loaded | 1536.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
nb instructions | 43 |
nb uops | 42 |
loop length | 330 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 0.60 | 8.00 | 8.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.00 |
cycles | 8.00 | 8.00 | 8.00 | 8.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 9.86 |
Stall cycles | 0.00 |
Front-end | 9.67 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 9.67 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R11,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM5,(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD (%R9,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD (%R8,%RAX,1),%ZMM6,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM7,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM8,0x40(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x40(%R9,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x40(%R8,%RAX,1),%ZMM9,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM10,0x40(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R11,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM11,0x80(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x80(%R9,%RAX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x80(%R8,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM13,0x80(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R11,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM14,0xc0(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0xc0(%R9,%RAX,1),%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0xc0(%R8,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM0,0xc0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x100(%R11,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM1,0x100(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x100(%R9,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x100(%R8,%RAX,1),%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM3,0x100(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x140(%R11,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM4,0x140(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x140(%R9,%RAX,1),%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x140(%R8,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM6,0x140(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM7,0x180(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x180(%R9,%RAX,1),%ZMM7,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x180(%R8,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM9,0x180(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM10,0x1c0(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x1c0(%R9,%RAX,1),%ZMM10,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x1c0(%R8,%RAX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM12,0x1c0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x200,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41d035 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x305> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
nb instructions | 43 |
nb uops | 42 |
loop length | 330 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 0 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 0.60 | 8.00 | 8.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.00 |
cycles | 8.00 | 8.00 | 8.00 | 8.00 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 9.86 |
Stall cycles | 0.00 |
Front-end | 9.67 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 9.67 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R11,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM5,(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD (%R9,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD (%R8,%RAX,1),%ZMM6,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM7,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM8,0x40(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x40(%R9,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x40(%R8,%RAX,1),%ZMM9,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM10,0x40(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R11,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM11,0x80(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x80(%R9,%RAX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x80(%R8,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM13,0x80(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R11,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM14,0xc0(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0xc0(%R9,%RAX,1),%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0xc0(%R8,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM0,0xc0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x100(%R11,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM1,0x100(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x100(%R9,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x100(%R8,%RAX,1),%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM3,0x100(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x140(%R11,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM4,0x140(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x140(%R9,%RAX,1),%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x140(%R8,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM6,0x140(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM7,0x180(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x180(%R9,%RAX,1),%ZMM7,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x180(%R8,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM9,0x180(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM10,0x1c0(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VADDPD 0x1c0(%R9,%RAX,1),%ZMM10,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD 0x1c0(%R8,%RAX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM12,0x1c0(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x200,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41d035 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x305> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |