Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 1.6% |
---|
Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 1.6% |
---|
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density1(i, j) = density0(i, j); |
38: energy1(i, j) = energy0(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42fc00 PUSH %RBP |
0x42fc01 MOV %RSP,%RBP |
0x42fc04 PUSH %R15 |
0x42fc06 PUSH %R14 |
0x42fc08 PUSH %R13 |
0x42fc0a PUSH %R12 |
0x42fc0c PUSH %RBX |
0x42fc0d AND $-0x40,%RSP |
0x42fc11 ADD $-0x80,%RSP |
0x42fc15 MOV 0x28(%RDI),%EAX |
0x42fc18 MOV 0x2c(%RDI),%EDX |
0x42fc1b MOV 0x20(%RDI),%EBX |
0x42fc1e MOV 0x24(%RDI),%ECX |
0x42fc21 ADD $0x2,%EDX |
0x42fc24 LEA 0x1(%RAX),%R15D |
0x42fc28 LEA 0x1(%RBX),%ESI |
0x42fc2b MOV %EDX,0x50(%RSP) |
0x42fc2f MOV %ESI,0x4c(%RSP) |
0x42fc33 CMP %EDX,%R15D |
0x42fc36 JGE 43012b |
0x42fc3c MOV %EDX,%EBX |
0x42fc3e LEA 0x2(%RCX),%R14D |
0x42fc42 SUB %R15D,%EBX |
0x42fc45 CMP %R14D,%ESI |
0x42fc48 JGE 43012b |
0x42fc4e MOV %RDI,%R13 |
0x42fc51 MOV %R14D,%EDI |
0x42fc54 SUB %ESI,%EDI |
0x42fc56 MOV %EDI,0x54(%RSP) |
0x42fc5a CALL 4046c0 <omp_get_num_threads@plt> |
0x42fc5f MOV %EAX,%R12D |
0x42fc62 CALL 4045b0 <omp_get_thread_num@plt> |
0x42fc67 XOR %EDX,%EDX |
0x42fc69 MOV %EAX,%R8D |
0x42fc6c MOV 0x54(%RSP),%EAX |
0x42fc70 IMUL %EBX,%EAX |
0x42fc73 DIV %R12D |
0x42fc76 MOV %EAX,%R12D |
0x42fc79 CMP %EDX,%R8D |
0x42fc7c JB 43014c |
0x42fc82 IMUL %R12D,%R8D |
0x42fc86 LEA (%R8,%RDX,1),%R9D |
0x42fc8a LEA (%R12,%R9,1),%R10D |
0x42fc8e MOV %R10D,0x48(%RSP) |
0x42fc93 CMP %R10D,%R9D |
0x42fc96 JAE 43012b |
0x42fc9c MOV %R9D,%EAX |
0x42fc9f XOR %EDX,%EDX |
0x42fca1 MOV 0x4c(%RSP),%R11D |
0x42fca6 MOV 0x8(%R13),%RSI |
0x42fcaa DIVL 0x54(%RSP) |
0x42fcae MOV 0x18(%R13),%RBX |
0x42fcb2 MOV %RSI,0x38(%RSP) |
0x42fcb7 MOV %RBX,0x28(%RSP) |
0x42fcbc ADD %EDX,%R11D |
0x42fcbf ADD %R15D,%EAX |
0x42fcc2 MOV %R14D,%EDX |
0x42fcc5 MOV (%R13),%R15 |
0x42fcc9 MOV 0x10(%R13),%R14 |
0x42fccd MOV %R11D,0x7c(%RSP) |
0x42fcd2 SUB %R11D,%EDX |
0x42fcd5 MOVSXD %EAX,%RBX |
0x42fcd8 MOV %R15,0x40(%RSP) |
0x42fcdd MOV %R14,0x30(%RSP) |
0x42fce2 NOPW (%RAX,%RAX,1) |
(203) 0x42fce8 CMP %EDX,%R12D |
(203) 0x42fceb CMOVBE %R12D,%EDX |
(203) 0x42fcef LEA (%R9,%RDX,1),%ECX |
(203) 0x42fcf3 MOV %ECX,0x78(%RSP) |
(203) 0x42fcf7 CMP %ECX,%R9D |
(203) 0x42fcfa JAE 4300fd |
(203) 0x42fd00 MOV 0x30(%RSP),%R12 |
(203) 0x42fd05 MOV 0x38(%RSP),%RDI |
(203) 0x42fd0a LEA -0x1(%RDX),%EAX |
(203) 0x42fd0d MOV 0x28(%RSP),%RCX |
(203) 0x42fd12 MOV 0x40(%RSP),%R13 |
(203) 0x42fd17 MOV (%R12),%RSI |
(203) 0x42fd1b MOV (%RDI),%R8 |
(203) 0x42fd1e MOV (%RCX),%R10 |
(203) 0x42fd21 MOV (%R13),%R11 |
(203) 0x42fd25 IMUL %RBX,%R8 |
(203) 0x42fd29 MOV 0x10(%R13),%R15 |
(203) 0x42fd2d MOV 0x10(%RDI),%R14 |
(203) 0x42fd31 IMUL %RBX,%RSI |
(203) 0x42fd35 MOV 0x10(%R12),%R13 |
(203) 0x42fd3a MOV 0x10(%RCX),%R12 |
(203) 0x42fd3e IMUL %RBX,%R10 |
(203) 0x42fd42 IMUL %RBX,%R11 |
(203) 0x42fd46 MOV %R8,0x60(%RSP) |
(203) 0x42fd4b MOV %RSI,0x68(%RSP) |
(203) 0x42fd50 MOV %R10,0x70(%RSP) |
(203) 0x42fd55 CMP $0x6,%EAX |
(203) 0x42fd58 JBE 430140 |
(203) 0x42fd5e MOVSXD 0x7c(%RSP),%RAX |
(203) 0x42fd63 LEA (%R8,%RAX,1),%RCX |
(203) 0x42fd67 LEA (%R11,%RAX,1),%RDI |
(203) 0x42fd6b LEA (%R14,%RCX,8),%R8 |
(203) 0x42fd6f MOV 0x70(%RSP),%RCX |
(203) 0x42fd74 LEA (%RSI,%RAX,1),%RSI |
(203) 0x42fd78 LEA (%R15,%RDI,8),%R10 |
(203) 0x42fd7c LEA (%R13,%RSI,8),%RDI |
(203) 0x42fd81 ADD %RCX,%RAX |
(203) 0x42fd84 MOV %EDX,%ECX |
(203) 0x42fd86 SHR $0x3,%ECX |
(203) 0x42fd89 LEA (%R12,%RAX,8),%RSI |
(203) 0x42fd8d XOR %EAX,%EAX |
(203) 0x42fd8f SAL $0x6,%RCX |
(203) 0x42fd93 MOV %RCX,0x58(%RSP) |
(203) 0x42fd98 SUB $0x40,%RCX |
(203) 0x42fd9c SHR $0x6,%RCX |
(203) 0x42fda0 INC %RCX |
(203) 0x42fda3 AND $0x7,%ECX |
(203) 0x42fda6 JE 42fec4 |
(203) 0x42fdac CMP $0x1,%RCX |
(203) 0x42fdb0 JE 42fe99 |
(203) 0x42fdb6 CMP $0x2,%RCX |
(203) 0x42fdba JE 42fe79 |
(203) 0x42fdc0 CMP $0x3,%RCX |
(203) 0x42fdc4 JE 42fe59 |
(203) 0x42fdca CMP $0x4,%RCX |
(203) 0x42fdce JE 42fe39 |
(203) 0x42fdd0 CMP $0x5,%RCX |
(203) 0x42fdd4 JE 42fe19 |
(203) 0x42fdd6 CMP $0x6,%RCX |
(203) 0x42fdda JE 42fdf9 |
(203) 0x42fddc VMOVUPD (%R10),%ZMM3 |
(203) 0x42fde2 MOV $0x40,%EAX |
(203) 0x42fde7 VMOVUPD %ZMM3,(%R8) |
(203) 0x42fded VMOVUPD (%RDI),%ZMM4 |
(203) 0x42fdf3 VMOVUPD %ZMM4,(%RSI) |
(203) 0x42fdf9 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(203) 0x42fe00 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(203) 0x42fe07 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(203) 0x42fe0e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(203) 0x42fe15 ADD $0x40,%RAX |
(203) 0x42fe19 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(203) 0x42fe20 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(203) 0x42fe27 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(203) 0x42fe2e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(203) 0x42fe35 ADD $0x40,%RAX |
(203) 0x42fe39 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(203) 0x42fe40 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(203) 0x42fe47 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(203) 0x42fe4e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(203) 0x42fe55 ADD $0x40,%RAX |
(203) 0x42fe59 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(203) 0x42fe60 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(203) 0x42fe67 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(203) 0x42fe6e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(203) 0x42fe75 ADD $0x40,%RAX |
(203) 0x42fe79 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(203) 0x42fe80 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(203) 0x42fe87 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(203) 0x42fe8e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(203) 0x42fe95 ADD $0x40,%RAX |
(203) 0x42fe99 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(203) 0x42fea0 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(203) 0x42fea7 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(203) 0x42feae VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(203) 0x42feb5 ADD $0x40,%RAX |
(203) 0x42feb9 CMP %RAX,0x58(%RSP) |
(203) 0x42febe JE 42ffd1 |
(204) 0x42fec4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(204) 0x42fecb VMOVUPD %ZMM14,(%R8,%RAX,1) |
(204) 0x42fed2 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(204) 0x42fed9 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(204) 0x42fee0 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(204) 0x42fee8 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(204) 0x42fef0 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(204) 0x42fef8 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(204) 0x42ff00 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(204) 0x42ff08 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(204) 0x42ff10 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(204) 0x42ff18 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(204) 0x42ff20 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(204) 0x42ff28 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(204) 0x42ff30 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(204) 0x42ff38 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(204) 0x42ff40 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(204) 0x42ff48 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(204) 0x42ff50 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(204) 0x42ff58 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(204) 0x42ff60 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(204) 0x42ff68 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(204) 0x42ff70 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(204) 0x42ff78 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(204) 0x42ff80 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(204) 0x42ff88 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(204) 0x42ff90 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(204) 0x42ff98 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(204) 0x42ffa0 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(204) 0x42ffa8 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(204) 0x42ffb0 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(204) 0x42ffb8 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(204) 0x42ffc0 ADD $0x200,%RAX |
(204) 0x42ffc6 CMP %RAX,0x58(%RSP) |
(204) 0x42ffcb JNE 42fec4 |
(203) 0x42ffd1 MOV 0x7c(%RSP),%R10D |
(203) 0x42ffd6 MOV %EDX,%R8D |
(203) 0x42ffd9 AND $-0x8,%R8D |
(203) 0x42ffdd ADD %R8D,%R9D |
(203) 0x42ffe0 LEA (%R8,%R10,1),%ESI |
(203) 0x42ffe4 TEST $0x7,%DL |
(203) 0x42ffe7 JE 4300f8 |
(203) 0x42ffed SUB %R8D,%EDX |
(203) 0x42fff0 LEA -0x1(%RDX),%EDI |
(203) 0x42fff3 CMP $0x2,%EDI |
(203) 0x42fff6 JBE 43004f |
(203) 0x42fff8 MOVSXD 0x7c(%RSP),%RCX |
(203) 0x42fffd MOV 0x60(%RSP),%R10 |
(203) 0x430002 MOV 0x68(%RSP),%RDI |
(203) 0x430007 LEA (%R11,%RCX,1),%RAX |
(203) 0x43000b ADD %RCX,%R10 |
(203) 0x43000e ADD %R8,%RAX |
(203) 0x430011 ADD %RCX,%RDI |
(203) 0x430014 ADD %R8,%R10 |
(203) 0x430017 VMOVUPD (%R15,%RAX,8),%YMM14 |
(203) 0x43001d MOV 0x70(%RSP),%RAX |
(203) 0x430022 ADD %R8,%RDI |
(203) 0x430025 VMOVUPD %YMM14,(%R14,%R10,8) |
(203) 0x43002b ADD %RAX,%RCX |
(203) 0x43002e VMOVUPD (%R13,%RDI,8),%YMM15 |
(203) 0x430035 ADD %R8,%RCX |
(203) 0x430038 VMOVUPD %YMM15,(%R12,%RCX,8) |
(203) 0x43003e TEST $0x3,%DL |
(203) 0x430041 JE 4300f8 |
(203) 0x430047 AND $-0x4,%EDX |
(203) 0x43004a ADD %EDX,%R9D |
(203) 0x43004d ADD %EDX,%ESI |
(203) 0x43004f MOVSXD %ESI,%R10 |
(203) 0x430052 MOV 0x60(%RSP),%RCX |
(203) 0x430057 MOV 0x68(%RSP),%RDI |
(203) 0x43005c LEA (%R11,%R10,1),%RDX |
(203) 0x430060 VMOVSD (%R15,%RDX,8),%XMM3 |
(203) 0x430066 LEA (%RCX,%R10,1),%R8 |
(203) 0x43006a LEA (%RDI,%R10,1),%RAX |
(203) 0x43006e LEA 0x1(%R9),%EDX |
(203) 0x430072 VMOVSD %XMM3,(%R14,%R8,8) |
(203) 0x430078 MOV 0x70(%RSP),%R8 |
(203) 0x43007d VMOVSD (%R13,%RAX,8),%XMM4 |
(203) 0x430084 LEA 0x1(%RSI),%EAX |
(203) 0x430087 ADD %R8,%R10 |
(203) 0x43008a VMOVSD %XMM4,(%R12,%R10,8) |
(203) 0x430090 MOV 0x78(%RSP),%R10D |
(203) 0x430095 CMP %R10D,%EDX |
(203) 0x430098 JAE 4300f8 |
(203) 0x43009a CLTQ |
(203) 0x43009c ADD $0x2,%R9D |
(203) 0x4300a0 ADD $0x2,%ESI |
(203) 0x4300a3 LEA (%R11,%RAX,1),%RDX |
(203) 0x4300a7 VMOVSD (%R15,%RDX,8),%XMM1 |
(203) 0x4300ad LEA (%RCX,%RAX,1),%RDX |
(203) 0x4300b1 VMOVSD %XMM1,(%R14,%RDX,8) |
(203) 0x4300b7 LEA (%RDI,%RAX,1),%RDX |
(203) 0x4300bb ADD %R8,%RAX |
(203) 0x4300be VMOVSD (%R13,%RDX,8),%XMM2 |
(203) 0x4300c5 VMOVSD %XMM2,(%R12,%RAX,8) |
(203) 0x4300cb CMP %R10D,%R9D |
(203) 0x4300ce JAE 4300f8 |
(203) 0x4300d0 MOVSXD %ESI,%R9 |
(203) 0x4300d3 ADD %R9,%R11 |
(203) 0x4300d6 ADD %R9,%RCX |
(203) 0x4300d9 ADD %R9,%RDI |
(203) 0x4300dc ADD %R9,%R8 |
(203) 0x4300df VMOVSD (%R15,%R11,8),%XMM0 |
(203) 0x4300e5 VMOVSD %XMM0,(%R14,%RCX,8) |
(203) 0x4300eb VMOVSD (%R13,%RDI,8),%XMM5 |
(203) 0x4300f2 VMOVSD %XMM5,(%R12,%R8,8) |
(203) 0x4300f8 MOV 0x78(%RSP),%R9D |
(203) 0x4300fd INC %RBX |
(203) 0x430100 LEA (%RBX),%R15D |
(203) 0x430103 CMP %R15D,0x50(%RSP) |
(203) 0x430108 JLE 430128 |
(203) 0x43010a MOV 0x48(%RSP),%R12D |
(203) 0x43010f MOV 0x4c(%RSP),%R11D |
(203) 0x430114 MOV 0x54(%RSP),%EDX |
(203) 0x430118 MOV %R11D,0x7c(%RSP) |
(203) 0x43011d SUB %R9D,%R12D |
(203) 0x430120 JMP 42fce8 |
0x430125 NOPL (%RAX) |
0x430128 VZEROUPPER |
0x43012b LEA -0x28(%RBP),%RSP |
0x43012f POP %RBX |
0x430130 POP %R12 |
0x430132 POP %R13 |
0x430134 POP %R14 |
0x430136 POP %R15 |
0x430138 POP %RBP |
0x430139 RET |
0x43013a NOPW (%RAX,%RAX,1) |
(203) 0x430140 MOV 0x7c(%RSP),%ESI |
(203) 0x430144 XOR %R8D,%R8D |
(203) 0x430147 JMP 42ffed |
0x43014c INC %R12D |
0x43014f XOR %EDX,%EDX |
0x430151 JMP 42fc82 |
0x430156 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43012b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43012b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43014c <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43012b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42fc82 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43012b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43012b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43014c <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43012b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42fc82 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼revert_kernel(int, int, int, int, clover::Buffer2D | 1.6 | 0.51 |
▼Loop 203 - revert.cpp:37-38 - exec– | 0 | 0.01 |
○Loop 204 - revert.cpp:37-38 - exec | 1.6 | 0.51 |