Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ... | Module: exec | Source: PdV.cpp:48-63 [...] | Coverage: 4.77% |
---|
Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ... | Module: exec | Source: PdV.cpp:48-63 [...] | Coverage: 4.77% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 48 - 63 |
-------------------------------------------------------------------------------- |
48: #pragma omp parallel for simd collapse(2) |
49: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
50: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
51: double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5; |
52: double right_flux = |
53: (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt * |
54: 0.5; |
55: double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5; |
56: double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) * |
57: 0.25 * dt * 0.5; |
58: double total_flux = right_flux - left_flux + top_flux - bottom_flux; |
59: double volume_change_s = volume(i, j) / (volume(i, j) + total_flux); |
60: double recip_volume = 1.0 / volume(i, j); |
61: double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume; |
62: energy1(i, j) = energy0(i, j) - energy_change; |
63: density1(i, j) = density0(i, j) * volume_change_s; |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x430160 PUSH %RBP |
0x430161 MOV %RSP,%RBP |
0x430164 PUSH %R15 |
0x430166 PUSH %R14 |
0x430168 PUSH %R13 |
0x43016a PUSH %R12 |
0x43016c PUSH %RBX |
0x43016d MOV %RDI,%RBX |
0x430170 AND $-0x40,%RSP |
0x430174 SUB $0x1c0,%RSP |
0x43017b MOV 0x68(%RDI),%EAX |
0x43017e MOV 0x6c(%RDI),%EDX |
0x430181 MOV 0x60(%RDI),%EDI |
0x430184 MOV 0x64(%RBX),%ECX |
0x430187 ADD $0x2,%EDX |
0x43018a LEA 0x1(%RAX),%R15D |
0x43018e LEA 0x1(%RDI),%ESI |
0x430191 MOV %EDX,0x80(%RSP) |
0x430198 MOV %ESI,0x7c(%RSP) |
0x43019c CMP %EDX,%R15D |
0x43019f JGE 430c8b |
0x4301a5 MOV %EDX,%R13D |
0x4301a8 LEA 0x2(%RCX),%R14D |
0x4301ac SUB %R15D,%R13D |
0x4301af CMP %R14D,%ESI |
0x4301b2 JGE 430c8b |
0x4301b8 MOV %R14D,%R8D |
0x4301bb SUB %ESI,%R8D |
0x4301be MOV %R8D,0x84(%RSP) |
0x4301c6 CALL 4046c0 <omp_get_num_threads@plt> |
0x4301cb MOV %EAX,%R12D |
0x4301ce CALL 4045b0 <omp_get_thread_num@plt> |
0x4301d3 XOR %EDX,%EDX |
0x4301d5 MOV %EAX,%R9D |
0x4301d8 MOV 0x84(%RSP),%EAX |
0x4301df IMUL %R13D,%EAX |
0x4301e3 DIV %R12D |
0x4301e6 MOV %EAX,%ECX |
0x4301e8 CMP %EDX,%R9D |
0x4301eb JB 430cb7 |
0x4301f1 IMUL %ECX,%R9D |
0x4301f5 LEA (%R9,%RDX,1),%EAX |
0x4301f9 LEA (%RCX,%RAX,1),%R10D |
0x4301fd MOV %EAX,0x1b8(%RSP) |
0x430204 MOV %R10D,0x78(%RSP) |
0x430209 CMP %R10D,%EAX |
0x43020c JAE 430c8b |
0x430212 XOR %EDX,%EDX |
0x430214 MOV 0x7c(%RSP),%R11D |
0x430219 VMOVSD 0x1c8ef(%RIP),%XMM2 |
0x430221 DIVL 0x84(%RSP) |
0x430228 MOV 0x8(%RBX),%RSI |
0x43022c MOV 0x10(%RBX),%R13 |
0x430230 MOV 0x58(%RBX),%R8 |
0x430234 MOV 0x18(%RBX),%R12 |
0x430238 MOV 0x40(%RBX),%R9 |
0x43023c MOV 0x20(%RBX),%R10 |
0x430240 MOV %RSI,0x70(%RSP) |
0x430245 VMOVSD 0x1c8cb(%RIP),%XMM3 |
0x43024d MOV %R13,0x60(%RSP) |
0x430252 MOV %R8,0x58(%RSP) |
0x430257 MOV %R12,0x50(%RSP) |
0x43025c MOV %R9,0x48(%RSP) |
0x430261 MOV %R10,0x40(%RSP) |
0x430266 VMULSD (%RBX),%XMM2,%XMM2 |
0x43026a VBROADCASTSD %XMM3,%YMM6 |
0x43026f VBROADCASTSD %XMM3,%ZMM4 |
0x430275 VBROADCASTSD %XMM2,%YMM1 |
0x43027a VBROADCASTSD %XMM2,%ZMM5 |
0x430280 LEA (%RDX,%R11,1),%EDI |
0x430284 LEA (%RAX,%R15,1),%R15D |
0x430288 MOV %R14D,%EAX |
0x43028b MOV 0x48(%RBX),%RDX |
0x43028f MOV 0x50(%RBX),%R14 |
0x430293 MOV 0x30(%RBX),%R11 |
0x430297 MOV %EDI,0x148(%RSP) |
0x43029e SUB %EDI,%EAX |
0x4302a0 MOV 0x38(%RBX),%RDI |
0x4302a4 MOV 0x28(%RBX),%RBX |
0x4302a8 MOVSXD %R15D,%R15 |
0x4302ab MOV %RDX,0x38(%RSP) |
0x4302b0 MOV %R14,0x68(%RSP) |
0x4302b5 MOV %R11,0x30(%RSP) |
0x4302ba MOV %RDI,0x28(%RSP) |
0x4302bf MOV %RBX,0x20(%RSP) |
0x4302c4 MOV %R15,0x140(%RSP) |
0x4302cc NOPL (%RAX) |
(205) 0x4302d0 CMP %EAX,%ECX |
(205) 0x4302d2 CMOVBE %ECX,%EAX |
(205) 0x4302d5 MOV 0x1b8(%RSP),%ECX |
(205) 0x4302dc MOV %EAX,0x14c(%RSP) |
(205) 0x4302e3 ADD %ECX,%EAX |
(205) 0x4302e5 MOV %EAX,0x1bc(%RSP) |
(205) 0x4302ec CMP %EAX,%ECX |
(205) 0x4302ee JAE 430c3e |
(205) 0x4302f4 MOV 0x68(%RSP),%R14 |
(205) 0x4302f9 MOV 0x140(%RSP),%RDI |
(205) 0x430301 MOV 0x70(%RSP),%RAX |
(205) 0x430306 MOV 0x58(%RSP),%R11 |
(205) 0x43030b MOV (%R14),%R8 |
(205) 0x43030e MOV %RDI,%RCX |
(205) 0x430311 MOV 0x60(%RSP),%R9 |
(205) 0x430316 MOV %RDI,%RBX |
(205) 0x430319 MOV 0x10(%RAX),%R13 |
(205) 0x43031d MOV (%RAX),%RSI |
(205) 0x430320 IMUL %R8,%RCX |
(205) 0x430324 MOV (%R11),%RAX |
(205) 0x430327 MOV 0x10(%R11),%R15 |
(205) 0x43032b MOV %RDI,%R11 |
(205) 0x43032e MOV (%R9),%RDX |
(205) 0x430331 MOV 0x10(%R9),%R10 |
(205) 0x430335 IMUL %RDI,%RSI |
(205) 0x430339 MOV %R13,0x90(%RSP) |
(205) 0x430341 IMUL %RAX,%R11 |
(205) 0x430345 MOV %R15,0x1b0(%RSP) |
(205) 0x43034d MOV 0x48(%RSP),%R15 |
(205) 0x430352 ADD %RCX,%R8 |
(205) 0x430355 IMUL %RDX,%RBX |
(205) 0x430359 MOV 0x10(%R14),%R12 |
(205) 0x43035d MOV %R10,0xc0(%RSP) |
(205) 0x430365 MOV %R8,0xb8(%RSP) |
(205) 0x43036d MOV 0x50(%RSP),%R8 |
(205) 0x430372 LEA (%RAX,%R11,1),%R14 |
(205) 0x430376 MOV %RDI,%RAX |
(205) 0x430379 MOV 0x10(%R15),%R10 |
(205) 0x43037d MOV %RSI,0x88(%RSP) |
(205) 0x430385 IMUL (%R8),%RDI |
(205) 0x430389 MOV 0x10(%R8),%R9 |
(205) 0x43038d ADD %RBX,%RDX |
(205) 0x430390 MOV %R14,0xd0(%RSP) |
(205) 0x430398 MOV %R10,0xe8(%RSP) |
(205) 0x4303a0 MOV %R9,0xd8(%RSP) |
(205) 0x4303a8 MOV %R12,0x1a8(%RSP) |
(205) 0x4303b0 MOV %RCX,0x98(%RSP) |
(205) 0x4303b8 MOV %RBX,0xa0(%RSP) |
(205) 0x4303c0 MOV %R11,0xa8(%RSP) |
(205) 0x4303c8 MOV %RDX,0xc8(%RSP) |
(205) 0x4303d0 MOV %RDI,0xb0(%RSP) |
(205) 0x4303d8 MOV (%R15),%RDX |
(205) 0x4303db MOV 0x40(%RSP),%R9 |
(205) 0x4303e0 MOV 0x38(%RSP),%R15 |
(205) 0x4303e5 IMUL %RAX,%RDX |
(205) 0x4303e9 MOV (%R9),%R8 |
(205) 0x4303ec MOV 0x10(%R9),%R14 |
(205) 0x4303f0 MOV 0x10(%R15),%R10 |
(205) 0x4303f4 IMUL %RAX,%R8 |
(205) 0x4303f8 MOV %R14,0xf8(%RSP) |
(205) 0x430400 MOV 0x30(%RSP),%R14 |
(205) 0x430405 MOV %RDX,0xe0(%RSP) |
(205) 0x43040d MOV (%R15),%RDX |
(205) 0x430410 MOV 0x28(%RSP),%R15 |
(205) 0x430415 MOV 0x10(%R14),%R9 |
(205) 0x430419 MOV %R10,0x138(%RSP) |
(205) 0x430421 MOV %R8,0xf0(%RSP) |
(205) 0x430429 MOV (%R14),%R8 |
(205) 0x43042c IMUL %RAX,%RDX |
(205) 0x430430 MOV 0x10(%R15),%R10 |
(205) 0x430434 MOV (%R15),%R14 |
(205) 0x430437 MOV %R9,0x128(%RSP) |
(205) 0x43043f IMUL %RAX,%R8 |
(205) 0x430443 MOV 0x20(%RSP),%R15 |
(205) 0x430448 IMUL %RAX,%R14 |
(205) 0x43044c MOV %R10,0x118(%RSP) |
(205) 0x430454 MOV 0x10(%R15),%R9 |
(205) 0x430458 MOV %RDX,0x100(%RSP) |
(205) 0x430460 MOV %R8,0x130(%RSP) |
(205) 0x430468 MOV (%R15),%R8 |
(205) 0x43046b MOV %R14,0x120(%RSP) |
(205) 0x430473 IMUL %RAX,%R8 |
(205) 0x430477 MOV 0x14c(%RSP),%EAX |
(205) 0x43047e MOV %R9,0x108(%RSP) |
(205) 0x430486 LEA -0x1(%RAX),%R10D |
(205) 0x43048a MOV %R8,0x110(%RSP) |
(205) 0x430492 CMP $0x6,%R10D |
(205) 0x430496 JBE 430ca0 |
(205) 0x43049c MOVSXD 0x148(%RSP),%RAX |
(205) 0x4304a4 MOV 0xb8(%RSP),%R9 |
(205) 0x4304ac MOV %R12,%R8 |
(205) 0x4304af LEA (%R9,%RAX,1),%R10 |
(205) 0x4304b3 ADD %RAX,%RSI |
(205) 0x4304b6 LEA (%R11,%RAX,1),%R9 |
(205) 0x4304ba ADD %RAX,%RCX |
(205) 0x4304bd SAL $0x3,%RSI |
(205) 0x4304c1 SAL $0x3,%R10 |
(205) 0x4304c5 LEA (%R12,%R10,1),%RDX |
(205) 0x4304c9 SAL $0x3,%RCX |
(205) 0x4304cd LEA (%R13,%RSI,1),%R15 |
(205) 0x4304d2 SAL $0x3,%R9 |
(205) 0x4304d6 LEA 0x8(%R13,%RSI,1),%R13 |
(205) 0x4304db LEA 0x8(%R8,%R10,1),%RSI |
(205) 0x4304e0 MOV 0xc0(%RSP),%R10 |
(205) 0x4304e8 MOV %RDX,0x160(%RSP) |
(205) 0x4304f0 LEA (%R12,%RCX,1),%R14 |
(205) 0x4304f4 MOV %RSI,0x198(%RSP) |
(205) 0x4304fc LEA 0x8(%R12,%RCX,1),%R12 |
(205) 0x430501 MOV 0x1b0(%RSP),%RSI |
(205) 0x430509 LEA (%RBX,%RAX,1),%RCX |
(205) 0x43050d MOV 0xc8(%RSP),%RDX |
(205) 0x430515 LEA (%R10,%RCX,8),%RBX |
(205) 0x430519 MOV 0xd0(%RSP),%RCX |
(205) 0x430521 LEA (%RSI,%R9,1),%R11 |
(205) 0x430525 MOV %R11,0x1a0(%RSP) |
(205) 0x43052d LEA 0x8(%RSI,%R9,1),%R11 |
(205) 0x430532 LEA (%RDX,%RAX,1),%R8 |
(205) 0x430536 LEA (%RCX,%RAX,1),%R9 |
(205) 0x43053a MOV 0xe0(%RSP),%RCX |
(205) 0x430542 LEA (%R10,%R8,8),%R10 |
(205) 0x430546 SAL $0x3,%R9 |
(205) 0x43054a LEA (%RSI,%R9,1),%RDX |
(205) 0x43054e LEA 0x8(%RSI,%R9,1),%R9 |
(205) 0x430553 ADD %RAX,%RCX |
(205) 0x430556 LEA (%RDI,%RAX,1),%RSI |
(205) 0x43055a MOV %RDX,0x190(%RSP) |
(205) 0x430562 MOV 0xd8(%RSP),%RDI |
(205) 0x43056a MOV 0xe8(%RSP),%RDX |
(205) 0x430572 LEA (%RDI,%RSI,8),%R8 |
(205) 0x430576 MOV 0xf0(%RSP),%RDI |
(205) 0x43057e LEA (%RDX,%RCX,8),%RSI |
(205) 0x430582 MOV 0xf8(%RSP),%RDX |
(205) 0x43058a MOV %RSI,0x188(%RSP) |
(205) 0x430592 MOV 0x100(%RSP),%RSI |
(205) 0x43059a LEA (%RDI,%RAX,1),%RCX |
(205) 0x43059e LEA (%RDX,%RCX,8),%RDX |
(205) 0x4305a2 MOV 0x138(%RSP),%RDI |
(205) 0x4305aa LEA (%RSI,%RAX,1),%RCX |
(205) 0x4305ae MOV 0x130(%RSP),%RSI |
(205) 0x4305b6 LEA (%RDI,%RCX,8),%RDI |
(205) 0x4305ba LEA (%RSI,%RAX,1),%RCX |
(205) 0x4305be MOV 0x128(%RSP),%RSI |
(205) 0x4305c6 LEA (%RSI,%RCX,8),%RCX |
(205) 0x4305ca MOV 0x120(%RSP),%RSI |
(205) 0x4305d2 MOV %RCX,0x180(%RSP) |
(205) 0x4305da LEA (%RSI,%RAX,1),%RCX |
(205) 0x4305de MOV 0x118(%RSP),%RSI |
(205) 0x4305e6 LEA (%RSI,%RCX,8),%RCX |
(205) 0x4305ea MOV 0x110(%RSP),%RSI |
(205) 0x4305f2 MOV %RCX,0x158(%RSP) |
(205) 0x4305fa MOV 0x108(%RSP),%RCX |
(205) 0x430602 ADD %RSI,%RAX |
(205) 0x430605 LEA (%RCX,%RAX,8),%RSI |
(205) 0x430609 MOV 0x14c(%RSP),%ECX |
(205) 0x430610 XOR %EAX,%EAX |
(205) 0x430612 SHR $0x3,%ECX |
(205) 0x430615 SAL $0x6,%RCX |
(205) 0x430619 MOV %RCX,0x150(%RSP) |
(205) 0x430621 NOPL (%RAX) |
(207) 0x430628 MOV 0x160(%RSP),%RCX |
(207) 0x430630 VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(207) 0x430637 VMOVUPD (%R13,%RAX,1),%ZMM12 |
(207) 0x43063f VMOVUPD (%RCX,%RAX,1),%ZMM7 |
(207) 0x430646 MOV 0x1a0(%RSP),%RCX |
(207) 0x43064e VADDPD %ZMM9,%ZMM9,%ZMM11 |
(207) 0x430654 VMOVUPD (%R10,%RAX,1),%ZMM9 |
(207) 0x43065b VMOVUPD (%RCX,%RAX,1),%ZMM0 |
(207) 0x430662 MOV 0x198(%RSP),%RCX |
(207) 0x43066a VADDPD (%R14,%RAX,1),%ZMM7,%ZMM10 |
(207) 0x430671 VADDPD %ZMM12,%ZMM12,%ZMM7 |
(207) 0x430677 VMOVUPD (%RCX,%RAX,1),%ZMM13 |
(207) 0x43067e MOV 0x190(%RSP),%RCX |
(207) 0x430686 VADDPD (%R11,%RAX,1),%ZMM0,%ZMM8 |
(207) 0x43068d VMOVUPD (%RCX,%RAX,1),%ZMM0 |
(207) 0x430694 VADDPD (%R12,%RAX,1),%ZMM13,%ZMM15 |
(207) 0x43069b VMOVUPD (%R15,%RAX,1),%ZMM13 |
(207) 0x4306a2 MOV 0x188(%RSP),%RCX |
(207) 0x4306aa VMULPD %ZMM11,%ZMM8,%ZMM14 |
(207) 0x4306b0 VADDPD (%R9,%RAX,1),%ZMM0,%ZMM8 |
(207) 0x4306b7 VADDPD %ZMM9,%ZMM9,%ZMM11 |
(207) 0x4306bd VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(207) 0x4306c4 MOV 0x180(%RSP),%RCX |
(207) 0x4306cc VMULPD %ZMM11,%ZMM8,%ZMM12 |
(207) 0x4306d2 VADDPD (%RDI,%RAX,1),%ZMM9,%ZMM11 |
(207) 0x4306d9 VMOVUPD (%R8,%RAX,1),%ZMM8 |
(207) 0x4306e0 VFMADD132PD %ZMM15,%ZMM12,%ZMM7 |
(207) 0x4306e6 VADDPD %ZMM13,%ZMM13,%ZMM15 |
(207) 0x4306ec VDIVPD (%RDX,%RAX,1),%ZMM11,%ZMM12 |
(207) 0x4306f3 VDIVPD %ZMM8,%ZMM4,%ZMM13 |
(207) 0x4306f9 VFMADD231PD %ZMM10,%ZMM15,%ZMM14 |
(207) 0x4306ff VMULPD %ZMM13,%ZMM12,%ZMM15 |
(207) 0x430705 VSUBPD %ZMM14,%ZMM7,%ZMM10 |
(207) 0x43070b VMULPD %ZMM5,%ZMM10,%ZMM0 |
(207) 0x430711 VADDPD %ZMM8,%ZMM0,%ZMM14 |
(207) 0x430717 VFNMADD213PD (%RCX,%RAX,1),%ZMM15,%ZMM0 |
(207) 0x43071e MOV 0x158(%RSP),%RCX |
(207) 0x430726 VDIVPD %ZMM14,%ZMM8,%ZMM7 |
(207) 0x43072c VMOVUPD %ZMM0,(%RCX,%RAX,1) |
(207) 0x430733 MOV 0x150(%RSP),%RCX |
(207) 0x43073b VMULPD (%RDX,%RAX,1),%ZMM7,%ZMM10 |
(207) 0x430742 VMOVUPD %ZMM10,(%RSI,%RAX,1) |
(207) 0x430749 ADD $0x40,%RAX |
(207) 0x43074d CMP %RCX,%RAX |
(207) 0x430750 JNE 430628 |
(205) 0x430756 MOV 0x14c(%RSP),%R15D |
(205) 0x43075e MOV 0x148(%RSP),%R14D |
(205) 0x430766 MOV %R15D,%EDX |
(205) 0x430769 AND $-0x8,%EDX |
(205) 0x43076c LEA (%RDX,%R14,1),%R13D |
(205) 0x430770 ADD %EDX,0x1b8(%RSP) |
(205) 0x430777 MOV %R13D,0x190(%RSP) |
(205) 0x43077f TEST $0x7,%R15B |
(205) 0x430783 JE 430c2e |
(205) 0x430789 MOV 0x14c(%RSP),%R12D |
(205) 0x430791 SUB %EDX,%R12D |
(205) 0x430794 MOV %R12D,0x188(%RSP) |
(205) 0x43079c DEC %R12D |
(205) 0x43079f CMP $0x2,%R12D |
(205) 0x4307a3 JBE 4309fa |
(205) 0x4307a9 MOVSXD 0x148(%RSP),%RAX |
(205) 0x4307b1 MOV 0xb8(%RSP),%R11 |
(205) 0x4307b9 MOV 0xa8(%RSP),%R10 |
(205) 0x4307c1 MOV 0xb0(%RSP),%R15 |
(205) 0x4307c9 LEA (%R11,%RAX,1),%R8 |
(205) 0x4307cd MOV 0xf0(%RSP),%R11 |
(205) 0x4307d5 MOV 0xe0(%RSP),%R14 |
(205) 0x4307dd LEA (%R10,%RAX,1),%R9 |
(205) 0x4307e1 LEA (%R15,%RAX,1),%R13 |
(205) 0x4307e5 MOV 0xf8(%RSP),%R15 |
(205) 0x4307ed MOV 0x88(%RSP),%RBX |
(205) 0x4307f5 LEA (%R11,%RAX,1),%R10 |
(205) 0x4307f9 LEA (%R14,%RAX,1),%R12 |
(205) 0x4307fd MOV 0x100(%RSP),%R14 |
(205) 0x430805 MOV 0x98(%RSP),%RDI |
(205) 0x43080d ADD %RDX,%R10 |
(205) 0x430810 LEA (%RBX,%RAX,1),%RCX |
(205) 0x430814 LEA (%R12,%RDX,1),%RBX |
(205) 0x430818 ADD %RDX,%R8 |
(205) 0x43081b LEA (%R15,%R10,8),%R15 |
(205) 0x43081f MOV 0x110(%RSP),%R10 |
(205) 0x430827 LEA (%R14,%RAX,1),%R12 |
(205) 0x43082b ADD %RAX,%RDI |
(205) 0x43082e ADD %RDX,%RDI |
(205) 0x430831 ADD %RDX,%R9 |
(205) 0x430834 MOV %RBX,0x1a0(%RSP) |
(205) 0x43083c MOV 0xd0(%RSP),%RSI |
(205) 0x430844 LEA (%R10,%RAX,1),%R14 |
(205) 0x430848 MOV 0x130(%RSP),%RBX |
(205) 0x430850 MOV 0x120(%RSP),%R11 |
(205) 0x430858 ADD %RDX,%RCX |
(205) 0x43085b LEA (%R14,%RDX,1),%R10 |
(205) 0x43085f MOV 0x1a8(%RSP),%R14 |
(205) 0x430867 LEA (%RSI,%RAX,1),%RSI |
(205) 0x43086b ADD %RDX,%R13 |
(205) 0x43086e MOV %R10,0x198(%RSP) |
(205) 0x430876 MOV 0xa0(%RSP),%R10 |
(205) 0x43087e LEA (%RBX,%RAX,1),%RBX |
(205) 0x430882 ADD %RAX,%R11 |
(205) 0x430885 VMOVUPD (%R14,%R8,8),%YMM0 |
(205) 0x43088b ADD %RDX,%RSI |
(205) 0x43088e ADD %RDX,%R12 |
(205) 0x430891 ADD %RDX,%RBX |
(205) 0x430894 ADD %RDX,%R11 |
(205) 0x430897 VADDPD (%R14,%RDI,8),%YMM0,%YMM14 |
(205) 0x43089d LEA (%R10,%RAX,1),%R14 |
(205) 0x4308a1 MOV 0xc0(%RSP),%R10 |
(205) 0x4308a9 ADD %RDX,%R14 |
(205) 0x4308ac VMOVUPD (%R10,%R14,8),%YMM8 |
(205) 0x4308b2 MOV 0x1b0(%RSP),%R14 |
(205) 0x4308ba VMOVUPD (%R14,%R9,8),%YMM7 |
(205) 0x4308c0 VADDPD %YMM8,%YMM8,%YMM9 |
(205) 0x4308c5 VADDPD 0x8(%R14,%R9,8),%YMM7,%YMM11 |
(205) 0x4308cc MOV 0x1a8(%RSP),%R14 |
(205) 0x4308d4 MOV 0x90(%RSP),%R9 |
(205) 0x4308dc VMOVUPD 0x8(%R14,%R8,8),%YMM15 |
(205) 0x4308e3 VMOVUPD 0x8(%R9,%RCX,8),%YMM13 |
(205) 0x4308ea VMULPD %YMM11,%YMM9,%YMM12 |
(205) 0x4308ef VADDPD 0x8(%R14,%RDI,8),%YMM15,%YMM10 |
(205) 0x4308f6 MOV 0xc8(%RSP),%RDI |
(205) 0x4308fe VADDPD %YMM13,%YMM13,%YMM0 |
(205) 0x430903 ADD %RDI,%RAX |
(205) 0x430906 ADD %RDX,%RAX |
(205) 0x430909 VMOVUPD (%R10,%RAX,8),%YMM8 |
(205) 0x43090f MOV 0x1b0(%RSP),%RDX |
(205) 0x430917 VMOVUPD (%R9,%RCX,8),%YMM15 |
(205) 0x43091d MOV 0xd8(%RSP),%RAX |
(205) 0x430925 VMOVUPD (%RDX,%RSI,8),%YMM7 |
(205) 0x43092a VADDPD %YMM8,%YMM8,%YMM9 |
(205) 0x43092f MOV 0x138(%RSP),%RCX |
(205) 0x430937 MOV 0xe8(%RSP),%R8 |
(205) 0x43093f VADDPD 0x8(%RDX,%RSI,8),%YMM7,%YMM11 |
(205) 0x430945 MOV 0x1a0(%RSP),%RSI |
(205) 0x43094d VMOVAPD %YMM7,0x160(%RSP) |
(205) 0x430956 VMULPD %YMM11,%YMM9,%YMM13 |
(205) 0x43095b VMOVUPD (%RCX,%R12,8),%YMM9 |
(205) 0x430961 MOV 0x118(%RSP),%R12 |
(205) 0x430969 VADDPD (%R8,%RSI,8),%YMM9,%YMM7 |
(205) 0x43096f VFMADD132PD %YMM10,%YMM13,%YMM0 |
(205) 0x430974 VADDPD %YMM15,%YMM15,%YMM10 |
(205) 0x430979 VDIVPD (%R15),%YMM7,%YMM13 |
(205) 0x43097e VFMADD132PD %YMM14,%YMM12,%YMM10 |
(205) 0x430983 VSUBPD %YMM10,%YMM0,%YMM14 |
(205) 0x430988 VMOVUPD (%RAX,%R13,8),%YMM0 |
(205) 0x43098e MOV 0x128(%RSP),%R13 |
(205) 0x430996 VDIVPD %YMM0,%YMM6,%YMM15 |
(205) 0x43099a VMULPD %YMM1,%YMM14,%YMM12 |
(205) 0x43099e VADDPD %YMM0,%YMM12,%YMM8 |
(205) 0x4309a2 VDIVPD %YMM8,%YMM0,%YMM11 |
(205) 0x4309a7 VMULPD %YMM15,%YMM13,%YMM10 |
(205) 0x4309ac VFNMADD213PD (%R13,%RBX,8),%YMM10,%YMM12 |
(205) 0x4309b3 MOV 0x198(%RSP),%RBX |
(205) 0x4309bb VMOVUPD %YMM12,(%R12,%R11,8) |
(205) 0x4309c1 MOV 0x188(%RSP),%R11D |
(205) 0x4309c9 VMULPD (%R15),%YMM11,%YMM14 |
(205) 0x4309ce MOV 0x108(%RSP),%R15 |
(205) 0x4309d6 VMOVUPD %YMM14,(%R15,%RBX,8) |
(205) 0x4309dc TEST $0x3,%R11B |
(205) 0x4309e0 JE 430c2e |
(205) 0x4309e6 AND $-0x4,%R11D |
(205) 0x4309ea ADD %R11D,0x1b8(%RSP) |
(205) 0x4309f2 ADD %R11D,0x190(%RSP) |
(205) 0x4309fa MOV 0x1a8(%RSP),%RDX |
(205) 0x430a02 MOVSXD 0x190(%RSP),%R9 |
(205) 0x430a0a MOV 0x90(%RSP),%R14 |
(205) 0x430a12 MOV 0x88(%RSP),%RDI |
(205) 0x430a1a MOV 0x98(%RSP),%RAX |
(205) 0x430a22 MOV 0xb8(%RSP),%RCX |
(205) 0x430a2a MOV %R9,0x198(%RSP) |
(205) 0x430a32 MOV %R9,%R10 |
(205) 0x430a35 MOV 0x1b0(%RSP),%R12 |
(205) 0x430a3d MOV 0xc0(%RSP),%R13 |
(205) 0x430a45 LEA (%R14,%RDI,8),%R9 |
(205) 0x430a49 MOV 0xa0(%RSP),%RSI |
(205) 0x430a51 MOV 0xa8(%RSP),%RBX |
(205) 0x430a59 LEA (%RDX,%RAX,8),%R8 |
(205) 0x430a5d LEA (%RDX,%RCX,8),%RDI |
(205) 0x430a61 MOV 0xc8(%RSP),%R11 |
(205) 0x430a69 MOV 0xd0(%RSP),%RDX |
(205) 0x430a71 MOV 0xd8(%RSP),%RAX |
(205) 0x430a79 LEA (%R13,%RSI,8),%R15 |
(205) 0x430a7e LEA (%R12,%RBX,8),%RSI |
(205) 0x430a82 MOV 0xe0(%RSP),%RBX |
(205) 0x430a8a LEA (%R13,%R11,8),%R14 |
(205) 0x430a8f LEA (%R12,%RDX,8),%RCX |
(205) 0x430a93 MOV 0xb0(%RSP),%R13 |
(205) 0x430a9b MOV 0xe8(%RSP),%R12 |
(205) 0x430aa3 MOV 0xf8(%RSP),%R11 |
(205) 0x430aab MOV 0xf0(%RSP),%RDX |
(205) 0x430ab3 LEA (%RAX,%R13,8),%R13 |
(205) 0x430ab7 LEA (%R12,%RBX,8),%R12 |
(205) 0x430abb MOV 0x138(%RSP),%RAX |
(205) 0x430ac3 MOV 0x100(%RSP),%RBX |
(205) 0x430acb LEA (%R11,%RDX,8),%RDX |
(205) 0x430acf LEA (%RAX,%RBX,8),%R11 |
(205) 0x430ad3 MOV 0x128(%RSP),%RAX |
(205) 0x430adb MOV 0x130(%RSP),%RBX |
(205) 0x430ae3 MOV %R11,0x1b0(%RSP) |
(205) 0x430aeb LEA (%RAX,%RBX,8),%R11 |
(205) 0x430aef MOV 0x118(%RSP),%RAX |
(205) 0x430af7 MOV 0x120(%RSP),%RBX |
(205) 0x430aff MOV %R11,0x1a8(%RSP) |
(205) 0x430b07 LEA (%RAX,%RBX,8),%R11 |
(205) 0x430b0b MOV 0x108(%RSP),%RAX |
(205) 0x430b13 MOV 0x110(%RSP),%RBX |
(205) 0x430b1b LEA (%RAX,%RBX,8),%RBX |
(205) 0x430b1f MOV 0x1b8(%RSP),%EAX |
(205) 0x430b26 SUB %R10D,%EAX |
(205) 0x430b29 MOV %EAX,0x1a0(%RSP) |
(205) 0x430b30 MOV 0x198(%RSP),%RAX |
(205) 0x430b38 MOV %R11,0x198(%RSP) |
(206) 0x430b40 VMOVSD (%RSI,%RAX,8),%XMM0 |
(206) 0x430b45 VMOVSD (%R15,%RAX,8),%XMM9 |
(206) 0x430b4b VMOVSD 0x8(%R9,%RAX,8),%XMM15 |
(206) 0x430b52 VMOVSD (%R8,%RAX,8),%XMM12 |
(206) 0x430b58 VADDSD 0x8(%RSI,%RAX,8),%XMM0,%XMM8 |
(206) 0x430b5e VADDSD %XMM9,%XMM9,%XMM7 |
(206) 0x430b63 VMOVSD (%RCX,%RAX,8),%XMM0 |
(206) 0x430b68 VMOVSD (%R14,%RAX,8),%XMM9 |
(206) 0x430b6e VMOVSD 0x8(%R8,%RAX,8),%XMM14 |
(206) 0x430b75 VADDSD %XMM15,%XMM15,%XMM10 |
(206) 0x430b7a VADDSD (%RDI,%RAX,8),%XMM12,%XMM11 |
(206) 0x430b7f MOV 0x1b0(%RSP),%R10 |
(206) 0x430b87 VMULSD %XMM7,%XMM8,%XMM13 |
(206) 0x430b8b VADDSD 0x8(%RCX,%RAX,8),%XMM0,%XMM8 |
(206) 0x430b91 VADDSD %XMM9,%XMM9,%XMM7 |
(206) 0x430b96 MOV 0x1a8(%RSP),%R11 |
(206) 0x430b9e VADDSD 0x8(%RDI,%RAX,8),%XMM14,%XMM12 |
(206) 0x430ba4 VMOVSD (%R9,%RAX,8),%XMM14 |
(206) 0x430baa VMULSD %XMM7,%XMM8,%XMM15 |
(206) 0x430bae VMOVSD (%R12,%RAX,8),%XMM8 |
(206) 0x430bb4 VADDSD (%R10,%RAX,8),%XMM8,%XMM7 |
(206) 0x430bba MOV 0x198(%RSP),%R10 |
(206) 0x430bc2 VFMADD132SD %XMM12,%XMM15,%XMM10 |
(206) 0x430bc7 VADDSD %XMM14,%XMM14,%XMM12 |
(206) 0x430bcc VDIVSD (%RDX,%RAX,8),%XMM7,%XMM15 |
(206) 0x430bd1 VFMADD132SD %XMM11,%XMM13,%XMM12 |
(206) 0x430bd6 VSUBSD %XMM12,%XMM10,%XMM11 |
(206) 0x430bdb VMOVSD (%R13,%RAX,8),%XMM10 |
(206) 0x430be2 VDIVSD %XMM10,%XMM3,%XMM14 |
(206) 0x430be7 VMULSD %XMM2,%XMM11,%XMM13 |
(206) 0x430beb VADDSD %XMM10,%XMM13,%XMM0 |
(206) 0x430bf0 VDIVSD %XMM0,%XMM10,%XMM9 |
(206) 0x430bf4 VMULSD %XMM14,%XMM15,%XMM12 |
(206) 0x430bf9 VFNMADD213SD (%R11,%RAX,8),%XMM12,%XMM13 |
(206) 0x430bff MOV 0x1bc(%RSP),%R11D |
(206) 0x430c07 VMOVSD %XMM13,(%R10,%RAX,8) |
(206) 0x430c0d MOV 0x1a0(%RSP),%R10D |
(206) 0x430c15 VMULSD (%RDX,%RAX,8),%XMM9,%XMM11 |
(206) 0x430c1a VMOVSD %XMM11,(%RBX,%RAX,8) |
(206) 0x430c1f INC %RAX |
(206) 0x430c22 ADD %EAX,%R10D |
(206) 0x430c25 CMP %R11D,%R10D |
(206) 0x430c28 JB 430b40 |
(205) 0x430c2e MOV 0x1bc(%RSP),%R9D |
(205) 0x430c36 MOV %R9D,0x1b8(%RSP) |
(205) 0x430c3e INCQ 0x140(%RSP) |
(205) 0x430c46 MOV 0x140(%RSP),%R8 |
(205) 0x430c4e ADD $0,%R8D |
(205) 0x430c52 CMP %R8D,0x80(%RSP) |
(205) 0x430c5a JLE 430c88 |
(205) 0x430c5c MOV 0x78(%RSP),%ECX |
(205) 0x430c60 MOV 0x1b8(%RSP),%EDI |
(205) 0x430c67 MOV 0x7c(%RSP),%R15D |
(205) 0x430c6c MOV 0x84(%RSP),%EAX |
(205) 0x430c73 SUB %EDI,%ECX |
(205) 0x430c75 MOV %R15D,0x148(%RSP) |
(205) 0x430c7d JMP 4302d0 |
0x430c82 NOPW (%RAX,%RAX,1) |
0x430c88 VZEROUPPER |
0x430c8b LEA -0x28(%RBP),%RSP |
0x430c8f POP %RBX |
0x430c90 POP %R12 |
0x430c92 POP %R13 |
0x430c94 POP %R14 |
0x430c96 POP %R15 |
0x430c98 POP %RBP |
0x430c99 RET |
0x430c9a NOPW (%RAX,%RAX,1) |
(205) 0x430ca0 MOV 0x148(%RSP),%R13D |
(205) 0x430ca8 XOR %EDX,%EDX |
(205) 0x430caa MOV %R13D,0x190(%RSP) |
(205) 0x430cb2 JMP 430789 |
0x430cb7 INC %ECX |
0x430cb9 XOR %EDX,%EDX |
0x430cbb JMP 4301f1 |
Path / |
Source file and lines | PdV.cpp:48-63 |
Module | exec |
nb instructions | 101 |
nb uops | 111 |
loop length | 407 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 2 |
nb stack references | 19 |
micro-operation queue | 18.50 cycles |
front end | 18.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 9.33 | 9.33 | 13.00 | 7.40 | 7.20 | 13.00 | 13.00 | 13.00 | 7.20 | 9.33 |
cycles | 7.20 | 11.93 | 9.33 | 9.33 | 13.00 | 7.40 | 7.20 | 13.00 | 13.00 | 13.00 | 7.20 | 9.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 17.71-17.85 |
Stall cycles | 0.00 |
Front-end | 18.50 |
Dispatch | 13.00 |
DIV/SQRT | 12.00 |
Overall L1 | 18.50 |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 9% |
load | 11% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 10% |
load | 11% |
store | 10% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x1c0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x68(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x6c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x64(%RBX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RDI),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 430c8b <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb2b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 430c8b <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb2b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x84(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 430cb7 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb57> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RAX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 430c8b <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb2b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x7c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1c8ef(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x84(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x1c8cb(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RBX),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM3,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM2,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM2,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RDX,%R11,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x48(%RBX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R15D,%R15 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %RDX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4301f1 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x91> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | PdV.cpp:48-63 |
Module | exec |
nb instructions | 101 |
nb uops | 111 |
loop length | 407 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 2 |
nb stack references | 19 |
micro-operation queue | 18.50 cycles |
front end | 18.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 9.33 | 9.33 | 13.00 | 7.40 | 7.20 | 13.00 | 13.00 | 13.00 | 7.20 | 9.33 |
cycles | 7.20 | 11.93 | 9.33 | 9.33 | 13.00 | 7.40 | 7.20 | 13.00 | 13.00 | 13.00 | 7.20 | 9.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 17.71-17.85 |
Stall cycles | 0.00 |
Front-end | 18.50 |
Dispatch | 13.00 |
DIV/SQRT | 12.00 |
Overall L1 | 18.50 |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 9% |
load | 11% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 10% |
load | 11% |
store | 10% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x1c0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x68(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x6c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x64(%RBX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RDI),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 430c8b <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb2b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 430c8b <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb2b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x84(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 430cb7 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb57> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RAX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 430c8b <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb2b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x7c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1c8ef(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x84(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x1c8cb(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RBX),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM3,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM2,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM2,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RDX,%R11,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x48(%RBX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R15D,%R15 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %RDX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4301f1 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x91> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D | 4.77 | 1.52 |
▼Loop 205 - PdV.cpp:51-63 - exec– | 0.01 | 0 |
○Loop 207 - PdV.cpp:51-63 - exec | 4.76 | 1.51 |
○Loop 206 - PdV.cpp:55-63 - exec | 0 | 0 |