Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.34% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.34% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
48: post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
0x418080 PUSH %RBP |
0x418081 MOV %RSP,%RBP |
0x418084 PUSH %R15 |
0x418086 PUSH %R14 |
0x418088 PUSH %R13 |
0x41808a PUSH %R12 |
0x41808c MOV %RDI,%R12 |
0x41808f PUSH %RBX |
0x418090 AND $-0x40,%RSP |
0x418094 SUB $0xc0,%RSP |
0x41809b MOV 0x30(%RDI),%EAX |
0x41809e MOV 0x34(%RDI),%ECX |
0x4180a1 MOV 0x28(%RDI),%EDI |
0x4180a4 MOV 0x2c(%R12),%EDX |
0x4180a9 ADD $0x4,%ECX |
0x4180ac LEA -0x1(%RAX),%R15D |
0x4180b0 DEC %EDI |
0x4180b2 MOV %ECX,0x5c(%RSP) |
0x4180b6 MOV %EDI,0x58(%RSP) |
0x4180ba CMP %ECX,%R15D |
0x4180bd JGE 418813 |
0x4180c3 MOV %ECX,%EBX |
0x4180c5 LEA 0x4(%RDX),%R14D |
0x4180c9 SUB %R15D,%EBX |
0x4180cc CMP %R14D,%EDI |
0x4180cf JGE 418813 |
0x4180d5 MOV %R14D,%ESI |
0x4180d8 SUB %EDI,%ESI |
0x4180da MOV %ESI,0x88(%RSP) |
0x4180e1 CALL 4046c0 <omp_get_num_threads@plt> |
0x4180e6 MOV %EAX,%R13D |
0x4180e9 CALL 4045b0 <omp_get_thread_num@plt> |
0x4180ee XOR %EDX,%EDX |
0x4180f0 MOV %EAX,%R8D |
0x4180f3 MOV 0x88(%RSP),%EAX |
0x4180fa IMUL %EBX,%EAX |
0x4180fd DIV %R13D |
0x418100 MOV %EAX,%ESI |
0x418102 CMP %EDX,%R8D |
0x418105 JB 418847 |
0x41810b IMUL %ESI,%R8D |
0x41810f LEA (%R8,%RDX,1),%R9D |
0x418113 LEA (%RSI,%R9,1),%R10D |
0x418117 MOV %R10D,0x54(%RSP) |
0x41811c CMP %R10D,%R9D |
0x41811f JAE 418813 |
0x418125 MOV %R9D,%EAX |
0x418128 XOR %EDX,%EDX |
0x41812a MOV 0x58(%RSP),%R11D |
0x41812f MOV (%R12),%RCX |
0x418133 DIVL 0x88(%RSP) |
0x41813a MOV 0x8(%R12),%RDI |
0x41813f MOV 0x18(%R12),%RBX |
0x418144 MOV %RCX,0x48(%RSP) |
0x418149 MOV %RDI,0x40(%RSP) |
0x41814e MOV %RBX,0x30(%RSP) |
0x418153 MOV %R14D,%R10D |
0x418156 MOV 0x10(%R12),%R14 |
0x41815b MOV 0x20(%R12),%R12 |
0x418160 MOV %R14,0x38(%RSP) |
0x418165 MOV %R12,0x28(%RSP) |
0x41816a ADD %EDX,%R11D |
0x41816d LEA (%RAX,%R15,1),%R15D |
0x418171 MOV %R11D,0xa0(%RSP) |
0x418179 SUB %R11D,%R10D |
0x41817c MOVSXD %R15D,%RCX |
0x41817f NOP |
(95) 0x418180 CMP %R10D,%ESI |
(95) 0x418183 CMOVBE %ESI,%R10D |
(95) 0x418187 LEA (%R9,%R10,1),%ESI |
(95) 0x41818b MOV %R10D,%EDX |
(95) 0x41818e MOV %ESI,0x8c(%RSP) |
(95) 0x418195 CMP %ESI,%R9D |
(95) 0x418198 JAE 418828 |
(95) 0x41819e MOV 0x38(%RSP),%RAX |
(95) 0x4181a3 LEA 0x1(%RCX),%R14 |
(95) 0x4181a7 MOV 0x48(%RSP),%R8 |
(95) 0x4181ac MOV 0x40(%RSP),%R10 |
(95) 0x4181b1 MOV 0x30(%RSP),%R13 |
(95) 0x4181b6 MOV %R14,0x60(%RSP) |
(95) 0x4181bb MOV (%RAX),%R12 |
(95) 0x4181be MOV (%R8),%RSI |
(95) 0x4181c1 MOV (%R10),%R11 |
(95) 0x4181c4 MOV 0x10(%RAX),%RDI |
(95) 0x4181c8 IMUL %R12,%R14 |
(95) 0x4181cc MOV 0x28(%RSP),%RAX |
(95) 0x4181d1 MOV 0x10(%R8),%R15 |
(95) 0x4181d5 IMUL %RCX,%RSI |
(95) 0x4181d9 MOV 0x10(%R10),%R8 |
(95) 0x4181dd MOV 0x10(%R13),%R10 |
(95) 0x4181e1 IMUL %RCX,%R11 |
(95) 0x4181e5 MOV %R15,0x98(%RSP) |
(95) 0x4181ed MOV %R14,%RBX |
(95) 0x4181f0 MOV %R14,0x78(%RSP) |
(95) 0x4181f5 SUB %R12,%RBX |
(95) 0x4181f8 MOV (%R13),%R12 |
(95) 0x4181fc MOV 0x10(%RAX),%R13 |
(95) 0x418200 MOV %RSI,0x68(%RSP) |
(95) 0x418205 MOV %R11,0x70(%RSP) |
(95) 0x41820a IMUL %RCX,%R12 |
(95) 0x41820e MOV %RBX,0x80(%RSP) |
(95) 0x418216 IMUL (%RAX),%RCX |
(95) 0x41821a MOV %R10,0xa8(%RSP) |
(95) 0x418222 MOV %R13,0xb8(%RSP) |
(95) 0x41822a MOV %R12,0x90(%RSP) |
(95) 0x418232 MOV %RCX,0xb0(%RSP) |
(95) 0x41823a LEA -0x1(%RDX),%ECX |
(95) 0x41823d CMP $0x6,%ECX |
(95) 0x418240 JBE 418838 |
(95) 0x418246 MOVSXD 0xa0(%RSP),%RAX |
(95) 0x41824e LEA 0x1(%RAX,%R11,1),%R11 |
(95) 0x418253 LEA (%RAX,%RSI,1),%R10 |
(95) 0x418257 SAL $0x3,%R11 |
(95) 0x41825b LEA (%RAX,%R14,1),%R14 |
(95) 0x41825f LEA (%RAX,%RBX,1),%RBX |
(95) 0x418263 LEA (%R8,%R11,1),%RCX |
(95) 0x418267 LEA -0x8(%R8,%R11,1),%RSI |
(95) 0x41826c MOV 0xb0(%RSP),%R11 |
(95) 0x418274 LEA (%RAX,%R12,1),%R12 |
(95) 0x418278 LEA (%R15,%R10,8),%R15 |
(95) 0x41827c MOV 0xa8(%RSP),%R10 |
(95) 0x418284 ADD %R11,%RAX |
(95) 0x418287 MOV %EDX,%R11D |
(95) 0x41828a LEA (%RDI,%R14,8),%R13 |
(95) 0x41828e SHR $0x3,%R11D |
(95) 0x418292 LEA (%R10,%R12,8),%R12 |
(95) 0x418296 LEA (%RDI,%RBX,8),%R14 |
(95) 0x41829a MOV 0xb8(%RSP),%RBX |
(95) 0x4182a2 SAL $0x6,%R11 |
(95) 0x4182a6 LEA -0x40(%R11),%R10 |
(95) 0x4182aa LEA (%RBX,%RAX,8),%RBX |
(95) 0x4182ae XOR %EAX,%EAX |
(95) 0x4182b0 SHR $0x6,%R10 |
(95) 0x4182b4 INC %R10 |
(95) 0x4182b7 AND $0x3,%R10D |
(95) 0x4182bb JE 4183c3 |
(95) 0x4182c1 CMP $0x1,%R10 |
(95) 0x4182c5 JE 41836a |
(95) 0x4182cb CMP $0x2,%R10 |
(95) 0x4182cf JE 41831a |
(95) 0x4182d1 VMOVUPD (%R15),%ZMM4 |
(95) 0x4182d7 VMOVUPD (%RSI),%ZMM5 |
(95) 0x4182dd MOV $0x40,%EAX |
(95) 0x4182e2 VADDPD (%RCX),%ZMM4,%ZMM0 |
(95) 0x4182e8 VADDPD (%R14),%ZMM5,%ZMM1 |
(95) 0x4182ee VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(95) 0x4182f4 VADDPD (%R13),%ZMM2,%ZMM3 |
(95) 0x4182fb VMOVUPD %ZMM3,(%R12) |
(95) 0x418302 VMOVUPD (%RSI),%ZMM6 |
(95) 0x418308 VSUBPD (%RCX),%ZMM6,%ZMM7 |
(95) 0x41830e VADDPD %ZMM3,%ZMM7,%ZMM8 |
(95) 0x418314 VMOVUPD %ZMM8,(%RBX) |
(95) 0x41831a VMOVUPD (%R15,%RAX,1),%ZMM9 |
(95) 0x418321 VMOVUPD (%RSI,%RAX,1),%ZMM11 |
(95) 0x418328 VADDPD (%RCX,%RAX,1),%ZMM9,%ZMM10 |
(95) 0x41832f VADDPD (%R14,%RAX,1),%ZMM11,%ZMM12 |
(95) 0x418336 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(95) 0x41833c VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(95) 0x418344 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(95) 0x41834b VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(95) 0x418352 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM4 |
(95) 0x418359 VADDPD %ZMM14,%ZMM4,%ZMM0 |
(95) 0x41835f VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(95) 0x418366 ADD $0x40,%RAX |
(95) 0x41836a VMOVUPD (%R15,%RAX,1),%ZMM5 |
(95) 0x418371 VMOVUPD (%RSI,%RAX,1),%ZMM1 |
(95) 0x418378 VADDPD (%RCX,%RAX,1),%ZMM5,%ZMM2 |
(95) 0x41837f VADDPD (%R14,%RAX,1),%ZMM1,%ZMM3 |
(95) 0x418386 VSUBPD %ZMM3,%ZMM2,%ZMM6 |
(95) 0x41838c VADDPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(95) 0x418394 VMOVUPD %ZMM7,(%R12,%RAX,1) |
(95) 0x41839b VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(95) 0x4183a2 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(95) 0x4183a9 VADDPD %ZMM7,%ZMM9,%ZMM10 |
(95) 0x4183af VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(95) 0x4183b6 ADD $0x40,%RAX |
(95) 0x4183ba CMP %RAX,%R11 |
(95) 0x4183bd JE 41851a |
(96) 0x4183c3 VMOVUPD (%R15,%RAX,1),%ZMM11 |
(96) 0x4183ca VMOVUPD (%RSI,%RAX,1),%ZMM13 |
(96) 0x4183d1 VADDPD (%RCX,%RAX,1),%ZMM11,%ZMM12 |
(96) 0x4183d8 VADDPD (%R14,%RAX,1),%ZMM13,%ZMM14 |
(96) 0x4183df VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(96) 0x4183e5 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM4 |
(96) 0x4183ed VMOVUPD %ZMM4,(%R12,%RAX,1) |
(96) 0x4183f4 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(96) 0x4183fb VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM5 |
(96) 0x418402 VADDPD %ZMM4,%ZMM5,%ZMM2 |
(96) 0x418408 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(96) 0x41840f VMOVUPD 0x40(%R15,%RAX,1),%ZMM1 |
(96) 0x418417 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM6 |
(96) 0x41841f VADDPD 0x40(%RCX,%RAX,1),%ZMM1,%ZMM3 |
(96) 0x418427 VADDPD 0x40(%R14,%RAX,1),%ZMM6,%ZMM7 |
(96) 0x41842f VSUBPD %ZMM7,%ZMM3,%ZMM8 |
(96) 0x418435 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(96) 0x41843d VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(96) 0x418445 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(96) 0x41844d VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(96) 0x418455 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(96) 0x41845b VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(96) 0x418463 VMOVUPD 0x80(%R15,%RAX,1),%ZMM13 |
(96) 0x41846b VMOVUPD 0x80(%RSI,%RAX,1),%ZMM15 |
(96) 0x418473 VADDPD 0x80(%RCX,%RAX,1),%ZMM13,%ZMM14 |
(96) 0x41847b VADDPD 0x80(%R14,%RAX,1),%ZMM15,%ZMM4 |
(96) 0x418483 VSUBPD %ZMM4,%ZMM14,%ZMM0 |
(96) 0x418489 VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM5 |
(96) 0x418491 VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(96) 0x418499 VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(96) 0x4184a1 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(96) 0x4184a9 VADDPD %ZMM5,%ZMM1,%ZMM3 |
(96) 0x4184af VMOVUPD %ZMM3,0x80(%RBX,%RAX,1) |
(96) 0x4184b7 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM6 |
(96) 0x4184bf VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM8 |
(96) 0x4184c7 VADDPD 0xc0(%RCX,%RAX,1),%ZMM6,%ZMM7 |
(96) 0x4184cf VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM9 |
(96) 0x4184d7 VSUBPD %ZMM9,%ZMM7,%ZMM10 |
(96) 0x4184dd VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(96) 0x4184e5 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(96) 0x4184ed VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(96) 0x4184f5 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(96) 0x4184fd VADDPD %ZMM11,%ZMM13,%ZMM14 |
(96) 0x418503 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(96) 0x41850b ADD $0x100,%RAX |
(96) 0x418511 CMP %RAX,%R11 |
(96) 0x418514 JNE 4183c3 |
(95) 0x41851a MOV 0xa0(%RSP),%R15D |
(95) 0x418522 MOV %EDX,%R13D |
(95) 0x418525 AND $-0x8,%R13D |
(95) 0x418529 ADD %R13D,%R9D |
(95) 0x41852c LEA (%R13,%R15,1),%ESI |
(95) 0x418531 TEST $0x7,%DL |
(95) 0x418534 JE 4187db |
(95) 0x41853a SUB %R13D,%EDX |
(95) 0x41853d LEA -0x1(%RDX),%ECX |
(95) 0x418540 CMP $0x2,%ECX |
(95) 0x418543 JBE 418610 |
(95) 0x418549 MOVSXD 0xa0(%RSP),%RAX |
(95) 0x418551 MOV 0x70(%RSP),%R14 |
(95) 0x418556 MOV 0x78(%RSP),%R15 |
(95) 0x41855b MOV 0x68(%RSP),%R10 |
(95) 0x418560 LEA (%R14,%RAX,1),%R12 |
(95) 0x418564 LEA 0x1(%R13,%R12,1),%R11 |
(95) 0x418569 LEA (%R15,%RAX,1),%R12 |
(95) 0x41856d MOV 0x90(%RSP),%R15 |
(95) 0x418575 SAL $0x3,%R11 |
(95) 0x418579 ADD %R13,%R12 |
(95) 0x41857c LEA (%R10,%RAX,1),%R14 |
(95) 0x418580 MOV 0x80(%RSP),%R10 |
(95) 0x418588 LEA (%R8,%R11,1),%RBX |
(95) 0x41858c VMOVUPD (%RDI,%R12,8),%YMM15 |
(95) 0x418592 LEA -0x8(%R8,%R11,1),%RCX |
(95) 0x418597 MOV 0x98(%RSP),%R11 |
(95) 0x41859f VMOVUPD (%RBX),%YMM0 |
(95) 0x4185a3 ADD %R13,%R14 |
(95) 0x4185a6 LEA (%R15,%RAX,1),%R12 |
(95) 0x4185aa VADDPD (%R11,%R14,8),%YMM15,%YMM4 |
(95) 0x4185b0 LEA (%R10,%RAX,1),%R14 |
(95) 0x4185b4 MOV 0xa8(%RSP),%R11 |
(95) 0x4185bc ADD %R13,%R12 |
(95) 0x4185bf VSUBPD (%RCX),%YMM0,%YMM5 |
(95) 0x4185c3 ADD %R13,%R14 |
(95) 0x4185c6 VADDPD %YMM5,%YMM4,%YMM2 |
(95) 0x4185ca VSUBPD (%RDI,%R14,8),%YMM2,%YMM3 |
(95) 0x4185d0 VMOVUPD %YMM3,(%R11,%R12,8) |
(95) 0x4185d6 VMOVUPD (%RCX),%YMM1 |
(95) 0x4185da VSUBPD (%RBX),%YMM1,%YMM6 |
(95) 0x4185de MOV 0xb0(%RSP),%RBX |
(95) 0x4185e6 ADD %RBX,%RAX |
(95) 0x4185e9 VADDPD %YMM3,%YMM6,%YMM7 |
(95) 0x4185ed ADD %R13,%RAX |
(95) 0x4185f0 MOV 0xb8(%RSP),%R13 |
(95) 0x4185f8 VMOVUPD %YMM7,(%R13,%RAX,8) |
(95) 0x4185ff TEST $0x3,%DL |
(95) 0x418602 JE 4187db |
(95) 0x418608 AND $-0x4,%EDX |
(95) 0x41860b ADD %EDX,%R9D |
(95) 0x41860e ADD %EDX,%ESI |
(95) 0x418610 MOV 0x70(%RSP),%R15 |
(95) 0x418615 LEA 0x1(%RSI),%EDX |
(95) 0x418618 MOV 0x68(%RSP),%R14 |
(95) 0x41861d MOVSXD %ESI,%RAX |
(95) 0x418620 MOVSXD %EDX,%RDX |
(95) 0x418623 MOV 0x98(%RSP),%R12 |
(95) 0x41862b MOV 0x78(%RSP),%R13 |
(95) 0x418630 LEA (%R15,%RDX,1),%RCX |
(95) 0x418634 LEA (%R14,%RAX,1),%RBX |
(95) 0x418638 LEA (%R8,%RCX,8),%RCX |
(95) 0x41863c VMOVSD (%R12,%RBX,8),%XMM8 |
(95) 0x418642 LEA (%R15,%RAX,1),%R10 |
(95) 0x418646 MOV 0x80(%RSP),%R12 |
(95) 0x41864e VMOVSD (%RCX),%XMM10 |
(95) 0x418652 LEA (%R8,%R10,8),%R10 |
(95) 0x418656 LEA (%R13,%RAX,1),%R11 |
(95) 0x41865b VADDSD (%RDI,%R11,8),%XMM8,%XMM9 |
(95) 0x418661 LEA (%R12,%RAX,1),%RBX |
(95) 0x418665 MOV 0x90(%RSP),%R11 |
(95) 0x41866d VSUBSD (%R10),%XMM10,%XMM11 |
(95) 0x418672 LEA (%R11,%RAX,1),%R11 |
(95) 0x418676 VADDSD %XMM11,%XMM9,%XMM12 |
(95) 0x41867b VSUBSD (%RDI,%RBX,8),%XMM12,%XMM13 |
(95) 0x418680 MOV 0xa8(%RSP),%RBX |
(95) 0x418688 VMOVSD %XMM13,(%RBX,%R11,8) |
(95) 0x41868e MOV 0xb0(%RSP),%R11 |
(95) 0x418696 MOV 0x8c(%RSP),%EBX |
(95) 0x41869d VMOVSD (%R10),%XMM14 |
(95) 0x4186a2 MOV 0xb8(%RSP),%R10 |
(95) 0x4186aa ADD %R11,%RAX |
(95) 0x4186ad VSUBSD (%RCX),%XMM14,%XMM15 |
(95) 0x4186b1 VADDSD %XMM13,%XMM15,%XMM4 |
(95) 0x4186b6 VMOVSD %XMM4,(%R10,%RAX,8) |
(95) 0x4186bc LEA 0x1(%R9),%EAX |
(95) 0x4186c0 CMP %EBX,%EAX |
(95) 0x4186c2 JAE 4187db |
(95) 0x4186c8 LEA 0x2(%RSI),%EAX |
(95) 0x4186cb MOV %R15,%RBX |
(95) 0x4186ce LEA (%RDX,%R14,1),%R11 |
(95) 0x4186d2 ADD $0x2,%R9D |
(95) 0x4186d6 CLTQ |
(95) 0x4186d8 LEA (%R15,%RAX,1),%R15 |
(95) 0x4186dc LEA (%R8,%R15,8),%R10 |
(95) 0x4186e0 MOV 0x98(%RSP),%R15 |
(95) 0x4186e8 MOV %R10,0xa0(%RSP) |
(95) 0x4186f0 VMOVSD (%R15,%R11,8),%XMM0 |
(95) 0x4186f6 MOV %R12,%R15 |
(95) 0x4186f9 LEA (%R12,%RDX,1),%R12 |
(95) 0x4186fd VMOVSD (%RDI,%R12,8),%XMM2 |
(95) 0x418703 MOV 0x90(%RSP),%R12 |
(95) 0x41870b VADDSD (%R10),%XMM0,%XMM5 |
(95) 0x418710 LEA (%R13,%RDX,1),%R10 |
(95) 0x418715 VADDSD (%RCX),%XMM2,%XMM3 |
(95) 0x418719 LEA (%R12,%RDX,1),%R11 |
(95) 0x41871d VSUBSD %XMM3,%XMM5,%XMM1 |
(95) 0x418721 VADDSD (%RDI,%R10,8),%XMM1,%XMM6 |
(95) 0x418727 MOV 0xa8(%RSP),%R10 |
(95) 0x41872f VMOVSD %XMM6,(%R10,%R11,8) |
(95) 0x418735 MOV 0xb0(%RSP),%R11 |
(95) 0x41873d VMOVSD (%RCX),%XMM7 |
(95) 0x418741 MOV 0xa0(%RSP),%RCX |
(95) 0x418749 ADD %R11,%RDX |
(95) 0x41874c VSUBSD (%RCX),%XMM7,%XMM8 |
(95) 0x418750 MOV 0xb8(%RSP),%RCX |
(95) 0x418758 VADDSD %XMM6,%XMM8,%XMM9 |
(95) 0x41875c VMOVSD %XMM9,(%RCX,%RDX,8) |
(95) 0x418761 MOV 0x8c(%RSP),%EDX |
(95) 0x418768 CMP %EDX,%R9D |
(95) 0x41876b JAE 4187db |
(95) 0x41876d ADD $0x3,%ESI |
(95) 0x418770 ADD %RAX,%R14 |
(95) 0x418773 ADD %RAX,%R15 |
(95) 0x418776 ADD %RAX,%R13 |
(95) 0x418779 MOVSXD %ESI,%R9 |
(95) 0x41877c MOV 0x98(%RSP),%RSI |
(95) 0x418784 VMOVSD (%RDI,%R15,8),%XMM12 |
(95) 0x41878a ADD %RAX,%R12 |
(95) 0x41878d ADD %RBX,%R9 |
(95) 0x418790 MOV 0xa0(%RSP),%RBX |
(95) 0x418798 ADD %RAX,%R11 |
(95) 0x41879b VMOVSD (%RSI,%R14,8),%XMM10 |
(95) 0x4187a1 LEA (%R8,%R9,8),%R8 |
(95) 0x4187a5 VADDSD (%RBX),%XMM12,%XMM13 |
(95) 0x4187a9 VADDSD (%R8),%XMM10,%XMM11 |
(95) 0x4187ae VSUBSD %XMM13,%XMM11,%XMM14 |
(95) 0x4187b3 VADDSD (%RDI,%R13,8),%XMM14,%XMM15 |
(95) 0x4187b9 MOV 0xb8(%RSP),%RDI |
(95) 0x4187c1 VMOVSD %XMM15,(%R10,%R12,8) |
(95) 0x4187c7 VMOVSD (%RBX),%XMM4 |
(95) 0x4187cb VSUBSD (%R8),%XMM4,%XMM0 |
(95) 0x4187d0 VADDSD %XMM15,%XMM0,%XMM5 |
(95) 0x4187d5 VMOVSD %XMM5,(%RDI,%R11,8) |
(95) 0x4187db MOV 0x8c(%RSP),%R9D |
(95) 0x4187e3 MOV 0x60(%RSP),%RCX |
(95) 0x4187e8 LEA (%RCX),%EAX |
(95) 0x4187ea CMP %EAX,0x5c(%RSP) |
(95) 0x4187ee JLE 418810 |
(95) 0x4187f0 MOV 0x54(%RSP),%ESI |
(95) 0x4187f4 MOV 0x58(%RSP),%EDX |
(95) 0x4187f8 MOV 0x88(%RSP),%R10D |
(95) 0x418800 MOV %EDX,0xa0(%RSP) |
(95) 0x418807 SUB %R9D,%ESI |
(95) 0x41880a JMP 418180 |
0x41880f NOP |
0x418810 VZEROUPPER |
0x418813 LEA -0x28(%RBP),%RSP |
0x418817 POP %RBX |
0x418818 POP %R12 |
0x41881a POP %R13 |
0x41881c POP %R14 |
0x41881e POP %R15 |
0x418820 POP %RBP |
0x418821 RET |
0x418822 NOPW (%RAX,%RAX,1) |
(95) 0x418828 LEA 0x1(%RCX),%R13 |
(95) 0x41882c MOV %R13,0x60(%RSP) |
(95) 0x418831 JMP 4187e3 |
0x418833 NOPL (%RAX,%RAX,1) |
(95) 0x418838 MOV 0xa0(%RSP),%ESI |
(95) 0x41883f XOR %R13D,%R13D |
(95) 0x418842 JMP 41853a |
0x418847 INC %ESI |
0x418849 XOR %EDX,%EDX |
0x41884b JMP 41810b |
Path / |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418813 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418813 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 418847 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 418813 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41810b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418813 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 418813 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 418847 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 418813 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41810b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.34 | 0.43 |
▼Loop 95 - advec_cell.cpp:44-48 - exec– | 0 | 0 |
○Loop 96 - advec_cell.cpp:47-48 - exec | 1.34 | 0.43 |