Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.73% |
---|
Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.73% |
---|
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 157 - 160 |
-------------------------------------------------------------------------------- |
157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
160: node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1)); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41f5f0 PUSH %RBP |
0x41f5f1 MOV %RSP,%RBP |
0x41f5f4 PUSH %R15 |
0x41f5f6 PUSH %R14 |
0x41f5f8 PUSH %R13 |
0x41f5fa PUSH %R12 |
0x41f5fc PUSH %RBX |
0x41f5fd AND $-0x40,%RSP |
0x41f601 SUB $0x40,%RSP |
0x41f605 MOV 0x18(%RDI),%EAX |
0x41f608 MOV 0x1c(%RDI),%EDX |
0x41f60b MOV 0x10(%RDI),%ESI |
0x41f60e MOV 0x14(%RDI),%EBX |
0x41f611 ADD $0x4,%EDX |
0x41f614 LEA -0x1(%RAX),%R15D |
0x41f618 LEA 0x1(%RSI),%ECX |
0x41f61b MOV %EDX,0x20(%RSP) |
0x41f61f MOV %ECX,0x1c(%RSP) |
0x41f623 CMP %EDX,%R15D |
0x41f626 JGE 41fa8b |
0x41f62c LEA 0x3(%RBX),%R13D |
0x41f630 MOV %EDX,%EBX |
0x41f632 SUB %R15D,%EBX |
0x41f635 CMP %R13D,%ECX |
0x41f638 JGE 41fa8b |
0x41f63e MOV %RDI,%R14 |
0x41f641 MOV %R13D,%EDI |
0x41f644 SUB %ECX,%EDI |
0x41f646 MOV %EDI,0x24(%RSP) |
0x41f64a CALL 4046c0 <omp_get_num_threads@plt> |
0x41f64f MOV %EAX,%R12D |
0x41f652 CALL 4045b0 <omp_get_thread_num@plt> |
0x41f657 MOV 0x24(%RSP),%R9D |
0x41f65c XOR %EDX,%EDX |
0x41f65e MOV %EAX,%R8D |
0x41f661 IMUL %R9D,%EBX |
0x41f665 MOV %EBX,%EAX |
0x41f667 DIV %R12D |
0x41f66a MOV %EAX,%EDI |
0x41f66c CMP %EDX,%R8D |
0x41f66f JB 41faab |
0x41f675 IMUL %EDI,%R8D |
0x41f679 LEA (%R8,%RDX,1),%R12D |
0x41f67d LEA (%RDI,%R12,1),%R10D |
0x41f681 MOV %R10D,0x18(%RSP) |
0x41f686 CMP %R10D,%R12D |
0x41f689 JAE 41fa8b |
0x41f68f MOV %R12D,%EAX |
0x41f692 XOR %EDX,%EDX |
0x41f694 MOV 0x1c(%RSP),%R11D |
0x41f699 MOV 0x8(%R14),%RCX |
0x41f69d DIVL 0x24(%RSP) |
0x41f6a1 VMOVSD 0x2cecf(%RIP),%XMM3 |
0x41f6a9 MOV %RCX,0x8(%RSP) |
0x41f6ae VBROADCASTSD %XMM3,%YMM4 |
0x41f6b3 VBROADCASTSD %XMM3,%ZMM2 |
0x41f6b9 ADD %R15D,%EAX |
0x41f6bc MOV (%R14),%R15 |
0x41f6bf LEA (%RDX,%R11,1),%ESI |
0x41f6c3 MOV %R13D,%EDX |
0x41f6c6 CLTQ |
0x41f6c8 MOV %ESI,0x3c(%RSP) |
0x41f6cc SUB %ESI,%EDX |
0x41f6ce MOV %R15,0x10(%RSP) |
0x41f6d3 MOV %RAX,0x30(%RSP) |
0x41f6d8 NOPL (%RAX,%RAX,1) |
(131) 0x41f6e0 CMP %EDX,%EDI |
(131) 0x41f6e2 CMOVBE %EDI,%EDX |
(131) 0x41f6e5 LEA (%R12,%RDX,1),%R13D |
(131) 0x41f6e9 MOV %R13D,0x38(%RSP) |
(131) 0x41f6ee CMP %R13D,%R12D |
(131) 0x41f6f1 JAE 41fa54 |
(131) 0x41f6f7 MOV 0x10(%RSP),%RBX |
(131) 0x41f6fc MOV 0x30(%RSP),%R9 |
(131) 0x41f701 LEA -0x1(%RDX),%EDI |
(131) 0x41f704 MOV 0x8(%RSP),%R14 |
(131) 0x41f709 MOV (%RBX),%R8 |
(131) 0x41f70c MOV %R9,%R10 |
(131) 0x41f70f MOV 0x10(%RBX),%RCX |
(131) 0x41f713 IMUL (%R14),%R9 |
(131) 0x41f717 MOV 0x10(%R14),%R15 |
(131) 0x41f71b IMUL %R8,%R10 |
(131) 0x41f71f MOV %R9,0x28(%RSP) |
(131) 0x41f724 ADD %R10,%R8 |
(131) 0x41f727 CMP $0x6,%EDI |
(131) 0x41f72a JBE 41faa0 |
(131) 0x41f730 MOVSXD 0x3c(%RSP),%R11 |
(131) 0x41f735 XOR %EAX,%EAX |
(131) 0x41f737 LEA (%R11,%R10,1),%RDI |
(131) 0x41f73b LEA (%R11,%R8,1),%RSI |
(131) 0x41f73f ADD %R9,%R11 |
(131) 0x41f742 LEA (%R15,%R11,8),%RBX |
(131) 0x41f746 SAL $0x3,%RDI |
(131) 0x41f74a MOV %EDX,%R11D |
(131) 0x41f74d SAL $0x3,%RSI |
(131) 0x41f751 SHR $0x3,%R11D |
(131) 0x41f755 LEA -0x8(%RCX,%RDI,1),%R14 |
(131) 0x41f75a LEA -0x8(%RCX,%RSI,1),%R13 |
(131) 0x41f75f ADD %RCX,%RDI |
(131) 0x41f762 SAL $0x6,%R11 |
(131) 0x41f766 ADD %RCX,%RSI |
(131) 0x41f769 LEA -0x40(%R11),%R9 |
(131) 0x41f76d SHR $0x6,%R9 |
(131) 0x41f771 INC %R9 |
(131) 0x41f774 AND $0x3,%R9D |
(131) 0x41f778 JE 41f82b |
(131) 0x41f77e CMP $0x1,%R9 |
(131) 0x41f782 JE 41f7ee |
(131) 0x41f784 CMP $0x2,%R9 |
(131) 0x41f788 JE 41f7ba |
(131) 0x41f78a VMOVUPD (%R14),%ZMM7 |
(131) 0x41f790 VMOVUPD (%R13),%ZMM1 |
(131) 0x41f797 MOV $0x40,%EAX |
(131) 0x41f79c VADDPD (%RDI),%ZMM7,%ZMM0 |
(131) 0x41f7a2 VADDPD (%RSI),%ZMM1,%ZMM5 |
(131) 0x41f7a8 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(131) 0x41f7ae VMULPD %ZMM2,%ZMM6,%ZMM8 |
(131) 0x41f7b4 VMOVUPD %ZMM8,(%RBX) |
(131) 0x41f7ba VMOVUPD (%R14,%RAX,1),%ZMM9 |
(131) 0x41f7c1 VMOVUPD (%R13,%RAX,1),%ZMM11 |
(131) 0x41f7c9 VADDPD (%RDI,%RAX,1),%ZMM9,%ZMM10 |
(131) 0x41f7d0 VADDPD (%RSI,%RAX,1),%ZMM11,%ZMM12 |
(131) 0x41f7d7 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(131) 0x41f7dd VMULPD %ZMM2,%ZMM13,%ZMM14 |
(131) 0x41f7e3 VMOVUPD %ZMM14,(%RBX,%RAX,1) |
(131) 0x41f7ea ADD $0x40,%RAX |
(131) 0x41f7ee VMOVUPD (%R14,%RAX,1),%ZMM15 |
(131) 0x41f7f5 VMOVUPD (%R13,%RAX,1),%ZMM7 |
(131) 0x41f7fd VADDPD (%RDI,%RAX,1),%ZMM15,%ZMM0 |
(131) 0x41f804 VADDPD (%RSI,%RAX,1),%ZMM7,%ZMM1 |
(131) 0x41f80b VADDPD %ZMM1,%ZMM0,%ZMM5 |
(131) 0x41f811 VMULPD %ZMM2,%ZMM5,%ZMM6 |
(131) 0x41f817 VMOVUPD %ZMM6,(%RBX,%RAX,1) |
(131) 0x41f81e ADD $0x40,%RAX |
(131) 0x41f822 CMP %RAX,%R11 |
(131) 0x41f825 JE 41f906 |
(132) 0x41f82b VMOVUPD (%R14,%RAX,1),%ZMM8 |
(132) 0x41f832 VMOVUPD (%R13,%RAX,1),%ZMM10 |
(132) 0x41f83a VADDPD (%RDI,%RAX,1),%ZMM8,%ZMM9 |
(132) 0x41f841 VADDPD (%RSI,%RAX,1),%ZMM10,%ZMM11 |
(132) 0x41f848 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(132) 0x41f84e VMULPD %ZMM2,%ZMM12,%ZMM13 |
(132) 0x41f854 VMOVUPD %ZMM13,(%RBX,%RAX,1) |
(132) 0x41f85b VMOVUPD 0x40(%R14,%RAX,1),%ZMM14 |
(132) 0x41f863 VMOVUPD 0x40(%R13,%RAX,1),%ZMM0 |
(132) 0x41f86b VADDPD 0x40(%RDI,%RAX,1),%ZMM14,%ZMM15 |
(132) 0x41f873 VADDPD 0x40(%RSI,%RAX,1),%ZMM0,%ZMM7 |
(132) 0x41f87b VADDPD %ZMM7,%ZMM15,%ZMM1 |
(132) 0x41f881 VMULPD %ZMM2,%ZMM1,%ZMM5 |
(132) 0x41f887 VMOVUPD %ZMM5,0x40(%RBX,%RAX,1) |
(132) 0x41f88f VMOVUPD 0x80(%R14,%RAX,1),%ZMM6 |
(132) 0x41f897 VMOVUPD 0x80(%R13,%RAX,1),%ZMM9 |
(132) 0x41f89f VADDPD 0x80(%RDI,%RAX,1),%ZMM6,%ZMM8 |
(132) 0x41f8a7 VADDPD 0x80(%RSI,%RAX,1),%ZMM9,%ZMM10 |
(132) 0x41f8af VADDPD %ZMM10,%ZMM8,%ZMM11 |
(132) 0x41f8b5 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(132) 0x41f8bb VMOVUPD %ZMM12,0x80(%RBX,%RAX,1) |
(132) 0x41f8c3 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM13 |
(132) 0x41f8cb VMOVUPD 0xc0(%R13,%RAX,1),%ZMM15 |
(132) 0x41f8d3 VADDPD 0xc0(%RDI,%RAX,1),%ZMM13,%ZMM14 |
(132) 0x41f8db VADDPD 0xc0(%RSI,%RAX,1),%ZMM15,%ZMM0 |
(132) 0x41f8e3 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(132) 0x41f8e9 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(132) 0x41f8ef VMOVUPD %ZMM1,0xc0(%RBX,%RAX,1) |
(132) 0x41f8f7 ADD $0x100,%RAX |
(132) 0x41f8fd CMP %RAX,%R11 |
(132) 0x41f900 JNE 41f82b |
(131) 0x41f906 MOV 0x3c(%RSP),%ESI |
(131) 0x41f90a MOV %EDX,%EAX |
(131) 0x41f90c AND $-0x8,%EAX |
(131) 0x41f90f ADD %EAX,%R12D |
(131) 0x41f912 ADD %EAX,%ESI |
(131) 0x41f914 TEST $0x7,%DL |
(131) 0x41f917 JE 41fa4f |
(131) 0x41f91d SUB %EAX,%EDX |
(131) 0x41f91f LEA -0x1(%RDX),%EDI |
(131) 0x41f922 CMP $0x2,%EDI |
(131) 0x41f925 JBE 41f97d |
(131) 0x41f927 MOVSXD 0x3c(%RSP),%R14 |
(131) 0x41f92c MOV 0x28(%RSP),%R11 |
(131) 0x41f931 LEA (%R10,%R14,1),%R13 |
(131) 0x41f935 LEA (%R8,%R14,1),%RBX |
(131) 0x41f939 ADD %RAX,%R13 |
(131) 0x41f93c ADD %RAX,%RBX |
(131) 0x41f93f ADD %R11,%RAX |
(131) 0x41f942 VMOVUPD -0x8(%RCX,%R13,8),%YMM5 |
(131) 0x41f949 VMOVUPD (%RCX,%RBX,8),%YMM8 |
(131) 0x41f94e ADD %R14,%RAX |
(131) 0x41f951 VADDPD -0x8(%RCX,%RBX,8),%YMM5,%YMM6 |
(131) 0x41f957 VADDPD (%RCX,%R13,8),%YMM8,%YMM9 |
(131) 0x41f95d VADDPD %YMM9,%YMM6,%YMM10 |
(131) 0x41f962 VMULPD %YMM4,%YMM10,%YMM11 |
(131) 0x41f966 VMOVUPD %YMM11,(%R15,%RAX,8) |
(131) 0x41f96c TEST $0x3,%DL |
(131) 0x41f96f JE 41fa4f |
(131) 0x41f975 AND $-0x4,%EDX |
(131) 0x41f978 ADD %EDX,%R12D |
(131) 0x41f97b ADD %EDX,%ESI |
(131) 0x41f97d MOVSXD %ESI,%RDX |
(131) 0x41f980 LEA -0x1(%RSI),%EAX |
(131) 0x41f983 MOV 0x28(%RSP),%RBX |
(131) 0x41f988 LEA (%RDX,%R10,1),%R9 |
(131) 0x41f98c CLTQ |
(131) 0x41f98e LEA (%R8,%RDX,1),%R14 |
(131) 0x41f992 LEA (%RCX,%R9,8),%RDI |
(131) 0x41f996 LEA (%R10,%RAX,1),%R11 |
(131) 0x41f99a ADD %R8,%RAX |
(131) 0x41f99d ADD %RBX,%RDX |
(131) 0x41f9a0 VMOVSD (%RCX,%R11,8),%XMM12 |
(131) 0x41f9a6 VMOVSD (%RDI),%XMM14 |
(131) 0x41f9aa LEA (%RCX,%R14,8),%R13 |
(131) 0x41f9ae MOV 0x38(%RSP),%R9D |
(131) 0x41f9b3 VADDSD (%RCX,%RAX,8),%XMM12,%XMM13 |
(131) 0x41f9b8 VADDSD (%R13),%XMM14,%XMM15 |
(131) 0x41f9be LEA 0x1(%RSI),%EAX |
(131) 0x41f9c1 VADDSD %XMM15,%XMM13,%XMM0 |
(131) 0x41f9c6 VMULSD %XMM3,%XMM0,%XMM7 |
(131) 0x41f9ca VMOVSD %XMM7,(%R15,%RDX,8) |
(131) 0x41f9d0 LEA 0x1(%R12),%EDX |
(131) 0x41f9d5 CMP %R9D,%EDX |
(131) 0x41f9d8 JAE 41fa4f |
(131) 0x41f9da CLTQ |
(131) 0x41f9dc VMOVSD (%R13),%XMM1 |
(131) 0x41f9e2 ADD $0x2,%R12D |
(131) 0x41f9e6 ADD $0x2,%ESI |
(131) 0x41f9e9 LEA (%R10,%RAX,1),%R14 |
(131) 0x41f9ed LEA (%R8,%RAX,1),%RDX |
(131) 0x41f9f1 ADD %RBX,%RAX |
(131) 0x41f9f4 LEA (%RCX,%R14,8),%R11 |
(131) 0x41f9f8 LEA (%RCX,%RDX,8),%R14 |
(131) 0x41f9fc VMOVSD (%R14),%XMM6 |
(131) 0x41fa01 VADDSD (%RDI),%XMM1,%XMM5 |
(131) 0x41fa05 VADDSD (%R11),%XMM6,%XMM8 |
(131) 0x41fa0a VADDSD %XMM8,%XMM5,%XMM9 |
(131) 0x41fa0f VMULSD %XMM3,%XMM9,%XMM10 |
(131) 0x41fa13 VMOVSD %XMM10,(%R15,%RAX,8) |
(131) 0x41fa19 CMP %R9D,%R12D |
(131) 0x41fa1c JAE 41fa4f |
(131) 0x41fa1e MOVSXD %ESI,%R12 |
(131) 0x41fa21 ADD %R12,%RBX |
(131) 0x41fa24 ADD %R12,%R10 |
(131) 0x41fa27 ADD %R8,%R12 |
(131) 0x41fa2a VMOVSD (%RCX,%R10,8),%XMM11 |
(131) 0x41fa30 VMOVSD (%RCX,%R12,8),%XMM13 |
(131) 0x41fa36 VADDSD (%R11),%XMM11,%XMM12 |
(131) 0x41fa3b VADDSD (%R14),%XMM13,%XMM14 |
(131) 0x41fa40 VADDSD %XMM14,%XMM12,%XMM15 |
(131) 0x41fa45 VMULSD %XMM3,%XMM15,%XMM0 |
(131) 0x41fa49 VMOVSD %XMM0,(%R15,%RBX,8) |
(131) 0x41fa4f MOV 0x38(%RSP),%R12D |
(131) 0x41fa54 INCQ 0x30(%RSP) |
(131) 0x41fa59 MOV 0x30(%RSP),%RCX |
(131) 0x41fa5e ADD $0,%ECX |
(131) 0x41fa61 CMP %ECX,0x20(%RSP) |
(131) 0x41fa65 JLE 41fa88 |
(131) 0x41fa67 MOV 0x18(%RSP),%EDI |
(131) 0x41fa6b MOV 0x1c(%RSP),%R8D |
(131) 0x41fa70 MOV 0x24(%RSP),%EDX |
(131) 0x41fa74 MOV %R8D,0x3c(%RSP) |
(131) 0x41fa79 SUB %R12D,%EDI |
(131) 0x41fa7c JMP 41f6e0 |
0x41fa81 NOPL (%RAX) |
0x41fa88 VZEROUPPER |
0x41fa8b LEA -0x28(%RBP),%RSP |
0x41fa8f POP %RBX |
0x41fa90 POP %R12 |
0x41fa92 POP %R13 |
0x41fa94 POP %R14 |
0x41fa96 POP %R15 |
0x41fa98 POP %RBP |
0x41fa99 RET |
0x41fa9a NOPW (%RAX,%RAX,1) |
(131) 0x41faa0 MOV 0x3c(%RSP),%ESI |
(131) 0x41faa4 XOR %EAX,%EAX |
(131) 0x41faa6 JMP 41f91d |
0x41faab INC %EDI |
0x41faad XOR %EDX,%EDX |
0x41faaf JMP 41f675 |
0x41fab4 NOPW %CS:(%RAX,%RAX,1) |
0x41fabf NOP |
Path / |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41fa8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41fa8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41faab <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41fa8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x2cecf(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41f675 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41fa8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41fa8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41faab <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41fa8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x2cecf(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41f675 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 0.73 | 0.23 |
▼Loop 131 - advec_mom.cpp:160-160 - exec– | 0.01 | 0 |
○Loop 132 - advec_mom.cpp:160-160 - exec | 0.73 | 0.23 |