Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.74% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.74% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 85 - 88 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
87: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
88: node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0)); |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41d970 PUSH %RBP |
0x41d971 MOV %RSP,%RBP |
0x41d974 PUSH %R15 |
0x41d976 PUSH %R14 |
0x41d978 MOV %RDI,%R14 |
0x41d97b PUSH %R13 |
0x41d97d PUSH %R12 |
0x41d97f PUSH %RBX |
0x41d980 AND $-0x40,%RSP |
0x41d984 SUB $0x40,%RSP |
0x41d988 MOV 0x18(%RDI),%EAX |
0x41d98b MOV 0x1c(%RDI),%EDX |
0x41d98e MOV 0x10(%RDI),%ESI |
0x41d991 MOV 0x14(%R14),%ECX |
0x41d995 ADD $0x3,%EDX |
0x41d998 LEA 0x1(%RAX),%R13D |
0x41d99c LEA -0x1(%RSI),%EDI |
0x41d99f MOV %EDX,0x1c(%RSP) |
0x41d9a3 MOV %EDI,0x18(%RSP) |
0x41d9a7 CMP %EDX,%R13D |
0x41d9aa JGE 41de1b |
0x41d9b0 MOV %EDX,%EBX |
0x41d9b2 LEA 0x4(%RCX),%R15D |
0x41d9b6 SUB %R13D,%EBX |
0x41d9b9 CMP %R15D,%EDI |
0x41d9bc JGE 41de1b |
0x41d9c2 MOV %R15D,%R8D |
0x41d9c5 SUB %EDI,%R8D |
0x41d9c8 MOV %R8D,0x28(%RSP) |
0x41d9cd CALL 4046c0 <omp_get_num_threads@plt> |
0x41d9d2 MOV %EAX,%R12D |
0x41d9d5 CALL 4045b0 <omp_get_thread_num@plt> |
0x41d9da XOR %EDX,%EDX |
0x41d9dc MOV %EAX,%R9D |
0x41d9df MOV 0x28(%RSP),%EAX |
0x41d9e3 IMUL %EBX,%EAX |
0x41d9e6 DIV %R12D |
0x41d9e9 MOV %EAX,%EDI |
0x41d9eb CMP %EDX,%R9D |
0x41d9ee JB 41de3c |
0x41d9f4 IMUL %EDI,%R9D |
0x41d9f8 LEA (%R9,%RDX,1),%R12D |
0x41d9fc LEA (%RDI,%R12,1),%R10D |
0x41da00 MOV %R10D,0x14(%RSP) |
0x41da05 CMP %R10D,%R12D |
0x41da08 JAE 41de1b |
0x41da0e MOV %R12D,%EAX |
0x41da11 XOR %EDX,%EDX |
0x41da13 MOV 0x18(%RSP),%R11D |
0x41da18 MOV (%R14),%RSI |
0x41da1b DIVL 0x28(%RSP) |
0x41da1f MOV 0x8(%R14),%R14 |
0x41da23 VMOVSD 0x2eb4d(%RIP),%XMM3 |
0x41da2b MOV %RSI,0x8(%RSP) |
0x41da30 MOV %R14,(%RSP) |
0x41da34 VBROADCASTSD %XMM3,%YMM4 |
0x41da39 VBROADCASTSD %XMM3,%ZMM2 |
0x41da3f ADD %R13D,%EAX |
0x41da42 ADD %EDX,%R11D |
0x41da45 MOV %R15D,%EDX |
0x41da48 MOV %EAX,0x38(%RSP) |
0x41da4c CLTQ |
0x41da4e SUB %R11D,%EDX |
0x41da51 MOV %R11D,0x3c(%RSP) |
0x41da56 MOV %RAX,0x20(%RSP) |
0x41da5b NOPL (%RAX,%RAX,1) |
(122) 0x41da60 CMP %EDX,%EDI |
(122) 0x41da62 CMOVBE %EDI,%EDX |
(122) 0x41da65 LEA (%R12,%RDX,1),%R13D |
(122) 0x41da69 MOV %R13D,0x2c(%RSP) |
(122) 0x41da6e CMP %R13D,%R12D |
(122) 0x41da71 JAE 41dde6 |
(122) 0x41da77 MOV 0x8(%RSP),%RDI |
(122) 0x41da7c MOV 0x38(%RSP),%R15D |
(122) 0x41da81 LEA -0x1(%RDX),%R9D |
(122) 0x41da85 MOV 0x20(%RSP),%R10 |
(122) 0x41da8a MOV (%RSP),%R8 |
(122) 0x41da8e LEA -0x1(%R15),%EBX |
(122) 0x41da92 MOV 0x10(%RDI),%RCX |
(122) 0x41da96 MOV (%RDI),%RDI |
(122) 0x41da99 MOVSXD %EBX,%RSI |
(122) 0x41da9c MOV 0x10(%R8),%R15 |
(122) 0x41daa0 IMUL %RDI,%RSI |
(122) 0x41daa4 IMUL %R10,%RDI |
(122) 0x41daa8 IMUL (%R8),%R10 |
(122) 0x41daac MOV %R10,0x30(%RSP) |
(122) 0x41dab1 CMP $0x6,%R9D |
(122) 0x41dab5 JBE 41de30 |
(122) 0x41dabb MOV %EDX,%R9D |
(122) 0x41dabe MOVSXD 0x3c(%RSP),%RAX |
(122) 0x41dac3 SHR $0x3,%R9D |
(122) 0x41dac7 SAL $0x6,%R9 |
(122) 0x41dacb LEA (%RSI,%RAX,1),%R11 |
(122) 0x41dacf LEA (%RDI,%RAX,1),%RBX |
(122) 0x41dad3 ADD %R10,%RAX |
(122) 0x41dad6 LEA -0x40(%R9),%R8 |
(122) 0x41dada SAL $0x3,%R11 |
(122) 0x41dade SAL $0x3,%RBX |
(122) 0x41dae2 LEA (%R15,%RAX,8),%R10 |
(122) 0x41dae6 SHR $0x6,%R8 |
(122) 0x41daea LEA (%RCX,%R11,1),%R13 |
(122) 0x41daee LEA (%RCX,%RBX,1),%R14 |
(122) 0x41daf2 XOR %EAX,%EAX |
(122) 0x41daf4 INC %R8 |
(122) 0x41daf7 LEA 0x8(%RCX,%R11,1),%R11 |
(122) 0x41dafc LEA 0x8(%RCX,%RBX,1),%RBX |
(122) 0x41db01 AND $0x3,%R8D |
(122) 0x41db05 JE 41dbb8 |
(122) 0x41db0b CMP $0x1,%R8 |
(122) 0x41db0f JE 41db7b |
(122) 0x41db11 CMP $0x2,%R8 |
(122) 0x41db15 JE 41db47 |
(122) 0x41db17 VMOVUPD (%R13),%ZMM7 |
(122) 0x41db1e VMOVUPD (%R11),%ZMM1 |
(122) 0x41db24 MOV $0x40,%EAX |
(122) 0x41db29 VADDPD (%R14),%ZMM7,%ZMM0 |
(122) 0x41db2f VADDPD (%RBX),%ZMM1,%ZMM5 |
(122) 0x41db35 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(122) 0x41db3b VMULPD %ZMM2,%ZMM6,%ZMM8 |
(122) 0x41db41 VMOVUPD %ZMM8,(%R10) |
(122) 0x41db47 VMOVUPD (%R13,%RAX,1),%ZMM9 |
(122) 0x41db4f VMOVUPD (%R11,%RAX,1),%ZMM11 |
(122) 0x41db56 VADDPD (%R14,%RAX,1),%ZMM9,%ZMM10 |
(122) 0x41db5d VADDPD (%RBX,%RAX,1),%ZMM11,%ZMM12 |
(122) 0x41db64 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(122) 0x41db6a VMULPD %ZMM2,%ZMM13,%ZMM14 |
(122) 0x41db70 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(122) 0x41db77 ADD $0x40,%RAX |
(122) 0x41db7b VMOVUPD (%R13,%RAX,1),%ZMM15 |
(122) 0x41db83 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(122) 0x41db8a VADDPD (%R14,%RAX,1),%ZMM15,%ZMM0 |
(122) 0x41db91 VADDPD (%RBX,%RAX,1),%ZMM7,%ZMM1 |
(122) 0x41db98 VADDPD %ZMM1,%ZMM0,%ZMM5 |
(122) 0x41db9e VMULPD %ZMM2,%ZMM5,%ZMM6 |
(122) 0x41dba4 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(122) 0x41dbab ADD $0x40,%RAX |
(122) 0x41dbaf CMP %RAX,%R9 |
(122) 0x41dbb2 JE 41dc93 |
(123) 0x41dbb8 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(123) 0x41dbc0 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(123) 0x41dbc7 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM9 |
(123) 0x41dbce VADDPD (%RBX,%RAX,1),%ZMM10,%ZMM11 |
(123) 0x41dbd5 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(123) 0x41dbdb VMULPD %ZMM2,%ZMM12,%ZMM13 |
(123) 0x41dbe1 VMOVUPD %ZMM13,(%R10,%RAX,1) |
(123) 0x41dbe8 VMOVUPD 0x40(%R13,%RAX,1),%ZMM14 |
(123) 0x41dbf0 VMOVUPD 0x40(%R11,%RAX,1),%ZMM0 |
(123) 0x41dbf8 VADDPD 0x40(%R14,%RAX,1),%ZMM14,%ZMM15 |
(123) 0x41dc00 VADDPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM7 |
(123) 0x41dc08 VADDPD %ZMM7,%ZMM15,%ZMM1 |
(123) 0x41dc0e VMULPD %ZMM2,%ZMM1,%ZMM5 |
(123) 0x41dc14 VMOVUPD %ZMM5,0x40(%R10,%RAX,1) |
(123) 0x41dc1c VMOVUPD 0x80(%R13,%RAX,1),%ZMM6 |
(123) 0x41dc24 VMOVUPD 0x80(%R11,%RAX,1),%ZMM9 |
(123) 0x41dc2c VADDPD 0x80(%R14,%RAX,1),%ZMM6,%ZMM8 |
(123) 0x41dc34 VADDPD 0x80(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(123) 0x41dc3c VADDPD %ZMM10,%ZMM8,%ZMM11 |
(123) 0x41dc42 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(123) 0x41dc48 VMOVUPD %ZMM12,0x80(%R10,%RAX,1) |
(123) 0x41dc50 VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 |
(123) 0x41dc58 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM15 |
(123) 0x41dc60 VADDPD 0xc0(%R14,%RAX,1),%ZMM13,%ZMM14 |
(123) 0x41dc68 VADDPD 0xc0(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(123) 0x41dc70 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(123) 0x41dc76 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(123) 0x41dc7c VMOVUPD %ZMM1,0xc0(%R10,%RAX,1) |
(123) 0x41dc84 ADD $0x100,%RAX |
(123) 0x41dc8a CMP %RAX,%R9 |
(123) 0x41dc8d JNE 41dbb8 |
(122) 0x41dc93 MOV 0x3c(%RSP),%EAX |
(122) 0x41dc97 MOV %EDX,%R14D |
(122) 0x41dc9a AND $-0x8,%R14D |
(122) 0x41dc9e ADD %R14D,%R12D |
(122) 0x41dca1 ADD %R14D,%EAX |
(122) 0x41dca4 TEST $0x7,%DL |
(122) 0x41dca7 JE 41dde1 |
(122) 0x41dcad SUB %R14D,%EDX |
(122) 0x41dcb0 LEA -0x1(%RDX),%R13D |
(122) 0x41dcb4 CMP $0x2,%R13D |
(122) 0x41dcb8 JBE 41dd10 |
(122) 0x41dcba MOVSXD 0x3c(%RSP),%R9 |
(122) 0x41dcbf MOV 0x30(%RSP),%R10 |
(122) 0x41dcc4 LEA (%RSI,%R9,1),%RBX |
(122) 0x41dcc8 LEA (%RDI,%R9,1),%R11 |
(122) 0x41dccc ADD %R10,%R9 |
(122) 0x41dccf ADD %R14,%RBX |
(122) 0x41dcd2 ADD %R14,%R11 |
(122) 0x41dcd5 ADD %R14,%R9 |
(122) 0x41dcd8 VMOVUPD 0x8(%RCX,%RBX,8),%YMM5 |
(122) 0x41dcde VMOVUPD (%RCX,%R11,8),%YMM8 |
(122) 0x41dce4 VADDPD 0x8(%RCX,%R11,8),%YMM5,%YMM6 |
(122) 0x41dceb VADDPD (%RCX,%RBX,8),%YMM8,%YMM9 |
(122) 0x41dcf0 VADDPD %YMM9,%YMM6,%YMM10 |
(122) 0x41dcf5 VMULPD %YMM4,%YMM10,%YMM11 |
(122) 0x41dcf9 VMOVUPD %YMM11,(%R15,%R9,8) |
(122) 0x41dcff TEST $0x3,%DL |
(122) 0x41dd02 JE 41dde1 |
(122) 0x41dd08 AND $-0x4,%EDX |
(122) 0x41dd0b ADD %EDX,%R12D |
(122) 0x41dd0e ADD %EDX,%EAX |
(122) 0x41dd10 LEA 0x1(%RAX),%R14D |
(122) 0x41dd14 MOVSXD %EAX,%RDX |
(122) 0x41dd17 MOVSXD %R14D,%R8 |
(122) 0x41dd1a MOV 0x30(%RSP),%R14 |
(122) 0x41dd1f LEA (%R8,%RSI,1),%R13 |
(122) 0x41dd23 LEA (%R8,%RDI,1),%RBX |
(122) 0x41dd27 LEA (%RCX,%R13,8),%R9 |
(122) 0x41dd2b LEA (%RDI,%RDX,1),%R13 |
(122) 0x41dd2f VMOVSD (%RCX,%R13,8),%XMM12 |
(122) 0x41dd35 VMOVSD (%R9),%XMM14 |
(122) 0x41dd3a LEA (%R14,%RDX,1),%R11 |
(122) 0x41dd3e LEA (%RCX,%RBX,8),%R10 |
(122) 0x41dd42 ADD %RSI,%RDX |
(122) 0x41dd45 MOV 0x2c(%RSP),%R13D |
(122) 0x41dd4a VADDSD (%RCX,%RDX,8),%XMM12,%XMM13 |
(122) 0x41dd4f VADDSD (%R10),%XMM14,%XMM15 |
(122) 0x41dd54 LEA 0x1(%R12),%EDX |
(122) 0x41dd59 VADDSD %XMM15,%XMM13,%XMM0 |
(122) 0x41dd5e VMULSD %XMM3,%XMM0,%XMM7 |
(122) 0x41dd62 VMOVSD %XMM7,(%R15,%R11,8) |
(122) 0x41dd68 CMP %R13D,%EDX |
(122) 0x41dd6b JAE 41dde1 |
(122) 0x41dd6d LEA 0x2(%RAX),%EBX |
(122) 0x41dd70 VMOVSD (%R10),%XMM1 |
(122) 0x41dd75 ADD %R14,%R8 |
(122) 0x41dd78 ADD $0x2,%R12D |
(122) 0x41dd7c MOVSXD %EBX,%RDX |
(122) 0x41dd7f LEA (%RSI,%RDX,1),%R11 |
(122) 0x41dd83 VADDSD (%R9),%XMM1,%XMM5 |
(122) 0x41dd88 LEA (%RCX,%R11,8),%RBX |
(122) 0x41dd8c LEA (%RDI,%RDX,1),%R11 |
(122) 0x41dd90 LEA (%RCX,%R11,8),%R11 |
(122) 0x41dd94 VMOVSD (%R11),%XMM6 |
(122) 0x41dd99 VADDSD (%RBX),%XMM6,%XMM8 |
(122) 0x41dd9d VADDSD %XMM8,%XMM5,%XMM9 |
(122) 0x41dda2 VMULSD %XMM3,%XMM9,%XMM10 |
(122) 0x41dda6 VMOVSD %XMM10,(%R15,%R8,8) |
(122) 0x41ddac CMP %R13D,%R12D |
(122) 0x41ddaf JAE 41dde1 |
(122) 0x41ddb1 ADD $0x3,%EAX |
(122) 0x41ddb4 VMOVSD (%RBX),%XMM13 |
(122) 0x41ddb8 ADD %RDX,%R14 |
(122) 0x41ddbb CLTQ |
(122) 0x41ddbd ADD %RAX,%RSI |
(122) 0x41ddc0 ADD %RDI,%RAX |
(122) 0x41ddc3 VADDSD (%R11),%XMM13,%XMM14 |
(122) 0x41ddc8 VMOVSD (%RCX,%RSI,8),%XMM11 |
(122) 0x41ddcd VADDSD (%RCX,%RAX,8),%XMM11,%XMM12 |
(122) 0x41ddd2 VADDSD %XMM14,%XMM12,%XMM15 |
(122) 0x41ddd7 VMULSD %XMM3,%XMM15,%XMM0 |
(122) 0x41dddb VMOVSD %XMM0,(%R15,%R14,8) |
(122) 0x41dde1 MOV 0x2c(%RSP),%R12D |
(122) 0x41dde6 INCL 0x38(%RSP) |
(122) 0x41ddea INCQ 0x20(%RSP) |
(122) 0x41ddef MOV 0x38(%RSP),%ECX |
(122) 0x41ddf3 CMP %ECX,0x1c(%RSP) |
(122) 0x41ddf7 JLE 41de18 |
(122) 0x41ddf9 MOV 0x14(%RSP),%EDI |
(122) 0x41ddfd MOV 0x18(%RSP),%ESI |
(122) 0x41de01 MOV 0x28(%RSP),%EDX |
(122) 0x41de05 MOV %ESI,0x3c(%RSP) |
(122) 0x41de09 SUB %R12D,%EDI |
(122) 0x41de0c JMP 41da60 |
0x41de11 NOPL (%RAX) |
0x41de18 VZEROUPPER |
0x41de1b LEA -0x28(%RBP),%RSP |
0x41de1f POP %RBX |
0x41de20 POP %R12 |
0x41de22 POP %R13 |
0x41de24 POP %R14 |
0x41de26 POP %R15 |
0x41de28 POP %RBP |
0x41de29 RET |
0x41de2a NOPW (%RAX,%RAX,1) |
(122) 0x41de30 MOV 0x3c(%RSP),%EAX |
(122) 0x41de34 XOR %R14D,%R14D |
(122) 0x41de37 JMP 41dcad |
0x41de3c INC %EDI |
0x41de3e XOR %EDX,%EDX |
0x41de40 JMP 41d9f4 |
0x41de45 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41de1b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41de1b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41de3c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41de1b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x2eb4d(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41d9f4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41de1b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 41de1b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 41de3c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 41de1b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x2eb4d(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 41d9f4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 0.74 | 0.24 |
▼Loop 122 - advec_mom.cpp:87-88 - exec– | 0.01 | 0 |
○Loop 123 - advec_mom.cpp:88-88 - exec | 0.74 | 0.23 |