Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4] [clone .lto_priv.0] | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
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Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4] [clone .lto_priv.0] | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
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/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp: 77 - 82 |
-------------------------------------------------------------------------------- |
77: #pragma omp parallel for simd collapse(2) |
78: for (int j = (0); j < (yrange1); j++) { |
79: for (int i = (0); i < (xrange1); i++) { |
80: field.volume(i, j) = dx * dy; |
81: field.xarea(i, j) = field.celldy[j]; |
82: field.yarea(i, j) = field.celldx[i]; |
/scratch_na/users/xoserete/qaas_runs/171-320-5323/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42f230 PUSH %RBP |
0x42f231 MOV %RSP,%RBP |
0x42f234 PUSH %R15 |
0x42f236 PUSH %R14 |
0x42f238 PUSH %R13 |
0x42f23a PUSH %R12 |
0x42f23c PUSH %RBX |
0x42f23d AND $-0x40,%RSP |
0x42f241 SUB $0x40,%RSP |
0x42f245 MOV 0x1c(%RDI),%R14D |
0x42f249 MOV 0x18(%RDI),%R15D |
0x42f24d MOV %R14D,0x10(%RSP) |
0x42f252 MOV %R15D,0x4(%RSP) |
0x42f257 TEST %R14D,%R14D |
0x42f25a JLE 42f7b3 |
0x42f260 TEST %R15D,%R15D |
0x42f263 JLE 42f7b3 |
0x42f269 MOV %RDI,%R12 |
0x42f26c CALL 4046c0 <omp_get_num_threads@plt> |
0x42f271 MOV %EAX,%EBX |
0x42f273 CALL 4045b0 <omp_get_thread_num@plt> |
0x42f278 XOR %EDX,%EDX |
0x42f27a MOV %EAX,%ESI |
0x42f27c MOV %R14D,%EAX |
0x42f27f IMUL %R15D,%EAX |
0x42f283 DIV %EBX |
0x42f285 MOV %EAX,%ECX |
0x42f287 CMP %EDX,%ESI |
0x42f289 JB 42f7d4 |
0x42f28f IMUL %ECX,%ESI |
0x42f292 LEA (%RSI,%RDX,1),%R10D |
0x42f296 LEA (%RCX,%R10,1),%EDI |
0x42f29a MOV %EDI,(%RSP) |
0x42f29d CMP %EDI,%R10D |
0x42f2a0 JAE 42f7b3 |
0x42f2a6 MOV 0x4(%RSP),%R8D |
0x42f2ab MOV %R10D,%EAX |
0x42f2ae XOR %EDX,%EDX |
0x42f2b0 VMOVSD 0x8(%R12),%XMM2 |
0x42f2b7 MOV 0x10(%R12),%R13 |
0x42f2bc DIV %R8D |
0x42f2bf VMULSD (%R12),%XMM2,%XMM8 |
0x42f2c5 VBROADCASTSD %XMM8,%YMM3 |
0x42f2ca VBROADCASTSD %XMM8,%ZMM0 |
0x42f2d0 SUB %EDX,%R8D |
0x42f2d3 MOV %EDX,0x30(%RSP) |
0x42f2d7 MOVSXD %EAX,%RBX |
0x42f2da MOV %R8D,%EDX |
0x42f2dd NOPL (%RAX) |
(197) 0x42f2e0 CMP %EDX,%ECX |
(197) 0x42f2e2 CMOVBE %ECX,%EDX |
(197) 0x42f2e5 LEA (%R10,%RDX,1),%ECX |
(197) 0x42f2e9 MOV %ECX,0x14(%RSP) |
(197) 0x42f2ed CMP %ECX,%R10D |
(197) 0x42f2f0 JAE 42f788 |
(197) 0x42f2f6 MOV 0x290(%R13),%R11 |
(197) 0x42f2fd MOV 0x2a8(%R13),%RDI |
(197) 0x42f304 LEA -0x1(%RDX),%R8D |
(197) 0x42f308 MOV 0x2c0(%R13),%RAX |
(197) 0x42f30f MOV 0x248(%R13),%R9 |
(197) 0x42f316 IMUL %RBX,%R11 |
(197) 0x42f31a MOV 0x2d0(%R13),%RSI |
(197) 0x42f321 MOV 0x2a0(%R13),%R15 |
(197) 0x42f328 IMUL %RBX,%RDI |
(197) 0x42f32c MOV 0x2b8(%R13),%R14 |
(197) 0x42f333 MOV 0x228(%R13),%R12 |
(197) 0x42f33a LEA (%R9,%RBX,8),%RCX |
(197) 0x42f33e IMUL %RBX,%RAX |
(197) 0x42f342 MOV %RSI,0x38(%RSP) |
(197) 0x42f347 MOV %R11,0x18(%RSP) |
(197) 0x42f34c MOV %RDI,0x20(%RSP) |
(197) 0x42f351 MOV %RAX,0x28(%RSP) |
(197) 0x42f356 CMP $0x6,%R8D |
(197) 0x42f35a JBE 42f7c8 |
(197) 0x42f360 MOVSXD 0x30(%RSP),%RAX |
(197) 0x42f365 LEA (%RDI,%RAX,1),%RSI |
(197) 0x42f369 MOV 0x28(%RSP),%RDI |
(197) 0x42f36e LEA (%R11,%RAX,1),%R11 |
(197) 0x42f372 LEA (%R14,%RSI,8),%R9 |
(197) 0x42f376 MOV 0x38(%RSP),%RSI |
(197) 0x42f37b LEA (%R12,%RAX,8),%R8 |
(197) 0x42f37f ADD %RDI,%RAX |
(197) 0x42f382 LEA (%R15,%R11,8),%R11 |
(197) 0x42f386 LEA (%RSI,%RAX,8),%RDI |
(197) 0x42f38a MOV %EDX,%ESI |
(197) 0x42f38c XOR %EAX,%EAX |
(197) 0x42f38e SHR $0x3,%ESI |
(197) 0x42f391 SAL $0x6,%RSI |
(197) 0x42f395 MOV %RSI,0x8(%RSP) |
(197) 0x42f39a SUB $0x40,%RSI |
(197) 0x42f39e SHR $0x6,%RSI |
(197) 0x42f3a2 INC %RSI |
(197) 0x42f3a5 AND $0x7,%ESI |
(197) 0x42f3a8 JE 42f4f0 |
(197) 0x42f3ae CMP $0x1,%RSI |
(197) 0x42f3b2 JE 42f4bf |
(197) 0x42f3b8 CMP $0x2,%RSI |
(197) 0x42f3bc JE 42f499 |
(197) 0x42f3c2 CMP $0x3,%RSI |
(197) 0x42f3c6 JE 42f473 |
(197) 0x42f3cc CMP $0x4,%RSI |
(197) 0x42f3d0 JE 42f44d |
(197) 0x42f3d2 CMP $0x5,%RSI |
(197) 0x42f3d6 JE 42f427 |
(197) 0x42f3d8 CMP $0x6,%RSI |
(197) 0x42f3dc JE 42f401 |
(197) 0x42f3de VMOVUPD %ZMM0,(%R11) |
(197) 0x42f3e4 MOV $0x40,%EAX |
(197) 0x42f3e9 VBROADCASTSD (%RCX),%ZMM1 |
(197) 0x42f3ef VMOVUPD %ZMM1,(%R9) |
(197) 0x42f3f5 VMOVUPD (%R8),%ZMM5 |
(197) 0x42f3fb VMOVUPD %ZMM5,(%RDI) |
(197) 0x42f401 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(197) 0x42f408 VBROADCASTSD (%RCX),%ZMM4 |
(197) 0x42f40e VMOVUPD %ZMM4,(%R9,%RAX,1) |
(197) 0x42f415 VMOVUPD (%R8,%RAX,1),%ZMM7 |
(197) 0x42f41c VMOVUPD %ZMM7,(%RDI,%RAX,1) |
(197) 0x42f423 ADD $0x40,%RAX |
(197) 0x42f427 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(197) 0x42f42e VBROADCASTSD (%RCX),%ZMM6 |
(197) 0x42f434 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(197) 0x42f43b VMOVUPD (%R8,%RAX,1),%ZMM9 |
(197) 0x42f442 VMOVUPD %ZMM9,(%RDI,%RAX,1) |
(197) 0x42f449 ADD $0x40,%RAX |
(197) 0x42f44d VMOVUPD %ZMM0,(%R11,%RAX,1) |
(197) 0x42f454 VBROADCASTSD (%RCX),%ZMM10 |
(197) 0x42f45a VMOVUPD %ZMM10,(%R9,%RAX,1) |
(197) 0x42f461 VMOVUPD (%R8,%RAX,1),%ZMM11 |
(197) 0x42f468 VMOVUPD %ZMM11,(%RDI,%RAX,1) |
(197) 0x42f46f ADD $0x40,%RAX |
(197) 0x42f473 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(197) 0x42f47a VBROADCASTSD (%RCX),%ZMM12 |
(197) 0x42f480 VMOVUPD %ZMM12,(%R9,%RAX,1) |
(197) 0x42f487 VMOVUPD (%R8,%RAX,1),%ZMM13 |
(197) 0x42f48e VMOVUPD %ZMM13,(%RDI,%RAX,1) |
(197) 0x42f495 ADD $0x40,%RAX |
(197) 0x42f499 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(197) 0x42f4a0 VBROADCASTSD (%RCX),%ZMM14 |
(197) 0x42f4a6 VMOVUPD %ZMM14,(%R9,%RAX,1) |
(197) 0x42f4ad VMOVUPD (%R8,%RAX,1),%ZMM15 |
(197) 0x42f4b4 VMOVUPD %ZMM15,(%RDI,%RAX,1) |
(197) 0x42f4bb ADD $0x40,%RAX |
(197) 0x42f4bf VMOVUPD %ZMM0,(%R11,%RAX,1) |
(197) 0x42f4c6 VBROADCASTSD (%RCX),%ZMM2 |
(197) 0x42f4cc VMOVUPD %ZMM2,(%R9,%RAX,1) |
(197) 0x42f4d3 VMOVUPD (%R8,%RAX,1),%ZMM1 |
(197) 0x42f4da VMOVUPD %ZMM1,(%RDI,%RAX,1) |
(197) 0x42f4e1 ADD $0x40,%RAX |
(197) 0x42f4e5 CMP %RAX,0x8(%RSP) |
(197) 0x42f4ea JE 42f62d |
(198) 0x42f4f0 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(198) 0x42f4f7 VBROADCASTSD (%RCX),%ZMM5 |
(198) 0x42f4fd VMOVUPD %ZMM5,(%R9,%RAX,1) |
(198) 0x42f504 VMOVUPD (%R8,%RAX,1),%ZMM4 |
(198) 0x42f50b VMOVUPD %ZMM4,(%RDI,%RAX,1) |
(198) 0x42f512 VMOVUPD %ZMM0,0x40(%R11,%RAX,1) |
(198) 0x42f51a VBROADCASTSD (%RCX),%ZMM7 |
(198) 0x42f520 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(198) 0x42f528 VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 |
(198) 0x42f530 VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) |
(198) 0x42f538 VMOVUPD %ZMM0,0x80(%R11,%RAX,1) |
(198) 0x42f540 VBROADCASTSD (%RCX),%ZMM9 |
(198) 0x42f546 VMOVUPD %ZMM9,0x80(%R9,%RAX,1) |
(198) 0x42f54e VMOVUPD 0x80(%R8,%RAX,1),%ZMM10 |
(198) 0x42f556 VMOVUPD %ZMM10,0x80(%RDI,%RAX,1) |
(198) 0x42f55e VMOVUPD %ZMM0,0xc0(%R11,%RAX,1) |
(198) 0x42f566 VBROADCASTSD (%RCX),%ZMM11 |
(198) 0x42f56c VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(198) 0x42f574 VMOVUPD 0xc0(%R8,%RAX,1),%ZMM12 |
(198) 0x42f57c VMOVUPD %ZMM12,0xc0(%RDI,%RAX,1) |
(198) 0x42f584 VMOVUPD %ZMM0,0x100(%R11,%RAX,1) |
(198) 0x42f58c VBROADCASTSD (%RCX),%ZMM13 |
(198) 0x42f592 VMOVUPD %ZMM13,0x100(%R9,%RAX,1) |
(198) 0x42f59a VMOVUPD 0x100(%R8,%RAX,1),%ZMM14 |
(198) 0x42f5a2 VMOVUPD %ZMM14,0x100(%RDI,%RAX,1) |
(198) 0x42f5aa VMOVUPD %ZMM0,0x140(%R11,%RAX,1) |
(198) 0x42f5b2 VBROADCASTSD (%RCX),%ZMM15 |
(198) 0x42f5b8 VMOVUPD %ZMM15,0x140(%R9,%RAX,1) |
(198) 0x42f5c0 VMOVUPD 0x140(%R8,%RAX,1),%ZMM2 |
(198) 0x42f5c8 VMOVUPD %ZMM2,0x140(%RDI,%RAX,1) |
(198) 0x42f5d0 VMOVUPD %ZMM0,0x180(%R11,%RAX,1) |
(198) 0x42f5d8 VBROADCASTSD (%RCX),%ZMM1 |
(198) 0x42f5de VMOVUPD %ZMM1,0x180(%R9,%RAX,1) |
(198) 0x42f5e6 VMOVUPD 0x180(%R8,%RAX,1),%ZMM5 |
(198) 0x42f5ee VMOVUPD %ZMM5,0x180(%RDI,%RAX,1) |
(198) 0x42f5f6 VMOVUPD %ZMM0,0x1c0(%R11,%RAX,1) |
(198) 0x42f5fe VBROADCASTSD (%RCX),%ZMM4 |
(198) 0x42f604 VMOVUPD %ZMM4,0x1c0(%R9,%RAX,1) |
(198) 0x42f60c VMOVUPD 0x1c0(%R8,%RAX,1),%ZMM7 |
(198) 0x42f614 VMOVUPD %ZMM7,0x1c0(%RDI,%RAX,1) |
(198) 0x42f61c ADD $0x200,%RAX |
(198) 0x42f622 CMP %RAX,0x8(%RSP) |
(198) 0x42f627 JNE 42f4f0 |
(197) 0x42f62d MOV 0x30(%RSP),%R11D |
(197) 0x42f632 MOV %EDX,%R9D |
(197) 0x42f635 AND $-0x8,%R9D |
(197) 0x42f639 ADD %R9D,%R10D |
(197) 0x42f63c LEA (%R9,%R11,1),%EDI |
(197) 0x42f640 TEST $0x7,%DL |
(197) 0x42f643 JE 42f783 |
(197) 0x42f649 SUB %R9D,%EDX |
(197) 0x42f64c LEA -0x1(%RDX),%R8D |
(197) 0x42f650 CMP $0x2,%R8D |
(197) 0x42f654 JBE 42f6b9 |
(197) 0x42f656 MOVSXD 0x30(%RSP),%RAX |
(197) 0x42f65b MOV 0x18(%RSP),%RSI |
(197) 0x42f660 MOV 0x20(%RSP),%R8 |
(197) 0x42f665 VMOVSD (%RCX),%XMM6 |
(197) 0x42f669 LEA (%RSI,%RAX,1),%R11 |
(197) 0x42f66d LEA (%R8,%RAX,1),%RSI |
(197) 0x42f671 MOV 0x28(%RSP),%R8 |
(197) 0x42f676 ADD %R9,%R11 |
(197) 0x42f679 VBROADCASTSD %XMM6,%YMM9 |
(197) 0x42f67e ADD %R9,%RSI |
(197) 0x42f681 VMOVUPD %YMM3,(%R15,%R11,8) |
(197) 0x42f687 LEA (%RAX,%R9,1),%R11 |
(197) 0x42f68b VMOVUPD %YMM9,(%R14,%RSI,8) |
(197) 0x42f691 ADD %R8,%RAX |
(197) 0x42f694 ADD %R9,%RAX |
(197) 0x42f697 VMOVUPD (%R12,%R11,8),%YMM10 |
(197) 0x42f69d MOV 0x38(%RSP),%R9 |
(197) 0x42f6a2 VMOVUPD %YMM10,(%R9,%RAX,8) |
(197) 0x42f6a8 TEST $0x3,%DL |
(197) 0x42f6ab JE 42f783 |
(197) 0x42f6b1 AND $-0x4,%EDX |
(197) 0x42f6b4 ADD %EDX,%R10D |
(197) 0x42f6b7 ADD %EDX,%EDI |
(197) 0x42f6b9 MOV 0x18(%RSP),%R9 |
(197) 0x42f6be MOVSXD %EDI,%RAX |
(197) 0x42f6c1 MOV 0x20(%RSP),%R11 |
(197) 0x42f6c6 LEA (,%RAX,8),%R8 |
(197) 0x42f6ce LEA (%R9,%RAX,1),%RDX |
(197) 0x42f6d2 LEA (%R11,%RAX,1),%RSI |
(197) 0x42f6d6 MOV %R8,0x30(%RSP) |
(197) 0x42f6db MOV 0x28(%RSP),%R8 |
(197) 0x42f6e0 VMOVSD %XMM8,(%R15,%RDX,8) |
(197) 0x42f6e6 MOV 0x38(%RSP),%RDX |
(197) 0x42f6eb VMOVSD (%RCX),%XMM11 |
(197) 0x42f6ef VMOVSD %XMM11,(%R14,%RSI,8) |
(197) 0x42f6f5 LEA 0x1(%R10),%ESI |
(197) 0x42f6f9 VMOVSD (%R12,%RAX,8),%XMM12 |
(197) 0x42f6ff ADD %R8,%RAX |
(197) 0x42f702 VMOVSD %XMM12,(%RDX,%RAX,8) |
(197) 0x42f707 MOV 0x14(%RSP),%EDX |
(197) 0x42f70b LEA 0x1(%RDI),%EAX |
(197) 0x42f70e CMP %EDX,%ESI |
(197) 0x42f710 JAE 42f783 |
(197) 0x42f712 CLTQ |
(197) 0x42f714 ADD $0x2,%R10D |
(197) 0x42f718 ADD $0x2,%EDI |
(197) 0x42f71b LEA (%R9,%RAX,1),%RSI |
(197) 0x42f71f VMOVSD %XMM8,(%R15,%RSI,8) |
(197) 0x42f725 LEA (%R11,%RAX,1),%RSI |
(197) 0x42f729 ADD %R8,%RAX |
(197) 0x42f72c VMOVSD (%RCX),%XMM13 |
(197) 0x42f730 VMOVSD %XMM13,(%R14,%RSI,8) |
(197) 0x42f736 MOV 0x30(%RSP),%RSI |
(197) 0x42f73b VMOVSD 0x8(%R12,%RSI,1),%XMM14 |
(197) 0x42f742 MOV %R8,%RSI |
(197) 0x42f745 MOV 0x38(%RSP),%R8 |
(197) 0x42f74a VMOVSD %XMM14,(%R8,%RAX,8) |
(197) 0x42f750 CMP %EDX,%R10D |
(197) 0x42f753 JAE 42f783 |
(197) 0x42f755 MOVSXD %EDI,%R10 |
(197) 0x42f758 ADD %R10,%R9 |
(197) 0x42f75b ADD %R10,%R11 |
(197) 0x42f75e ADD %R10,%RSI |
(197) 0x42f761 VMOVSD %XMM8,(%R15,%R9,8) |
(197) 0x42f767 MOV 0x30(%RSP),%R15 |
(197) 0x42f76c VMOVSD (%RCX),%XMM15 |
(197) 0x42f770 VMOVSD %XMM15,(%R14,%R11,8) |
(197) 0x42f776 VMOVSD 0x10(%R12,%R15,1),%XMM2 |
(197) 0x42f77d VMOVSD %XMM2,(%R8,%RSI,8) |
(197) 0x42f783 MOV 0x14(%RSP),%R10D |
(197) 0x42f788 INC %RBX |
(197) 0x42f78b CMP %EBX,0x10(%RSP) |
(197) 0x42f78f JLE 42f7b0 |
(197) 0x42f791 MOV (%RSP),%ECX |
(197) 0x42f794 MOV 0x4(%RSP),%EDX |
(197) 0x42f798 MOVL $0,0x30(%RSP) |
(197) 0x42f7a0 SUB %R10D,%ECX |
(197) 0x42f7a3 JMP 42f2e0 |
0x42f7a8 NOPL (%RAX,%RAX,1) |
0x42f7b0 VZEROUPPER |
0x42f7b3 LEA -0x28(%RBP),%RSP |
0x42f7b7 POP %RBX |
0x42f7b8 POP %R12 |
0x42f7ba POP %R13 |
0x42f7bc POP %R14 |
0x42f7be POP %R15 |
0x42f7c0 POP %RBP |
0x42f7c1 RET |
0x42f7c2 NOPW (%RAX,%RAX,1) |
(197) 0x42f7c8 MOV 0x30(%RSP),%EDI |
(197) 0x42f7cc XOR %R9D,%R9D |
(197) 0x42f7cf JMP 42f649 |
0x42f7d4 INC %ECX |
0x42f7d6 XOR %EDX,%EDX |
0x42f7d8 JMP 42f28f |
0x42f7dd NOPL (%RAX) |
Path / |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42f7b3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42f7b3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42f7d4 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42f7b3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42f28f <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42f7b3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 42f7b3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42f7d4 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42f7b3 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42f28f <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4] [clone .lto_priv.0]– | 0.03 | 0.01 |
▼Loop 197 - initialise_chunk.cpp:77-82 - exec– | 0 | 0 |
○Loop 198 - initialise_chunk.cpp:80-82 - exec | 0.03 | 0.01 |