OV - - Function .omp_outlined..576

	Function: .omp_outlined..576	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage: 3.59%

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x260a10 PUSH	%RBP

0x260a11 MOV	%RSP,%RBP

0x260a14 PUSH	%R15

0x260a16 PUSH	%R14

0x260a18 PUSH	%R13

0x260a1a PUSH	%R12

0x260a1c PUSH	%RBX

0x260a1d SUB	$0x68,%RSP

0x260a21 MOV	(%RDX),%EAX

0x260a23 MOV	%RAX,-0x68(%RBP)

0x260a27 INC	%EAX

0x260a29 MOV	(%RCX),%EBX

0x260a2b ADD	$0x2,%EBX

0x260a2e MOV	%RAX,-0x60(%RBP)

0x260a32 SUB	%EAX,%EBX

0x260a34 JLE	260acc

0x260a3a MOV	(%R8),%EAX

0x260a3d MOV	%RAX,-0x58(%RBP)

0x260a41 LEA	0x1(%RAX),%R15D

0x260a45 MOV	(%R9),%R13D

0x260a48 ADD	$0x2,%R13D

0x260a4c CMP	%R15D,%R13D

0x260a4f JLE	260acc

0x260a51 SUB	%R15D,%R13D

0x260a54 IMUL	%R13,%RBX

0x260a58 DEC	%RBX

0x260a5b MOVQ	$0,-0x40(%RBP)

0x260a63 MOV	%RBX,-0x30(%RBP)

0x260a67 MOVQ	$0x1,-0x70(%RBP)

0x260a6f MOVL	$0,-0x38(%RBP)

0x260a76 MOV	(%RDI),%ESI

0x260a78 SUB	$0x8,%RSP

0x260a7c LEA	-0x70(%RBP),%RAX

0x260a80 LEA	-0x38(%RBP),%RCX

0x260a84 LEA	-0x40(%RBP),%R8

0x260a88 LEA	-0x30(%RBP),%R9

0x260a8c MOV	$0x214c68,%EDI

0x260a91 MOV	%ESI,-0x34(%RBP)

0x260a94 MOV	$0x22,%EDX

0x260a99 PUSH	$0x1

0x260a9b PUSH	$0x1

0x260a9d PUSH	%RAX

0x260a9e CALL	261360 <@plt_start@+0x4f0>

0x260aa3 ADD	$0x20,%RSP

0x260aa7 MOV	-0x30(%RBP),%RAX

0x260aab CMP	%RBX,%RAX

0x260aae CMOVL	%RAX,%RBX

0x260ab2 MOV	%RBX,-0x30(%RBP)

0x260ab6 MOV	-0x40(%RBP),%R14

0x260aba CMP	%RBX,%R14

0x260abd JLE	260adb

0x260abf MOV	$0x214c80,%EDI

0x260ac4 MOV	-0x34(%RBP),%ESI

0x260ac7 CALL	261370 <@plt_start@+0x500>

0x260acc ADD	$0x68,%RSP

0x260ad0 POP	%RBX

0x260ad1 POP	%R12

0x260ad3 POP	%R13

0x260ad5 POP	%R14

0x260ad7 POP	%R15

0x260ad9 POP	%RBP

0x260ada RET

0x260adb MOV	0x28(%RBP),%RAX

0x260adf MOV	0x20(%RBP),%RCX

0x260ae3 MOV	0x8(%RCX),%RCX

0x260ae7 MOV	0x8(%RAX),%RSI

0x260aeb VMOVAPD	-0x5dd93(%RIP),%XMM13

0x260af3 VMOVSD	-0x5de33(%RIP),%XMM14

0x260afb VMOVSD	-0x5de13(%RIP),%XMM15

0x260b03 MOV	%R13,-0x50(%RBP)

0x260b07 JMP	260beb

0x260b0c NOPL	(%RAX)

(641) 0x260b10 VMOVSD	%XMM7,-0x48(%RBP)

(641) 0x260b15 VMOVAPD	%XMM3,-0x90(%RBP)

(641) 0x260b1d VMOVAPD	%XMM5,-0x80(%RBP)

(641) 0x260b22 CALL	2613a0 <@plt_start@+0x530>

(641) 0x260b27 VMOVAPD	-0x80(%RBP),%XMM5

(641) 0x260b2c VMOVAPD	-0x90(%RBP),%XMM3

(641) 0x260b34 VMOVSD	-0x48(%RBP),%XMM7

(641) 0x260b39 VMOVSD	-0x5de51(%RIP),%XMM15

(641) 0x260b41 VMOVSD	-0x5de81(%RIP),%XMM14

(641) 0x260b49 VMOVAPD	-0x5ddf1(%RIP),%XMM13

(641) 0x260b51 MOV	0x20(%RBP),%RAX

(641) 0x260b55 MOV	0x8(%RAX),%RCX

(641) 0x260b59 VMULSD	(%RCX,%RBX,8),%XMM0,%XMM1

(641) 0x260b5e VDIVSD	%XMM3,%XMM1,%XMM1

(641) 0x260b62 VMOVAPD	-0x5de3a(%RIP),%XMM2

(641) 0x260b6a VANDPD	%XMM2,%XMM1,%XMM1

(641) 0x260b6e MOV	0x28(%RBP),%RAX

(641) 0x260b72 MOV	0x8(%RAX),%RSI

(641) 0x260b76 VMULSD	(%RSI,%R15,8),%XMM0,%XMM0

(641) 0x260b7c VDIVSD	%XMM5,%XMM0,%XMM0

(641) 0x260b80 VANDPD	%XMM2,%XMM0,%XMM0

(641) 0x260b84 VMINSD	%XMM1,%XMM0,%XMM2

(641) 0x260b88 VCMPSD	$0x3,%XMM1,%XMM1,%XMM1

(641) 0x260b8d VBLENDVPD	%XMM1,%XMM0,%XMM2,%XMM0

(641) 0x260b93 VMULSD	%XMM0,%XMM0,%XMM0

(641) 0x260b97 MOV	0x40(%RBP),%RDX

(641) 0x260b9b MOV	0x10(%RDX),%RAX

(641) 0x260b9f MOV	(%RDX),%RDX

(641) 0x260ba2 IMUL	%R15,%RDX

(641) 0x260ba6 ADD	%RBX,%RDX

(641) 0x260ba9 VMOVSD	(%RAX,%RDX,8),%XMM1

(641) 0x260bae VADDSD	%XMM1,%XMM1,%XMM1

(641) 0x260bb2 VMULSD	%XMM0,%XMM1,%XMM0

(641) 0x260bb6 VMULSD	%XMM0,%XMM7,%XMM0

(641) 0x260bba VMULSD	%XMM0,%XMM7,%XMM0

(641) 0x260bbe MOV	0x38(%RBP),%RDX

(641) 0x260bc2 MOV	0x10(%RDX),%RAX

(641) 0x260bc6 IMUL	(%RDX),%R15

(641) 0x260bca ADD	%RBX,%R15

(641) 0x260bcd VMOVSD	%XMM0,(%RAX,%R15,8)

(641) 0x260bd3 LEA	0x1(%R14),%RAX

(641) 0x260bd7 CMP	-0x30(%RBP),%R14

(641) 0x260bdb MOV	%RAX,%R14

(641) 0x260bde MOV	%R13,%R15

(641) 0x260be1 MOV	-0x50(%RBP),%R13

(641) 0x260be5 JGE	260abf

(641) 0x260beb MOV	%R14,%RAX

(641) 0x260bee SHR	$0x20,%RAX

(641) 0x260bf2 JE	260c00

(641) 0x260bf4 MOV	%R14,%RAX

(641) 0x260bf7 CQTO

(641) 0x260bf9 IDIV	%R13

(641) 0x260bfc JMP	260c08

0x260bfe XCHG	%AX,%AX

(641) 0x260c00 MOV	%R14D,%EAX

(641) 0x260c03 XOR	%EDX,%EDX

(641) 0x260c05 DIV	%R13D

(641) 0x260c08 MOV	-0x60(%RBP),%R12

(641) 0x260c0c LEA	(%R12,%RAX,1),%EDI

(641) 0x260c10 MOV	%R15,%R13

(641) 0x260c13 LEA	(%R15,%RDX,1),%R11D

(641) 0x260c17 MOVSXD	%EDI,%R15

(641) 0x260c1a MOV	0x10(%RBP),%RDI

(641) 0x260c1e MOV	(%RDI),%R8

(641) 0x260c21 MOV	0x10(%RDI),%R9

(641) 0x260c25 MOV	%R8,%R10

(641) 0x260c28 IMUL	%R15,%R10

(641) 0x260c2c MOVSXD	%R11D,%RBX

(641) 0x260c2f LEA	(%R10,%RBX,1),%R11

(641) 0x260c33 INC	%R11

(641) 0x260c36 LEA	(%R12,%RAX,1),%EDI

(641) 0x260c3a INC	%EDI

(641) 0x260c3c MOVSXD	%EDI,%RDI

(641) 0x260c3f IMUL	%RDI,%R8

(641) 0x260c43 VMOVSD	(%R9,%R11,8),%XMM0

(641) 0x260c49 LEA	(%R8,%RBX,1),%R11

(641) 0x260c4d INC	%R11

(641) 0x260c50 ADD	%RBX,%R10

(641) 0x260c53 ADD	%RBX,%R8

(641) 0x260c56 VMOVSD	(%R9,%R11,8),%XMM1

(641) 0x260c5c MOV	0x18(%RBP),%R12

(641) 0x260c60 MOV	(%R12),%R11

(641) 0x260c64 VMOVSD	(%R9,%R10,8),%XMM4

(641) 0x260c6a MOV	0x10(%R12),%R10

(641) 0x260c6f VMOVSD	(%R9,%R8,8),%XMM5

(641) 0x260c75 MOV	%R11,%R8

(641) 0x260c78 IMUL	%RDI,%R8

(641) 0x260c7c LEA	(%R8,%RBX,1),%R9

(641) 0x260c80 INC	%R9

(641) 0x260c83 ADD	%RBX,%R8

(641) 0x260c86 VMOVSD	(%R10,%R8,8),%XMM6

(641) 0x260c8c IMUL	%R15,%R11

(641) 0x260c90 VMOVSD	(%R10,%R9,8),%XMM7

(641) 0x260c96 LEA	(%R11,%RBX,1),%R8

(641) 0x260c9a INC	%R8

(641) 0x260c9d ADD	%RBX,%R11

(641) 0x260ca0 VMOVSD	(%R10,%R11,8),%XMM8

(641) 0x260ca6 VMOVSD	(%R10,%R8,8),%XMM9

(641) 0x260cac MOV	0x30(%RBP),%R9

(641) 0x260cb0 MOV	(%R9),%R8

(641) 0x260cb3 MOV	0x10(%R9),%R9

(641) 0x260cb7 IMUL	%R8,%RDI

(641) 0x260cbb ADD	-0x68(%RBP),%EAX

(641) 0x260cbe CLTQ

(641) 0x260cc0 IMUL	%R8,%RAX

(641) 0x260cc4 IMUL	%R15,%R8

(641) 0x260cc8 ADD	-0x58(%RBP),%EDX

(641) 0x260ccb MOVSXD	%EDX,%RDX

(641) 0x260cce ADD	%R8,%RDX

(641) 0x260cd1 ADD	%RBX,%R8

(641) 0x260cd4 INC	%R8

(641) 0x260cd7 VMOVSD	(%R9,%R8,8),%XMM2

(641) 0x260cdd ADD	%RBX,%RDI

(641) 0x260ce0 VMOVHPD	(%R9,%RDI,8),%XMM2,%XMM10

(641) 0x260ce6 VMOVSD	(%R9,%RDX,8),%XMM2

(641) 0x260cec ADD	%RBX,%RAX

(641) 0x260cef VMOVHPD	(%R9,%RAX,8),%XMM2,%XMM11

(641) 0x260cf5 VADDSD	%XMM1,%XMM0,%XMM2

(641) 0x260cf9 VADDSD	%XMM5,%XMM4,%XMM3

(641) 0x260cfd VSUBSD	%XMM3,%XMM2,%XMM3

(641) 0x260d01 VADDSD	%XMM7,%XMM6,%XMM2

(641) 0x260d05 VADDSD	%XMM9,%XMM8,%XMM12

(641) 0x260d0a VSUBSD	%XMM12,%XMM2,%XMM2

(641) 0x260d0f VUNPCKLPD	%XMM7,%XMM1,%XMM1

(641) 0x260d13 VUNPCKLPD	%XMM9,%XMM5,%XMM5

(641) 0x260d18 VADDPD	%XMM5,%XMM1,%XMM1

(641) 0x260d1c VUNPCKLPD	%XMM8,%XMM4,%XMM4

(641) 0x260d21 VSUBPD	%XMM4,%XMM1,%XMM1

(641) 0x260d25 VUNPCKLPD	%XMM6,%XMM0,%XMM0

(641) 0x260d29 VSUBPD	%XMM0,%XMM1,%XMM0

(641) 0x260d2d VMULPD	%XMM0,%XMM13,%XMM7

(641) 0x260d31 VMOVSD	(%RCX,%RBX,8),%XMM6

(641) 0x260d36 VMOVSD	(%RSI,%R15,8),%XMM5

(641) 0x260d3c VMULSD	%XMM5,%XMM2,%XMM0

(641) 0x260d40 VMULSD	%XMM3,%XMM6,%XMM1

(641) 0x260d44 VADDSD	%XMM0,%XMM1,%XMM12

(641) 0x260d48 VSUBPD	%XMM11,%XMM10,%XMM0

(641) 0x260d4d VUNPCKLPD	%XMM5,%XMM6,%XMM1

(641) 0x260d51 VMOVSD	0x8(%RCX,%RBX,8),%XMM4

(641) 0x260d57 VMOVHPD	0x10(%RSI,%R15,8),%XMM4,%XMM4

(641) 0x260d5e VADDPD	%XMM4,%XMM1,%XMM1

(641) 0x260d62 VDIVPD	%XMM1,%XMM0,%XMM1

(641) 0x260d66 VMULPD	%XMM1,%XMM1,%XMM8

(641) 0x260d6a VPERMILPD	$0x1,%XMM8,%XMM9

(641) 0x260d70 VADDSD	%XMM9,%XMM8,%XMM0

(641) 0x260d75 VMAXSD	%XMM15,%XMM0,%XMM4

(641) 0x260d7a VXORPD	%XMM0,%XMM0,%XMM0

(641) 0x260d7e VUCOMISD	%XMM0,%XMM12

(641) 0x260d82 JAE	260bbe

(641) 0x260d88 VUNPCKLPD	%XMM6,%XMM5,%XMM10

(641) 0x260d8c VDIVPD	%XMM10,%XMM7,%XMM7

(641) 0x260d91 VMULSD	%XMM3,%XMM14,%XMM3

(641) 0x260d95 VDIVSD	%XMM6,%XMM3,%XMM3

(641) 0x260d99 VMULSD	%XMM2,%XMM14,%XMM2

(641) 0x260d9d VDIVSD	%XMM5,%XMM2,%XMM2

(641) 0x260da1 VMULSD	%XMM2,%XMM9,%XMM2

(641) 0x260da5 VMULSD	%XMM3,%XMM8,%XMM3

(641) 0x260da9 VADDSD	%XMM2,%XMM3,%XMM3

(641) 0x260dad VPERMILPD	$0x1,%XMM7,%XMM2

(641) 0x260db3 VADDSD	%XMM2,%XMM7,%XMM2

(641) 0x260db7 VMULSD	%XMM1,%XMM2,%XMM5

(641) 0x260dbb VPERMILPD	$0x1,%XMM1,%XMM2

(641) 0x260dc1 VMULSD	%XMM2,%XMM5,%XMM5

(641) 0x260dc5 VADDSD	%XMM3,%XMM5,%XMM3

(641) 0x260dc9 VDIVSD	%XMM4,%XMM3,%XMM7

(641) 0x260dcd VUCOMISD	-0x5e0d5(%RIP),%XMM7

(641) 0x260dd5 JA	260bbe

(641) 0x260ddb VMOVAPD	-0x5e0b3(%RIP),%XMM5

(641) 0x260de3 VANDPD	%XMM5,%XMM1,%XMM0

(641) 0x260de7 VMAXSD	%XMM15,%XMM0,%XMM0

(641) 0x260dec VMOVAPD	-0x5e064(%RIP),%XMM6

(641) 0x260df4 VXORPD	%XMM6,%XMM0,%XMM3

(641) 0x260df8 VXORPD	%XMM4,%XMM4,%XMM4

(641) 0x260dfc VCMPSD	$0x1,%XMM4,%XMM1,%XMM1

(641) 0x260e01 VBLENDVPD	%XMM1,%XMM3,%XMM0,%XMM3

(641) 0x260e07 VANDPD	%XMM5,%XMM2,%XMM0

(641) 0x260e0b VMAXSD	%XMM15,%XMM0,%XMM0

(641) 0x260e10 VXORPD	%XMM6,%XMM0,%XMM1

(641) 0x260e14 VCMPSD	$0x1,%XMM4,%XMM3,%XMM2

(641) 0x260e19 VBLENDVPD	%XMM2,%XMM1,%XMM0,%XMM5

(641) 0x260e1f VMULSD	%XMM5,%XMM5,%XMM0

(641) 0x260e23 VMULSD	%XMM3,%XMM3,%XMM1

(641) 0x260e27 VADDSD	%XMM0,%XMM1,%XMM0

(641) 0x260e2b VUCOMISD	%XMM4,%XMM0

(641) 0x260e2f JB	260b10

(641) 0x260e35 VSQRTSD	%XMM0,%XMM0,%XMM0

(641) 0x260e39 JMP	260b51

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:36-64
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.17 to 1.67 cycles (7.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.17 to 1.46 cycles (8.34x speedup).

Details

3% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

11% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	73
nb uops	73
loop length	258
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.75	6.75	6.50	6.50	3.50	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.75	6.75	6.50	6.50	3.50	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	9.00
Overall L1	12.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	11%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	8%
store	10%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

8% of peak load performance is reached (8.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (5.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.17 to 9.00 cycles (1.35x speedup).

ASM code

In the binary file, the address of the function is: 260a10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x68,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RDX),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RCX),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD $0x2,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB %EAX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 260acc <.omp_outlined..576+0xbc>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%R8),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA 0x1(%RAX),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%R9),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD $0x2,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %R15D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 260acc <.omp_outlined..576+0xbc>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
SUB %R15D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	3	1
DEC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0x1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x70(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x214c68,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 261360 <@plt_start@+0x4f0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	1	0.50
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RBX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 260adb <.omp_outlined..576+0xcb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV $0x214c80,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 261370 <@plt_start@+0x500>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x68,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
VMOVAPD -0x5dd93(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVSD -0x5de33(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD -0x5de13(%RIP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
MOV %R13,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JMP 260beb <.omp_outlined..576+0x1db>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:36-64
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.17 to 1.67 cycles (7.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

11% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	73
nb uops	73
loop length	258
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.75	6.75	6.50	6.50	3.50	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.75	6.75	6.50	6.50	3.50	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	9.00
Overall L1	12.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	11%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	8%
store	10%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

8% of peak load performance is reached (8.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (5.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 260a10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x68,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RDX),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RCX),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD $0x2,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB %EAX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 260acc <.omp_outlined..576+0xbc>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%R8),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA 0x1(%RAX),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%R9),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD $0x2,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %R15D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 260acc <.omp_outlined..576+0xbc>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
SUB %R15D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	3	1
DEC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0x1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x70(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x214c68,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 261360 <@plt_start@+0x4f0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	1	0.50
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RBX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 260adb <.omp_outlined..576+0xcb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV $0x214c80,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 261370 <@plt_start@+0x500>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x68,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
VMOVAPD -0x5dd93(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVSD -0x5de33(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD -0x5de13(%RIP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
MOV %R13,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JMP 260beb <.omp_outlined..576+0x1db>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0.01	1	0	1	0.01	1	0.01	1	0	0.84	0.32	0.56	0.95

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	61.67	3.59
2x2	4	1	2	2	30.91	3.59
2x4	8	1	4	4	15.49	3.58
2x8	16	1	7.97	8	7.85	3.58
2x16	32	1	15.96	16	4.01	3.39
2x32	64	1	32.09	32	2.09	2.87
2x64	128	0.84	53.57	64	1.47	1.95
2x96	192	0.56	54.04	96	1.25	2.18

Name	Coverage (%)	Time (s)
▼.omp_outlined..576–	3.59	61.61
○Loop 641 - viscosity.cpp:37-64 - exec	3.59	61.6

Report Configuration

Code clean check

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Vectorization

Details

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency