OV - - Function .omp_outlined..334

	Function: .omp_outlined..334	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage: 6.87%

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x23d670 PUSH	%RBP

0x23d671 MOV	%RSP,%RBP

0x23d674 PUSH	%R15

0x23d676 PUSH	%R14

0x23d678 PUSH	%R13

0x23d67a PUSH	%R12

0x23d67c PUSH	%RBX

0x23d67d SUB	$0x58,%RSP

0x23d681 MOV	(%RDX),%EAX

0x23d683 INC	%EAX

0x23d685 MOV	(%RCX),%EBX

0x23d687 ADD	$0x2,%EBX

0x23d68a MOV	%EAX,-0x44(%RBP)

0x23d68d SUB	%EAX,%EBX

0x23d68f JLE	23db05

0x23d695 MOV	(%R8),%R12D

0x23d698 INC	%R12D

0x23d69b MOV	(%R9),%R13D

0x23d69e ADD	$0x2,%R13D

0x23d6a2 CMP	%R12D,%R13D

0x23d6a5 JLE	23db05

0x23d6ab SUB	%R12D,%R13D

0x23d6ae IMUL	%R13,%RBX

0x23d6b2 DEC	%RBX

0x23d6b5 MOVQ	$0,-0x50(%RBP)

0x23d6bd MOV	%RBX,-0x38(%RBP)

0x23d6c1 MOVQ	$0x1,-0x70(%RBP)

0x23d6c9 MOVL	$0,-0x48(%RBP)

0x23d6d0 MOV	$0x7fefffffffffffff,%RAX

0x23d6da MOV	%RAX,-0x30(%RBP)

0x23d6de MOV	(%RDI),%ESI

0x23d6e0 SUB	$0x8,%RSP

0x23d6e4 LEA	-0x70(%RBP),%RAX

0x23d6e8 LEA	-0x48(%RBP),%RCX

0x23d6ec LEA	-0x50(%RBP),%R8

0x23d6f0 LEA	-0x38(%RBP),%R9

0x23d6f4 MOV	$0x212348,%EDI

0x23d6f9 MOV	%ESI,-0x3c(%RBP)

0x23d6fc MOV	$0x22,%EDX

0x23d701 PUSH	$0x1

0x23d703 PUSH	$0x1

0x23d705 PUSH	%RAX

0x23d706 CALL	261360 <@plt_start@+0x4f0>

0x23d70b ADD	$0x20,%RSP

0x23d70f MOV	-0x38(%RBP),%RAX

0x23d713 CMP	%RBX,%RAX

0x23d716 CMOVL	%RAX,%RBX

0x23d71a MOV	%RBX,-0x38(%RBP)

0x23d71e MOV	-0x50(%RBP),%R14

0x23d722 CMP	%RBX,%R14

0x23d725 JLE	23d7af

0x23d72b MOV	0x80(%RBP),%RBX

0x23d732 MOV	$0x212360,%EDI

0x23d737 MOV	-0x3c(%RBP),%R14D

0x23d73b MOV	%R14D,%ESI

0x23d73e CALL	261370 <@plt_start@+0x500>

0x23d743 LEA	-0x30(%RBP),%RAX

0x23d747 MOV	%RAX,-0x68(%RBP)

0x23d74b SUB	$0x8,%RSP

0x23d74f LEA	-0x68(%RBP),%R8

0x23d753 MOV	$0x212378,%EDI

0x23d758 MOV	$0x8,%ECX

0x23d75d MOV	$0x23db20,%R9D

0x23d763 MOV	%R14D,%ESI

0x23d766 MOV	$0x1,%EDX

0x23d76b PUSH	$0x264000

0x23d770 CALL	2613b0 <@plt_start@+0x540>

0x23d775 ADD	$0x10,%RSP

0x23d779 CMP	$0x2,%EAX

0x23d77c JE	23dae4

0x23d782 CMP	$0x1,%EAX

0x23d785 JNE	23db05

0x23d78b VMOVSD	(%RBX),%XMM0

0x23d78f VMINSD	-0x30(%RBP),%XMM0,%XMM0

0x23d794 VMOVSD	%XMM0,(%RBX)

0x23d798 MOV	$0x212378,%EDI

0x23d79d MOV	$0x264000,%EDX

0x23d7a2 MOV	%R14D,%ESI

0x23d7a5 CALL	2613c0 <@plt_start@+0x550>

0x23d7aa JMP	23db05

0x23d7af MOV	0x78(%RBP),%R10

0x23d7b3 MOV	0x70(%RBP),%R11

0x23d7b7 MOV	0x68(%RBP),%R15

0x23d7bb VXORPD	%XMM9,%XMM9,%XMM9

0x23d7c0 VMOVSD	-0x3aad8(%RIP),%XMM10

0x23d7c8 VMOVAPD	-0x3aaa0(%RIP),%XMM11

0x23d7d0 VMOVSD	-0x3ab40(%RIP),%XMM12

0x23d7d8 VMOVSD	-0x3aad8(%RIP),%XMM13

0x23d7e0 VMOVAPD	-0x3aa18(%RIP),%XMM14

0x23d7e8 VMOVSD	-0x3ab20(%RIP),%XMM15

0x23d7f0 MOV	%R12D,-0x40(%RBP)

0x23d7f4 JMP	23da3b

0x23d7f9 NOPL	(%RAX)

(197) 0x23d800 MOV	%R13,%R15

(197) 0x23d803 MOV	%R10,%R13

(197) 0x23d806 MOV	%R14,-0x60(%RBP)

(197) 0x23d80a MOV	%R11,%R14

(197) 0x23d80d VMOVSD	%XMM7,-0x58(%RBP)

(197) 0x23d812 VMOVAPD	%XMM8,-0x80(%RBP)

(197) 0x23d817 CALL	2613a0 <@plt_start@+0x530>

(197) 0x23d81c VMOVAPD	-0x80(%RBP),%XMM8

(197) 0x23d821 VMOVSD	-0x58(%RBP),%XMM7

(197) 0x23d826 VMOVSD	-0x3ab5e(%RIP),%XMM15

(197) 0x23d82e VMOVAPD	-0x3aa66(%RIP),%XMM14

(197) 0x23d836 VMOVSD	-0x3ab36(%RIP),%XMM13

(197) 0x23d83e VMOVSD	-0x3abae(%RIP),%XMM12

(197) 0x23d846 VMOVAPD	-0x3ab1e(%RIP),%XMM11

(197) 0x23d84e VMOVSD	-0x3ab66(%RIP),%XMM10

(197) 0x23d856 VXORPD	%XMM9,%XMM9,%XMM9

(197) 0x23d85b MOV	%R14,%R11

(197) 0x23d85e MOV	-0x60(%RBP),%R14

(197) 0x23d862 MOV	%R13,%R10

(197) 0x23d865 MOV	%R15,%R13

(197) 0x23d868 MOV	0x68(%RBP),%R15

(197) 0x23d86c MOV	0x40(%RBP),%RAX

(197) 0x23d870 MOV	(%RAX),%RCX

(197) 0x23d873 MOV	0x10(%RAX),%RDX

(197) 0x23d877 MOV	%RCX,%RSI

(197) 0x23d87a IMUL	%R12,%RSI

(197) 0x23d87e LEA	(%RSI,%RBX,1),%RAX

(197) 0x23d882 VMOVSD	(%RDX,%RAX,8),%XMM1

(197) 0x23d887 LEA	0x1(%R12),%EAX

(197) 0x23d88c CLTQ

(197) 0x23d88e IMUL	%RAX,%RCX

(197) 0x23d892 LEA	(%RCX,%RBX,1),%RDI

(197) 0x23d896 VADDSD	(%RDX,%RDI,8),%XMM1,%XMM1

(197) 0x23d89b MOV	0x48(%RBP),%R8

(197) 0x23d89f MOV	0x10(%R8),%RDI

(197) 0x23d8a3 MOV	(%R8),%R8

(197) 0x23d8a6 IMUL	%R12,%R8

(197) 0x23d8aa LEA	(%R8,%RBX,1),%R9

(197) 0x23d8ae VMULSD	(%RDI,%R9,8),%XMM1,%XMM1

(197) 0x23d8b4 ADD	%RBX,%RSI

(197) 0x23d8b7 INC	%RSI

(197) 0x23d8ba VMOVSD	(%RDX,%RSI,8),%XMM2

(197) 0x23d8bf LEA	0x1(%RCX,%RBX,1),%RCX

(197) 0x23d8c4 VADDSD	(%RDX,%RCX,8),%XMM2,%XMM2

(197) 0x23d8c9 LEA	0x1(%R8,%RBX,1),%RCX

(197) 0x23d8ce VMULSD	(%RDI,%RCX,8),%XMM2,%XMM3

(197) 0x23d8d3 MOV	0x58(%RBP),%RDX

(197) 0x23d8d7 MOV	0x10(%RDX),%RCX

(197) 0x23d8db MOV	(%RDX),%RDX

(197) 0x23d8de IMUL	%R12,%RDX

(197) 0x23d8e2 ADD	%RBX,%RDX

(197) 0x23d8e5 VMOVSD	(%RCX,%RDX,8),%XMM2

(197) 0x23d8ea MOV	0x60(%RBP),%RDX

(197) 0x23d8ee MOV	(%RDX),%RCX

(197) 0x23d8f1 MOV	0x10(%RDX),%RDX

(197) 0x23d8f5 MOV	%RCX,%RSI

(197) 0x23d8f8 IMUL	%R12,%RSI

(197) 0x23d8fc LEA	(%RSI,%RBX,1),%RDI

(197) 0x23d900 VMOVSD	(%RDX,%RDI,8),%XMM4

(197) 0x23d905 ADD	%RBX,%RSI

(197) 0x23d908 INC	%RSI

(197) 0x23d90b VADDSD	(%RDX,%RSI,8),%XMM4,%XMM4

(197) 0x23d910 IMUL	%RAX,%RCX

(197) 0x23d914 LEA	(%RCX,%RBX,1),%RSI

(197) 0x23d918 VMOVSD	(%RDX,%RSI,8),%XMM5

(197) 0x23d91d ADD	%RBX,%RCX

(197) 0x23d920 INC	%RCX

(197) 0x23d923 VADDSD	(%RDX,%RCX,8),%XMM5,%XMM5

(197) 0x23d928 MOV	(%R15),%RCX

(197) 0x23d92b MOV	0x10(%R15),%RDX

(197) 0x23d92f IMUL	%RCX,%R12

(197) 0x23d933 ADD	%RBX,%R12

(197) 0x23d936 VMULSD	(%RDX,%R12,8),%XMM4,%XMM4

(197) 0x23d93c IMUL	%RAX,%RCX

(197) 0x23d940 ADD	%RBX,%RCX

(197) 0x23d943 VMULSD	(%RDX,%RCX,8),%XMM5,%XMM5

(197) 0x23d948 VMINSD	%XMM7,%XMM8,%XMM6

(197) 0x23d94c VCMPSD	$0x3,%XMM7,%XMM7,%XMM7

(197) 0x23d951 VBLENDVPD	%XMM7,%XMM8,%XMM6,%XMM6

(197) 0x23d957 VMAXSD	%XMM10,%XMM0,%XMM0

(197) 0x23d95c MOV	0x38(%RBP),%RAX

(197) 0x23d960 VMULSD	(%RAX),%XMM6,%XMM6

(197) 0x23d964 VDIVSD	%XMM0,%XMM6,%XMM0

(197) 0x23d968 VADDSD	%XMM3,%XMM9,%XMM6

(197) 0x23d96c VSUBSD	%XMM1,%XMM6,%XMM6

(197) 0x23d970 MOV	0x50(%RBP),%RAX

(197) 0x23d974 VMOVSD	(%RAX),%XMM7

(197) 0x23d978 VADDSD	%XMM7,%XMM7,%XMM7

(197) 0x23d97c VMULSD	%XMM2,%XMM7,%XMM7

(197) 0x23d980 VANDPD	%XMM1,%XMM11,%XMM1

(197) 0x23d984 VANDPD	%XMM3,%XMM11,%XMM3

(197) 0x23d988 VMAXSD	%XMM1,%XMM3,%XMM8

(197) 0x23d98c VCMPSD	$0x3,%XMM1,%XMM1,%XMM1

(197) 0x23d991 VBLENDVPD	%XMM1,%XMM3,%XMM8,%XMM1

(197) 0x23d997 VMULSD	%XMM2,%XMM10,%XMM3

(197) 0x23d99b VCMPSD	$0x3,%XMM1,%XMM1,%XMM8

(197) 0x23d9a0 VMAXSD	%XMM1,%XMM3,%XMM1

(197) 0x23d9a4 VBLENDVPD	%XMM8,%XMM3,%XMM1,%XMM1

(197) 0x23d9aa VDIVSD	%XMM1,%XMM7,%XMM1

(197) 0x23d9ae VADDSD	%XMM5,%XMM6,%XMM6

(197) 0x23d9b2 VSUBSD	%XMM4,%XMM6,%XMM6

(197) 0x23d9b6 VMOVSD	(%R11),%XMM7

(197) 0x23d9bb VADDSD	%XMM7,%XMM7,%XMM7

(197) 0x23d9bf VANDPD	%XMM4,%XMM11,%XMM4

(197) 0x23d9c3 VANDPD	%XMM5,%XMM11,%XMM5

(197) 0x23d9c7 VMAXSD	%XMM4,%XMM5,%XMM8

(197) 0x23d9cb VCMPSD	$0x3,%XMM4,%XMM4,%XMM4

(197) 0x23d9d0 VBLENDVPD	%XMM4,%XMM5,%XMM8,%XMM4

(197) 0x23d9d6 VCMPSD	$0x3,%XMM4,%XMM4,%XMM5

(197) 0x23d9db VMAXSD	%XMM4,%XMM3,%XMM4

(197) 0x23d9df VBLENDVPD	%XMM5,%XMM3,%XMM4,%XMM3

(197) 0x23d9e5 VADDSD	%XMM2,%XMM2,%XMM4

(197) 0x23d9e9 VDIVSD	%XMM4,%XMM6,%XMM4

(197) 0x23d9ed VDIVSD	%XMM4,%XMM12,%XMM5

(197) 0x23d9f1 VMULSD	(%R10),%XMM5,%XMM5

(197) 0x23d9f6 VMULSD	%XMM7,%XMM2,%XMM2

(197) 0x23d9fa VCMPSD	$0x1,%XMM13,%XMM4,%XMM4

(197) 0x23da00 VBLENDVPD	%XMM4,%XMM5,%XMM14,%XMM4

(197) 0x23da06 VDIVSD	%XMM3,%XMM2,%XMM2

(197) 0x23da0a VMINSD	%XMM15,%XMM4,%XMM3

(197) 0x23da0f VMINSD	%XMM3,%XMM2,%XMM2

(197) 0x23da13 VMINSD	%XMM2,%XMM1,%XMM1

(197) 0x23da17 VMINSD	%XMM1,%XMM0,%XMM0

(197) 0x23da1b VMOVSD	-0x30(%RBP),%XMM1

(197) 0x23da20 VMINSD	%XMM0,%XMM1,%XMM0

(197) 0x23da24 VMOVSD	%XMM0,-0x30(%RBP)

(197) 0x23da29 CMP	-0x38(%RBP),%R14

(197) 0x23da2d LEA	0x1(%R14),%R14

(197) 0x23da31 MOV	-0x40(%RBP),%R12D

(197) 0x23da35 JGE	23d72b

(197) 0x23da3b MOV	%R14,%RAX

(197) 0x23da3e SHR	$0x20,%RAX

(197) 0x23da42 JE	23da50

(197) 0x23da44 MOV	%R14,%RAX

(197) 0x23da47 CQTO

(197) 0x23da49 IDIV	%R13

(197) 0x23da4c JMP	23da58

0x23da4e XCHG	%AX,%AX

(197) 0x23da50 MOV	%R14D,%EAX

(197) 0x23da53 XOR	%EDX,%EDX

(197) 0x23da55 DIV	%R13D

(197) 0x23da58 ADD	-0x44(%RBP),%EAX

(197) 0x23da5b ADD	%R12D,%EDX

(197) 0x23da5e MOVSXD	%EDX,%RBX

(197) 0x23da61 MOV	0x10(%RBP),%RCX

(197) 0x23da65 MOV	0x8(%RCX),%RCX

(197) 0x23da69 VMOVSD	(%RCX,%RBX,8),%XMM7

(197) 0x23da6e MOVSXD	%EAX,%R12

(197) 0x23da71 MOV	0x18(%RBP),%RAX

(197) 0x23da75 MOV	0x8(%RAX),%RAX

(197) 0x23da79 VMOVSD	(%RAX,%R12,8),%XMM8

(197) 0x23da7f MOV	0x20(%RBP),%RCX

(197) 0x23da83 MOV	0x10(%RCX),%RAX

(197) 0x23da87 MOV	(%RCX),%RCX

(197) 0x23da8a IMUL	%R12,%RCX

(197) 0x23da8e ADD	%RBX,%RCX

(197) 0x23da91 VMOVSD	(%RAX,%RCX,8),%XMM0

(197) 0x23da96 MOV	0x28(%RBP),%RCX

(197) 0x23da9a MOV	0x10(%RCX),%RAX

(197) 0x23da9e MOV	(%RCX),%RCX

(197) 0x23daa1 IMUL	%R12,%RCX

(197) 0x23daa5 ADD	%RBX,%RCX

(197) 0x23daa8 VMOVSD	(%RAX,%RCX,8),%XMM1

(197) 0x23daad VADDSD	%XMM1,%XMM1,%XMM1

(197) 0x23dab1 MOV	0x30(%RBP),%RCX

(197) 0x23dab5 MOV	0x10(%RCX),%RAX

(197) 0x23dab9 MOV	(%RCX),%RCX

(197) 0x23dabc IMUL	%R12,%RCX

(197) 0x23dac0 ADD	%RBX,%RCX

(197) 0x23dac3 VDIVSD	(%RAX,%RCX,8),%XMM1,%XMM1

(197) 0x23dac8 VMULSD	%XMM0,%XMM0,%XMM0

(197) 0x23dacc VADDSD	%XMM1,%XMM0,%XMM0

(197) 0x23dad0 VUCOMISD	%XMM9,%XMM0

(197) 0x23dad5 JB	23d800

(197) 0x23dadb VSQRTSD	%XMM0,%XMM0,%XMM0

(197) 0x23dadf JMP	23d86c

0x23dae4 MOV	(%RBX),%RAX

0x23dae7 VMOVSD	-0x30(%RBP),%XMM0

0x23daec NOPL	(%RAX)

(196) 0x23daf0 VMOVQ	%RAX,%XMM1

(196) 0x23daf5 VMINSD	%XMM0,%XMM1,%XMM1

(196) 0x23daf9 VMOVQ	%XMM1,%RCX

(196) 0x23dafe LOCK CMPXCHG	%RCX,(%RBX)

(196) 0x23db03 JNE	23daf0

0x23db05 ADD	$0x58,%RSP

0x23db09 POP	%RBX

0x23db0a POP	%R12

0x23db0c POP	%R13

0x23db0e POP	%R14

0x23db10 POP	%R15

0x23db12 POP	%RBP

0x23db13 RET

0x23db14 INT	$0x3

0x23db15 INT	$0x3

0x23db16 INT	$0x3

0x23db17 INT	$0x3

0x23db18 INT	$0x3

0x23db19 INT	$0x3

0x23db1a INT	$0x3

0x23db1b INT	$0x3

0x23db1c INT	$0x3

0x23db1d INT	$0x3

0x23db1e INT	$0x3

0x23db1f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:49-75
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.67 to 3.67 cycles (4.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.67 to 2.17 cycles (8.15x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes (21 double precision FP elements). The binary function is storing 72 bytes (9 double precision FP elements).

General properties

nb instructions	117
nb uops	106
loop length	441
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.67 cycles
front end	17.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.50	10.50	6.00	12.33	12.33	12.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	10.50	10.50	10.50	10.50	6.00	12.33	12.33	12.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.67
Dispatch	12.33
Overall L1	17.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	27%
load	22%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	8%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	15%
load	15%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	10%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.67 cycles. At this rate:

9% of peak load performance is reached (9.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.08 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.67 to 12.33 cycles (1.43x speedup).

ASM code

In the binary file, the address of the function is: 23d670

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDX),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RCX),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x2,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB %EAX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R8),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%R9),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x2,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SUB %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
DEC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0x1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x7fefffffffffffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x70(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x48(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x50(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x38(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x212348,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 261360 <@plt_start@+0x4f0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVL %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x50(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RBX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 23d7af <.omp_outlined..334+0x13f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x80(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV $0x212360,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x3c(%RBP),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 261370 <@plt_start@+0x500>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x68(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x212378,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x8,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x23db20,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x264000	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 2613b0 <@plt_start@+0x540>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 23dae4 <.omp_outlined..334+0x474>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMINSD -0x30(%RBP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	2	0.50
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV $0x212378,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x264000,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2613c0 <@plt_start@+0x550>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x78(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x70(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x68(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD -0x3aad8(%RIP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVAPD -0x3aaa0(%RIP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD -0x3ab40(%RIP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x3aad8(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVAPD -0x3aa18(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD -0x3ab20(%RIP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %R12D,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 23da3b <.omp_outlined..334+0x3cb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV (%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:49-75
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.67 to 3.67 cycles (4.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	117
nb uops	106
loop length	441
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.67 cycles
front end	17.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.50	10.50	6.00	12.33	12.33	12.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	10.50	10.50	10.50	10.50	6.00	12.33	12.33	12.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.67
Dispatch	12.33
Overall L1	17.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	27%
load	22%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	8%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	15%
load	15%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	10%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.67 cycles. At this rate:

9% of peak load performance is reached (9.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.08 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 23d670

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDX),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RCX),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x2,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB %EAX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R8),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%R9),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x2,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SUB %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
DEC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0x1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x7fefffffffffffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x70(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x48(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x50(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x38(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x212348,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 261360 <@plt_start@+0x4f0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVL %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x50(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RBX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 23d7af <.omp_outlined..334+0x13f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x80(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV $0x212360,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x3c(%RBP),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 261370 <@plt_start@+0x500>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x68(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x212378,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x8,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x23db20,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x264000	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 2613b0 <@plt_start@+0x540>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 23dae4 <.omp_outlined..334+0x474>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMINSD -0x30(%RBP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	2	0.50
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV $0x212378,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x264000,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2613c0 <@plt_start@+0x550>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 23db05 <.omp_outlined..334+0x495>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x78(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x70(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x68(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD -0x3aad8(%RIP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVAPD -0x3aaa0(%RIP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD -0x3ab40(%RIP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x3aad8(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVAPD -0x3aa18(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD -0x3ab20(%RIP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %R12D,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 23da3b <.omp_outlined..334+0x3cb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV (%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.01	0	1.01	0	1.01	0	1.01	0	1.01	0	0.99	0.05	0.72	0.9

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	118.02	6.87
2x2	4	1.01	2.03	2	58.17	6.76
2x4	8	1.01	4.06	4	29.16	6.74
2x8	16	1.01	8.11	8	14.58	6.74
2x16	32	1.01	16.15	16	8.19	6.4
2x32	64	1.01	32.39	32	3.68	5.45
2x64	128	0.99	63.04	64	2.2	3.15
2x96	192	0.72	69.35	96	2.04	3.24

Name	Coverage (%)	Time (s)
▼.omp_outlined..334–	6.87	117.89
○Loop 197 - calc_dt.cpp:49-75 - exec	6.87	117.87
○Loop 196 - calc_dt.cpp:49-49 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency