OV - - Loop 165

	Loop Id: 165	Module: exec	Source: advec_mom.cpp:86-88 [...]	Coverage: 1.7%

0x238160 MOV	%R15,%RAX

0x238163 CQTO

0x238165 IDIV	%R14

0x238168 MOV	%RDX,%RSI

0x23816b MOV	-0x48(%RBP),%RDI    [18]

0x23816f MOV	%RSI,-0xd8(%RBP)    [18]

0x238176 LEA	(%R12,%RCX,1),%EDX

0x23817a MOV	%EDX,-0x40(%RBP)    [18]

0x23817d LEA	(%R12,%RAX,1),%EDX

0x238181 MOV	%EDX,-0x6c(%RBP)    [18]

0x238184 MOV	-0x80(%RBP),%R8    [18]

0x238188 LEA	(%R8,%R9,1),%R10D

0x23818c MOV	%R9,-0xf0(%RBP)    [18]

0x238193 LEA	(%R8,%RSI,1),%R9D

0x238197 MOVSXD	%R10D,%R15

0x23819a MOVSXD	%R9D,%R9

0x23819d ADD	%EDI,%ECX

0x23819f ADD	%EDI,%EAX

0x2381a1 MOVSXD	%ECX,%R13

0x2381a4 MOVSXD	%EAX,%RDX

0x2381a7 MOV	-0x78(%RBP),%R14    [18]

0x2381ab IMUL	%R14,%R13

0x2381af IMUL	%R14,%RDX

0x2381b3 MOV	%RDX,-0xe0(%RBP)    [18]

0x2381ba LEA	(%R15,%R13,1),%RAX

0x2381be MOV	%R15,-0x100(%RBP)    [18]

0x2381c5 MOV	-0xa0(%RBP),%RCX    [18]

0x2381cc VMOVSD	(%RCX,%RAX,8),%XMM1    [6]

0x2381d1 LEA	(%RDX,%R9,1),%RAX

0x2381d5 MOV	%R9,-0xf8(%RBP)    [18]

0x2381dc VMOVHPD	(%RCX,%RAX,8),%XMM1,%XMM1    [16]

0x2381e1 MOV	-0x58(%RBP),%RAX    [18]

0x2381e5 ADD	%R8D,%EAX

0x2381e8 MOVSXD	%EAX,%RSI

0x2381eb MOV	-0x30(%RBP),%RAX    [18]

0x2381ef LEA	(%R12,%RAX,1),%EDX

0x2381f3 MOV	%EDX,-0x68(%RBP)    [18]

0x2381f6 ADD	%EDI,%EAX

0x2381f8 MOVSXD	%EAX,%R10

0x2381fb IMUL	%R14,%R10

0x2381ff LEA	(%R10,%RSI,1),%RAX

0x238203 MOV	%RSI,%RDX

0x238206 MOV	%RSI,-0xe8(%RBP)    [18]

0x23820d VMOVSD	(%RCX,%RAX,8),%XMM2    [11]

0x238212 MOV	-0x50(%RBP),%RAX    [18]

0x238216 ADD	%R8D,%EAX

0x238219 CLTQ

0x23821b MOV	%RAX,-0x30(%RBP)    [18]

0x23821f LEA	(%R12,%R11,1),%R8D

0x238223 ADD	%EDI,%R11D

0x238226 MOVSXD	%R11D,%RSI

0x238229 IMUL	%R14,%RSI

0x23822d ADD	%RSI,%RAX

0x238230 VMOVHPD	(%RCX,%RAX,8),%XMM2,%XMM2    [20]

0x238235 MOVSXD	-0x40(%RBP),%RAX    [18]

0x238239 MOV	%RAX,-0x40(%RBP)    [18]

0x23823d MOV	%R14,%R12

0x238240 IMUL	%RAX,%R12

0x238244 LEA	(%R12,%R15,1),%R11

0x238248 VMOVSD	(%RCX,%R11,8),%XMM3    [13]

0x23824e MOVSXD	-0x6c(%RBP),%R11    [18]

0x238252 MOV	%R14,%RBX

0x238255 IMUL	%R11,%RBX

0x238259 LEA	(%RBX,%R9,1),%RDI

0x23825d VMOVHPD	(%RCX,%RDI,8),%XMM3,%XMM3    [12]

0x238262 MOVSXD	-0x68(%RBP),%RDI    [18]

0x238266 MOV	%R14,%R15

0x238269 IMUL	%RDI,%R15

0x23826d LEA	(%R15,%RDX,1),%R9

0x238271 VMOVSD	(%RCX,%R9,8),%XMM4    [15]

0x238277 MOVSXD	%R8D,%R8

0x23827a MOV	%R14,%R9

0x23827d IMUL	%R8,%R9

0x238281 MOV	-0x30(%RBP),%RAX    [18]

0x238285 LEA	(%R9,%RAX,1),%RDX

0x238289 VMOVHPD	(%RCX,%RDX,8),%XMM4,%XMM4    [17]

0x23828e MOV	-0x88(%RBP),%R14    [18]

0x238295 MOV	-0xf0(%RBP),%RAX    [18]

0x23829c ADD	%R14D,%EAX

0x23829f MOVSXD	%EAX,%RDX

0x2382a2 ADD	%RDX,%R13

0x2382a5 VMOVSD	(%RCX,%R13,8),%XMM5    [2]

0x2382ab MOV	-0xd8(%RBP),%RAX    [18]

0x2382b2 ADD	%R14D,%EAX

0x2382b5 MOVSXD	%EAX,%R13

0x2382b8 MOV	-0xe0(%RBP),%RAX    [18]

0x2382bf ADD	%R13,%RAX

0x2382c2 VMOVHPD	(%RCX,%RAX,8),%XMM5,%XMM5    [4]

0x2382c7 MOV	-0x58(%RBP),%RAX    [18]

0x2382cb ADD	%R14D,%EAX

0x2382ce CLTQ

0x2382d0 ADD	%RAX,%R10

0x2382d3 VMOVSD	(%RCX,%R10,8),%XMM6    [1]

0x2382d9 MOV	-0x50(%RBP),%R10    [18]

0x2382dd ADD	%R14D,%R10D

0x2382e0 MOVSXD	%R10D,%R10

0x2382e3 ADD	%R10,%RSI

0x2382e6 VMOVHPD	(%RCX,%RSI,8),%XMM6,%XMM6    [5]

0x2382eb ADD	%RAX,%R15

0x2382ee ADD	%RDX,%R12

0x2382f1 ADD	%R13,%RBX

0x2382f4 VMOVSD	(%RCX,%R12,8),%XMM7    [8]

0x2382fa VMOVHPD	(%RCX,%RBX,8),%XMM7,%XMM7    [19]

0x2382ff ADD	%R10,%R9

0x238302 VMOVSD	(%RCX,%R15,8),%XMM8    [7]

0x238308 VMOVHPD	(%RCX,%R9,8),%XMM8,%XMM8    [10]

0x23830e MOV	-0x98(%RBP),%RAX    [18]

0x238315 IMUL	%RAX,%RDI

0x238319 ADD	-0xe8(%RBP),%RDI    [18]

0x238320 IMUL	%RAX,%R8

0x238324 ADD	-0x30(%RBP),%R8    [18]

0x238328 MOV	-0x40(%RBP),%RCX    [18]

0x23832c IMUL	%RAX,%RCX

0x238330 ADD	-0x100(%RBP),%RCX    [18]

0x238337 IMUL	%RAX,%R11

0x23833b ADD	-0xf8(%RBP),%R11    [18]

0x238342 VINSERTF128	$0x1,%XMM1,%YMM2,%YMM1

0x238348 VINSERTF128	$0x1,%XMM3,%YMM4,%YMM2

0x23834e VADDPD	%YMM2,%YMM1,%YMM1

0x238352 VINSERTF128	$0x1,%XMM5,%YMM6,%YMM2

0x238358 VADDPD	%YMM2,%YMM1,%YMM1

0x23835c VINSERTF128	$0x1,%XMM7,%YMM8,%YMM2

0x238362 VADDPD	%YMM2,%YMM1,%YMM1

0x238366 VMULPD	%YMM0,%YMM1,%YMM1

0x23836a MOV	-0x90(%RBP),%RAX    [18]

0x238371 VMOVLPD	%XMM1,(%RAX,%RDI,8)    [9]

0x238376 VMOVHPD	%XMM1,(%RAX,%R8,8)    [14]

0x23837c VEXTRACTF128	$0x1,%YMM1,%XMM1

0x238382 VMOVLPD	%XMM1,(%RAX,%RCX,8)    [21]

0x238387 VMOVHPD	%XMM1,(%RAX,%R11,8)    [3]

0x23838d MOV	-0x110(%RBP),%RCX    [18]

0x238394 ADD	$0x4,%RCX

0x238398 MOV	-0x108(%RBP),%RDX    [18]

0x23839f ADD	$-0x4,%RDX

0x2383a3 MOV	-0xd0(%RBP),%R12    [18]

0x2383aa MOV	-0xc8(%RBP),%R14    [18]

0x2383b1 MOV	-0xc0(%RBP),%R10    [18]

0x2383b8 JE	238489

0x2383be LEA	0x1(%RCX),%R8

0x2383c2 MOV	%RCX,%RAX

0x2383c5 SHR	$0x20,%RAX

0x2383c9 MOV	%RDX,-0x108(%RBP)    [18]

0x2383d0 JE	2383e0

0x2383d2 MOV	%RCX,%RAX

0x2383d5 CQTO

0x2383d7 IDIV	%R14

0x2383da MOV	%RDX,-0x58(%RBP)    [18]

0x2383de JMP	2383eb

0x2383e0 MOV	%ECX,%EAX

0x2383e2 XOR	%EDX,%EDX

0x2383e4 DIV	%R14D

0x2383e7 MOV	%RDX,-0x58(%RBP)    [18]

0x2383eb MOV	%RAX,-0x30(%RBP)    [18]

0x2383ef MOV	-0x38(%RBP),%R12    [18]

0x2383f3 LEA	0x2(%RCX),%R10

0x2383f7 MOV	%R8,%RAX

0x2383fa SHR	$0x20,%RAX

0x2383fe JE	238420

0x238400 MOV	%R8,%RAX

0x238403 CQTO

0x238405 IDIV	%R14

0x238408 MOV	%RDX,-0x50(%RBP)    [18]

0x23840c MOV	%RAX,%R11

0x23840f JMP	23842f

0x238420 MOV	%R8D,%EAX

0x238423 XOR	%EDX,%EDX

0x238425 DIV	%R14D

0x238428 MOV	%RDX,-0x50(%RBP)    [18]

0x23842c MOV	%EAX,%R11D

0x23842f LEA	0x3(%RCX),%R15

0x238433 MOV	%R10,%RAX

0x238436 SHR	$0x20,%RAX

0x23843a MOV	%RCX,-0x110(%RBP)    [18]

0x238441 JE	238460

0x238443 MOV	%R10,%RAX

0x238446 CQTO

0x238448 IDIV	%R14

0x23844b MOV	%RDX,%R9

0x23844e MOV	%RAX,%RCX

0x238451 JMP	23846d

0x238460 MOV	%R10D,%EAX

0x238463 XOR	%EDX,%EDX

0x238465 DIV	%R14D

0x238468 MOV	%EDX,%R9D

0x23846b MOV	%EAX,%ECX

0x23846d MOV	%R15,%RAX

0x238470 SHR	$0x20,%RAX

0x238474 JNE	238160

0x23847a MOV	%R15D,%EAX

0x23847d XOR	%EDX,%EDX

0x23847f DIV	%R14D

0x238482 MOV	%EDX,%ESI

0x238484 JMP	23816b

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 86 - 88

--------------------------------------------------------------------------------

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	5.67 - 7.85
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.20 - 4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58 - 2.19
Bottlenecks	P8, P9,
Function	.omp_outlined..8.314
Source	advec_mom.cpp:86-88,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	52.00 - 72.00
CQA cycles if no scalar integer	9.17
CQA cycles if FP arith vectorized	52.00 - 72.00
CQA cycles if fully vectorized	10.00 - 15.00
Front-end cycles	32.83
DIV/SQRT cycles	21.75
P0 cycles	21.75
P1 cycles	21.75
P2 cycles	21.75
P3 cycles	9.00
P4 cycles	22.67
P5 cycles	22.67
P6 cycles	22.67
P7 cycles	2.00
P8 cycles	5.83
P9 cycles	5.50
P10 cycles	5.67
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	52.00 - 72.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	193.00
Nb uops	197.00
Nb loads	46.00
Nb stores	22.00
Nb stack references	25.00
FLOP/cycle	0.31 - 0.22
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.22 - 10.00
Bytes prefetched	0.00
Bytes loaded	356.00
Bytes stored	164.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	45.45
Vector-efficiency ratio all	15.14
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	11.65
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	18.18

Metric	Value
CQA speedup if no scalar integer	5.67 - 7.85
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.20 - 4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58 - 2.19
Bottlenecks	P8, P9,
Function	.omp_outlined..8.314
Source	advec_mom.cpp:86-88,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	52.00 - 72.00
CQA cycles if no scalar integer	9.17
CQA cycles if FP arith vectorized	52.00 - 72.00
CQA cycles if fully vectorized	10.00 - 15.00
Front-end cycles	32.83
DIV/SQRT cycles	21.75
P0 cycles	21.75
P1 cycles	21.75
P2 cycles	21.75
P3 cycles	9.00
P4 cycles	22.67
P5 cycles	22.67
P6 cycles	22.67
P7 cycles	2.00
P8 cycles	5.83
P9 cycles	5.50
P10 cycles	5.67
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	52.00 - 72.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	193.00
Nb uops	197.00
Nb loads	46.00
Nb stores	22.00
Nb stack references	25.00
FLOP/cycle	0.31 - 0.22
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.22 - 10.00
Bytes prefetched	0.00
Bytes loaded	356.00
Bytes stored	164.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	45.45
Vector-efficiency ratio all	15.14
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	11.65
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	18.18

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..8.314
Source file and lines	advec_mom.cpp:86-88
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:86-88
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 72.00 to 9.17 cycles (7.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 72.00 to 15.00 cycles (4.80x speedup).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 72.00 to 32.83 cycles (2.19x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 72.00 to 31.50 cycles (2.29x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 4 occurrences
IDIV: 4 occurrences
VMOVHPD: 2 occurrences

Vector unaligned load/store instructions

Detected 5 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences
VINSERTF128: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 2 occurrences
CQTO: 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: addition or subtraction
4: multiply

The binary loop is loading 356 bytes (44 double precision FP elements). The binary loop is storing 164 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	193
nb uops	197
loop length	781
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	6
used zmm registers	0
nb stack references	25
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.83 cycles
front end	32.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	21.75	21.75	21.75	21.75	9.00	22.67	22.67	22.67	2.00	5.83	5.50	5.67	2.00	2.00
cycles	21.75	21.75	21.75	21.75	9.00	22.67	22.67	22.67	2.00	5.83	5.50	5.67	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

52.00-72.00

Cycles summary

Front-end	32.83
Dispatch	22.67
DIV/SQRT	52.00-72.00
Overall L1	52.00-72.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	31%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	14%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	45%

Vector efficiency ratios

INT

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	19%
load	12%
store	12%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	12%
store	11%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 72.00 cycles. At this rate:

5% of peak load performance is reached (4.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2383be

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RSI,-0xd8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R12,%RCX,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R12,%RAX,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,-0x6c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x80(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R8,%R9,1),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,-0xf0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R8,%RSI,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R9D,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %ECX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R14,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R14,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RDX,-0xe0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R15,%R13,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,-0x100(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0xa0(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RCX,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%RDX,%R9,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVHPD (%RCX,%RAX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R12,%RAX,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R14,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R10,%RSI,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVSD (%RCX,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R12,%R11,1),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RAX,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOVSXD -0x40(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R12,%R15,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R11,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSXD -0x6c(%RBP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RBX,%R9,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RDI,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOVSXD -0x68(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RDI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R15,%RDX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R9,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R9,%RAX,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RDX,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x88(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xf0(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R13,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0xd8(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe0(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RAX,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
ADD %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R10,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RSI,8),%XMM6,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R13,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R12,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%RBX,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R15,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R9,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x98(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0xe8(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x100(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0xf8(%RBP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VINSERTF128 $0x1,%XMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF128 $0x1,%XMM3,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VADDPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VINSERTF128 $0x1,%XMM5,%YMM6,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VADDPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VINSERTF128 $0x1,%XMM7,%YMM8,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VADDPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %YMM0,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVLPD %XMM1,(%RAX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM1,(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVLPD %XMM1,(%RAX,%RCX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM1,(%RAX,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
MOV -0x110(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x4,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x108(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $-0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xd0(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xc8(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xc0(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 238489 <.omp_outlined..8.314+0x489>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RCX),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,-0x108(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 2383e0 <.omp_outlined..8.314+0x3e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 2383eb <.omp_outlined..8.314+0x3eb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RCX),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 238420 <.omp_outlined..8.314+0x420>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23842f <.omp_outlined..8.314+0x42f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x3(%RCX),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,-0x110(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 238460 <.omp_outlined..8.314+0x460>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23846d <.omp_outlined..8.314+0x46d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 238160 <.omp_outlined..8.314+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23816b <.omp_outlined..8.314+0x16b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..8.314
Source file and lines	advec_mom.cpp:86-88
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:86-88
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 72.00 to 9.17 cycles (7.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 72.00 to 31.50 cycles (2.29x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 4 occurrences
IDIV: 4 occurrences
VMOVHPD: 2 occurrences

Vector unaligned load/store instructions

Detected 5 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences
VINSERTF128: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 2 occurrences
CQTO: 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: addition or subtraction
4: multiply

The binary loop is loading 356 bytes (44 double precision FP elements). The binary loop is storing 164 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	193
nb uops	197
loop length	781
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	6
used zmm registers	0
nb stack references	25
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.83 cycles
front end	32.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	21.75	21.75	21.75	21.75	9.00	22.67	22.67	22.67	2.00	5.83	5.50	5.67	2.00	2.00
cycles	21.75	21.75	21.75	21.75	9.00	22.67	22.67	22.67	2.00	5.83	5.50	5.67	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

52.00-72.00

Cycles summary

Front-end	32.83
Dispatch	22.67
DIV/SQRT	52.00-72.00
Overall L1	52.00-72.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	31%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	14%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	45%

Vector efficiency ratios

INT

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	19%
load	12%
store	12%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	12%
store	11%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 72.00 cycles. At this rate:

5% of peak load performance is reached (4.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2383be

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RSI,-0xd8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R12,%RCX,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R12,%RAX,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,-0x6c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x80(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R8,%R9,1),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,-0xf0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R8,%RSI,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R9D,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %ECX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R14,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R14,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RDX,-0xe0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R15,%R13,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,-0x100(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0xa0(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RCX,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%RDX,%R9,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVHPD (%RCX,%RAX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R12,%RAX,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R14,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R10,%RSI,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVSD (%RCX,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R12,%R11,1),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RAX,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOVSXD -0x40(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R12,%R15,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R11,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSXD -0x6c(%RBP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RBX,%R9,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RDI,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOVSXD -0x68(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RDI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R15,%RDX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R9,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R9,%RAX,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RDX,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x88(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xf0(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R13,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0xd8(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EAX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe0(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RAX,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
ADD %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R10,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R14D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RCX,%RSI,8),%XMM6,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R13,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R12,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%RBX,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R15,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R9,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x98(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0xe8(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x100(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0xf8(%RBP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VINSERTF128 $0x1,%XMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF128 $0x1,%XMM3,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VADDPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VINSERTF128 $0x1,%XMM5,%YMM6,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VADDPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VINSERTF128 $0x1,%XMM7,%YMM8,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VADDPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %YMM0,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVLPD %XMM1,(%RAX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM1,(%RAX,%R8,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVLPD %XMM1,(%RAX,%RCX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM1,(%RAX,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
MOV -0x110(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x4,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x108(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $-0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xd0(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xc8(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xc0(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 238489 <.omp_outlined..8.314+0x489>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RCX),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,-0x108(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 2383e0 <.omp_outlined..8.314+0x3e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 2383eb <.omp_outlined..8.314+0x3eb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RCX),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 238420 <.omp_outlined..8.314+0x420>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23842f <.omp_outlined..8.314+0x42f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x3(%RCX),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,-0x110(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 238460 <.omp_outlined..8.314+0x460>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R14	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23846d <.omp_outlined..8.314+0x46d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 238160 <.omp_outlined..8.314+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23816b <.omp_outlined..8.314+0x16b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1.01	0	1.01	0	1.01	0	0.68	0.36	0.45	0.71

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	29.12	1.7
2x2	4	1	2	2	14.62	1.7
2x4	8	1	3.99	4	7.32	1.69
2x8	16	1.01	8.04	8	3.65	1.68
2x16	32	1.01	16.17	16	1.81	1.58
2x32	64	1.01	32.34	32	0.93	1.35
2x64	128	0.68	43.45	64	0.79	1.13
2x96	192	0.45	42.81	96	0.72	1.29

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency