OV - - Loop 171

	Loop Id: 171	Module: exec	Source: advec_mom.cpp:147-149 [...]	Coverage: 2.93%

0x239e10 MOV	%R9,%RAX

0x239e13 CQTO

0x239e15 IDIV	%RBX

0x239e18 ADD	%R15D,%R8D

0x239e1b ADD	%R15D,%EAX

0x239e1e MOV	-0x38(%RBP),%R15    [11]

0x239e22 LEA	(%R15,%RDI,1),%R9D

0x239e26 LEA	(%R15,%RDX,1),%R13D

0x239e2a MOVSXD	%R9D,%R15

0x239e2d MOVSXD	%R13D,%R9

0x239e30 MOVSXD	%R8D,%R8

0x239e33 CLTQ

0x239e35 MOV	-0x78(%RBP),%R12    [11]

0x239e39 MOV	%R12,%R13

0x239e3c IMUL	%R8,%R13

0x239e40 ADD	%R15,%R13

0x239e43 MOV	-0x70(%RBP),%RBX    [11]

0x239e47 VMOVSD	(%RBX,%R13,8),%XMM0    [10]

0x239e4d IMUL	%RAX,%R12

0x239e51 ADD	%R9,%R12

0x239e54 VMOVHPD	(%RBX,%R12,8),%XMM0,%XMM0    [6]

0x239e5a MOV	-0x50(%RBP),%R13    [11]

0x239e5e ADD	%R13D,%EDI

0x239e61 ADD	%R13D,%EDX

0x239e64 MOVSXD	%EDI,%RDI

0x239e67 MOVSXD	%EDX,%RDX

0x239e6a MOV	-0x68(%RBP),%RBX    [11]

0x239e6e MOV	%RBX,%R13

0x239e71 IMUL	%R8,%R13

0x239e75 ADD	%R13,%RDI

0x239e78 VMOVSD	(%R10,%RDI,8),%XMM1    [3]

0x239e7e MOV	%RBX,%RDI

0x239e81 IMUL	%RAX,%RDI

0x239e85 ADD	%RDI,%RDX

0x239e88 VMOVHPD	(%R10,%RDX,8),%XMM1,%XMM1    [2]

0x239e8e ADD	%R15,%R13

0x239e91 VMOVSD	(%R10,%R13,8),%XMM2    [7]

0x239e97 ADD	%R9,%RDI

0x239e9a VMOVHPD	(%R10,%RDI,8),%XMM2,%XMM2    [9]

0x239ea0 MOV	-0x80(%RBP),%RDI    [11]

0x239ea4 MOV	%RDI,%RDX

0x239ea7 IMUL	%R8,%RDX

0x239eab ADD	%R15,%RDX

0x239eae MOV	-0x60(%RBP),%RBX    [11]

0x239eb2 IMUL	%RBX,%R8

0x239eb6 ADD	%R15,%R8

0x239eb9 MOV	-0x58(%RBP),%R15    [11]

0x239ebd VMOVSD	(%R15,%R8,8),%XMM3    [4]

0x239ec3 IMUL	%RAX,%RDI

0x239ec7 IMUL	%RBX,%RAX

0x239ecb ADD	%R9,%RAX

0x239ece VMOVHPD	(%R15,%RAX,8),%XMM3,%XMM3    [5]

0x239ed4 ADD	%R9,%RDI

0x239ed7 VMOVSD	(%R11,%RDX,8),%XMM4    [1]

0x239edd VMOVHPD	(%R11,%RDI,8),%XMM4,%XMM4    [8]

0x239ee3 VMULPD	%XMM0,%XMM4,%XMM0

0x239ee7 VADDPD	%XMM1,%XMM0,%XMM0

0x239eeb VSUBPD	%XMM2,%XMM0,%XMM0

0x239eef VDIVPD	%XMM3,%XMM0,%XMM0

0x239ef3 VMOVLPD	%XMM0,(%R11,%RDX,8)    [1]

0x239ef9 VMOVHPD	%XMM0,(%R11,%RDI,8)    [8]

0x239eff ADD	$0x2,%RSI

0x239f03 ADD	$-0x2,%R14

0x239f07 MOV	-0xa8(%RBP),%RBX    [11]

0x239f0e JE	239f58

0x239f10 LEA	0x1(%RSI),%R9

0x239f14 MOV	%RSI,%RAX

0x239f17 SHR	$0x20,%RAX

0x239f1b JE	239f30

0x239f1d MOV	%RSI,%RAX

0x239f20 CQTO

0x239f22 IDIV	%RBX

0x239f25 MOV	%RDX,%RDI

0x239f28 MOV	%RAX,%R8

0x239f2b JMP	239f3b

0x239f30 MOV	%ESI,%EAX

0x239f32 XOR	%EDX,%EDX

0x239f34 DIV	%EBX

0x239f36 MOV	%EDX,%EDI

0x239f38 MOV	%EAX,%R8D

0x239f3b MOV	-0x2c(%RBP),%R15D    [11]

0x239f3f MOV	%R9,%RAX

0x239f42 SHR	$0x20,%RAX

0x239f46 JNE	239e10

0x239f4c MOV	%R9D,%EAX

0x239f4f XOR	%EDX,%EDX

0x239f51 DIV	%EBX

0x239f53 JMP	239e18

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 147 - 149

--------------------------------------------------------------------------------

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	3.60 - 4.60
CQA speedup if FP arith vectorized	1.12
CQA speedup if fully vectorized	3.60 - 3.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35 - 1.73
Bottlenecks
Function	.omp_outlined..14.317
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	18.00 - 23.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.50 - 20.50
CQA cycles if fully vectorized	5.00 - 6.25
Front-end cycles	13.33
DIV/SQRT cycles	9.56
P0 cycles	9.56
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	3.88
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	1.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	18.00 - 23.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	80.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.44 - 0.35
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.75 - 9.57
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	9.00
Stride indirect	0.00
Vectorization ratio all	19.07
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	14.58
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.60 - 4.60
CQA speedup if FP arith vectorized	1.12
CQA speedup if fully vectorized	3.60 - 3.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33 - 1.70
Bottlenecks	P8, P9,
Function	.omp_outlined..14.317
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	18.00 - 23.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.50 - 20.50
CQA cycles if fully vectorized	5.00 - 6.25
Front-end cycles	13.50
DIV/SQRT cycles	9.75
P0 cycles	9.75
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	4.50
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	1.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	18.00 - 23.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	81.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.44 - 0.35
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.48 - 9.56
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	9.00
Stride indirect	0.00
Vectorization ratio all	19.05
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	14.58
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.80 - 5.80
CQA speedup if FP arith vectorized	1.09
CQA speedup if fully vectorized	3.17 - 3.41
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44 - 2.20
Bottlenecks	P8, P9,
Function	.omp_outlined..14.317
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	19.00 - 29.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	16.50 - 26.50
CQA cycles if fully vectorized	6.00 - 8.50
Front-end cycles	13.17
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	4.00
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	1.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	19.00 - 29.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.42 - 0.28
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.93 - 9.05
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	9.00
Stride indirect	0.00
Vectorization ratio all	18.18
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.77
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	16.67
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.40
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	4.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P8, P9,
Function	.omp_outlined..14.317
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	17.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	4.00
Front-end cycles	13.50
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	4.00
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	1.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	17.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	81.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.47
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.12
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	9.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.60 - 4.60
CQA speedup if FP arith vectorized	1.12
CQA speedup if fully vectorized	3.60 - 3.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37 - 1.75
Bottlenecks	P8, P9,
Function	.omp_outlined..14.317
Source	advec_mom.cpp:147-149,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	18.00 - 23.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.50 - 20.50
CQA cycles if fully vectorized	5.00 - 6.25
Front-end cycles	13.17
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	3.00
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	1.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	18.00 - 23.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	79.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	10.00
FLOP/cycle	0.44 - 0.35
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.48 - 9.56
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	9.00
Stride indirect	0.00
Vectorization ratio all	19.05
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	14.58
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..14.317
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 2 (including vectorization).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 23.00 to 6.25 cycles (3.68x speedup).

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.00 to 13.00 cycles (1.77x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1.33 occurrences
IDIV: 1.33 occurrences
VMOVHPD: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1.33 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
2: multiply
2: divide

The binary loop is loading 156 bytes (19 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	80
loop length	301.50
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.56	9.56	9.50	9.50	3.88	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00
cycles	9.56	9.56	9.50	9.50	3.88	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	18.00-23.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.33
Dispatch	9.56
DIV/SQRT	18.00-23.00
Data deps.	1.00
Overall L1	18.00-23.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	33%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	14%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

7% of peak load performance is reached (7.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.72 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	.omp_outlined..14.317
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 5.00 cycles (4.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 13.50 cycles (1.70x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.00 to 13.17 cycles (1.75x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences
VMOVHPD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
2: multiply
2: divide

The binary loop is loading 156 bytes (19 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	80
nb uops	81
loop length	306
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.75	9.75	9.50	9.50	4.50	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00
cycles	9.75	9.75	9.50	9.50	4.50	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	18.00-23.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.50
Dispatch	9.75
DIV/SQRT	18.00-23.00
Data deps.	1.00
Overall L1	18.00-23.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	33%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	14%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

7% of peak load performance is reached (6.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.70 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 239f10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD %R15D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R15D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R15,%RDI,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R15,%RDX,1),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R9D,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R13D,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV -0x78(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RBX,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RBX,%R12,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R13D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R13D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%RDI,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R13,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDI,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R15,%R8,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RBX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R15,%RAX,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVPD %XMM3,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVLPD %XMM0,(%R11,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM0,(%R11,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x2,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xa8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 239f58 <.omp_outlined..14.317+0x2a8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 239f30 <.omp_outlined..14.317+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 239f3b <.omp_outlined..14.317+0x28b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 239e10 <.omp_outlined..14.317+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
JMP 239e18 <.omp_outlined..14.317+0x168>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..14.317
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.00 to 5.00 cycles (5.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.00 to 12.83 cycles (2.26x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 2 occurrences
VMOVHPD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
2: multiply
2: divide

The binary loop is loading 156 bytes (19 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	79
loop length	302
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.50	9.50	4.00	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00
cycles	9.50	9.50	9.50	9.50	4.00	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	19.00-29.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.17
Dispatch	9.50
DIV/SQRT	19.00-29.00
Data deps.	1.00
Overall L1	19.00-29.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	18%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	33%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	16%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 29.00 cycles. At this rate:

5% of peak load performance is reached (5.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.55 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 239f10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
ADD %R15D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R15D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R15,%RDI,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R15,%RDX,1),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R9D,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R13D,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV -0x78(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RBX,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RBX,%R12,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R13D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R13D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%RDI,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R13,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDI,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R15,%R8,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RBX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R15,%RAX,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVPD %XMM3,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVLPD %XMM0,(%R11,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM0,(%R11,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x2,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xa8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 239f58 <.omp_outlined..14.317+0x2a8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 239f30 <.omp_outlined..14.317+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 239f3b <.omp_outlined..14.317+0x28b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 239e10 <.omp_outlined..14.317+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined..14.317
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 5.00 cycles (3.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.00 to 4.00 cycles (4.25x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 13.17 cycles (1.29x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences
VMOVHPD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
2: multiply
2: divide

The binary loop is loading 156 bytes (19 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	81
loop length	301
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.50	9.50	4.00	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00
cycles	9.50	9.50	9.50	9.50	4.00	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	17.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.50
Dispatch	9.50
DIV/SQRT	17.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	20%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	33%
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

9% of peak load performance is reached (9.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 239f10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD %R15D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R15D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R15,%RDI,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R15,%RDX,1),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R9D,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R13D,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV -0x78(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RBX,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RBX,%R12,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R13D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R13D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%RDI,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R13,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDI,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R15,%R8,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RBX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R15,%RAX,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVPD %XMM3,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVLPD %XMM0,(%R11,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM0,(%R11,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x2,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xa8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 239f58 <.omp_outlined..14.317+0x2a8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 239f30 <.omp_outlined..14.317+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 239e10 <.omp_outlined..14.317+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
JMP 239e18 <.omp_outlined..14.317+0x168>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..14.317
Source file and lines	advec_mom.cpp:147-149
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:147-149
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 5.00 cycles (4.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.00 to 12.83 cycles (1.79x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences
VMOVHPD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
2: multiply
2: divide

The binary loop is loading 156 bytes (19 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	78
nb uops	79
loop length	297
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.50	9.50	3.00	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00
cycles	9.50	9.50	9.50	9.50	3.00	7.33	7.33	7.33	1.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	18.00-23.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.17
Dispatch	9.50
DIV/SQRT	18.00-23.00
Data deps.	1.00
Overall L1	18.00-23.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	0%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	33%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	12%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	14%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

7% of peak load performance is reached (6.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.70 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 239f10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
ADD %R15D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R15D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R15,%RDI,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R15,%RDX,1),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R9D,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R13D,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV -0x78(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RBX,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%RBX,%R12,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R13D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R13D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%RDI,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R13,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R10,%RDI,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R8,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R15,%R8,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RBX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R15,%RAX,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVPD %XMM3,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVLPD %XMM0,(%R11,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVHPD %XMM0,(%R11,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0.50	0.50	9-11	1
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x2,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xa8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 239f58 <.omp_outlined..14.317+0x2a8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 239f30 <.omp_outlined..14.317+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 239e10 <.omp_outlined..14.317+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	-0	0.98	0.05	0.71	0.95	0.36	2.37	0.24	3.17

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	50.37	2.93
2x2	4	1	2	2	25.21	2.93
2x4	8	1	4.01	4	12.59	2.91
2x8	16	1	8.01	8	6.33	2.91
2x16	32	0.98	15.72	16	3.38	2.81
2x32	64	0.71	22.76	32	2.49	3.3
2x64	128	0.36	22.96	64	2.58	3.69
2x96	192	0.24	22.96	96	2.25	4.17

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