OV - - Loop 183

	Loop Id: 183	Module: exec	Source: build_field.cpp:119-128 [...]	Coverage: 0.05%

0x23c8e0 MOV	%R9,%RAX

0x23c8e3 CQTO

0x23c8e5 IDIV	%R13

0x23c8e8 MOVSXD	%R8D,%R8

0x23c8eb MOVSXD	%EDX,%RDX

0x23c8ee MOVSXD	%EDI,%RDI

0x23c8f1 CLTQ

0x23c8f3 MOV	%RDI,%R9

0x23c8f6 MOV	-0xa0(%RBP),%R11    [14]

0x23c8fd IMUL	%R11,%R9

0x23c901 ADD	%R8,%R9

0x23c904 MOV	-0x58(%RBP),%RBX    [14]

0x23c908 MOVQ	$0,(%RBX,%R9,8)    [6]

0x23c910 MOV	%RAX,%R9

0x23c913 IMUL	%R11,%R9

0x23c917 ADD	%RDX,%R9

0x23c91a MOVQ	$0,(%RBX,%R9,8)    [11]

0x23c922 MOV	%RDI,%R9

0x23c925 IMUL	%R10,%R9

0x23c929 ADD	%R8,%R9

0x23c92c MOV	-0xe8(%RBP),%R11    [14]

0x23c933 MOVQ	$0,(%R11,%R9,8)    [10]

0x23c93b MOV	%RAX,%R9

0x23c93e IMUL	%R10,%R9

0x23c942 ADD	%RDX,%R9

0x23c945 MOVQ	$0,(%R11,%R9,8)    [8]

0x23c94d MOV	%RDI,%R9

0x23c950 MOV	-0x98(%RBP),%R15    [14]

0x23c957 IMUL	%R15,%R9

0x23c95b ADD	%R8,%R9

0x23c95e MOV	-0x50(%RBP),%R12    [14]

0x23c962 MOVQ	$0,(%R12,%R9,8)    [5]

0x23c96a MOV	%RAX,%R9

0x23c96d IMUL	%R15,%R9

0x23c971 ADD	%RDX,%R9

0x23c974 MOVQ	$0,(%R12,%R9,8)    [12]

0x23c97c MOV	%RDI,%R9

0x23c97f MOV	-0xd8(%RBP),%R12    [14]

0x23c986 IMUL	%R12,%R9

0x23c98a ADD	%R8,%R9

0x23c98d MOV	-0xe0(%RBP),%R15    [14]

0x23c994 MOVQ	$0,(%R15,%R9,8)    [9]

0x23c99c MOV	%RAX,%R9

0x23c99f IMUL	%R12,%R9

0x23c9a3 ADD	%RDX,%R9

0x23c9a6 MOVQ	$0,(%R15,%R9,8)    [4]

0x23c9ae MOV	%RDI,%R9

0x23c9b1 MOV	-0x88(%RBP),%R13    [14]

0x23c9b8 IMUL	%R13,%R9

0x23c9bc ADD	%R8,%R9

0x23c9bf MOV	-0x90(%RBP),%R14    [14]

0x23c9c6 MOVQ	$0,(%R14,%R9,8)    [16]

0x23c9ce MOV	%RAX,%R9

0x23c9d1 IMUL	%R13,%R9

0x23c9d5 ADD	%RDX,%R9

0x23c9d8 MOVQ	$0,(%R14,%R9,8)    [17]

0x23c9e0 MOV	%RDI,%R9

0x23c9e3 MOV	-0x80(%RBP),%R13    [14]

0x23c9e7 IMUL	%R13,%R9

0x23c9eb ADD	%R8,%R9

0x23c9ee MOV	-0x60(%RBP),%R14    [14]

0x23c9f2 MOVQ	$0,(%R14,%R9,8)    [2]

0x23c9fa MOV	%RAX,%R9

0x23c9fd IMUL	%R13,%R9

0x23ca01 ADD	%RDX,%R9

0x23ca04 MOVQ	$0,(%R14,%R9,8)    [3]

0x23ca0c MOV	%RDI,%R9

0x23ca0f MOV	-0x70(%RBP),%RBX    [14]

0x23ca13 IMUL	%RBX,%R9

0x23ca17 ADD	%R8,%R9

0x23ca1a MOV	-0x78(%RBP),%R13    [14]

0x23ca1e MOVQ	$0,(%R13,%R9,8)    [7]

0x23ca27 MOV	%RAX,%R9

0x23ca2a IMUL	%RBX,%R9

0x23ca2e ADD	%RDX,%R9

0x23ca31 MOVQ	$0,(%R13,%R9,8)    [1]

0x23ca3a MOV	-0x68(%RBP),%R9    [14]

0x23ca3e IMUL	%R9,%RDI

0x23ca42 ADD	%R8,%RDI

0x23ca45 IMUL	%R9,%RAX

0x23ca49 ADD	%RDX,%RAX

0x23ca4c MOV	-0xc8(%RBP),%RBX    [14]

0x23ca53 MOVQ	$0,(%RBX,%RDI,8)    [13]

0x23ca5b MOVQ	$0,(%RBX,%RAX,8)    [15]

0x23ca63 ADD	$0x2,%RSI

0x23ca67 MOV	-0xf0(%RBP),%RDX    [14]

0x23ca6e ADD	$-0x2,%RDX

0x23ca72 MOV	-0xd0(%RBP),%R13    [14]

0x23ca79 JE	23cad9

0x23ca7b LEA	0x1(%RSI),%R9

0x23ca7f MOV	%RSI,%RAX

0x23ca82 OR	%R13,%RAX

0x23ca85 SHR	$0x20,%RAX

0x23ca89 MOV	%RDX,-0xf0(%RBP)    [14]

0x23ca90 JE	23cab0

0x23ca92 MOV	%RSI,%RAX

0x23ca95 CQTO

0x23ca97 IDIV	%R13

0x23ca9a MOV	%RDX,%R8

0x23ca9d MOV	%RAX,%RDI

0x23caa0 JMP	23cabc

0x23cab0 MOV	%ESI,%EAX

0x23cab2 XOR	%EDX,%EDX

0x23cab4 DIVL	-0x2c(%RBP)    [14]

0x23cab7 MOV	%EDX,%R8D

0x23caba MOV	%EAX,%EDI

0x23cabc MOV	%R9,%RAX

0x23cabf OR	%R13,%RAX

0x23cac2 SHR	$0x20,%RAX

0x23cac6 JNE	23c8e0

0x23cacc MOV	%R9D,%EAX

0x23cacf XOR	%EDX,%EDX

0x23cad1 DIVL	-0x2c(%RBP)    [14]

0x23cad4 JMP	23c8e8

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp: 119 - 128

--------------------------------------------------------------------------------

119:     for (int j = (0); j < (yrange); j++) {

120:       for (int i = (0); i < (xrange); i++) {

121:         field.density0(i, j) = 0.0;

122:         field.density1(i, j) = 0.0;

123:         field.energy0(i, j) = 0.0;

124:         field.energy1(i, j) = 0.0;

125:         field.pressure(i, j) = 0.0;

126:         field.viscosity(i, j) = 0.0;

127:         field.soundspeed(i, j) = 0.0;

128:         field.volume(i, j) = 0.0;

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.81 - 5.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10 - 1.14
Bottlenecks
Function	.omp_outlined..2.325
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	17.67 - 19.50
CQA cycles if no scalar integer	17.67 - 19.50
CQA cycles if FP arith vectorized	17.67 - 19.50
CQA cycles if fully vectorized	2.59 - 3.84
Front-end cycles	17.67
DIV/SQRT cycles	10.06
P0 cycles	16.00
P1 cycles	10.06
P2 cycles	10.00
P3 cycles	3.88
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	13.00 - 18.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	106.00
Nb loads	18.00
Nb stores	17.00
Nb stack references	17.75
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.39 - 15.62
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	136.00
Stride 0	1.00
Stride 1	5.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.73
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.62
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	11.59

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.13 - 4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11 - 1.01
Bottlenecks	P8, P9,
Function	.omp_outlined..2.325
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	17.83 - 18.00
CQA cycles if no scalar integer	17.83 - 18.00
CQA cycles if FP arith vectorized	17.83 - 18.00
CQA cycles if fully vectorized	2.50 - 3.75
Front-end cycles	17.83
DIV/SQRT cycles	10.25
P0 cycles	16.00
P1 cycles	10.25
P2 cycles	10.00
P3 cycles	4.50
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	13.00 - 18.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	106.00
Nb uops	107.00
Nb loads	18.00
Nb stores	17.00
Nb stack references	18.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.33 - 15.48
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	136.00
Stride 0	1.00
Stride 1	5.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.88
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.62
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.95 - 4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08 - 1.38
Bottlenecks	P8, P9,
Function	.omp_outlined..2.325
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	17.33 - 24.00
CQA cycles if no scalar integer	17.33 - 24.00
CQA cycles if FP arith vectorized	17.33 - 24.00
CQA cycles if fully vectorized	3.50 - 6.00
Front-end cycles	17.33
DIV/SQRT cycles	10.00
P0 cycles	16.00
P1 cycles	10.00
P2 cycles	10.00
P3 cycles	4.00
P4 cycles	11.33
P5 cycles	11.33
P6 cycles	11.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	14.00 - 24.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	104.00
Nb loads	17.00
Nb stores	17.00
Nb stack references	17.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.33 - 15.69
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	136.00
Stride 0	1.00
Stride 1	5.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.62
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	.omp_outlined..2.325
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	1.88
Front-end cycles	18.00
DIV/SQRT cycles	10.00
P0 cycles	16.00
P1 cycles	10.00
P2 cycles	10.00
P3 cycles	4.00
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	12.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	108.00
Nb loads	19.00
Nb stores	17.00
Nb stack references	18.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.56
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	136.00
Stride 0	1.00
Stride 1	5.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.10
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.62
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.00 - 4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09 - 1.03
Bottlenecks	P8, P9,
Function	.omp_outlined..2.325
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	17.50 - 18.00
CQA cycles if no scalar integer	17.50 - 18.00
CQA cycles if FP arith vectorized	17.50 - 18.00
CQA cycles if fully vectorized	2.50 - 3.75
Front-end cycles	17.50
DIV/SQRT cycles	10.00
P0 cycles	16.00
P1 cycles	10.00
P2 cycles	10.00
P3 cycles	3.00
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	13.00 - 18.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	104.00
Nb uops	105.00
Nb loads	18.00
Nb stores	17.00
Nb stack references	18.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.33 - 15.77
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	136.00
Stride 0	1.00
Stride 1	5.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.61
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.62
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2.325
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 2 (including vectorization).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 19.50 to 3.84 cycles (5.07x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 19.50 to 17.17 cycles (1.14x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1.33 occurrences
IDIV: 1.33 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1.33 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 140 bytes. The binary loop is storing 136 bytes.

General properties

nb instructions	105
nb uops	106
loop length	466.50
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	17.75

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	17.67 cycles
front end	17.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.06	16.00	10.06	10.00	3.88	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.06	16.00	10.06	10.00	3.88	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	13.00-18.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.67
Dispatch	16.00
DIV/SQRT	13.00-18.00
Data deps.	0.00
Overall L1	17.67-19.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.50 cycles. At this rate:

7% of peak load performance is reached (7.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.08 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	.omp_outlined..2.325
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 140 bytes. The binary loop is storing 136 bytes.

General properties

nb instructions	106
nb uops	107
loop length	471
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	16.00	10.25	10.00	4.50	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.25	16.00	10.25	10.00	4.50	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	13.00-18.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.83
Dispatch	16.00
DIV/SQRT	13.00-18.00
Data deps.	0.00
Overall L1	17.83-18.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

8% of peak load performance is reached (7.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23ca7b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe8(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x98(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xd8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe0(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x88(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x90(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x68(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R9,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xc8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $-0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xd0(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 23cad9 <.omp_outlined..2.325+0x3a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,-0xf0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 23cab0 <.omp_outlined..2.325+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R13	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23cabc <.omp_outlined..2.325+0x38c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 23c8e0 <.omp_outlined..2.325+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIVL -0x2c(%RBP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	10-17	6
JMP 23c8e8 <.omp_outlined..2.325+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..2.325
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 24.00 to 6.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 17.33 cycles (1.38x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.00 to 17.00 cycles (1.41x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 136 bytes.

General properties

nb instructions	105
nb uops	104
loop length	466
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.33 cycles
front end	17.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.00	16.00	10.00	10.00	4.00	11.33	11.33	11.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.00	16.00	10.00	10.00	4.00	11.33	11.33	11.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	14.00-24.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.33
Dispatch	16.00
DIV/SQRT	14.00-24.00
Data deps.	0.00
Overall L1	17.33-24.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

5% of peak load performance is reached (5.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23ca7b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R13	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe8(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x98(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xd8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe0(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x88(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x90(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x68(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R9,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xc8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $-0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xd0(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 23cad9 <.omp_outlined..2.325+0x3a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,-0xf0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 23cab0 <.omp_outlined..2.325+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R13	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 23cabc <.omp_outlined..2.325+0x38c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 23c8e0 <.omp_outlined..2.325+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined..2.325
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 136 bytes.

General properties

nb instructions	105
nb uops	108
loop length	467
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.00	16.00	10.00	10.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.00	16.00	10.00	10.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.00
Dispatch	16.00
DIV/SQRT	12.00
Data deps.	0.00
Overall L1	18.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.00 to 16.00 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 23ca7b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe8(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x98(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xd8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe0(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x88(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x90(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x68(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R9,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xc8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $-0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xd0(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 23cad9 <.omp_outlined..2.325+0x3a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,-0xf0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 23cab0 <.omp_outlined..2.325+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIVL -0x2c(%RBP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	10-17	6
MOV %EDX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 23c8e0 <.omp_outlined..2.325+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIVL -0x2c(%RBP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	10-17	6
JMP 23c8e8 <.omp_outlined..2.325+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..2.325
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.00 to 17.00 cycles (1.06x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 140 bytes. The binary loop is storing 136 bytes.

General properties

nb instructions	104
nb uops	105
loop length	462
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.00	16.00	10.00	10.00	3.00	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.00	16.00	10.00	10.00	3.00	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	13.00-18.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.50
Dispatch	16.00
DIV/SQRT	13.00-18.00
Data deps.	0.00
Overall L1	17.50-18.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

8% of peak load performance is reached (7.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23ca7b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R13	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOVSXD %R8D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CLTQ
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%RBX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe8(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R11,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x98(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R12,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0xd8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xe0(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R15,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x88(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x90(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R14,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x78(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,(%R13,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x68(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R9,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xc8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ $0,(%RBX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $-0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0xd0(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 23cad9 <.omp_outlined..2.325+0x3a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA 0x1(%RSI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,-0xf0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 23cab0 <.omp_outlined..2.325+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIVL -0x2c(%RBP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	10-17	6
MOV %EDX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 23c8e0 <.omp_outlined..2.325+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.05	-0	1.08	-0	1.08	-0	0.97	0	0.81	0.01	0.3	0.04	0.2	0.06

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.8	0.05
2x2	4	1.05	2.11	2	0.4	0.04
2x4	8	1.08	4.33	4	0.2	0.04
2x8	16	1.08	8.67	8	0.11	0.04
2x16	32	0.97	15.6	16	0.06	0.04
2x32	64	0.81	26	32	0.04	0.04
2x64	128	0.3	19.5	64	0.06	0.06
2x96	192	0.2	19.5	96	0.06	0.07

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