OV - - Loop 280

	Loop Id: 280	Module: exec	Source: generate_chunk.cpp:86-123 [...]	Coverage: 0.02%

0x246cc0 MOV	-0x2c(%RBP),%R15D    [54]

0x246cc4 MOV	-0x38(%RBP),%R10    [54]

0x246cc8 MOV	0x18(%RBP),%R14    [54]

0x246ccc MOV	0x10(%RBP),%R9    [54]

0x246cd0 LEA	0x1(%R12),%RAX

0x246cd5 CMP	-0x40(%RBP),%R12    [54]

0x246cd9 MOV	%RAX,%R12

0x246cdc JGE	246c71

0x246cde MOV	%R12,%RAX

0x246ce1 OR	%R10,%RAX

0x246ce4 SHR	$0x20,%RAX

0x246ce8 JE	246d00

0x246cea MOV	%R12,%RAX

0x246ced CQTO

0x246cef IDIV	%R10

0x246cf2 MOV	%RAX,%R13

0x246cf5 JMP	246d0b

0x246d00 MOV	%R12D,%EAX

0x246d03 XOR	%EDX,%EDX

0x246d05 DIV	%R15D

0x246d08 MOV	%EAX,%R13D

0x246d0b MOVSXD	%ECX,%RAX

0x246d0e MOV	0x8(%RBX),%RSI    [61]

0x246d12 VMOVSD	(%RSI,%RAX,8),%XMM1    [20]

0x246d17 MOV	0x8(%R9),%RSI    [6]

0x246d1b VMOVSD	(%RSI,%RAX,8),%XMM0    [4]

0x246d20 MOV	0x8(%R14),%RSI    [41]

0x246d24 MOV	(%RSI,%RAX,4),%ESI    [19]

0x246d27 CMP	$0x3,%ESI

0x246d2a JE	246f20

0x246d30 CMP	$0x2,%ESI

0x246d33 JE	2470a0

0x246d39 CMP	$0x1,%ESI

0x246d3c JNE	246cd0

0x246d3e SAL	$0x20,%RDX

0x246d42 MOV	$0x100000000,%RSI

0x246d4c LEA	(%RDX,%RSI,1),%RDI

0x246d50 MOV	0x258(%R11),%RSI    [28]

0x246d57 SAR	$0x1d,%RDI

0x246d5b VMOVSD	(%RSI,%RDI,1),%XMM2    [29]

0x246d60 VUCOMISD	%XMM1,%XMM2

0x246d64 JB	246cd0

0x246d6a MOV	%RDX,%RDI

0x246d6d SAR	$0x1d,%RDI

0x246d71 MOV	0x28(%RBP),%R8    [54]

0x246d75 MOV	0x8(%R8),%R8    [42]

0x246d79 VMOVSD	(%R8,%RAX,8),%XMM1    [26]

0x246d7f VUCOMISD	(%RSI,%RDI,1),%XMM1    [40]

0x246d84 JBE	246cd0

0x246d8a MOV	%R13,%RSI

0x246d8d SAL	$0x20,%RSI

0x246d91 MOV	$0x100000000,%RDI

0x246d9b LEA	(%RSI,%RDI,1),%R8

0x246d9f MOV	0x278(%R11),%RDI    [28]

0x246da6 SAR	$0x1d,%R8

0x246daa VMOVSD	(%RDI,%R8,1),%XMM1    [48]

0x246db0 VUCOMISD	%XMM0,%XMM1

0x246db4 JB	246cd0

0x246dba MOV	%RSI,%R8

0x246dbd SAR	$0x1d,%R8

0x246dc1 MOV	0x30(%RBP),%R9    [54]

0x246dc5 MOV	0x8(%R9),%R9    [8]

0x246dc9 VMOVSD	(%R9,%RAX,8),%XMM0    [17]

0x246dcf VUCOMISD	(%RDI,%R8,1),%XMM0    [58]

0x246dd5 JBE	246ccc

0x246ddb SAR	$0x20,%RDX

0x246ddf SAR	$0x20,%RSI

0x246de3 MOV	0x38(%RBP),%RDI    [54]

0x246de7 MOV	0x8(%RDI),%RDI    [24]

0x246deb VMOVSD	(%RDI,%RAX,8),%XMM0    [10]

0x246df0 MOV	0x40(%R11),%RDI    [28]

0x246df4 MOV	0x30(%R11),%R8    [28]

0x246df8 IMUL	%RSI,%R8

0x246dfc ADD	%RDX,%R8

0x246dff VMOVSD	%XMM0,(%RDI,%R8,8)    [21]

0x246e05 MOV	0x40(%RBP),%RDI    [54]

0x246e09 MOV	0x8(%RDI),%RDI    [65]

0x246e0d VMOVSD	(%RDI,%RAX,8),%XMM0    [5]

0x246e12 MOV	0x10(%R11),%RDI    [28]

0x246e16 MOV	(%R11),%R8    [28]

0x246e19 IMUL	%RSI,%R8

0x246e1d ADD	%RDX,%R8

0x246e20 VMOVSD	%XMM0,(%RDI,%R8,8)    [2]

0x246e26 MOV	0x48(%RBP),%RDX    [54]

0x246e2a MOV	0x8(%RDX),%RDI    [11]

0x246e2e MOV	0xa8(%R11),%R10    [28]

0x246e35 MOV	0xb8(%R11),%R8    [28]

0x246e3c MOV	0x50(%RBP),%RDX    [54]

0x246e40 MOV	0x8(%RDX),%R9    [49]

0x246e44 MOV	0xe8(%R11),%RDX    [28]

0x246e4b MOV	0xd8(%R11),%R14    [28]

0x246e52 MOV	%R14,-0x68(%RBP)    [54]

0x246e56 MOV	-0x30(%RBP),%R11D    [54]

0x246e5a IMUL	%R13D,%R11D

0x246e5e ADD	%R12D,%R11D

0x246e61 MOVSXD	%R11D,%R11

0x246e64 MOV	%RSI,%R15

0x246e67 IMUL	%R10,%R15

0x246e6b MOV	%RSI,%R13

0x246e6e IMUL	%R14,%R13

0x246e72 VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x246e77 LEA	(%R15,%R11,1),%R14

0x246e7b VMOVSD	%XMM0,(%R8,%R14,8)    [64]

0x246e81 VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x246e87 LEA	(%R13,%R11,1),%R14

0x246e8c VMOVSD	%XMM0,(%RDX,%R14,8)    [53]

0x246e92 VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x246e97 LEA	0x1(%R11,%R15,1),%R14

0x246e9c MOV	-0x2c(%RBP),%R15D    [54]

0x246ea0 VMOVSD	%XMM0,(%R8,%R14,8)    [12]

0x246ea6 VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x246eac LEA	(%R11,%R13,1),%R14

0x246eb0 INC	%R14

0x246eb3 VMOVSD	%XMM0,(%RDX,%R14,8)    [13]

0x246eb9 INC	%RSI

0x246ebc IMUL	%RSI,%R10

0x246ec0 IMUL	-0x68(%RBP),%RSI    [54]

0x246ec5 VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x246eca LEA	(%R10,%R11,1),%R14

0x246ece VMOVSD	%XMM0,(%R8,%R14,8)    [60]

0x246ed4 VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x246eda LEA	(%RSI,%R11,1),%R14

0x246ede VMOVSD	%XMM0,(%RDX,%R14,8)    [67]

0x246ee4 MOV	0x18(%RBP),%R14    [54]

0x246ee8 VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x246eed LEA	0x1(%R11,%R10,1),%RDI

0x246ef2 MOV	-0x38(%RBP),%R10    [54]

0x246ef6 VMOVSD	%XMM0,(%R8,%RDI,8)    [25]

0x246efc VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x246f02 LEA	(%R11,%RSI,1),%RAX

0x246f06 INC	%RAX

0x246f09 MOV	0x20(%RBP),%R11    [54]

0x246f0d VMOVSD	%XMM0,(%RDX,%RAX,8)    [34]

0x246f12 JMP	246ccc

0x246f20 MOVSXD	%EDX,%RSI

0x246f23 MOV	0x258(%R11),%RDX    [28]

0x246f2a VMOVSD	(%RDX,%RSI,8),%XMM2    [52]

0x246f2f VUCOMISD	%XMM1,%XMM2

0x246f33 JNE	246cd0

0x246f39 JP	246cd0

0x246f3f MOVSXD	%R13D,%RDX

0x246f42 MOV	0x278(%R11),%RDI    [28]

0x246f49 VMOVSD	(%RDI,%RDX,8),%XMM1    [9]

0x246f4e VUCOMISD	%XMM0,%XMM1

0x246f52 JNE	246cd0

0x246f58 JP	246cd0

0x246f5e MOV	0x38(%RBP),%RDI    [54]

0x246f62 MOV	0x8(%RDI),%RDI    [24]

0x246f66 VMOVSD	(%RDI,%RAX,8),%XMM0    [10]

0x246f6b MOV	0x40(%R11),%RDI    [28]

0x246f6f MOV	0x30(%R11),%R8    [28]

0x246f73 IMUL	%RDX,%R8

0x246f77 ADD	%RSI,%R8

0x246f7a VMOVSD	%XMM0,(%RDI,%R8,8)    [37]

0x246f80 MOV	0x40(%RBP),%RDI    [54]

0x246f84 MOV	0x8(%RDI),%RDI    [65]

0x246f88 VMOVSD	(%RDI,%RAX,8),%XMM0    [5]

0x246f8d MOV	0x10(%R11),%RDI    [28]

0x246f91 MOV	(%R11),%R8    [28]

0x246f94 IMUL	%RDX,%R8

0x246f98 ADD	%RSI,%R8

0x246f9b VMOVSD	%XMM0,(%RDI,%R8,8)    [15]

0x246fa1 MOV	0x48(%RBP),%RSI    [54]

0x246fa5 MOV	0x8(%RSI),%RDI    [11]

0x246fa9 MOV	0xa8(%R11),%R10    [28]

0x246fb0 MOV	0xb8(%R11),%R8    [28]

0x246fb7 MOV	0x50(%RBP),%RSI    [54]

0x246fbb MOV	0x8(%RSI),%R9    [49]

0x246fbf MOV	0xe8(%R11),%RSI    [28]

0x246fc6 MOV	0xd8(%R11),%RBX    [28]

0x246fcd MOV	-0x30(%RBP),%R11D    [54]

0x246fd1 IMUL	%R13D,%R11D

0x246fd5 ADD	%R12D,%R11D

0x246fd8 MOVSXD	%R11D,%R11

0x246fdb MOV	%RDX,%R14

0x246fde IMUL	%R10,%R14

0x246fe2 MOV	%RDX,%R15

0x246fe5 IMUL	%RBX,%R15

0x246fe9 VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x246fee LEA	(%R14,%R11,1),%R13

0x246ff2 VMOVSD	%XMM0,(%R8,%R13,8)    [44]

0x246ff8 VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x246ffe LEA	(%R15,%R11,1),%R13

0x247002 VMOVSD	%XMM0,(%RSI,%R13,8)    [45]

0x247008 VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x24700d LEA	0x1(%R11,%R14,1),%R14

0x247012 VMOVSD	%XMM0,(%R8,%R14,8)    [63]

0x247018 VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x24701e LEA	0x1(%R11,%R15,1),%R14

0x247023 MOV	-0x2c(%RBP),%R15D    [54]

0x247027 VMOVSD	%XMM0,(%RSI,%R14,8)    [46]

0x24702d MOV	0x18(%RBP),%R14    [54]

0x247031 INC	%RDX

0x247034 IMUL	%RDX,%R10

0x247038 IMUL	%RBX,%RDX

0x24703c VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x247041 LEA	(%R10,%R11,1),%RBX

0x247045 VMOVSD	%XMM0,(%R8,%RBX,8)    [33]

0x24704b VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x247051 LEA	(%RDX,%R11,1),%RBX

0x247055 VMOVSD	%XMM0,(%RSI,%RBX,8)    [3]

0x24705a MOV	-0x50(%RBP),%RBX    [54]

0x24705e VMOVSD	(%RDI,%RAX,8),%XMM0    [66]

0x247063 LEA	0x1(%R11,%R10,1),%RDI

0x247068 MOV	-0x38(%RBP),%R10    [54]

0x24706c VMOVSD	%XMM0,(%R8,%RDI,8)    [7]

0x247072 VMOVSD	(%R9,%RAX,8),%XMM0    [55]

0x247078 MOV	0x10(%RBP),%R9    [54]

0x24707c LEA	(%R11,%RDX,1),%RAX

0x247080 INC	%RAX

0x247083 MOV	0x20(%RBP),%R11    [54]

0x247087 VMOVSD	%XMM0,(%RSI,%RAX,8)    [32]

0x24708c JMP	246cd0

0x2470a0 MOVSXD	%EDX,%R15

0x2470a3 MOV	0x218(%R11),%RAX    [28]

0x2470aa MOV	0x238(%R11),%RCX    [28]

0x2470b1 VMOVSD	(%RAX,%R15,8),%XMM2    [22]

0x2470b7 VSUBSD	%XMM1,%XMM2,%XMM1

0x2470bb MOVSXD	%R13D,%R14

0x2470be VMOVSD	(%RCX,%R14,8),%XMM2    [47]

0x2470c4 VSUBSD	%XMM0,%XMM2,%XMM0

0x2470c8 VMULSD	%XMM0,%XMM0,%XMM0

0x2470cc VMULSD	%XMM1,%XMM1,%XMM1

0x2470d0 VADDSD	%XMM0,%XMM1,%XMM0

0x2470d4 VUCOMISD	%XMM3,%XMM0

0x2470d8 JB	2470e0

0x2470da VSQRTSD	%XMM0,%XMM0,%XMM0

0x2470de JMP	2470ed

0x2470e0 CALL	2613a0 <@plt_start@+0x530>

0x2470e5 VXORPD	%XMM3,%XMM3,%XMM3

0x2470e9 MOV	0x20(%RBP),%R11    [54]

0x2470ed MOV	-0x58(%RBP),%RAX    [54]

0x2470f1 MOV	(%RAX),%ECX    [18]

0x2470f3 MOVSXD	%ECX,%RAX

0x2470f6 MOV	0x58(%RBP),%RDX    [54]

0x2470fa MOV	0x8(%RDX),%RDX    [1]

0x2470fe VMOVSD	(%RDX,%RAX,8),%XMM1    [14]

0x247103 VUCOMISD	%XMM0,%XMM1

0x247107 JB	246cc0

0x24710d MOV	0x38(%RBP),%RDX    [54]

0x247111 MOV	0x8(%RDX),%RDX    [24]

0x247115 VMOVSD	(%RDX,%RAX,8),%XMM0    [59]

0x24711a MOV	0x40(%R11),%RDX    [27]

0x24711e MOV	0x30(%R11),%RSI    [27]

0x247122 IMUL	%R14,%RSI

0x247126 ADD	%R15,%RSI

0x247129 VMOVSD	%XMM0,(%RDX,%RSI,8)    [31]

0x24712e MOV	0x40(%RBP),%RDX    [54]

0x247132 MOV	0x8(%RDX),%RDX    [65]

0x247136 VMOVSD	(%RDX,%RAX,8),%XMM0    [57]

0x24713b MOV	0x10(%R11),%RDX    [27]

0x24713f MOV	(%R11),%RSI    [27]

0x247142 IMUL	%R14,%RSI

0x247146 ADD	%R15,%RSI

0x247149 VMOVSD	%XMM0,(%RDX,%RSI,8)    [23]

0x24714e MOV	0x48(%RBP),%RDX    [54]

0x247152 MOV	0x8(%RDX),%RSI    [11]

0x247156 MOV	0xa8(%R11),%R9    [27]

0x24715d MOV	0xb8(%R11),%RDI    [27]

0x247164 MOV	0x50(%RBP),%RDX    [54]

0x247168 MOV	0x8(%RDX),%R8    [49]

0x24716c MOV	0xe8(%R11),%RDX    [27]

0x247173 MOV	0x20(%RBP),%R10    [54]

0x247177 MOV	0xd8(%R10),%R11    [16]

0x24717e MOV	-0x30(%RBP),%R10D    [54]

0x247182 IMUL	%R13D,%R10D

0x247186 ADD	%R12D,%R10D

0x247189 MOVSXD	%R10D,%R10

0x24718c MOV	%R14,%R15

0x24718f IMUL	%R9,%R15

0x247193 MOV	%R14,%R13

0x247196 IMUL	%R11,%R13

0x24719a VMOVSD	(%RSI,%RAX,8),%XMM0    [38]

0x24719f LEA	(%R15,%R10,1),%RBX

0x2471a3 VMOVSD	%XMM0,(%RDI,%RBX,8)    [51]

0x2471a8 VMOVSD	(%R8,%RAX,8),%XMM0    [36]

0x2471ae LEA	(%R13,%R10,1),%RBX

0x2471b3 VMOVSD	%XMM0,(%RDX,%RBX,8)    [50]

0x2471b8 VMOVSD	(%RSI,%RAX,8),%XMM0    [38]

0x2471bd LEA	0x1(%R10,%R15,1),%RBX

0x2471c2 VMOVSD	%XMM0,(%RDI,%RBX,8)    [56]

0x2471c7 VMOVSD	(%R8,%RAX,8),%XMM0    [36]

0x2471cd LEA	(%R10,%R13,1),%RBX

0x2471d1 INC	%RBX

0x2471d4 VMOVSD	%XMM0,(%RDX,%RBX,8)    [30]

0x2471d9 MOV	-0x50(%RBP),%RBX    [54]

0x2471dd INC	%R14

0x2471e0 IMUL	%R14,%R9

0x2471e4 IMUL	%R11,%R14

0x2471e8 VMOVSD	(%RSI,%RAX,8),%XMM0    [38]

0x2471ed LEA	(%R9,%R10,1),%R11

0x2471f1 VMOVSD	%XMM0,(%RDI,%R11,8)    [43]

0x2471f7 VMOVSD	(%R8,%RAX,8),%XMM0    [36]

0x2471fd LEA	(%R14,%R10,1),%R11

0x247201 VMOVSD	%XMM0,(%RDX,%R11,8)    [39]

0x247207 MOV	0x20(%RBP),%R11    [54]

0x24720b VMOVSD	(%RSI,%RAX,8),%XMM0    [38]

0x247210 LEA	0x1(%R10,%R9,1),%RSI

0x247215 VMOVSD	%XMM0,(%RDI,%RSI,8)    [35]

0x24721a VMOVSD	(%R8,%RAX,8),%XMM0    [36]

0x247220 LEA	(%R10,%R14,1),%RAX

0x247224 INC	%RAX

0x247227 VMOVSD	%XMM0,(%RDX,%RAX,8)    [62]

0x24722c JMP	246cc0

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 86 - 123

--------------------------------------------------------------------------------

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	2.28
CQA speedup if FP arith vectorized	1.76
CQA speedup if fully vectorized	4.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..2.368
Source	generate_chunk.cpp:86-98,generate_chunk.cpp:105-123,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	57.00
CQA cycles if no scalar integer	25.00
CQA cycles if FP arith vectorized	32.33
CQA cycles if fully vectorized	12.13
Front-end cycles	53.50
DIV/SQRT cycles	25.75
P0 cycles	25.75
P1 cycles	25.50
P2 cycles	25.50
P3 cycles	12.50
P4 cycles	57.00
P5 cycles	57.00
P6 cycles	57.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	19.00
P12 cycles	19.00
P13 cycles	21.50 - 26.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	304.00
Nb uops	321.00
Nb loads	132.00
Nb stores	31.00
Nb stack references	17.00
FLOP/cycle	0.11
Nb FLOP add-sub	3.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.32
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	248.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	7.14
Vector-efficiency ratio all	12.37
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	10.42
Vector-efficiency ratio other	12.05

Metric	Value
CQA speedup if no scalar integer	2.28
CQA speedup if FP arith vectorized	1.76
CQA speedup if fully vectorized	4.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..2.368
Source	generate_chunk.cpp:86-98,generate_chunk.cpp:105-123,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	57.00
CQA cycles if no scalar integer	25.00
CQA cycles if FP arith vectorized	32.33
CQA cycles if fully vectorized	12.13
Front-end cycles	53.50
DIV/SQRT cycles	25.75
P0 cycles	25.75
P1 cycles	25.50
P2 cycles	25.50
P3 cycles	12.50
P4 cycles	57.00
P5 cycles	57.00
P6 cycles	57.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	19.00
P12 cycles	19.00
P13 cycles	21.50 - 26.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	304.00
Nb uops	321.00
Nb loads	132.00
Nb stores	31.00
Nb stack references	17.00
FLOP/cycle	0.11
Nb FLOP add-sub	3.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.32
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	248.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.06
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	7.14
Vector-efficiency ratio all	12.37
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	10.42
Vector-efficiency ratio other	12.05

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2.368
Source file and lines	generate_chunk.cpp:86-123
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:86-98,105-123
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=30
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 30 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 57.00 to 25.00 cycles (2.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 57.00 to 12.13 cycles (4.70x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 57.00 to 53.50 cycles (1.07x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences
LEA: 7 occurrences
VUCOMISD: 8 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
2: multiply
1: square root

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 248 bytes (31 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	304
nb uops	321
loop length	1360
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	53.50 cycles
front end	53.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	25.75	25.75	25.50	25.50	12.50	57.00	57.00	57.00	1.50	1.50	5.50	5.50	19.00	19.00
cycles	25.75	25.75	25.50	25.50	12.50	57.00	57.00	57.00	1.50	1.50	5.50	5.50	19.00	19.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

21.50-26.50

Cycles summary

Front-end	53.50
Dispatch	57.00
DIV/SQRT	21.50-26.50
Overall L1	57.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	9%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	10%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 57.00 cycles. At this rate:

18% of peak load performance is reached (17.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 246cde

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x1(%R12),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP -0x40(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JGE 246c71 <.omp_outlined..2.368+0xa1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 246d00 <.omp_outlined..2.368+0x130>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R10	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 246d0b <.omp_outlined..2.368+0x13b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R15D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %ECX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RBX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RSI,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x8(%R9),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RSI,%RAX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP $0x3,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 246f20 <.omp_outlined..2.368+0x350>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 2470a0 <.omp_outlined..2.368+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SAL $0x20,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x100000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
LEA (%RDX,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x258(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAR $0x1d,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD (%RSI,%RDI,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x28(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%R8),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R8,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD (%RSI,%RDI,1),%XMM1	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JBE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x20,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x100000000,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
LEA (%RSI,%RDI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x278(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAR $0x1d,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD (%RDI,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x30(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%R9),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD (%RDI,%R8,1),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JBE 246ccc <.omp_outlined..2.368+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SAR $0x20,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SAR $0x20,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x40(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xa8(%R11),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xb8(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x50(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xd8(%R11),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x30(%RBP),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13D,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R14,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R13,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R15,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R11,%R13,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RSI,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL -0x68(%RBP),%RSI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%RSI,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R10,1),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%R8,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R11,%RSI,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 246ccc <.omp_outlined..2.368+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOVSXD %EDX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x258(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RSI,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JNE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JP 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R13D,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x278(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RDX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JNE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JP 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x40(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x48(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RSI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xa8(%R11),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xb8(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x50(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xd8(%R11),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13D,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RBX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R14,%R11,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R11,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RSI,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R14,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R15,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RSI,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RDX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RBX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R11,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%RDX,%R11,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RSI,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R10,1),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%R8,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R11,%RDX,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOVSXD %EDX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x218(%R11),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x238(%R11),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RAX,%R15,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM1,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSXD %R13D,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R14,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUCOMISD %XMM3,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 2470e0 <.omp_outlined..2.368+0x510>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
JMP 2470ed <.omp_outlined..2.368+0x51d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
CALL 2613a0 <@plt_start@+0x530>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RAX),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ECX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x58(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 246cc0 <.omp_outlined..2.368+0xf0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x40(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RSI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RSI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xa8(%R11),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xb8(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x50(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x20(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xd8(%R10),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13D,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R9,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R10,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R13,%R10,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R10,%R15,1),%RBX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVSD %XMM0,(%RDI,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R13,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R14,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R11,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R9,%R10,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R14,%R10,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R10,%R9,1),%RSI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVSD %XMM0,(%RDI,%RSI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R14,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 246cc0 <.omp_outlined..2.368+0xf0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..2.368
Source file and lines	generate_chunk.cpp:86-123
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:86-98,105-123
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=30
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 57.00 to 53.50 cycles (1.07x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences
LEA: 7 occurrences
VUCOMISD: 8 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
2: multiply
1: square root

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 248 bytes (31 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	304
nb uops	321
loop length	1360
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	53.50 cycles
front end	53.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	25.75	25.75	25.50	25.50	12.50	57.00	57.00	57.00	1.50	1.50	5.50	5.50	19.00	19.00
cycles	25.75	25.75	25.50	25.50	12.50	57.00	57.00	57.00	1.50	1.50	5.50	5.50	19.00	19.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

21.50-26.50

Cycles summary

Front-end	53.50
Dispatch	57.00
DIV/SQRT	21.50-26.50
Overall L1	57.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	9%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	10%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 57.00 cycles. At this rate:

18% of peak load performance is reached (17.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 246cde

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x1(%R12),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP -0x40(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JGE 246c71 <.omp_outlined..2.368+0xa1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
OR %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 246d00 <.omp_outlined..2.368+0x130>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R10	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 246d0b <.omp_outlined..2.368+0x13b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R15D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %ECX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RBX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RSI,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x8(%R9),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RSI,%RAX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP $0x3,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 246f20 <.omp_outlined..2.368+0x350>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 2470a0 <.omp_outlined..2.368+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SAL $0x20,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x100000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
LEA (%RDX,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x258(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAR $0x1d,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD (%RSI,%RDI,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x28(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%R8),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R8,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD (%RSI,%RDI,1),%XMM1	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JBE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x20,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x100000000,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
LEA (%RSI,%RDI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x278(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAR $0x1d,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD (%RDI,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x30(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%R9),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD (%RDI,%R8,1),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JBE 246ccc <.omp_outlined..2.368+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SAR $0x20,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SAR $0x20,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x40(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RSI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xa8(%R11),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xb8(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x50(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xd8(%R11),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV -0x30(%RBP),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13D,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R14,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R13,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R15,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R11,%R13,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RSI,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL -0x68(%RBP),%RSI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%RSI,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R10,1),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%R8,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R11,%RSI,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 246ccc <.omp_outlined..2.368+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOVSXD %EDX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x258(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RSI,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JNE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JP 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R13D,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x278(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RDX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JNE 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JP 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x40(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x48(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RSI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xa8(%R11),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xb8(%R11),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x50(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xd8(%R11),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13D,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R10,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RBX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R14,%R11,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R11,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RSI,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R14,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVSD %XMM0,(%R8,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R15,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RSI,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RDX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RBX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R11,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%R8,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%RDX,%R11,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RSI,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R11,%R10,1),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%R8,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R9,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R11,%RDX,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 246cd0 <.omp_outlined..2.368+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOVSXD %EDX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x218(%R11),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x238(%R11),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RAX,%R15,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM1,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSXD %R13D,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%R14,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUCOMISD %XMM3,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 2470e0 <.omp_outlined..2.368+0x510>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
JMP 2470ed <.omp_outlined..2.368+0x51d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
CALL 2613a0 <@plt_start@+0x530>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RAX),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ECX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x58(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 246cc0 <.omp_outlined..2.368+0xf0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x40(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RSI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RDX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R15,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RSI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xa8(%R11),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xb8(%R11),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x50(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RDX),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%R11),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x20(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xd8(%R10),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R13D,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R12D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R9,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R11,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R10,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R13,%R10,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R10,%R15,1),%RBX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVSD %XMM0,(%RDI,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R13,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R14,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R11,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R9,%R10,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDI,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R14,%R10,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%R10,%R9,1),%RSI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVSD %XMM0,(%RDI,%RSI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R10,%R14,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 246cc0 <.omp_outlined..2.368+0xf0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	0.94	0	1.06	-0	1.06	-0	1.06	-0	1	0	0.35	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.45	0.02
2x2	4	1	2	2	0.28	0.02
2x4	8	0.94	3.78	4	0.2	0.02
2x8	16	1.06	8.5	8	0.11	0.02
2x16	32	1.06	17	16	0.06	0.02
2x32	64	1.06	34	32	0.03	0.01
2x64	128	1	1	64	0.01	0.01
2x96	192	0.35	34	96	0.01	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency