OV - - Loop 641

	Loop Id: 641	Module: exec	Source: viscosity.cpp:37-64 [...]	Coverage: 3.59%

0x260b10 VMOVSD	%XMM7,-0x48(%RBP)    [25]

0x260b15 VMOVAPD	%XMM3,-0x90(%RBP)    [25]

0x260b1d VMOVAPD	%XMM5,-0x80(%RBP)    [25]

0x260b22 CALL	2613a0 <@plt_start@+0x530>

0x260b27 VMOVAPD	-0x80(%RBP),%XMM5    [25]

0x260b2c VMOVAPD	-0x90(%RBP),%XMM3    [25]

0x260b34 VMOVSD	-0x48(%RBP),%XMM7    [25]

0x260b39 VMOVSD	-0x5de51(%RIP),%XMM15    [17]

0x260b41 VMOVSD	-0x5de81(%RIP),%XMM14    [17]

0x260b49 VMOVAPD	-0x5ddf1(%RIP),%XMM13    [17]

0x260b51 MOV	0x20(%RBP),%RAX    [25]

0x260b55 MOV	0x8(%RAX),%RCX    [7]

0x260b59 VMULSD	(%RCX,%RBX,8),%XMM0,%XMM1    [2]

0x260b5e VDIVSD	%XMM3,%XMM1,%XMM1

0x260b62 VMOVAPD	-0x5de3a(%RIP),%XMM2    [17]

0x260b6a VANDPD	%XMM2,%XMM1,%XMM1

0x260b6e MOV	0x28(%RBP),%RAX    [25]

0x260b72 MOV	0x8(%RAX),%RSI    [13]

0x260b76 VMULSD	(%RSI,%R15,8),%XMM0,%XMM0    [22]

0x260b7c VDIVSD	%XMM5,%XMM0,%XMM0

0x260b80 VANDPD	%XMM2,%XMM0,%XMM0

0x260b84 VMINSD	%XMM1,%XMM0,%XMM2

0x260b88 VCMPSD	$0x3,%XMM1,%XMM1,%XMM1

0x260b8d VBLENDVPD	%XMM1,%XMM0,%XMM2,%XMM0

0x260b93 VMULSD	%XMM0,%XMM0,%XMM0

0x260b97 MOV	0x40(%RBP),%RDX    [25]

0x260b9b MOV	0x10(%RDX),%RAX    [27]

0x260b9f MOV	(%RDX),%RDX    [27]

0x260ba2 IMUL	%R15,%RDX

0x260ba6 ADD	%RBX,%RDX

0x260ba9 VMOVSD	(%RAX,%RDX,8),%XMM1    [15]

0x260bae VADDSD	%XMM1,%XMM1,%XMM1

0x260bb2 VMULSD	%XMM0,%XMM1,%XMM0

0x260bb6 VMULSD	%XMM0,%XMM7,%XMM0

0x260bba VMULSD	%XMM0,%XMM7,%XMM0

0x260bbe MOV	0x38(%RBP),%RDX    [25]

0x260bc2 MOV	0x10(%RDX),%RAX    [9]

0x260bc6 IMUL	(%RDX),%R15    [9]

0x260bca ADD	%RBX,%R15

0x260bcd VMOVSD	%XMM0,(%RAX,%R15,8)    [8]

0x260bd3 LEA	0x1(%R14),%RAX

0x260bd7 CMP	-0x30(%RBP),%R14    [25]

0x260bdb MOV	%RAX,%R14

0x260bde MOV	%R13,%R15

0x260be1 MOV	-0x50(%RBP),%R13    [25]

0x260be5 JGE	260abf

0x260beb MOV	%R14,%RAX

0x260bee SHR	$0x20,%RAX

0x260bf2 JE	260c00

0x260bf4 MOV	%R14,%RAX

0x260bf7 CQTO

0x260bf9 IDIV	%R13

0x260bfc JMP	260c08

0x260c00 MOV	%R14D,%EAX

0x260c03 XOR	%EDX,%EDX

0x260c05 DIV	%R13D

0x260c08 MOV	-0x60(%RBP),%R12    [25]

0x260c0c LEA	(%R12,%RAX,1),%EDI

0x260c10 MOV	%R15,%R13

0x260c13 LEA	(%R15,%RDX,1),%R11D

0x260c17 MOVSXD	%EDI,%R15

0x260c1a MOV	0x10(%RBP),%RDI    [25]

0x260c1e MOV	(%RDI),%R8    [11]

0x260c21 MOV	0x10(%RDI),%R9    [11]

0x260c25 MOV	%R8,%R10

0x260c28 IMUL	%R15,%R10

0x260c2c MOVSXD	%R11D,%RBX

0x260c2f LEA	(%R10,%RBX,1),%R11

0x260c33 INC	%R11

0x260c36 LEA	(%R12,%RAX,1),%EDI

0x260c3a INC	%EDI

0x260c3c MOVSXD	%EDI,%RDI

0x260c3f IMUL	%RDI,%R8

0x260c43 VMOVSD	(%R9,%R11,8),%XMM0    [24]

0x260c49 LEA	(%R8,%RBX,1),%R11

0x260c4d INC	%R11

0x260c50 ADD	%RBX,%R10

0x260c53 ADD	%RBX,%R8

0x260c56 VMOVSD	(%R9,%R11,8),%XMM1    [23]

0x260c5c MOV	0x18(%RBP),%R12    [25]

0x260c60 MOV	(%R12),%R11    [21]

0x260c64 VMOVSD	(%R9,%R10,8),%XMM4    [4]

0x260c6a MOV	0x10(%R12),%R10    [21]

0x260c6f VMOVSD	(%R9,%R8,8),%XMM5    [26]

0x260c75 MOV	%R11,%R8

0x260c78 IMUL	%RDI,%R8

0x260c7c LEA	(%R8,%RBX,1),%R9

0x260c80 INC	%R9

0x260c83 ADD	%RBX,%R8

0x260c86 VMOVSD	(%R10,%R8,8),%XMM6    [10]

0x260c8c IMUL	%R15,%R11

0x260c90 VMOVSD	(%R10,%R9,8),%XMM7    [20]

0x260c96 LEA	(%R11,%RBX,1),%R8

0x260c9a INC	%R8

0x260c9d ADD	%RBX,%R11

0x260ca0 VMOVSD	(%R10,%R11,8),%XMM8    [5]

0x260ca6 VMOVSD	(%R10,%R8,8),%XMM9    [18]

0x260cac MOV	0x30(%RBP),%R9    [25]

0x260cb0 MOV	(%R9),%R8    [3]

0x260cb3 MOV	0x10(%R9),%R9    [3]

0x260cb7 IMUL	%R8,%RDI

0x260cbb ADD	-0x68(%RBP),%EAX    [25]

0x260cbe CLTQ

0x260cc0 IMUL	%R8,%RAX

0x260cc4 IMUL	%R15,%R8

0x260cc8 ADD	-0x58(%RBP),%EDX    [25]

0x260ccb MOVSXD	%EDX,%RDX

0x260cce ADD	%R8,%RDX

0x260cd1 ADD	%RBX,%R8

0x260cd4 INC	%R8

0x260cd7 VMOVSD	(%R9,%R8,8),%XMM2    [1]

0x260cdd ADD	%RBX,%RDI

0x260ce0 VMOVHPD	(%R9,%RDI,8),%XMM2,%XMM10    [12]

0x260ce6 VMOVSD	(%R9,%RDX,8),%XMM2    [19]

0x260cec ADD	%RBX,%RAX

0x260cef VMOVHPD	(%R9,%RAX,8),%XMM2,%XMM11    [6]

0x260cf5 VADDSD	%XMM1,%XMM0,%XMM2

0x260cf9 VADDSD	%XMM5,%XMM4,%XMM3

0x260cfd VSUBSD	%XMM3,%XMM2,%XMM3

0x260d01 VADDSD	%XMM7,%XMM6,%XMM2

0x260d05 VADDSD	%XMM9,%XMM8,%XMM12

0x260d0a VSUBSD	%XMM12,%XMM2,%XMM2

0x260d0f VUNPCKLPD	%XMM7,%XMM1,%XMM1

0x260d13 VUNPCKLPD	%XMM9,%XMM5,%XMM5

0x260d18 VADDPD	%XMM5,%XMM1,%XMM1

0x260d1c VUNPCKLPD	%XMM8,%XMM4,%XMM4

0x260d21 VSUBPD	%XMM4,%XMM1,%XMM1

0x260d25 VUNPCKLPD	%XMM6,%XMM0,%XMM0

0x260d29 VSUBPD	%XMM0,%XMM1,%XMM0

0x260d2d VMULPD	%XMM0,%XMM13,%XMM7

0x260d31 VMOVSD	(%RCX,%RBX,8),%XMM6    [14]

0x260d36 VMOVSD	(%RSI,%R15,8),%XMM5    [16]

0x260d3c VMULSD	%XMM5,%XMM2,%XMM0

0x260d40 VMULSD	%XMM3,%XMM6,%XMM1

0x260d44 VADDSD	%XMM0,%XMM1,%XMM12

0x260d48 VSUBPD	%XMM11,%XMM10,%XMM0

0x260d4d VUNPCKLPD	%XMM5,%XMM6,%XMM1

0x260d51 VMOVSD	0x8(%RCX,%RBX,8),%XMM4    [14]

0x260d57 VMOVHPD	0x10(%RSI,%R15,8),%XMM4,%XMM4    [16]

0x260d5e VADDPD	%XMM4,%XMM1,%XMM1

0x260d62 VDIVPD	%XMM1,%XMM0,%XMM1

0x260d66 VMULPD	%XMM1,%XMM1,%XMM8

0x260d6a VPERMILPD	$0x1,%XMM8,%XMM9

0x260d70 VADDSD	%XMM9,%XMM8,%XMM0

0x260d75 VMAXSD	%XMM15,%XMM0,%XMM4

0x260d7a VXORPD	%XMM0,%XMM0,%XMM0

0x260d7e VUCOMISD	%XMM0,%XMM12

0x260d82 JAE	260bbe

0x260d88 VUNPCKLPD	%XMM6,%XMM5,%XMM10

0x260d8c VDIVPD	%XMM10,%XMM7,%XMM7

0x260d91 VMULSD	%XMM3,%XMM14,%XMM3

0x260d95 VDIVSD	%XMM6,%XMM3,%XMM3

0x260d99 VMULSD	%XMM2,%XMM14,%XMM2

0x260d9d VDIVSD	%XMM5,%XMM2,%XMM2

0x260da1 VMULSD	%XMM2,%XMM9,%XMM2

0x260da5 VMULSD	%XMM3,%XMM8,%XMM3

0x260da9 VADDSD	%XMM2,%XMM3,%XMM3

0x260dad VPERMILPD	$0x1,%XMM7,%XMM2

0x260db3 VADDSD	%XMM2,%XMM7,%XMM2

0x260db7 VMULSD	%XMM1,%XMM2,%XMM5

0x260dbb VPERMILPD	$0x1,%XMM1,%XMM2

0x260dc1 VMULSD	%XMM2,%XMM5,%XMM5

0x260dc5 VADDSD	%XMM3,%XMM5,%XMM3

0x260dc9 VDIVSD	%XMM4,%XMM3,%XMM7

0x260dcd VUCOMISD	-0x5e0d5(%RIP),%XMM7    [17]

0x260dd5 JA	260bbe

0x260ddb VMOVAPD	-0x5e0b3(%RIP),%XMM5    [17]

0x260de3 VANDPD	%XMM5,%XMM1,%XMM0

0x260de7 VMAXSD	%XMM15,%XMM0,%XMM0

0x260dec VMOVAPD	-0x5e064(%RIP),%XMM6    [17]

0x260df4 VXORPD	%XMM6,%XMM0,%XMM3

0x260df8 VXORPD	%XMM4,%XMM4,%XMM4

0x260dfc VCMPSD	$0x1,%XMM4,%XMM1,%XMM1

0x260e01 VBLENDVPD	%XMM1,%XMM3,%XMM0,%XMM3

0x260e07 VANDPD	%XMM5,%XMM2,%XMM0

0x260e0b VMAXSD	%XMM15,%XMM0,%XMM0

0x260e10 VXORPD	%XMM6,%XMM0,%XMM1

0x260e14 VCMPSD	$0x1,%XMM4,%XMM3,%XMM2

0x260e19 VBLENDVPD	%XMM2,%XMM1,%XMM0,%XMM5

0x260e1f VMULSD	%XMM5,%XMM5,%XMM0

0x260e23 VMULSD	%XMM3,%XMM3,%XMM1

0x260e27 VADDSD	%XMM0,%XMM1,%XMM0

0x260e2b VUCOMISD	%XMM4,%XMM0

0x260e2f JB	260b10

0x260e35 VSQRTSD	%XMM0,%XMM0,%XMM0

0x260e39 JMP	260b51

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 37 - 64

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	1.30 - 1.41
CQA speedup if FP arith vectorized	1.96
CQA speedup if fully vectorized	3.56 - 3.59
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78 - 1.94
Bottlenecks	P8, P9,
Function	.omp_outlined..576
Source	viscosity.cpp:37-64,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	56.50 - 61.50
CQA cycles if no scalar integer	43.50
CQA cycles if FP arith vectorized	26.38 - 31.38
CQA cycles if fully vectorized	15.88 - 17.13
Front-end cycles	31.67
DIV/SQRT cycles	11.75
P0 cycles	11.75
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	6.00
P4 cycles	19.33
P5 cycles	19.33
P6 cycles	19.33
P7 cycles	18.75
P8 cycles	18.67
P9 cycles	18.83
P10 cycles	18.75
P11 cycles	3.50
P12 cycles	3.50
P13 cycles	56.50 - 61.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	186.00
Nb uops	190.00
Nb loads	53.00
Nb stores	4.00
Nb stack references	15.00
FLOP/cycle	0.94 - 0.86
Nb FLOP add-sub	23.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.33 - 9.06
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	27.93
Vectorization ratio load	19.35
Vectorization ratio store	50.00
Vectorization ratio mul	11.11
Vectorization ratio add_sub	27.78
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	20.00
Vectorization ratio other	41.18
Vector-efficiency ratio all	15.93
Vector-efficiency ratio load	14.92
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	13.89
Vector-efficiency ratio add_sub	15.97
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	14.38
Vector-efficiency ratio other	17.65

Metric	Value
CQA speedup if no scalar integer	1.30 - 1.41
CQA speedup if FP arith vectorized	1.96
CQA speedup if fully vectorized	3.56 - 3.59
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78 - 1.94
Bottlenecks	P8, P9,
Function	.omp_outlined..576
Source	viscosity.cpp:37-64,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	56.50 - 61.50
CQA cycles if no scalar integer	43.50
CQA cycles if FP arith vectorized	26.38 - 31.38
CQA cycles if fully vectorized	15.88 - 17.13
Front-end cycles	31.67
DIV/SQRT cycles	11.75
P0 cycles	11.75
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	6.00
P4 cycles	19.33
P5 cycles	19.33
P6 cycles	19.33
P7 cycles	18.75
P8 cycles	18.67
P9 cycles	18.83
P10 cycles	18.75
P11 cycles	3.50
P12 cycles	3.50
P13 cycles	56.50 - 61.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	186.00
Nb uops	190.00
Nb loads	53.00
Nb stores	4.00
Nb stack references	15.00
FLOP/cycle	0.94 - 0.86
Nb FLOP add-sub	23.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.33 - 9.06
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	27.93
Vectorization ratio load	19.35
Vectorization ratio store	50.00
Vectorization ratio mul	11.11
Vectorization ratio add_sub	27.78
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	20.00
Vectorization ratio other	41.18
Vector-efficiency ratio all	15.93
Vector-efficiency ratio load	14.92
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	13.89
Vector-efficiency ratio add_sub	15.97
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	14.38
Vector-efficiency ratio other	17.65

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..576
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:37-64
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 61.50 to 43.50 cycles (1.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 61.50 to 17.12 cycles (3.59x speedup).

Details

27% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

19% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
27% of SSE/AVX addition or subtraction instructions are used in vector version.
11% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 61.50 to 31.67 cycles (1.94x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 61.50 to 31.33 cycles (1.96x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

45 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 53 FP arithmetical operations:

23: addition or subtraction
20: multiply
9: divide
1: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	186
nb uops	190
loop length	812
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	15
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.67 cycles
front end	31.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.75	11.75	11.75	11.75	6.00	19.33	19.33	19.33	18.75	18.67	18.83	18.75	3.50	3.50
cycles	11.75	11.75	11.75	11.75	6.00	19.33	19.33	19.33	18.75	18.67	18.83	18.75	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

56.50-61.50

Cycles summary

Front-end	31.67
Dispatch	19.33
DIV/SQRT	56.50-61.50
Overall L1	56.50-61.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	29%
load	20%
store	50%
mul	11%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	46%

INT+FP

all	27%
load	19%
store	50%
mul	11%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	20%
other	41%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	15%
store	18%
mul	13%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	15%
other	18%

INT+FP

all	15%
load	14%
store	18%
mul	13%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	14%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 61.50 cycles. At this rate:

7% of peak load performance is reached (7.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 260beb

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD %XMM7,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPD %XMM3,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVAPD %XMM5,-0x80(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 2613a0 <@plt_start@+0x530>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
VMOVAPD -0x80(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVAPD -0x90(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD -0x48(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x5de51(%RIP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x5de81(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVAPD -0x5ddf1(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD (%RCX,%RBX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVAPD -0x5de3a(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VANDPD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD (%RSI,%R15,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM5,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VANDPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMINSD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VCMPSD $0x3,%XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VBLENDVPD %XMM1,%XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50
VMULSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R15,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RAX,%RDX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM0,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM0,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL (%RDX),%R15	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
ADD %RBX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RAX,%R15,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x1(%R14),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP -0x30(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JGE 260abf <.omp_outlined..576+0xaf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 260c00 <.omp_outlined..576+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R13	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
JMP 260c08 <.omp_outlined..576+0x1f8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R13D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV -0x60(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R12,%RAX,1),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R15,%RDX,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RDI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R15,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOVSXD %R11D,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%RBX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R12,%RAX,1),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%R9,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R8,%RBX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R9,%R11,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x18(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R12),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R9,%R10,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R12),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R9,%R8,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%RBX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R8,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %R15,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%R10,%R9,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R11,%RBX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R11,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R10,%R8,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x30(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R9),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x68(%RBP),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CLTQ
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R15,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x58(%RBP),%EDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R9,%R8,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R9,%RDI,8),%XMM2,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%R9,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R9,%RAX,8),%XMM2,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VADDSD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM5,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM3,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM7,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM9,%XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM12,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM7,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VUNPCKLPD %XMM9,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM5,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM8,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD %XMM4,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM6,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %XMM0,%XMM13,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD (%RCX,%RBX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RSI,%R15,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM5,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM0,%XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %XMM11,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM5,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVSD 0x8(%RCX,%RBX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD 0x10(%RSI,%R15,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VADDPD %XMM4,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVPD %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULPD %XMM1,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VPERMILPD $0x1,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM9,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMAXSD %XMM15,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VUCOMISD %XMM0,%XMM12	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JAE 260bbe <.omp_outlined..576+0x1ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VUNPCKLPD %XMM6,%XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VDIVPD %XMM10,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM3,%XMM14,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM6,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM2,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM5,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM2,%XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM2,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPERMILPD $0x1,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM2,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM1,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VPERMILPD $0x1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMULSD %XMM2,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM3,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVSD %XMM4,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VUCOMISD -0x5e0d5(%RIP),%XMM7	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JA 260bbe <.omp_outlined..576+0x1ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVAPD -0x5e0b3(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VANDPD %XMM5,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMAXSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VMOVAPD -0x5e064(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VXORPD %XMM6,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VCMPSD $0x1,%XMM4,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VBLENDVPD %XMM1,%XMM3,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50
VANDPD %XMM5,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMAXSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VXORPD %XMM6,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCMPSD $0x1,%XMM4,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VBLENDVPD %XMM2,%XMM1,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50
VMULSD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUCOMISD %XMM4,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 260b10 <.omp_outlined..576+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
JMP 260b51 <.omp_outlined..576+0x141>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..576
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:37-64
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

27% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

19% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
27% of SSE/AVX addition or subtraction instructions are used in vector version.
11% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 61.50 to 31.33 cycles (1.96x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences
IDIV: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
CQTO: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 53 FP arithmetical operations:

23: addition or subtraction
20: multiply
9: divide
1: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	186
nb uops	190
loop length	812
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	15
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.67 cycles
front end	31.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.75	11.75	11.75	11.75	6.00	19.33	19.33	19.33	18.75	18.67	18.83	18.75	3.50	3.50
cycles	11.75	11.75	11.75	11.75	6.00	19.33	19.33	19.33	18.75	18.67	18.83	18.75	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

56.50-61.50

Cycles summary

Front-end	31.67
Dispatch	19.33
DIV/SQRT	56.50-61.50
Overall L1	56.50-61.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	29%
load	20%
store	50%
mul	11%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	46%

INT+FP

all	27%
load	19%
store	50%
mul	11%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	20%
other	41%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	15%
store	18%
mul	13%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	15%
other	18%

INT+FP

all	15%
load	14%
store	18%
mul	13%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	14%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 61.50 cycles. At this rate:

7% of peak load performance is reached (7.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 260beb

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD %XMM7,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPD %XMM3,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVAPD %XMM5,-0x80(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 2613a0 <@plt_start@+0x530>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
VMOVAPD -0x80(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVAPD -0x90(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD -0x48(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x5de51(%RIP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x5de81(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVAPD -0x5ddf1(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD (%RCX,%RBX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVAPD -0x5de3a(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VANDPD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD (%RSI,%R15,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM5,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VANDPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMINSD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VCMPSD $0x3,%XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VBLENDVPD %XMM1,%XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50
VMULSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R15,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RAX,%RDX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM0,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM0,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL (%RDX),%R15	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
ADD %RBX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RAX,%R15,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x1(%R14),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP -0x30(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JGE 260abf <.omp_outlined..576+0xaf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JE 260c00 <.omp_outlined..576+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CQTO
IDIV %R13	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12
JMP 260c08 <.omp_outlined..576+0x1f8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
DIV %R13D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV -0x60(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R12,%RAX,1),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R15,%RDX,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RDI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %R15,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOVSXD %R11D,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%RBX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R12,%RAX,1),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%R9,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R8,%RBX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R9,%R11,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x18(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R12),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R9,%R10,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%R12),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%R9,%R8,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%RBX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R8,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %R15,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVSD (%R10,%R9,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R11,%RBX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R10,%R11,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R10,%R8,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x30(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R9),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x68(%RBP),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CLTQ
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R15,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD -0x58(%RBP),%EDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R9,%R8,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R9,%RDI,8),%XMM2,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%R9,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVHPD (%R9,%RAX,8),%XMM2,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VADDSD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM5,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM3,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM7,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM9,%XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM12,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM7,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VUNPCKLPD %XMM9,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM5,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM8,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD %XMM4,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM6,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %XMM0,%XMM13,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD (%RCX,%RBX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RSI,%R15,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM5,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM0,%XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %XMM11,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM5,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVSD 0x8(%RCX,%RBX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD 0x10(%RSI,%R15,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VADDPD %XMM4,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVPD %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULPD %XMM1,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VPERMILPD $0x1,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM9,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMAXSD %XMM15,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VUCOMISD %XMM0,%XMM12	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JAE 260bbe <.omp_outlined..576+0x1ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VUNPCKLPD %XMM6,%XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VDIVPD %XMM10,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM3,%XMM14,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM6,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM2,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM5,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM2,%XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM2,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPERMILPD $0x1,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM2,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM1,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VPERMILPD $0x1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMULSD %XMM2,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM3,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VDIVSD %XMM4,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VUCOMISD -0x5e0d5(%RIP),%XMM7	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JA 260bbe <.omp_outlined..576+0x1ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVAPD -0x5e0b3(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VANDPD %XMM5,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMAXSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VMOVAPD -0x5e064(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VXORPD %XMM6,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VCMPSD $0x1,%XMM4,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VBLENDVPD %XMM1,%XMM3,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50
VANDPD %XMM5,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMAXSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VXORPD %XMM6,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCMPSD $0x1,%XMM4,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VBLENDVPD %XMM2,%XMM1,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50
VMULSD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUCOMISD %XMM4,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 260b10 <.omp_outlined..576+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
JMP 260b51 <.omp_outlined..576+0x141>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/aocc_15/oneview_run_1708555871I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0.01	1	0	1	0.01	1	0.01	1	0	0.84	0.32	0.56	0.95

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	61.67	3.59
2x2	4	1	2	2	30.91	3.59
2x4	8	1	4	4	15.49	3.58
2x8	16	1	7.97	8	7.85	3.58
2x16	32	1	15.96	16	4.01	3.39
2x32	64	1	32.09	32	2.09	2.87
2x64	128	0.84	53.57	64	1.47	1.95
2x96	192	0.56	54.04	96	1.25	2.17

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency