OV - - Function _Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp

	Function: _Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage: 2.77%

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

0x437ef0 PUSH	%RBP

0x437ef1 MOV	%RSP,%RBP

0x437ef4 PUSH	%R15

0x437ef6 PUSH	%R14

0x437ef8 PUSH	%R13

0x437efa PUSH	%R12

0x437efc PUSH	%RBX

0x437efd MOV	%RDI,%RBX

0x437f00 AND	$-0x40,%RSP

0x437f04 ADD	$-0x80,%RSP

0x437f08 MOV	0x50(%RDI),%EAX

0x437f0b MOV	0x54(%RDI),%EDX

0x437f0e MOV	0x48(%RDI),%EDI

0x437f11 MOV	0x4c(%RBX),%ECX

0x437f14 ADD	$0x3,%EDX

0x437f17 INC	%EDI

0x437f19 LEA	0x1(%RAX),%R12D

0x437f1d MOV	%EDX,0x18(%RSP)

0x437f21 MOV	%EDI,0x14(%RSP)

0x437f25 CMP	%EDX,%R12D

0x437f28 JGE	4387b3

0x437f2e MOV	%EDX,%R13D

0x437f31 LEA	0x3(%RCX),%R14D

0x437f35 SUB	%R12D,%R13D

0x437f38 CMP	%R14D,%EDI

0x437f3b JGE	4387b3

0x437f41 MOV	%R14D,%ESI

0x437f44 SUB	%EDI,%ESI

0x437f46 MOV	%ESI,0x1c(%RSP)

0x437f4a CALL	404650 <omp_get_num_threads@plt>

0x437f4f MOV	%EAX,%R15D

0x437f52 CALL	404540 <omp_get_thread_num@plt>

0x437f57 XOR	%EDX,%EDX

0x437f59 MOV	%EAX,%R8D

0x437f5c MOV	0x1c(%RSP),%EAX

0x437f60 IMUL	%R13D,%EAX

0x437f64 DIV	%R15D

0x437f67 MOV	%EAX,%ECX

0x437f69 CMP	%EDX,%R8D

0x437f6c JB	4387db

0x437f72 IMUL	%ECX,%R8D

0x437f76 LEA	(%R8,%RDX,1),%R11D

0x437f7a LEA	(%RCX,%R11,1),%R9D

0x437f7e MOV	%R9D,0x10(%RSP)

0x437f83 CMP	%R9D,%R11D

0x437f86 JAE	4387b3

0x437f8c MOV	%R11D,%EAX

0x437f8f XOR	%EDX,%EDX

0x437f91 MOV	0x14(%RSP),%R10D

0x437f96 VMOVQ	0x8(%RBX),%XMM29

0x437f9d DIVL	0x1c(%RSP)

0x437fa1 VMOVQ	0x18(%RBX),%XMM28

0x437fa8 VMOVQ	0x28(%RBX),%XMM27

0x437faf VMOVSD	0x28807(%RIP),%XMM22

0x437fb9 VMOVQ	0x38(%RBX),%XMM26

0x437fc0 VMULSD	(%RBX),%XMM22,%XMM22

0x437fc6 VMOVQ	0x10(%RBX),%XMM25

0x437fcd VBROADCASTSD	%XMM22,%YMM23

0x437fd3 VMOVQ	0x20(%RBX),%XMM24

0x437fda VMOVQ	0x30(%RBX),%XMM16

0x437fe1 MOV	0x40(%RBX),%RBX

0x437fe5 VBROADCASTSD	%XMM22,%ZMM1

0x437feb VMOVQ	%RBX,%XMM17

0x437ff1 ADD	%EDX,%R10D

0x437ff4 MOV	%R14D,%EDX

0x437ff7 LEA	(%RAX,%R12,1),%R12D

0x437ffb SUB	%R10D,%EDX

0x437ffe MOVSXD	%R12D,%R14

0x438001 MOV	%R10D,0x4c(%RSP)

0x438006 MOV	%EDX,%R9D

0x438009 NOPL	(%RAX)

(229) 0x438010 CMP	%R9D,%ECX

(229) 0x438013 CMOVA	%R9D,%ECX

(229) 0x438017 LEA	(%R11,%RCX,1),%EDI

(229) 0x43801b MOV	%EDI,0x48(%RSP)

(229) 0x43801f CMP	%EDI,%R11D

(229) 0x438022 JAE	438786

(229) 0x438028 VMOVQ	%XMM28,%R15

(229) 0x43802e VMOVQ	%XMM27,%R12

(229) 0x438034 MOV	(%R15),%R8

(229) 0x438037 MOV	(%R12),%RDX

(229) 0x43803b MOV	0x10(%R15),%R10

(229) 0x43803f VMOVQ	%XMM25,%R15

(229) 0x438045 VMOVQ	%XMM29,%R13

(229) 0x43804b VMOVQ	%XMM26,%RBX

(229) 0x438051 VMOVQ	0x10(%R15),%XMM13

(229) 0x438057 MOV	(%R13),%RSI

(229) 0x43805b VMOVQ	0x10(%R13),%XMM15

(229) 0x438061 VMOVQ	0x10(%RBX),%XMM14

(229) 0x438066 MOV	(%RBX),%R13

(229) 0x438069 MOV	%R8,%RAX

(229) 0x43806c MOV	%RDX,%RDI

(229) 0x43806f IMUL	%R14,%RAX

(229) 0x438073 IMUL	%R14,%RDI

(229) 0x438077 IMUL	%R14,%RSI

(229) 0x43807b LEA	(%R8,%RAX,1),%R9

(229) 0x43807f MOV	(%R15),%R8

(229) 0x438082 IMUL	%R14,%R13

(229) 0x438086 VMOVQ	%XMM16,%R15

(229) 0x43808c ADD	%RDI,%RDX

(229) 0x43808f MOV	%R9,0x50(%RSP)

(229) 0x438094 MOV	0x10(%R12),%R9

(229) 0x438099 VMOVQ	%XMM24,%R12

(229) 0x43809f MOV	%RDX,0x58(%RSP)

(229) 0x4380a4 MOV	(%R12),%RDX

(229) 0x4380a8 MOV	0x10(%R12),%RBX

(229) 0x4380ad MOV	0x10(%R15),%R15

(229) 0x4380b1 MOV	%RSI,0x28(%RSP)

(229) 0x4380b6 MOV	%RAX,0x30(%RSP)

(229) 0x4380bb MOV	%RDI,0x38(%RSP)

(229) 0x4380c0 MOV	%R13,0x40(%RSP)

(229) 0x4380c5 IMUL	%R14,%R8

(229) 0x4380c9 IMUL	%R14,%RDX

(229) 0x4380cd MOV	%R8,0x60(%RSP)

(229) 0x4380d2 VMOVQ	%XMM16,%R8

(229) 0x4380d8 MOV	(%R8),%R12

(229) 0x4380db MOV	%RDX,0x70(%RSP)

(229) 0x4380e0 VMOVQ	%XMM17,%RDX

(229) 0x4380e6 MOV	(%RDX),%R8

(229) 0x4380e9 VMOVQ	0x10(%RDX),%XMM12

(229) 0x4380ee IMUL	%R14,%R12

(229) 0x4380f2 IMUL	%R14,%R8

(229) 0x4380f6 MOV	%R12,0x78(%RSP)

(229) 0x4380fb LEA	-0x1(%RCX),%R12D

(229) 0x4380ff MOV	%R8,0x68(%RSP)

(229) 0x438104 CMP	$0x6,%R12D

(229) 0x438108 JBE	4387d0

(229) 0x43810e MOVSXD	0x4c(%RSP),%RDX

(229) 0x438113 VMOVQ	%XMM15,%R8

(229) 0x438118 ADD	%RDX,%RSI

(229) 0x43811b LEA	(%RAX,%RDX,1),%RAX

(229) 0x43811f LEA	(%RDI,%RDX,1),%RDI

(229) 0x438123 LEA	(%R13,%RDX,1),%R13

(229) 0x438128 LEA	(%R8,%RSI,8),%RSI

(229) 0x43812c MOV	0x50(%RSP),%R8

(229) 0x438131 LEA	(%R10,%RAX,8),%R12

(229) 0x438135 MOV	0x58(%RSP),%RAX

(229) 0x43813a VMOVQ	%R12,%XMM18

(229) 0x438140 VMOVQ	%RSI,%XMM10

(229) 0x438145 LEA	(%R9,%RDI,8),%RSI

(229) 0x438149 VMOVQ	%XMM14,%RDI

(229) 0x43814e VMOVQ	%RSI,%XMM11

(229) 0x438153 LEA	(%RDI,%R13,8),%RSI

(229) 0x438157 VMOVQ	%XMM13,%RDI

(229) 0x43815c VMOVQ	%RSI,%XMM9

(229) 0x438161 ADD	%RDX,%R8

(229) 0x438164 LEA	(%R10,%R8,8),%R12

(229) 0x438168 LEA	(%RAX,%RDX,1),%R8

(229) 0x43816c MOV	0x60(%RSP),%RAX

(229) 0x438171 LEA	(%R9,%R8,8),%R8

(229) 0x438175 LEA	(%RAX,%RDX,1),%R13

(229) 0x438179 MOV	0x70(%RSP),%RAX

(229) 0x43817e LEA	(%RDI,%R13,8),%RSI

(229) 0x438182 VMOVQ	%RSI,%XMM3

(229) 0x438187 MOV	0x78(%RSP),%RSI

(229) 0x43818c LEA	(%RAX,%RDX,1),%RDI

(229) 0x438190 SAL	$0x3,%RDI

(229) 0x438194 LEA	(%RSI,%RDX,1),%RSI

(229) 0x438198 LEA	(%RBX,%RDI,1),%R13

(229) 0x43819c LEA	0x8(%RBX,%RDI,1),%RDI

(229) 0x4381a1 SAL	$0x3,%RSI

(229) 0x4381a5 LEA	(%R15,%RSI,1),%RAX

(229) 0x4381a9 VMOVQ	%RAX,%XMM4

(229) 0x4381ae LEA	0x8(%R15,%RSI,1),%RAX

(229) 0x4381b3 MOV	0x68(%RSP),%RSI

(229) 0x4381b8 ADD	%RSI,%RDX

(229) 0x4381bb VMOVQ	%XMM12,%RSI

(229) 0x4381c0 LEA	(%RSI,%RDX,8),%RDX

(229) 0x4381c4 MOV	%ECX,%ESI

(229) 0x4381c6 SHR	$0x3,%ESI

(229) 0x4381c9 VMOVQ	%RDX,%XMM2

(229) 0x4381ce MOV	%RSI,%RDX

(229) 0x4381d1 SAL	$0x6,%RDX

(229) 0x4381d5 MOV	%RDX,0x20(%RSP)

(229) 0x4381da XOR	%EDX,%EDX

(229) 0x4381dc AND	$0x1,%ESI

(229) 0x4381df JE	43827c

(229) 0x4381e5 VMOVQ	%XMM18,%RSI

(229) 0x4381eb VMOVQ	%XMM11,%RDX

(229) 0x4381f0 CMPQ	$0x40,0x20(%RSP)

(229) 0x4381f6 VMOVUPD	(%RSI),%ZMM5

(229) 0x4381fc VMOVUPD	(%RDX),%ZMM7

(229) 0x438202 VADDPD	(%R12),%ZMM5,%ZMM31

(229) 0x438209 VMOVQ	%XMM10,%RSI

(229) 0x43820e VADDPD	(%R8),%ZMM7,%ZMM0

(229) 0x438214 VMULPD	(%RSI),%ZMM1,%ZMM19

(229) 0x43821a VMOVQ	%XMM9,%RDX

(229) 0x43821f VMOVQ	%XMM4,%RSI

(229) 0x438224 VADDPD	%ZMM0,%ZMM31,%ZMM6

(229) 0x43822a VMULPD	%ZMM19,%ZMM6,%ZMM8

(229) 0x438230 VMOVUPD	%ZMM8,(%RDX)

(229) 0x438236 VMOVUPD	(%RSI),%ZMM5

(229) 0x43823c VMOVUPD	(%R13),%ZMM7

(229) 0x438243 VADDPD	(%RAX),%ZMM5,%ZMM20

(229) 0x438249 VADDPD	(%RDI),%ZMM7,%ZMM0

(229) 0x43824f VMOVQ	%XMM3,%RDX

(229) 0x438254 VMULPD	(%RDX),%ZMM1,%ZMM21

(229) 0x43825a VMOVQ	%XMM2,%RSI

(229) 0x43825f MOV	$0x40,%EDX

(229) 0x438264 VADDPD	%ZMM0,%ZMM20,%ZMM6

(229) 0x43826a VMULPD	%ZMM21,%ZMM6,%ZMM8

(229) 0x438270 VMOVUPD	%ZMM8,(%RSI)

(229) 0x438276 JE	4383cc

(229) 0x43827c MOV	%R11D,0xc(%RSP)

(229) 0x438281 MOV	%ECX,0x8(%RSP)

(229) 0x438285 MOV	%R14,(%RSP)

(229) 0x438289 VMOVQ	%R9,%XMM6

(229) 0x43828e VMOVQ	%XMM10,%RCX

(229) 0x438293 VMOVQ	%XMM18,%R11

(229) 0x438299 VMOVQ	%XMM11,%R14

  (230) 0x43829e VMOVUPD	(%R11,%RDX,1),%ZMM10

  (230) 0x4382a5 VMOVUPD	(%R14,%RDX,1),%ZMM11

  (230) 0x4382ac VADDPD	(%R12,%RDX,1),%ZMM10,%ZMM30

  (230) 0x4382b3 VMOVQ	%XMM9,%R9

  (230) 0x4382b8 VADDPD	(%R8,%RDX,1),%ZMM11,%ZMM5

  (230) 0x4382bf VMULPD	(%RCX,%RDX,1),%ZMM1,%ZMM18

  (230) 0x4382c6 VMOVQ	%XMM4,%RSI

  (230) 0x4382cb VADDPD	%ZMM5,%ZMM30,%ZMM7

  (230) 0x4382d1 VMULPD	%ZMM18,%ZMM7,%ZMM0

  (230) 0x4382d7 VMOVUPD	%ZMM0,(%R9,%RDX,1)

  (230) 0x4382de VMOVUPD	(%RSI,%RDX,1),%ZMM8

  (230) 0x4382e5 VMOVUPD	(%R13,%RDX,1),%ZMM10

  (230) 0x4382ed VADDPD	(%RAX,%RDX,1),%ZMM8,%ZMM31

  (230) 0x4382f4 VADDPD	(%RDI,%RDX,1),%ZMM10,%ZMM11

  (230) 0x4382fb VMOVQ	%XMM3,%R9

  (230) 0x438300 VMULPD	(%R9,%RDX,1),%ZMM1,%ZMM19

  (230) 0x438307 VMOVQ	%XMM2,%RSI

  (230) 0x43830c VMOVQ	%XMM9,%R9

  (230) 0x438311 VADDPD	%ZMM11,%ZMM31,%ZMM5

  (230) 0x438317 VMULPD	%ZMM19,%ZMM5,%ZMM7

  (230) 0x43831d VMOVUPD	%ZMM7,(%RSI,%RDX,1)

  (230) 0x438324 VMOVUPD	0x40(%R11,%RDX,1),%ZMM0

  (230) 0x43832c VMOVUPD	0x40(%R14,%RDX,1),%ZMM8

  (230) 0x438334 VADDPD	0x40(%R12,%RDX,1),%ZMM0,%ZMM20

  (230) 0x43833c VADDPD	0x40(%R8,%RDX,1),%ZMM8,%ZMM10

  (230) 0x438344 VMULPD	0x40(%RCX,%RDX,1),%ZMM1,%ZMM21

  (230) 0x43834c VMOVQ	%XMM4,%RSI

  (230) 0x438351 VADDPD	%ZMM10,%ZMM20,%ZMM11

  (230) 0x438357 VMULPD	%ZMM21,%ZMM11,%ZMM5

  (230) 0x43835d VMOVUPD	%ZMM5,0x40(%R9,%RDX,1)

  (230) 0x438365 VMOVUPD	0x40(%RSI,%RDX,1),%ZMM7

  (230) 0x43836d VMOVUPD	0x40(%R13,%RDX,1),%ZMM0

  (230) 0x438375 VADDPD	0x40(%RAX,%RDX,1),%ZMM7,%ZMM30

  (230) 0x43837d VADDPD	0x40(%RDI,%RDX,1),%ZMM0,%ZMM8

  (230) 0x438385 VMOVQ	%XMM3,%R9

  (230) 0x43838a VMULPD	0x40(%R9,%RDX,1),%ZMM1,%ZMM18

  (230) 0x438392 VMOVQ	%XMM2,%RSI

  (230) 0x438397 VADDPD	%ZMM8,%ZMM30,%ZMM10

  (230) 0x43839d VMULPD	%ZMM18,%ZMM10,%ZMM11

  (230) 0x4383a3 VMOVUPD	%ZMM11,0x40(%RSI,%RDX,1)

  (230) 0x4383ab SUB	$-0x80,%RDX

  (230) 0x4383af CMP	%RDX,0x20(%RSP)

  (230) 0x4383b4 JNE	43829e

(229) 0x4383ba MOV	0xc(%RSP),%R11D

(229) 0x4383bf MOV	0x8(%RSP),%ECX

(229) 0x4383c3 MOV	(%RSP),%R14

(229) 0x4383c7 VMOVQ	%XMM6,%R9

(229) 0x4383cc MOV	0x4c(%RSP),%R12D

(229) 0x4383d1 MOV	%ECX,%EDX

(229) 0x4383d3 AND	$-0x8,%EDX

(229) 0x4383d6 ADD	%EDX,%R11D

(229) 0x4383d9 LEA	(%RDX,%R12,1),%EDI

(229) 0x4383dd TEST	$0x7,%CL

(229) 0x4383e0 JE	438781

(229) 0x4383e6 SUB	%EDX,%ECX

(229) 0x4383e8 LEA	-0x1(%RCX),%R8D

(229) 0x4383ec CMP	$0x2,%R8D

(229) 0x4383f0 JBE	4384f4

(229) 0x4383f6 MOVSXD	0x4c(%RSP),%RAX

(229) 0x4383fb MOV	0x70(%RSP),%R13

(229) 0x438400 MOV	0x30(%RSP),%R12

(229) 0x438405 MOV	0x78(%RSP),%RSI

(229) 0x43840a LEA	(%R13,%RAX,1),%R8

(229) 0x43840f MOV	0x50(%RSP),%R13

(229) 0x438414 LEA	(%R12,%RAX,1),%R12

(229) 0x438418 ADD	%RDX,%R12

(229) 0x43841b ADD	%RAX,%RSI

(229) 0x43841e ADD	%RDX,%R8

(229) 0x438421 ADD	%RDX,%RSI

(229) 0x438424 SAL	$0x3,%RSI

(229) 0x438428 ADD	%RAX,%R13

(229) 0x43842b ADD	%RDX,%R13

(229) 0x43842e VMOVUPD	(%R10,%R13,8),%YMM9

(229) 0x438434 MOV	0x58(%RSP),%R13

(229) 0x438439 VADDPD	(%R10,%R12,8),%YMM9,%YMM3

(229) 0x43843f MOV	0x38(%RSP),%R12

(229) 0x438444 ADD	%RAX,%R13

(229) 0x438447 LEA	(%R12,%RAX,1),%R12

(229) 0x43844b ADD	%RDX,%R13

(229) 0x43844e ADD	%RDX,%R12

(229) 0x438451 VMOVUPD	(%R9,%R13,8),%YMM4

(229) 0x438457 VMOVQ	%XMM15,%R13

(229) 0x43845c VADDPD	(%R9,%R12,8),%YMM4,%YMM2

(229) 0x438462 MOV	0x28(%RSP),%R12

(229) 0x438467 ADD	%RAX,%R12

(229) 0x43846a ADD	%RDX,%R12

(229) 0x43846d VMULPD	(%R13,%R12,8),%YMM23,%YMM6

(229) 0x438475 MOV	0x40(%RSP),%R12

(229) 0x43847a VMOVQ	%XMM14,%R13

(229) 0x43847f VADDPD	%YMM2,%YMM3,%YMM5

(229) 0x438483 ADD	%RAX,%R12

(229) 0x438486 ADD	%RDX,%R12

(229) 0x438489 VMULPD	%YMM6,%YMM5,%YMM7

(229) 0x43848d VMOVUPD	%YMM7,(%R13,%R12,8)

(229) 0x438494 VMOVUPD	0x8(%RBX,%R8,8),%YMM0

(229) 0x43849b VMOVUPD	(%R15,%RSI,1),%YMM10

(229) 0x4384a1 VADDPD	0x8(%R15,%RSI,1),%YMM0,%YMM8

(229) 0x4384a8 MOV	0x60(%RSP),%RSI

(229) 0x4384ad VADDPD	(%RBX,%R8,8),%YMM10,%YMM11

(229) 0x4384b3 MOV	0x68(%RSP),%R12

(229) 0x4384b8 VMOVQ	%XMM13,%R8

(229) 0x4384bd ADD	%RAX,%RSI

(229) 0x4384c0 ADD	%R12,%RAX

(229) 0x4384c3 ADD	%RDX,%RSI

(229) 0x4384c6 ADD	%RDX,%RAX

(229) 0x4384c9 VMOVQ	%XMM12,%RDX

(229) 0x4384ce VMULPD	(%R8,%RSI,8),%YMM23,%YMM3

(229) 0x4384d5 VADDPD	%YMM11,%YMM8,%YMM9

(229) 0x4384da VMULPD	%YMM3,%YMM9,%YMM4

(229) 0x4384de VMOVUPD	%YMM4,(%RDX,%RAX,8)

(229) 0x4384e3 TEST	$0x3,%CL

(229) 0x4384e6 JE	438781

(229) 0x4384ec AND	$-0x4,%ECX

(229) 0x4384ef ADD	%ECX,%R11D

(229) 0x4384f2 ADD	%ECX,%EDI

(229) 0x4384f4 MOV	0x50(%RSP),%RCX

(229) 0x4384f9 MOV	0x30(%RSP),%RSI

(229) 0x4384fe MOVSXD	%EDI,%RDX

(229) 0x438501 MOV	0x38(%RSP),%R12

(229) 0x438506 MOV	0x40(%RSP),%RAX

(229) 0x43850b LEA	(%RCX,%RDX,1),%R13

(229) 0x43850f LEA	(%RSI,%RDX,1),%R8

(229) 0x438513 MOV	0x58(%RSP),%RCX

(229) 0x438518 MOV	0x28(%RSP),%RSI

(229) 0x43851d ADD	%RDX,%R12

(229) 0x438520 VMOVSD	(%R10,%R13,8),%XMM2

(229) 0x438526 VADDSD	(%R10,%R8,8),%XMM2,%XMM5

(229) 0x43852c VMOVQ	%XMM15,%R8

(229) 0x438531 VMOVSD	(%R9,%R12,8),%XMM6

(229) 0x438537 ADD	%RDX,%RAX

(229) 0x43853a LEA	(%RCX,%RDX,1),%R13

(229) 0x43853e LEA	(%RSI,%RDX,1),%R12

(229) 0x438542 VMOVQ	%XMM14,%RCX

(229) 0x438547 VADDSD	(%R9,%R13,8),%XMM6,%XMM7

(229) 0x43854d VMULSD	(%R8,%R12,8),%XMM22,%XMM8

(229) 0x438554 MOV	0x70(%RSP),%R13

(229) 0x438559 MOV	0x78(%RSP),%R12

(229) 0x43855e VADDSD	%XMM7,%XMM5,%XMM0

(229) 0x438562 VMULSD	%XMM8,%XMM0,%XMM10

(229) 0x438567 VMOVSD	%XMM10,(%RCX,%RAX,8)

(229) 0x43856c LEA	0x1(%RDI),%EAX

(229) 0x43856f CLTQ

(229) 0x438571 LEA	(%R12,%RAX,1),%R8

(229) 0x438575 LEA	(%RAX,%R13,1),%RSI

(229) 0x438579 ADD	%RDX,%R13

(229) 0x43857c ADD	%RDX,%R12

(229) 0x43857f VMOVSD	(%RBX,%R13,8),%XMM11

(229) 0x438585 LEA	(%R15,%R8,8),%RCX

(229) 0x438589 MOV	0x60(%RSP),%R13

(229) 0x43858e MOV	0x68(%RSP),%R8

(229) 0x438593 VADDSD	(%R15,%R12,8),%XMM11,%XMM9

(229) 0x438599 VMOVQ	%XMM13,%R12

(229) 0x43859e LEA	(%RBX,%RSI,8),%RSI

(229) 0x4385a2 VMOVSD	(%RCX),%XMM3

(229) 0x4385a6 VADDSD	(%RSI),%XMM3,%XMM4

(229) 0x4385aa VADDSD	%XMM4,%XMM9,%XMM2

(229) 0x4385ae ADD	%RDX,%R8

(229) 0x4385b1 ADD	%R13,%RDX

(229) 0x4385b4 LEA	0x1(%R11),%R13D

(229) 0x4385b8 VMULSD	(%R12,%RDX,8),%XMM22,%XMM5

(229) 0x4385bf VMOVQ	%XMM12,%RDX

(229) 0x4385c4 VMULSD	%XMM5,%XMM2,%XMM6

(229) 0x4385c8 VMOVSD	%XMM6,(%RDX,%R8,8)

(229) 0x4385ce MOV	0x48(%RSP),%R8D

(229) 0x4385d3 CMP	%R8D,%R13D

(229) 0x4385d6 JAE	438781

(229) 0x4385dc MOV	0x50(%RSP),%R12

(229) 0x4385e1 MOV	0x30(%RSP),%R8

(229) 0x4385e6 MOV	0x40(%RSP),%RDX

(229) 0x4385eb ADD	$0x2,%R11D

(229) 0x4385ef LEA	(%RAX,%R12,1),%R13

(229) 0x4385f3 MOV	0x58(%RSP),%R12

(229) 0x4385f8 ADD	%RAX,%R8

(229) 0x4385fb ADD	%RAX,%RDX

(229) 0x4385fe VMOVSD	(%R10,%R13,8),%XMM7

(229) 0x438604 VADDSD	(%R10,%R8,8),%XMM7,%XMM0

(229) 0x43860a MOV	0x38(%RSP),%R8

(229) 0x43860f LEA	(%RAX,%R12,1),%R13

(229) 0x438613 MOV	0x28(%RSP),%R12

(229) 0x438618 ADD	%RAX,%R8

(229) 0x43861b VMOVSD	(%R9,%R13,8),%XMM8

(229) 0x438621 VADDSD	(%R9,%R8,8),%XMM8,%XMM10

(229) 0x438627 VMOVQ	%XMM15,%R8

(229) 0x43862c VADDSD	%XMM10,%XMM0,%XMM11

(229) 0x438631 LEA	(%RAX,%R12,1),%R13

(229) 0x438635 VMOVQ	%XMM14,%R12

(229) 0x43863a VMULSD	(%R8,%R13,8),%XMM22,%XMM9

(229) 0x438641 MOV	0x70(%RSP),%R13

(229) 0x438646 VMULSD	%XMM9,%XMM11,%XMM3

(229) 0x43864b VMOVSD	%XMM3,(%R12,%RDX,8)

(229) 0x438651 LEA	0x2(%RDI),%EDX

(229) 0x438654 MOVSXD	%EDX,%RDX

(229) 0x438657 LEA	(%R13,%RDX,1),%R8

(229) 0x43865c MOV	0x78(%RSP),%R13

(229) 0x438661 LEA	(%RBX,%R8,8),%R12

(229) 0x438665 VMOVSD	(%R12),%XMM4

(229) 0x43866b VADDSD	(%RSI),%XMM4,%XMM2

(229) 0x43866f MOV	0x60(%RSP),%RSI

(229) 0x438674 ADD	%RDX,%R13

(229) 0x438677 LEA	(%R15,%R13,8),%R8

(229) 0x43867b MOV	0x68(%RSP),%R13

(229) 0x438680 VMOVSD	(%R8),%XMM5

(229) 0x438685 VADDSD	(%RCX),%XMM5,%XMM6

(229) 0x438689 VMOVQ	%XMM13,%RCX

(229) 0x43868e VADDSD	%XMM6,%XMM2,%XMM7

(229) 0x438692 ADD	%RAX,%R13

(229) 0x438695 ADD	%RSI,%RAX

(229) 0x438698 VMULSD	(%RCX,%RAX,8),%XMM22,%XMM0

(229) 0x43869f VMOVQ	%XMM12,%RAX

(229) 0x4386a4 VMULSD	%XMM0,%XMM7,%XMM8

(229) 0x4386a8 VMOVSD	%XMM8,(%RAX,%R13,8)

(229) 0x4386ae MOV	0x48(%RSP),%R13D

(229) 0x4386b3 CMP	%R13D,%R11D

(229) 0x4386b6 JAE	438781

(229) 0x4386bc MOV	0x30(%RSP),%RSI

(229) 0x4386c1 MOV	0x50(%RSP),%RCX

(229) 0x4386c6 MOV	0x58(%RSP),%RAX

(229) 0x4386cb ADD	$0x3,%EDI

(229) 0x4386ce MOV	0x40(%RSP),%R11

(229) 0x4386d3 MOVSXD	%EDI,%RDI

(229) 0x4386d6 VMOVQ	%XMM15,%R13

(229) 0x4386db ADD	%RDX,%RSI

(229) 0x4386de ADD	%RDX,%RCX

(229) 0x4386e1 ADD	%RDX,%RAX

(229) 0x4386e4 VMOVSD	(%R10,%RSI,8),%XMM10

(229) 0x4386ea VADDSD	(%R10,%RCX,8),%XMM10,%XMM11

(229) 0x4386f0 MOV	0x38(%RSP),%R10

(229) 0x4386f5 MOV	0x70(%RSP),%RCX

(229) 0x4386fa ADD	%RDX,%R11

(229) 0x4386fd VMOVQ	%XMM14,%RSI

(229) 0x438702 ADD	%RDX,%R10

(229) 0x438705 ADD	%RDI,%RCX

(229) 0x438708 VMOVSD	(%R9,%R10,8),%XMM9

(229) 0x43870e VADDSD	(%R9,%RAX,8),%XMM9,%XMM3

(229) 0x438714 MOV	0x28(%RSP),%R9

(229) 0x438719 VADDSD	%XMM3,%XMM11,%XMM4

(229) 0x43871d VMOVQ	%XMM12,%R10

(229) 0x438722 ADD	%RDX,%R9

(229) 0x438725 VMULSD	(%R13,%R9,8),%XMM22,%XMM15

(229) 0x43872d VMULSD	%XMM15,%XMM4,%XMM2

(229) 0x438732 VMOVSD	%XMM2,(%RSI,%R11,8)

(229) 0x438738 VMOVSD	(%RBX,%RCX,8),%XMM14

(229) 0x43873d MOV	0x78(%RSP),%RBX

(229) 0x438742 MOV	0x68(%RSP),%R11

(229) 0x438747 VADDSD	(%R12),%XMM14,%XMM5

(229) 0x43874d ADD	%RDI,%RBX

(229) 0x438750 ADD	%RDX,%R11

(229) 0x438753 VMOVSD	(%R15,%RBX,8),%XMM6

(229) 0x438759 MOV	0x60(%RSP),%R15

(229) 0x43875e VADDSD	(%R8),%XMM6,%XMM7

(229) 0x438763 VMOVQ	%XMM13,%R8

(229) 0x438768 VADDSD	%XMM7,%XMM5,%XMM0

(229) 0x43876c ADD	%RDX,%R15

(229) 0x43876f VMULSD	(%R8,%R15,8),%XMM22,%XMM13

(229) 0x438776 VMULSD	%XMM13,%XMM0,%XMM8

(229) 0x43877b VMOVSD	%XMM8,(%R10,%R11,8)

(229) 0x438781 MOV	0x48(%RSP),%R11D

(229) 0x438786 INC	%R14

(229) 0x438789 LEA	(%R14),%EAX

(229) 0x43878c CMP	%EAX,0x18(%RSP)

(229) 0x438790 JLE	4387b0

(229) 0x438792 MOV	0x10(%RSP),%ECX

(229) 0x438796 MOV	0x14(%RSP),%R13D

(229) 0x43879b MOV	0x1c(%RSP),%R9D

(229) 0x4387a0 SUB	%R11D,%ECX

(229) 0x4387a3 MOV	%R13D,0x4c(%RSP)

(229) 0x4387a8 JMP	438010

0x4387ad NOPL	(%RAX)

0x4387b0 VZEROUPPER

0x4387b3 LEA	-0x28(%RBP),%RSP

0x4387b7 POP	%RBX

0x4387b8 POP	%R12

0x4387ba POP	%R13

0x4387bc POP	%R14

0x4387be POP	%R15

0x4387c0 POP	%RBP

0x4387c1 RET

0x4387c2 NOPW	%CS:(%RAX,%RAX,1)

0x4387cd NOPL	(%RAX)

(229) 0x4387d0 MOV	0x4c(%RSP),%EDI

(229) 0x4387d4 XOR	%EDX,%EDX

(229) 0x4387d6 JMP	4383e6

0x4387db INC	%ECX

0x4387dd XOR	%EDX,%EDX

0x4387df JMP	437f72

0x4387e4 NOPW	%CS:(%RAX,%RAX,1)

0x4387ef NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 3.50 cycles (4.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.50 to 1.50 cycles (9.67x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 108 bytes (13 double precision FP elements). The binary function is storing 20 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	88
nb uops	87
loop length	344
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.25	7.25	7.25	7.25	6.00	8.00	8.00	8.00	0.50	1.50	1.00	0.00	0.00	0.00
cycles	7.25	7.25	7.25	7.25	6.00	8.00	8.00	8.00	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.50
Dispatch	8.00
DIV/SQRT	12.00
Overall L1	14.50

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	8%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	11%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

7% of peak load performance is reached (7.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 437ef0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD $-0x80,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV 0x50(%RDI),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x54(%RDI),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x48(%RDI),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x4c(%RBX),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
ADD $0x3,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RAX),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %EDX,0x18(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
MOV %EDI,0x14(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
CMP %EDX,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JGE 4387b3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x3(%RCX),%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP %R14D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JGE 4387b3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %EDI,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
CALL 404650 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404540 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x1c(%RSP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
IMUL %R13D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	3	1
DIV %R15D	2	2	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JB 4387db <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8eb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%RDX,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%R11,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %R9D,0x10(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
CMP %R9D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JAE 4387b3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV 0x14(%RSP),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
VMOVQ 0x8(%RBX),%XMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
DIVL 0x1c(%RSP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	0	10-17	6
VMOVQ 0x18(%RBX),%XMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVQ 0x28(%RBX),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVSD 0x28807(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVQ 0x38(%RBX),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMULSD (%RBX),%XMM22,%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	3	0.50
VMOVQ 0x10(%RBX),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VBROADCASTSD %XMM22,%YMM23	1	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50
VMOVQ 0x20(%RBX),%XMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVQ 0x30(%RBX),%XMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
MOV 0x40(%RBX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
VBROADCASTSD %XMM22,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %RBX,%XMM17	1	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%RAX,%R12,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB %R10D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVSXD %R12D,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %R10D,0x4c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 437f72 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 3.50 cycles (4.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 108 bytes (13 double precision FP elements). The binary function is storing 20 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	88
nb uops	87
loop length	344
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.25	7.25	7.25	7.25	6.00	8.00	8.00	8.00	0.50	1.50	1.00	0.00	0.00	0.00
cycles	7.25	7.25	7.25	7.25	6.00	8.00	8.00	8.00	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.50
Dispatch	8.00
DIV/SQRT	12.00
Overall L1	14.50

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	8%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	11%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

7% of peak load performance is reached (7.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 437ef0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD $-0x80,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV 0x50(%RDI),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x54(%RDI),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x48(%RDI),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x4c(%RBX),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
ADD $0x3,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RAX),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %EDX,0x18(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
MOV %EDI,0x14(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
CMP %EDX,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JGE 4387b3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x3(%RCX),%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP %R14D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JGE 4387b3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %EDI,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
CALL 404650 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404540 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x1c(%RSP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
IMUL %R13D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	3	1
DIV %R15D	2	2	0	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JB 4387db <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8eb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%RDX,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%R11,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %R9D,0x10(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
CMP %R9D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JAE 4387b3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV 0x14(%RSP),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
VMOVQ 0x8(%RBX),%XMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
DIVL 0x1c(%RSP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	0	10-17	6
VMOVQ 0x18(%RBX),%XMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVQ 0x28(%RBX),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVSD 0x28807(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVQ 0x38(%RBX),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMULSD (%RBX),%XMM22,%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	3	0.50
VMOVQ 0x10(%RBX),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VBROADCASTSD %XMM22,%YMM23	1	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50
VMOVQ 0x20(%RBX),%XMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
VMOVQ 0x30(%RBX),%XMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50
MOV 0x40(%RBX),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
VBROADCASTSD %XMM22,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %RBX,%XMM17	1	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%RAX,%R12,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB %R10D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVSXD %R12D,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %R10D,0x4c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 437f72 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.01	0	1.01	0	0.86	0.42	0.5	1.67	0.26	2.87	0.13	3.4	0.08	3.84

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	17.22	2.77
2x2	4	1.01	2.02	2	8.6	2.74
2x4	8	1.01	4.02	4	4.34	2.74
2x8	16	0.86	6.86	8	2.55	2.92
2x16	32	0.5	7.94	16	2.56	3.32
2x32	64	0.26	8.36	32	2.24	3.89
2x64	128	0.13	8.32	64	2.29	3.91
2x96	192	0.08	8.12	96	2.17	4.2

Name	Coverage (%)	Time (s)
▼_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0–	2.77	17.22
▼Loop 229 - flux_calc.cpp:38-40 - exec–	0	0.02
○Loop 230 - flux_calc.cpp:39-40 - exec	2.77	17.19

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency