OV - - Loop 160

	Loop Id: 160	Module: exec	Source: advec_cell.cpp:47-48	Coverage: 0.88%

0x426ffb VMOVUPD	(%R8,%RCX,1),%ZMM5    [6]

0x427002 VMOVUPD	(%R12,%RCX,1),%ZMM4    [1]

0x427009 VADDPD	(%R10,%RCX,1),%ZMM5,%ZMM0    [4]

0x427010 VADDPD	(%R13,%RCX,1),%ZMM4,%ZMM20    [3]

0x427018 VSUBPD	%ZMM20,%ZMM0,%ZMM1

0x42701e VADDPD	(%RSI,%RCX,1),%ZMM1,%ZMM2    [2]

0x427025 VMOVUPD	%ZMM2,(%R14,%RCX,1)    [7]

0x42702c VMOVUPD	(%R12,%RCX,1),%ZMM11    [1]

0x427033 VSUBPD	(%R10,%RCX,1),%ZMM11,%ZMM21    [4]

0x42703a VADDPD	%ZMM2,%ZMM21,%ZMM22

0x427040 VMOVUPD	%ZMM22,(%RAX,%RCX,1)    [5]

0x427047 VMOVUPD	0x40(%R8,%RCX,1),%ZMM12    [6]

0x42704f VMOVUPD	0x40(%R12,%RCX,1),%ZMM14    [1]

0x427057 VADDPD	0x40(%R10,%RCX,1),%ZMM12,%ZMM13    [4]

0x42705f VADDPD	0x40(%R13,%RCX,1),%ZMM14,%ZMM23    [3]

0x427067 VSUBPD	%ZMM23,%ZMM13,%ZMM5

0x42706d VADDPD	0x40(%RSI,%RCX,1),%ZMM5,%ZMM0    [2]

0x427075 VMOVUPD	%ZMM0,0x40(%R14,%RCX,1)    [7]

0x42707d VMOVUPD	0x40(%R12,%RCX,1),%ZMM4    [1]

0x427085 VSUBPD	0x40(%R10,%RCX,1),%ZMM4,%ZMM24    [4]

0x42708d VADDPD	%ZMM0,%ZMM24,%ZMM25

0x427093 VMOVUPD	%ZMM25,0x40(%RAX,%RCX,1)    [5]

0x42709b VMOVUPD	0x80(%R8,%RCX,1),%ZMM1    [6]

0x4270a3 VMOVUPD	0x80(%R12,%RCX,1),%ZMM2    [1]

0x4270ab VADDPD	0x80(%R10,%RCX,1),%ZMM1,%ZMM11    [4]

0x4270b3 VADDPD	0x80(%R13,%RCX,1),%ZMM2,%ZMM26    [3]

0x4270bb VSUBPD	%ZMM26,%ZMM11,%ZMM12

0x4270c1 VADDPD	0x80(%RSI,%RCX,1),%ZMM12,%ZMM13    [2]

0x4270c9 VMOVUPD	%ZMM13,0x80(%R14,%RCX,1)    [7]

0x4270d1 VMOVUPD	0x80(%R12,%RCX,1),%ZMM14    [1]

0x4270d9 VSUBPD	0x80(%R10,%RCX,1),%ZMM14,%ZMM27    [4]

0x4270e1 VADDPD	%ZMM13,%ZMM27,%ZMM28

0x4270e7 VMOVUPD	%ZMM28,0x80(%RAX,%RCX,1)    [5]

0x4270ef VMOVUPD	0xc0(%R8,%RCX,1),%ZMM5    [6]

0x4270f7 VMOVUPD	0xc0(%R12,%RCX,1),%ZMM4    [1]

0x4270ff VADDPD	0xc0(%R10,%RCX,1),%ZMM5,%ZMM0    [4]

0x427107 VADDPD	0xc0(%R13,%RCX,1),%ZMM4,%ZMM29    [3]

0x42710f VSUBPD	%ZMM29,%ZMM0,%ZMM1

0x427115 VADDPD	0xc0(%RSI,%RCX,1),%ZMM1,%ZMM11    [2]

0x42711d VMOVUPD	%ZMM11,0xc0(%R14,%RCX,1)    [7]

0x427125 VMOVUPD	0xc0(%R12,%RCX,1),%ZMM2    [1]

0x42712d VSUBPD	0xc0(%R10,%RCX,1),%ZMM2,%ZMM30    [4]

0x427135 VADDPD	%ZMM11,%ZMM30,%ZMM31

0x42713b VMOVUPD	%ZMM31,0xc0(%RAX,%RCX,1)    [5]

0x427143 ADD	$0x100,%RCX

0x42714a CMP	%RCX,%R9

0x42714d JNE	426ffb

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 47 - 48

--------------------------------------------------------------------------------

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P10, P11,
Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0
Source	advec_cell.cpp:47-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	21.33
P5 cycles	21.33
P6 cycles	21.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	24.00
P10 cycles	24.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	54.00
Nb loads	28.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	1792.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	5.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P10, P11,
Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0
Source	advec_cell.cpp:47-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	21.33
P5 cycles	21.33
P6 cycles	21.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	24.00
P10 cycles	24.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	54.00
Nb loads	28.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	1792.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	5.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0
Source file and lines	advec_cell.cpp:47-48
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:47-48.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 21.33 cycles (1.12x speedup).

Workaround

Reduce the number of FP add instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 1792 bytes (224 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	47
nb uops	54
loop length	344
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	21
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	12.00	12.00	12.00	0.00	0.00	12.00	12.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	21.33	21.33	21.33	0.00	0.00	24.00	24.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	24.00
Data deps.	1.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

77% of peak load performance is reached (74.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (21.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426ffb

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%R12,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD (%R10,%RCX,1),%ZMM5,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD (%R13,%RCX,1),%ZMM4,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM20,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%RSI,%RCX,1),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM2,(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD (%R12,%RCX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD (%R10,%RCX,1),%ZMM11,%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM2,%ZMM21,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM22,(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%R8,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%RCX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD 0x40(%R10,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD 0x40(%R13,%RCX,1),%ZMM14,%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM23,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%RSI,%RCX,1),%ZMM5,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM0,0x40(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%R12,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD 0x40(%R10,%RCX,1),%ZMM4,%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM24,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM25,0x40(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%R8,%RCX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%R12,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD 0x80(%R10,%RCX,1),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD 0x80(%R13,%RCX,1),%ZMM2,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM26,%ZMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%RSI,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM13,0x80(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%R12,%RCX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD 0x80(%R10,%RCX,1),%ZMM14,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM13,%ZMM27,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM28,0x80(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc0(%R12,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD 0xc0(%R10,%RCX,1),%ZMM5,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R13,%RCX,1),%ZMM4,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM29,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%RSI,%RCX,1),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM11,0xc0(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R12,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD 0xc0(%R10,%RCX,1),%ZMM2,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM11,%ZMM30,%ZMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM31,0xc0(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x100,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 426ffb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x30b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0
Source file and lines	advec_cell.cpp:47-48
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP add instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 1792 bytes (224 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	47
nb uops	54
loop length	344
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	21
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	12.00	12.00	12.00	0.00	0.00	12.00	12.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	21.33	21.33	21.33	0.00	0.00	24.00	24.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	24.00
Data deps.	1.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

77% of peak load performance is reached (74.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (21.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 426ffb

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%R12,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD (%R10,%RCX,1),%ZMM5,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD (%R13,%RCX,1),%ZMM4,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM20,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%RSI,%RCX,1),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM2,(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD (%R12,%RCX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD (%R10,%RCX,1),%ZMM11,%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM2,%ZMM21,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM22,(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%R8,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%RCX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD 0x40(%R10,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD 0x40(%R13,%RCX,1),%ZMM14,%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM23,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%RSI,%RCX,1),%ZMM5,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM0,0x40(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%R12,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD 0x40(%R10,%RCX,1),%ZMM4,%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM24,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM25,0x40(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%R8,%RCX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%R12,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD 0x80(%R10,%RCX,1),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD 0x80(%R13,%RCX,1),%ZMM2,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM26,%ZMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%RSI,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM13,0x80(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%R12,%RCX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD 0x80(%R10,%RCX,1),%ZMM14,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM13,%ZMM27,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM28,0x80(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc0(%R12,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VADDPD 0xc0(%R10,%RCX,1),%ZMM5,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R13,%RCX,1),%ZMM4,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD %ZMM29,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%RSI,%RCX,1),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM11,0xc0(%R14,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R12,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPD 0xc0(%R10,%RCX,1),%ZMM2,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VADDPD %ZMM11,%ZMM30,%ZMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM31,0xc0(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x100,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 426ffb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x30b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	-0	1.01	0	0.78	0.22	0.45	0.63	0.23	1.06	0.12	1.21	0.07	1.41

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	5.45	0.88
2x2	4	1	2.01	2	2.76	0.87
2x4	8	1.01	4.03	4	1.38	0.87
2x8	16	0.78	6.25	8	0.88	1.01
2x16	32	0.45	7.25	16	0.88	1.15
2x32	64	0.23	7.45	32	0.82	1.38
2x64	128	0.12	7.45	64	0.81	1.37
2x96	192	0.07	7.06	96	0.84	1.52

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency