OV - - Loop 171

	Loop Id: 171	Module: exec	Source: advec_cell.cpp:67-110 [...]	Coverage: 0.01%

0x4295d0 MOV	0xfc(%RSP),%ECX

0x4295d7 CMP	%R15D,%EDI

0x4295da CMOVBE	%EDI,%R15D

0x4295de MOV	%R15D,0xe8(%RSP)

0x4295e6 LEA	(%RCX,%R15,1),%R8D

0x4295ea CMP	%R8D,%ECX

0x4295ed JAE	42aba8

0x4295f3 MOV	0x38(%RSP),%R15

0x4295f8 MOV	0xf0(%RSP),%RDI

0x429600 MOV	0x40(%RSP),%RSI

0x429605 VMOVQ	%XMM8,%RDX

0x42960a MOV	0x30(%RSP),%RAX

0x42960f VMOVQ	%XMM9,%R12

0x429614 MOV	(%RDX),%RCX

0x429617 VMOVQ	%XMM12,%R13

0x42961c VMOVQ	0x10(%R12),%XMM1

0x429623 VMOVQ	0x10(%R13),%XMM13

0x429629 MOV	(%R15),%R9

0x42962c MOV	(%RSI),%R11

0x42962f MOV	0x10(%R15),%R10

0x429633 MOV	0x8(%RAX),%R14

0x429637 MOV	(%R12),%R15

0x42963b VMOVQ	0x10(%RSI),%XMM5

0x429640 MOV	0x10(%RDX),%RSI

0x429644 IMUL	%RDI,%RCX

0x429648 IMUL	%RDI,%R9

0x42964c IMUL	%RDI,%R15

0x429650 IMUL	%RDI,%R11

0x429654 VMOVQ	%R9,%XMM16

0x42965a VMOVQ	%XMM11,%R9

0x42965f MOV	(%R9),%RAX

0x429662 MOV	0x10(%R9),%RDX

0x429666 MOV	0xe8(%RSP),%R9D

0x42966e VMOVQ	%R15,%XMM14

0x429673 IMUL	%RDI,%RAX

0x429677 IMUL	(%R13),%RDI

0x42967c VMOVQ	%RDI,%XMM2

0x429681 LEA	-0x1(%R9),%EDI

0x429685 CMP	$0xe,%EDI

0x429688 JBE	42a92f

0x42968e MOVSXD	0xf8(%RSP),%RDI

0x429696 VMOVQ	%XMM5,%RBX

0x42969b VMOVQ	%XMM16,%R13

0x4296a1 VPBROADCASTD	0xf8(%RSP),%ZMM3

0x4296a9 MOV	%R10,0x98(%RSP)

0x4296b1 VBROADCASTSD	0x366f5(%RIP),%ZMM19

0x4296bb VBROADCASTSD	0x36ed3(%RIP),%ZMM24

0x4296c5 VBROADCASTSD	0x37009(%RIP),%ZMM23

0x4296cf SHR	$0x4,%R9D

0x4296d3 MOV	%R8D,0xe4(%RSP)

0x4296db MOV	%R11,0xb8(%RSP)

0x4296e3 MOV	%RSI,0xa8(%RSP)

0x4296eb VMOVQ	%XMM5,0xd8(%RSP)

0x4296f4 MOV	%RCX,0xa0(%RSP)

0x4296fc MOV	%RDX,0x88(%RSP)

0x429704 MOV	%RAX,0x80(%RSP)

0x42970c SAL	$0x7,%R9

0x429710 VMOVQ	%XMM8,0xd0(%RSP)

0x429719 VXORPD	%XMM22,%XMM22,%XMM22

0x42971f LEA	(%R11,%RDI,1),%R12

0x429723 MOV	%R9,0x218(%RSP)

0x42972b MOV	$-0x2,%R9D

0x429731 VPADDD	0x36fc5(%RIP),%ZMM3,%ZMM27

0x42973b LEA	(%RBX,%R12,8),%R15

0x42973f LEA	(%R14,%RDI,8),%R12

0x429743 VPBROADCASTD	%R9D,%ZMM7

0x429749 VBROADCASTSD	0x35f8d(%RIP),%ZMM21

0x429753 MOV	%R15,0x210(%RSP)

0x42975b LEA	(%R10,%R13,8),%R15

0x42975f MOV	%R12,0x288(%RSP)

0x429767 VBROADCASTSD	0x36fcf(%RIP),%ZMM20

0x429771 VMOVQ	%XMM14,%R13

0x429776 VMOVQ	%XMM9,0xc8(%RSP)

0x42977f LEA	(%RSI,%RCX,8),%RBX

0x429783 LEA	(%R13,%RDI,1),%R12

0x429788 VMOVQ	%XMM1,%R13

0x42978d VMOVQ	%XMM11,0xc0(%RSP)

0x429796 LEA	(%R13,%R12,8),%R12

0x42979b VMOVQ	%XMM2,%R13

0x4297a0 VMOVDQA32	%ZMM7,0x180(%RSP)

0x4297a8 ADD	%R13,%RDI

0x4297ab VMOVQ	%XMM13,%R13

0x4297b0 MOV	%R12,0x208(%RSP)

0x4297b8 LEA	(%RDX,%RAX,8),%R12

0x4297bc LEA	(%R13,%RDI,8),%RDI

0x4297c1 XOR	%R13D,%R13D

0x4297c4 VMOVQ	%XMM12,0xb0(%RSP)

0x4297cd MOV	%RDI,0x200(%RSP)

0x4297d5 MOV	$0x10,%EDI

0x4297da VMOVQ	%XMM16,0x90(%RSP)

0x4297e2 MOV	%R13,%R10

0x4297e5 VPBROADCASTD	%EDI,%ZMM6

0x4297eb MOV	$0x1,%EDI

0x4297f0 VMOVQ	%XMM1,0x78(%RSP)

0x4297f6 VPBROADCASTD	%EDI,%ZMM10

0x4297fc VMOVQ	%XMM14,0x70(%RSP)

0x429802 VMOVQ	%XMM13,0x68(%RSP)

0x429808 VMOVDQA32	%ZMM6,0x1c0(%RSP)

0x429810 VMOVDQA32	%ZMM10,0x140(%RSP)

0x429818 VMOVQ	%XMM2,0x60(%RSP)

0x42981e XCHG	%AX,%AX

  (173) 0x429820 MOV	0x210(%RSP),%R11

  (173) 0x429828 VMOVDQA32	%ZMM27,%ZMM12

  (173) 0x42982e VPADDD	0x140(%RSP),%ZMM12,%ZMM3

  (173) 0x429836 VPMINSD	0x100(%RSP),%ZMM3,%ZMM6

  (173) 0x42983e VPADDD	0x36f38(%RIP),%ZMM12,%ZMM14

  (173) 0x429848 VPADDD	0x180(%RSP),%ZMM12,%ZMM9

  (173) 0x429850 VPADDD	0x1c0(%RSP),%ZMM27,%ZMM27

  (173) 0x429858 VPMOVSXDQ	%YMM12,%ZMM11

  (173) 0x42985e VEXTRACTI32X8	$0x1,%ZMM12,%YMM2

  (173) 0x429865 VMOVUPD	(%R11,%R10,1),%ZMM4

  (173) 0x42986c VMOVUPD	0x40(%R11,%R10,1),%ZMM8

  (173) 0x429874 VPMOVSXDQ	%YMM2,%ZMM13

  (173) 0x42987a VEXTRACTI32X8	$0x1,%ZMM6,%YMM7

  (173) 0x429881 VEXTRACTI32X8	$0x1,%ZMM14,%YMM10

  (173) 0x429888 VMOVDQA	%YMM14,%YMM15

  (173) 0x42988d VPMOVSXDQ	%YMM7,%ZMM3

  (173) 0x429893 VPMOVSXDQ	%YMM14,%ZMM2

  (173) 0x429899 VMOVAPD	%ZMM4,0x400(%RSP)

  (173) 0x4298a1 VMOVAPD	0x400(%RSP),%ZMM5

  (173) 0x4298a9 VMOVAPD	%ZMM8,0x3c0(%RSP)

  (173) 0x4298b1 VMOVAPD	0x3c0(%RSP),%ZMM0

  (173) 0x4298b9 VMOVDQA64	%ZMM11,%ZMM14

  (173) 0x4298bf VPMOVSXDQ	%YMM10,%ZMM1

  (173) 0x4298c5 VCMPPD	$0xe,%ZMM22,%ZMM5,%K2

  (173) 0x4298cc VPMOVSXDQ	%YMM6,%ZMM5

  (173) 0x4298d2 VMOVDQA64	%ZMM13,%ZMM6

  (173) 0x4298d8 VCMPPD	$0xe,%ZMM22,%ZMM0,%K1

  (173) 0x4298df VMOVDQA64	%ZMM3,%ZMM0

  (173) 0x4298e5 VMOVDQA64	%ZMM5,%ZMM4

  (173) 0x4298eb VPMOVSXDQ	%YMM15,%ZMM14{%K2}

  (173) 0x4298f1 VMOVDQA64	%ZMM11,%ZMM2{%K2}

  (173) 0x4298f7 VPMOVSXDQ	%YMM10,%ZMM6{%K1}

  (173) 0x4298fd VPMOVSXDQ	%YMM10,%ZMM0{%K1}

  (173) 0x429903 VEXTRACTI64X4	$0x1,%ZMM14,%YMM10

  (173) 0x42990a VPMOVSXDQ	%YMM15,%ZMM4{%K2}

  (173) 0x429910 VPMOVSXDQ	%YMM9,%ZMM5{%K2}

  (173) 0x429916 VALIGNQ	$0x3,%YMM14,%YMM14,%YMM15

  (173) 0x42991d VEXTRACTI32X8	$0x1,%ZMM9,%YMM11

  (173) 0x429924 VPEXTRQ	$0x1,%XMM14,0x478(%RSP)

  (173) 0x42992f VMOVQ	%XMM14,%R8

  (173) 0x429934 VMOVQ	%XMM10,%R13

  (173) 0x429939 VMOVDQA64	%ZMM13,%ZMM1{%K1}

  (173) 0x42993f VPMOVSXDQ	%YMM11,%ZMM3{%K1}

  (173) 0x429945 VEXTRACTI64X2	$0x1,%YMM14,%XMM9

  (173) 0x42994c VMOVDQA64	%XMM15,%XMM28

  (173) 0x429952 VEXTRACTI64X2	$0x1,%YMM10,%XMM14

  (173) 0x429959 VMOVQ	%XMM9,%RDX

  (173) 0x42995e SAL	$0x3,%R8

  (173) 0x429962 VMOVQ	%XMM14,%R11

  (173) 0x429967 VALIGNQ	$0x3,%YMM6,%YMM6,%YMM13

  (173) 0x42996e MOV	%R8,0x470(%RSP)

  (173) 0x429976 LEA	(,%R13,8),%R9

  (173) 0x42997e LEA	(%R15,%R8,1),%RCX

  (173) 0x429982 VMOVQ	%XMM6,%R13

  (173) 0x429987 LEA	(,%R11,8),%R8

  (173) 0x42998f VEXTRACTI64X2	$0x1,%YMM6,%XMM8

  (173) 0x429996 VPEXTRQ	$0x1,%XMM6,%R11

  (173) 0x42999c MOV	%R8,0x448(%RSP)

  (173) 0x4299a4 MOV	%R9,0x458(%RSP)

  (173) 0x4299ac VEXTRACTI64X4	$0x1,%ZMM6,%YMM6

  (173) 0x4299b3 MOV	%RCX,0x468(%RSP)

  (173) 0x4299bb VEXTRACTI64X2	$0x1,%YMM6,%XMM15

  (173) 0x4299c2 LEA	(,%RDX,8),%RAX

  (173) 0x4299ca LEA	(%R15,%R8,1),%RDX

  (173) 0x4299ce VMOVQ	%XMM8,%R8

  (173) 0x4299d3 LEA	(%R15,%R9,1),%RDI

  (173) 0x4299d7 MOV	%RDX,0x440(%RSP)

  (173) 0x4299df LEA	(,%R8,8),%RDX

  (173) 0x4299e7 VMOVQ	%XMM15,%R8

  (173) 0x4299ec LEA	(,%R13,8),%R9

  (173) 0x4299f4 MOV	%RDX,0x3a8(%RSP)

  (173) 0x4299fc LEA	(%R15,%RDX,1),%R13

  (173) 0x429a00 LEA	(,%R8,8),%RDX

  (173) 0x429a08 MOV	0x440(%RSP),%R8

  (173) 0x429a10 MOV	%RDI,0x450(%RSP)

  (173) 0x429a18 MOV	%R9,0x3b8(%RSP)

  (173) 0x429a20 LEA	(%R15,%R9,1),%RDI

  (173) 0x429a24 VMOVQ	%XMM6,%R9

  (173) 0x429a29 VALIGNQ	$0x3,%YMM10,%YMM10,%YMM31

  (173) 0x429a30 MOV	%RDI,0x3b0(%RSP)

  (173) 0x429a38 MOV	%RDX,0x390(%RSP)

  (173) 0x429a40 MOV	%RAX,0x460(%RSP)

  (173) 0x429a48 MOV	%R13,0x3a0(%RSP)

  (173) 0x429a50 VPEXTRQ	$0x1,%XMM6,%R13

  (173) 0x429a56 VMOVSD	(%R8),%XMM7

  (173) 0x429a5b MOV	0x450(%RSP),%R8

  (173) 0x429a63 LEA	(,%R9,8),%RDI

  (173) 0x429a6b LEA	(%R15,%RAX,1),%RCX

  (173) 0x429a6f MOV	0x478(%RSP),%RSI

  (173) 0x429a77 LEA	(%R15,%RDI,1),%R9

  (173) 0x429a7b MOV	%RDI,0x398(%RSP)

  (173) 0x429a83 LEA	(%R15,%RDX,1),%RDI

  (173) 0x429a87 VMOVQ	%XMM31,%RDX

  (173) 0x429a8d VPEXTRQ	$0x1,%XMM10,%RAX

  (173) 0x429a93 VMOVHPD	(%R15,%RDX,8),%XMM7,%XMM14

  (173) 0x429a99 VANDPD	0x400(%RSP),%ZMM19,%ZMM10

  (173) 0x429aa1 VALIGNQ	$0x3,%YMM6,%YMM6,%YMM11

  (173) 0x429aa8 VMOVSD	(%R8),%XMM12

  (173) 0x429aad VMOVSD	(%RCX),%XMM6

  (173) 0x429ab1 VMOVHPD	(%R15,%RAX,8),%XMM12,%XMM8

  (173) 0x429ab7 MOV	%RCX,0x280(%RSP)

  (173) 0x429abf VMOVQ	%XMM28,%RCX

  (173) 0x429ac5 VINSERTF128	$0x1,%XMM14,%YMM8,%YMM15

  (173) 0x429acb MOV	%RDI,0x270(%RSP)

  (173) 0x429ad3 MOV	%R9,0x278(%RSP)

  (173) 0x429adb VMOVHPD	(%R15,%RCX,8),%XMM6,%XMM9

  (173) 0x429ae1 VMOVQ	%XMM13,%RCX

  (173) 0x429ae6 MOV	0x468(%RSP),%RDX

  (173) 0x429aee MOV	0x3a0(%RSP),%R8

  (173) 0x429af6 VALIGNQ	$0x3,%YMM1,%YMM1,%YMM25

  (173) 0x429afd VMOVSD	(%RDX),%XMM7

  (173) 0x429b01 VMOVHPD	(%R15,%RSI,8),%XMM7,%XMM14

  (173) 0x429b07 VMOVQ	%XMM11,%RSI

  (173) 0x429b0c VINSERTF128	$0x1,%XMM9,%YMM14,%YMM12

  (173) 0x429b12 VMOVSD	(%R9),%XMM9

  (173) 0x429b17 VMOVHPD	(%R15,%R13,8),%XMM9,%XMM7

  (173) 0x429b1d MOV	0x3b0(%RSP),%RDX

  (173) 0x429b25 VINSERTF64X4	$0x1,%YMM15,%ZMM12,%ZMM8

  (173) 0x429b2c VANDPD	0x3c0(%RSP),%ZMM19,%ZMM15

  (173) 0x429b34 VMOVSD	(%R8),%XMM12

  (173) 0x429b39 VDIVPD	%ZMM8,%ZMM10,%ZMM8

  (173) 0x429b3f VMOVSD	(%RDI),%XMM10

  (173) 0x429b43 MOV	0x288(%RSP),%RDI

  (173) 0x429b4b VMOVHPD	(%R15,%RSI,8),%XMM10,%XMM6

  (173) 0x429b51 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM14

  (173) 0x429b57 VMOVQ	%XMM4,%RSI

  (173) 0x429b5c VMOVHPD	(%R15,%RCX,8),%XMM12,%XMM10

  (173) 0x429b62 VMOVSD	(%RDX),%XMM6

  (173) 0x429b66 VMOVHPD	(%R15,%R11,8),%XMM6,%XMM9

  (173) 0x429b6c VPEXTRQ	$0x1,%XMM4,%RDX

  (173) 0x429b72 VINSERTF128	$0x1,%XMM10,%YMM9,%YMM7

  (173) 0x429b78 VINSERTF64X4	$0x1,%YMM14,%ZMM7,%ZMM14

  (173) 0x429b7f VEXTRACTI64X2	$0x1,%YMM4,%XMM6

  (173) 0x429b86 VDIVPD	%ZMM14,%ZMM15,%ZMM7

  (173) 0x429b8c VMOVUPD	(%RDI,%R10,1),%ZMM15

  (173) 0x429b93 VMOVQ	%XMM6,%R8

  (173) 0x429b98 VALIGNQ	$0x3,%YMM4,%YMM4,%YMM14

  (173) 0x429b9f VEXTRACTI64X4	$0x1,%ZMM4,%YMM4

  (173) 0x429ba6 VMOVQ	%XMM4,%RDI

  (173) 0x429bab VPEXTRQ	$0x1,%XMM4,%RCX

  (173) 0x429bb1 VMOVAPD	%ZMM15,0x340(%RSP)

  (173) 0x429bb9 VEXTRACTI64X2	$0x1,%YMM4,%XMM15

  (173) 0x429bc0 VALIGNQ	$0x3,%YMM4,%YMM4,%YMM10

  (173) 0x429bc7 VMOVSD	(%R14,%RDI,8),%XMM4

  (173) 0x429bcd VMOVQ	%XMM15,%R9

  (173) 0x429bd2 VMOVHPD	(%R14,%RCX,8),%XMM4,%XMM9

  (173) 0x429bd8 VMOVSD	(%R14,%R9,8),%XMM12

  (173) 0x429bde VMOVQ	%XMM10,%R9

  (173) 0x429be3 VMOVSD	(%R14,%R8,8),%XMM10

  (173) 0x429be9 VMOVQ	%XMM14,%R8

  (173) 0x429bee VMOVHPD	(%R14,%R9,8),%XMM12,%XMM6

  (173) 0x429bf4 VMOVHPD	(%R14,%R8,8),%XMM10,%XMM14

  (173) 0x429bfa VMOVSD	(%R14,%RSI,8),%XMM12

  (173) 0x429c00 VINSERTF128	$0x1,%XMM6,%YMM9,%YMM15

  (173) 0x429c06 VMOVHPD	(%R14,%RDX,8),%XMM12,%XMM6

  (173) 0x429c0c VPEXTRQ	$0x1,%XMM0,%RDX

  (173) 0x429c12 VINSERTF128	$0x1,%XMM14,%YMM6,%YMM4

  (173) 0x429c18 VADDPD	%ZMM24,%ZMM8,%ZMM14

  (173) 0x429c1e VINSERTF64X4	$0x1,%YMM15,%ZMM4,%ZMM9

  (173) 0x429c25 VMOVAPD	0x340(%RSP),%ZMM15

  (173) 0x429c2d MOV	0x288(%RSP),%RSI

  (173) 0x429c35 VMOVQ	%XMM28,0x2d0(%RSP)

  (173) 0x429c3d VMOVUPD	0x40(%RSI,%R10,1),%ZMM12

  (173) 0x429c45 VMOVQ	%XMM0,%RSI

  (173) 0x429c4a VDIVPD	%ZMM9,%ZMM15,%ZMM10

  (173) 0x429c50 VEXTRACTI64X2	$0x1,%YMM0,%XMM9

  (173) 0x429c57 VMOVAPD	%ZMM12,0x340(%RSP)

  (173) 0x429c5f VALIGNQ	$0x3,%YMM0,%YMM0,%YMM15

  (173) 0x429c66 VEXTRACTI64X4	$0x1,%ZMM0,%YMM0

  (173) 0x429c6d VMOVQ	%XMM9,%R8

  (173) 0x429c72 VMOVQ	%XMM0,%RDI

  (173) 0x429c77 VPEXTRQ	$0x1,%XMM0,%RCX

  (173) 0x429c7d VEXTRACTI64X2	$0x1,%YMM0,%XMM12

  (173) 0x429c84 VMULPD	%ZMM14,%ZMM10,%ZMM14

  (173) 0x429c8a VALIGNQ	$0x3,%YMM0,%YMM0,%YMM4

  (173) 0x429c91 VMOVSD	(%R14,%RDI,8),%XMM0

  (173) 0x429c97 VMOVQ	%XMM12,%R9

  (173) 0x429c9c VMOVHPD	(%R14,%RCX,8),%XMM0,%XMM10

  (173) 0x429ca2 VMOVQ	%XMM31,%RCX

  (173) 0x429ca8 VMOVSD	(%R14,%R9,8),%XMM6

  (173) 0x429cae VMOVQ	%XMM4,%R9

  (173) 0x429cb3 VMOVSD	(%R14,%R8,8),%XMM4

  (173) 0x429cb9 VMOVQ	%XMM15,%R8

  (173) 0x429cbe MOV	0x448(%RSP),%RDI

  (173) 0x429cc6 VMOVHPD	(%R14,%R9,8),%XMM6,%XMM9

  (173) 0x429ccc VMOVHPD	(%R14,%R8,8),%XMM4,%XMM15

  (173) 0x429cd2 VMOVSD	(%R14,%RSI,8),%XMM6

  (173) 0x429cd8 MOV	0x470(%RSP),%R9

  (173) 0x429ce0 VINSERTF128	$0x1,%XMM9,%YMM10,%YMM12

  (173) 0x429ce6 VMOVHPD	(%R14,%RDX,8),%XMM6,%XMM9

  (173) 0x429cec MOV	0x458(%RSP),%RDX

  (173) 0x429cf4 MOV	0x460(%RSP),%RSI

  (173) 0x429cfc VINSERTF128	$0x1,%XMM15,%YMM9,%YMM0

  (173) 0x429d02 VADDPD	%ZMM24,%ZMM7,%ZMM15

  (173) 0x429d08 VMOVQ	%XMM28,%R8

  (173) 0x429d0e VSUBPD	%ZMM8,%ZMM23,%ZMM9

  (173) 0x429d14 VINSERTF64X4	$0x1,%YMM12,%ZMM0,%ZMM10

  (173) 0x429d1b VMOVAPD	0x340(%RSP),%ZMM12

  (173) 0x429d23 ADD	%RBX,%RDI

  (173) 0x429d26 VSUBPD	%ZMM8,%ZMM24,%ZMM8

  (173) 0x429d2c VMOVSD	(%RDI),%XMM0

  (173) 0x429d30 MOV	%RDI,0x258(%RSP)

  (173) 0x429d38 MOV	0x478(%RSP),%RDI

  (173) 0x429d40 ADD	%RBX,%R9

  (173) 0x429d43 LEA	(%RDX,%RBX,1),%RDX

  (173) 0x429d47 LEA	(%RSI,%RBX,1),%RSI

  (173) 0x429d4b MOV	%RDX,0x260(%RSP)

  (173) 0x429d53 MOV	%RSI,0x268(%RSP)

  (173) 0x429d5b VALIGNQ	$0x3,%YMM2,%YMM2,%YMM28

  (173) 0x429d62 VDIVPD	%ZMM10,%ZMM12,%ZMM4

  (173) 0x429d68 VMOVHPD	(%RBX,%RCX,8),%XMM0,%XMM10

  (173) 0x429d6d VMOVSD	(%RDX),%XMM12

  (173) 0x429d71 VMOVSD	(%RSI),%XMM0

  (173) 0x429d75 MOV	0x3b8(%RSP),%RCX

  (173) 0x429d7d MOV	0x3a8(%RSP),%RSI

  (173) 0x429d85 LEA	(%RCX,%RBX,1),%RCX

  (173) 0x429d89 ADD	%RBX,%RSI

  (173) 0x429d8c VMULPD	%ZMM15,%ZMM4,%ZMM6

  (173) 0x429d92 VMOVHPD	(%RBX,%RAX,8),%XMM12,%XMM4

  (173) 0x429d97 VSUBPD	%ZMM7,%ZMM23,%ZMM15

  (173) 0x429d9d VSUBPD	%ZMM7,%ZMM24,%ZMM7

  (173) 0x429da3 VINSERTF128	$0x1,%XMM10,%YMM4,%YMM12

  (173) 0x429da9 VMOVSD	(%R9),%XMM4

  (173) 0x429dae VMOVHPD	(%RBX,%R8,8),%XMM0,%XMM10

  (173) 0x429db4 VMOVHPD	(%RBX,%RDI,8),%XMM4,%XMM0

  (173) 0x429db9 MOV	0x398(%RSP),%RDI

  (173) 0x429dc1 MOV	0x390(%RSP),%RDX

  (173) 0x429dc9 VINSERTF128	$0x1,%XMM10,%YMM0,%YMM10

  (173) 0x429dcf VMOVQ	%XMM11,0x248(%RSP)

  (173) 0x429dd8 VINSERTF64X4	$0x1,%YMM12,%ZMM10,%ZMM0

  (173) 0x429ddf VMOVQ	%XMM13,0x250(%RSP)

  (173) 0x429de8 VPEXTRQ	$0x1,%XMM5,0x2c8(%RSP)

  (173) 0x429df3 VPEXTRQ	$0x1,%XMM3,0x2b8(%RSP)

  (173) 0x429dfe LEA	(%RDX,%RBX,1),%R8

  (173) 0x429e02 ADD	%RBX,%RDI

  (173) 0x429e05 VMOVQ	%XMM11,%RDX

  (173) 0x429e0a VMOVSD	(%R8),%XMM12

  (173) 0x429e0f VMOVSD	(%RDI),%XMM4

  (173) 0x429e13 VMOVHPD	(%RBX,%RDX,8),%XMM12,%XMM11

  (173) 0x429e18 VMOVHPD	(%RBX,%R13,8),%XMM4,%XMM10

  (173) 0x429e1e VMOVQ	%XMM13,%RDX

  (173) 0x429e23 VINSERTF128	$0x1,%XMM11,%YMM10,%YMM12

  (173) 0x429e29 VMOVSD	(%RCX),%XMM4

  (173) 0x429e2d VMOVSD	(%RSI),%XMM11

  (173) 0x429e31 VMOVHPD	(%RBX,%R11,8),%XMM4,%XMM10

  (173) 0x429e37 VMOVHPD	(%RBX,%RDX,8),%XMM11,%XMM13

  (173) 0x429e3c VMOVQ	%XMM5,%RDX

  (173) 0x429e41 VINSERTF128	$0x1,%XMM13,%YMM10,%YMM11

  (173) 0x429e47 VEXTRACTI64X2	$0x1,%YMM5,%XMM10

  (173) 0x429e4e VINSERTF64X4	$0x1,%YMM12,%ZMM11,%ZMM4

  (173) 0x429e55 SAL	$0x3,%RDX

  (173) 0x429e59 VALIGNQ	$0x3,%YMM5,%YMM5,%YMM13

  (173) 0x429e60 MOV	%RDX,0x340(%RSP)

  (173) 0x429e68 VEXTRACTI64X4	$0x1,%ZMM5,%YMM5

  (173) 0x429e6f VMOVQ	%XMM10,%RDX

  (173) 0x429e74 VPEXTRQ	$0x1,%XMM5,0x2c0(%RSP)

  (173) 0x429e7f VEXTRACTI64X2	$0x1,%YMM5,%XMM12

  (173) 0x429e86 SAL	$0x3,%RDX

  (173) 0x429e8a MOV	%RDX,0x388(%RSP)

  (173) 0x429e92 VMOVQ	%XMM5,%RDX

  (173) 0x429e97 SAL	$0x3,%RDX

  (173) 0x429e9b MOV	%RDX,0x380(%RSP)

  (173) 0x429ea3 VMOVQ	%XMM12,%RDX

  (173) 0x429ea8 VEXTRACTI64X2	$0x1,%YMM3,%XMM11

  (173) 0x429eaf SAL	$0x3,%RDX

  (173) 0x429eb3 MOV	%RDX,0x338(%RSP)

  (173) 0x429ebb VMOVQ	%XMM3,%RDX

  (173) 0x429ec0 SAL	$0x3,%RDX

  (173) 0x429ec4 MOV	%RDX,0x330(%RSP)

  (173) 0x429ecc VMOVQ	%XMM11,%RDX

  (173) 0x429ed1 VALIGNQ	$0x3,%YMM3,%YMM3,%YMM11

  (173) 0x429ed8 VEXTRACTI64X4	$0x1,%ZMM3,%YMM3

  (173) 0x429edf VPEXTRQ	$0x1,%XMM3,0x2b0(%RSP)

  (173) 0x429eea VEXTRACTI64X2	$0x1,%YMM3,%XMM10

  (173) 0x429ef1 SAL	$0x3,%RDX

  (173) 0x429ef5 MOV	%RDX,0x328(%RSP)

  (173) 0x429efd VMOVQ	%XMM3,%RDX

  (173) 0x429f02 SAL	$0x3,%RDX

  (173) 0x429f06 MOV	%RDX,0x320(%RSP)

  (173) 0x429f0e VMOVQ	%XMM10,%RDX

  (173) 0x429f13 SAL	$0x3,%RDX

  (173) 0x429f17 VALIGNQ	$0x3,%YMM5,%YMM5,%YMM12

  (173) 0x429f1e MOV	%RDX,0x318(%RSP)

  (173) 0x429f26 MOV	0x338(%RSP),%RDX

  (173) 0x429f2e VMOVQ	%XMM12,0x238(%RSP)

  (173) 0x429f37 VALIGNQ	$0x3,%YMM3,%YMM3,%YMM26

  (173) 0x429f3e VMOVSD	(%RBX,%RDX,1),%XMM3

  (173) 0x429f43 VMOVQ	%XMM12,%RDX

  (173) 0x429f48 VMOVHPD	(%RBX,%RDX,8),%XMM3,%XMM12

  (173) 0x429f4d MOV	0x380(%RSP),%RDX

  (173) 0x429f55 VMOVSD	(%RBX,%RDX,1),%XMM5

  (173) 0x429f5a MOV	0x2c0(%RSP),%RDX

  (173) 0x429f62 VMOVHPD	(%RBX,%RDX,8),%XMM5,%XMM10

  (173) 0x429f67 MOV	0x388(%RSP),%RDX

  (173) 0x429f6f VMOVQ	%XMM13,0x240(%RSP)

  (173) 0x429f78 VINSERTF128	$0x1,%XMM12,%YMM10,%YMM12

  (173) 0x429f7e VMOVQ	%XMM11,0x230(%RSP)

  (173) 0x429f87 VPEXTRQ	$0x1,%XMM2,0x2a8(%RSP)

  (173) 0x429f92 VPEXTRQ	$0x1,%XMM1,0x298(%RSP)

  (173) 0x429f9d VMOVQ	%XMM26,0x228(%RSP)

  (173) 0x429fa5 VMOVSD	(%RBX,%RDX,1),%XMM3

  (173) 0x429faa VMOVQ	%XMM13,%RDX

  (173) 0x429faf VMOVHPD	(%RBX,%RDX,8),%XMM3,%XMM13

  (173) 0x429fb4 MOV	0x340(%RSP),%RDX

  (173) 0x429fbc VMOVSD	(%RBX,%RDX,1),%XMM5

  (173) 0x429fc1 MOV	0x2c8(%RSP),%RDX

  (173) 0x429fc9 VMOVHPD	(%RBX,%RDX,8),%XMM5,%XMM10

  (173) 0x429fce MOV	0x318(%RSP),%RDX

  (173) 0x429fd6 VINSERTF128	$0x1,%XMM13,%YMM10,%YMM3

  (173) 0x429fdc VINSERTF64X4	$0x1,%YMM12,%ZMM3,%ZMM12

  (173) 0x429fe3 VSUBPD	%ZMM12,%ZMM0,%ZMM3

  (173) 0x429fe9 VMOVSD	(%RBX,%RDX,1),%XMM13

  (173) 0x429fee VMOVQ	%XMM26,%RDX

  (173) 0x429ff4 VMOVHPD	(%RBX,%RDX,8),%XMM13,%XMM5

  (173) 0x429ff9 MOV	0x320(%RSP),%RDX

  (173) 0x42a001 VMOVSD	(%RBX,%RDX,1),%XMM10

  (173) 0x42a006 MOV	0x2b0(%RSP),%RDX

  (173) 0x42a00e VMOVHPD	(%RBX,%RDX,8),%XMM10,%XMM12

  (173) 0x42a013 MOV	0x328(%RSP),%RDX

  (173) 0x42a01b VINSERTF128	$0x1,%XMM5,%YMM12,%YMM13

  (173) 0x42a021 VMOVSD	(%RBX,%RDX,1),%XMM5

  (173) 0x42a026 VMOVQ	%XMM11,%RDX

  (173) 0x42a02b VMOVHPD	(%RBX,%RDX,8),%XMM5,%XMM11

  (173) 0x42a030 MOV	0x330(%RSP),%RDX

  (173) 0x42a038 VMOVSD	(%RBX,%RDX,1),%XMM10

  (173) 0x42a03d MOV	0x2b8(%RSP),%RDX

  (173) 0x42a045 VMOVHPD	(%RBX,%RDX,8),%XMM10,%XMM12

  (173) 0x42a04a VMOVQ	%XMM2,%RDX

  (173) 0x42a04f VINSERTF128	$0x1,%XMM11,%YMM12,%YMM5

  (173) 0x42a055 VEXTRACTI64X2	$0x1,%YMM2,%XMM12

  (173) 0x42a05c VEXTRACTI64X4	$0x1,%ZMM2,%YMM2

  (173) 0x42a063 VINSERTF64X4	$0x1,%YMM13,%ZMM5,%ZMM13

  (173) 0x42a06a VSUBPD	%ZMM13,%ZMM4,%ZMM5

  (173) 0x42a070 VPEXTRQ	$0x1,%XMM2,0x2a0(%RSP)

  (173) 0x42a07b SAL	$0x3,%RDX

  (173) 0x42a07f MOV	%RDX,0x310(%RSP)

  (173) 0x42a087 VMOVQ	%XMM12,%RDX

  (173) 0x42a08c VEXTRACTI64X2	$0x1,%YMM2,%XMM10

  (173) 0x42a093 SAL	$0x3,%RDX

  (173) 0x42a097 MOV	%RDX,0x308(%RSP)

  (173) 0x42a09f VMOVQ	%XMM2,%RDX

  (173) 0x42a0a4 SAL	$0x3,%RDX

  (173) 0x42a0a8 MOV	%RDX,0x300(%RSP)

  (173) 0x42a0b0 VMOVQ	%XMM10,%RDX

  (173) 0x42a0b5 VEXTRACTI64X2	$0x1,%YMM1,%XMM13

  (173) 0x42a0bc SAL	$0x3,%RDX

  (173) 0x42a0c0 MOV	%RDX,0x2f8(%RSP)

  (173) 0x42a0c8 VMOVQ	%XMM1,%RDX

  (173) 0x42a0cd VEXTRACTI64X4	$0x1,%ZMM1,%YMM1

  (173) 0x42a0d4 SAL	$0x3,%RDX

  (173) 0x42a0d8 MOV	%RDX,0x2f0(%RSP)

  (173) 0x42a0e0 VMOVQ	%XMM13,%RDX

  (173) 0x42a0e5 VEXTRACTI64X2	$0x1,%YMM1,%XMM12

  (173) 0x42a0ec SAL	$0x3,%RDX

  (173) 0x42a0f0 MOV	%RDX,0x2e8(%RSP)

  (173) 0x42a0f8 VMOVQ	%XMM1,%RDX

  (173) 0x42a0fd VPEXTRQ	$0x1,%XMM1,0x290(%RSP)

  (173) 0x42a108 SAL	$0x3,%RDX

  (173) 0x42a10c MOV	%RDX,0x2e0(%RSP)

  (173) 0x42a114 VMOVQ	%XMM12,%RDX

  (173) 0x42a119 SAL	$0x3,%RDX

  (173) 0x42a11d VALIGNQ	$0x3,%YMM2,%YMM2,%YMM11

  (173) 0x42a124 MOV	%RDX,0x2d8(%RSP)

  (173) 0x42a12c MOV	0x2f8(%RSP),%RDX

  (173) 0x42a134 VMOVQ	%XMM11,0x220(%RSP)

  (173) 0x42a13d VALIGNQ	$0x3,%YMM1,%YMM1,%YMM26

  (173) 0x42a144 VMOVSD	(%RBX,%RDX,1),%XMM2

  (173) 0x42a149 VMOVQ	%XMM11,%RDX

  (173) 0x42a14e VMOVHPD	(%RBX,%RDX,8),%XMM2,%XMM11

  (173) 0x42a153 MOV	0x300(%RSP),%RDX

  (173) 0x42a15b VMOVSD	(%RBX,%RDX,1),%XMM13

  (173) 0x42a160 MOV	0x2a0(%RSP),%RDX

  (173) 0x42a168 VMOVHPD	(%RBX,%RDX,8),%XMM13,%XMM1

  (173) 0x42a16d MOV	0x308(%RSP),%RDX

  (173) 0x42a175 VINSERTF128	$0x1,%XMM11,%YMM1,%YMM12

  (173) 0x42a17b VMOVSD	(%RBX,%RDX,1),%XMM10

  (173) 0x42a180 VMOVQ	%XMM28,%RDX

  (173) 0x42a186 VMOVHPD	(%RBX,%RDX,8),%XMM10,%XMM2

  (173) 0x42a18b MOV	0x310(%RSP),%RDX

  (173) 0x42a193 VMOVSD	(%RBX,%RDX,1),%XMM11

  (173) 0x42a198 MOV	0x2a8(%RSP),%RDX

  (173) 0x42a1a0 VMOVHPD	(%RBX,%RDX,8),%XMM11,%XMM13

  (173) 0x42a1a5 MOV	0x2d8(%RSP),%RDX

  (173) 0x42a1ad VINSERTF128	$0x1,%XMM2,%YMM13,%YMM1

  (173) 0x42a1b3 VINSERTF64X4	$0x1,%YMM12,%ZMM1,%ZMM12

  (173) 0x42a1ba VSUBPD	%ZMM0,%ZMM12,%ZMM1

  (173) 0x42a1c0 VMOVSD	(%RBX,%RDX,1),%XMM10

  (173) 0x42a1c5 VMOVQ	%XMM26,%RDX

  (173) 0x42a1cb VMOVHPD	(%RBX,%RDX,8),%XMM10,%XMM2

  (173) 0x42a1d0 MOV	0x2e0(%RSP),%RDX

  (173) 0x42a1d8 VCMPPD	$0x2,%ZMM22,%ZMM1,%K3

  (173) 0x42a1df VMOVSD	(%RBX,%RDX,1),%XMM11

  (173) 0x42a1e4 MOV	0x290(%RSP),%RDX

  (173) 0x42a1ec VMOVHPD	(%RBX,%RDX,8),%XMM11,%XMM13

  (173) 0x42a1f1 MOV	0x2e8(%RSP),%RDX

  (173) 0x42a1f9 VINSERTF128	$0x1,%XMM2,%YMM13,%YMM12

  (173) 0x42a1ff VMOVSD	(%RBX,%RDX,1),%XMM10

  (173) 0x42a204 VMOVQ	%XMM25,%RDX

  (173) 0x42a20a VMOVHPD	(%RBX,%RDX,8),%XMM10,%XMM11

  (173) 0x42a20f MOV	0x2f0(%RSP),%RDX

  (173) 0x42a217 VMOVSD	(%RBX,%RDX,1),%XMM2

  (173) 0x42a21c MOV	0x298(%RSP),%RDX

  (173) 0x42a224 VMOVHPD	(%RBX,%RDX,8),%XMM2,%XMM13

  (173) 0x42a229 VINSERTF128	$0x1,%XMM11,%YMM13,%YMM10

  (173) 0x42a22f VBLENDMPD	%ZMM21,%ZMM24,%ZMM11{%K3}

  (173) 0x42a235 VINSERTF64X4	$0x1,%YMM12,%ZMM10,%ZMM12

  (173) 0x42a23c VMULPD	%ZMM11,%ZMM8,%ZMM11

  (173) 0x42a242 VSUBPD	%ZMM4,%ZMM12,%ZMM2

  (173) 0x42a248 VMULPD	%ZMM1,%ZMM3,%ZMM12

  (173) 0x42a24e VANDPD	%ZMM19,%ZMM1,%ZMM1

  (173) 0x42a254 VANDPD	%ZMM19,%ZMM3,%ZMM3

  (173) 0x42a25a VMULPD	%ZMM2,%ZMM5,%ZMM10

  (173) 0x42a260 VMULPD	%ZMM1,%ZMM9,%ZMM16

  (173) 0x42a266 VANDPD	%ZMM19,%ZMM2,%ZMM18

  (173) 0x42a26c VANDPD	%ZMM19,%ZMM5,%ZMM5

  (173) 0x42a272 VCMPPD	$0x2,%ZMM22,%ZMM2,%K4

  (173) 0x42a279 VMULPD	%ZMM18,%ZMM15,%ZMM2

  (173) 0x42a27f VFMADD231PD	%ZMM3,%ZMM14,%ZMM16

  (173) 0x42a285 VCMPPD	$0xe,%ZMM22,%ZMM12,%K5

  (173) 0x42a28c VMINPD	%ZMM1,%ZMM3,%ZMM12

  (173) 0x42a292 VFMADD231PD	%ZMM5,%ZMM6,%ZMM2

  (173) 0x42a298 VMINPD	%ZMM18,%ZMM5,%ZMM5

  (173) 0x42a29e VCMPPD	$0xe,%ZMM22,%ZMM10,%K6

  (173) 0x42a2a5 VBLENDMPD	%ZMM21,%ZMM24,%ZMM13{%K4}

  (173) 0x42a2ab VMULPD	%ZMM20,%ZMM16,%ZMM18

  (173) 0x42a2b1 VMULPD	%ZMM13,%ZMM7,%ZMM13

  (173) 0x42a2b7 VMULPD	%ZMM20,%ZMM2,%ZMM17

  (173) 0x42a2bd VMINPD	%ZMM12,%ZMM18,%ZMM3

  (173) 0x42a2c3 VMINPD	%ZMM5,%ZMM17,%ZMM2

  (173) 0x42a2c9 VFMADD231PD	%ZMM3,%ZMM11,%ZMM0{%K5}

  (173) 0x42a2cf VMULPD	0x400(%RSP),%ZMM0,%ZMM0

  (173) 0x42a2d7 MOV	0x208(%RSP),%RDX

  (173) 0x42a2df VFMADD231PD	%ZMM2,%ZMM13,%ZMM4{%K6}

  (173) 0x42a2e5 VMULPD	0x3c0(%RSP),%ZMM4,%ZMM4

  (173) 0x42a2ed VMOVUPD	%ZMM0,(%RDX,%R10,1)

  (173) 0x42a2f4 VMOVUPD	%ZMM4,0x40(%RDX,%R10,1)

  (173) 0x42a2fc MOV	0x258(%RSP),%RDX

  (173) 0x42a304 VMOVSD	(%R9),%XMM11

  (173) 0x42a309 MOV	0x478(%RSP),%R9

  (173) 0x42a311 VMOVSD	(%RDX),%XMM10

  (173) 0x42a315 VMOVQ	%XMM31,%RDX

  (173) 0x42a31b VMOVHPD	(%RBX,%R9,8),%XMM11,%XMM12

  (173) 0x42a321 VMOVHPD	(%RBX,%RDX,8),%XMM10,%XMM1

  (173) 0x42a326 MOV	0x260(%RSP),%RDX

  (173) 0x42a32e VMOVSD	(%R8),%XMM10

  (173) 0x42a333 MOV	0x248(%RSP),%R8

  (173) 0x42a33b VMOVSD	(%RDX),%XMM5

  (173) 0x42a33f MOV	0x268(%RSP),%RDX

  (173) 0x42a347 VMOVHPD	(%RBX,%RAX,8),%XMM5,%XMM2

  (173) 0x42a34c VMOVSD	(%RDI),%XMM5

  (173) 0x42a350 MOV	0x450(%RSP),%RDI

  (173) 0x42a358 VINSERTF128	$0x1,%XMM1,%YMM2,%YMM7

  (173) 0x42a35e VMOVHPD	(%RBX,%R8,8),%XMM10,%XMM1

  (173) 0x42a364 VMOVHPD	(%RBX,%R13,8),%XMM5,%XMM2

  (173) 0x42a36a VMOVSD	(%RDX),%XMM13

  (173) 0x42a36e MOV	0x2d0(%RSP),%RDX

  (173) 0x42a376 VMOVHPD	(%RBX,%RDX,8),%XMM13,%XMM8

  (173) 0x42a37b MOV	0x250(%RSP),%RDX

  (173) 0x42a383 VMOVSD	(%RSI),%XMM13

  (173) 0x42a387 VMOVQ	%XMM31,%RSI

  (173) 0x42a38d VINSERTF128	$0x1,%XMM8,%YMM12,%YMM3

  (173) 0x42a393 VMOVSD	(%RCX),%XMM12

  (173) 0x42a397 MOV	0x440(%RSP),%RCX

  (173) 0x42a39f VINSERTF64X4	$0x1,%YMM7,%ZMM3,%ZMM11

  (173) 0x42a3a6 VMOVHPD	(%RBX,%R11,8),%XMM12,%XMM3

  (173) 0x42a3ac VINSERTF128	$0x1,%XMM1,%YMM2,%YMM7

  (173) 0x42a3b2 VMOVHPD	(%RBX,%RDX,8),%XMM13,%XMM8

  (173) 0x42a3b7 VMOVSD	(%RCX),%XMM1

  (173) 0x42a3bb VMOVHPD	(%R15,%RSI,8),%XMM1,%XMM5

  (173) 0x42a3c1 VMOVSD	(%RDI),%XMM2

  (173) 0x42a3c5 MOV	0x468(%RSP),%RSI

  (173) 0x42a3cd MOV	0x280(%RSP),%RCX

  (173) 0x42a3d5 VINSERTF128	$0x1,%XMM8,%YMM3,%YMM10

  (173) 0x42a3db MOV	%R8,%RDI

  (173) 0x42a3de VINSERTF64X4	$0x1,%YMM7,%ZMM10,%ZMM10

  (173) 0x42a3e5 VMOVHPD	(%R15,%RAX,8),%XMM2,%XMM7

  (173) 0x42a3eb VINSERTF128	$0x1,%XMM5,%YMM7,%YMM8

  (173) 0x42a3f1 VMOVSD	(%RSI),%XMM3

  (173) 0x42a3f5 MOV	%R9,%RSI

  (173) 0x42a3f8 VMOVHPD	(%R15,%R9,8),%XMM3,%XMM1

  (173) 0x42a3fe MOV	0x270(%RSP),%R9

  (173) 0x42a406 VMOVSD	(%RCX),%XMM13

  (173) 0x42a40a MOV	0x2d0(%RSP),%RCX

  (173) 0x42a412 VMOVSD	(%R9),%XMM2

  (173) 0x42a417 VMOVHPD	(%R15,%R8,8),%XMM2,%XMM7

  (173) 0x42a41d MOV	0x278(%RSP),%R8

  (173) 0x42a425 MOV	0x3a0(%RSP),%R9

  (173) 0x42a42d VMOVHPD	(%R15,%RCX,8),%XMM13,%XMM12

  (173) 0x42a433 VINSERTF128	$0x1,%XMM12,%YMM1,%YMM5

  (173) 0x42a439 VINSERTF64X4	$0x1,%YMM8,%ZMM5,%ZMM13

  (173) 0x42a440 VMULPD	%ZMM13,%ZMM11,%ZMM11

  (173) 0x42a446 VMOVSD	(%R8),%XMM8

  (173) 0x42a44b MOV	0x3b0(%RSP),%R8

  (173) 0x42a453 VMOVSD	(%R9),%XMM1

  (173) 0x42a458 MOV	0x448(%RSP),%R9

  (173) 0x42a460 VMOVHPD	(%R15,%R13,8),%XMM8,%XMM12

  (173) 0x42a466 VMOVHPD	(%R15,%RDX,8),%XMM1,%XMM5

  (173) 0x42a46c VINSERTF128	$0x1,%XMM7,%YMM12,%YMM3

  (173) 0x42a472 VMOVSD	(%R8),%XMM2

  (173) 0x42a477 VMOVHPD	(%R15,%R11,8),%XMM2,%XMM7

  (173) 0x42a47d VMOVQ	%XMM31,%R8

  (173) 0x42a483 VINSERTF128	$0x1,%XMM5,%YMM7,%YMM8

  (173) 0x42a489 VINSERTF64X4	$0x1,%YMM3,%ZMM8,%ZMM12

  (173) 0x42a490 VMOVSD	(%R9,%R12,1),%XMM3

  (173) 0x42a496 MOV	0x458(%RSP),%R9

  (173) 0x42a49e VMOVHPD	(%R12,%R8,8),%XMM3,%XMM5

  (173) 0x42a4a4 VMULPD	%ZMM12,%ZMM10,%ZMM10

  (173) 0x42a4aa VMOVSD	(%R9,%R12,1),%XMM1

  (173) 0x42a4b0 VMOVHPD	(%R12,%RAX,8),%XMM1,%XMM2

  (173) 0x42a4b6 MOV	0x460(%RSP),%RAX

  (173) 0x42a4be VINSERTF128	$0x1,%XMM5,%YMM2,%YMM7

  (173) 0x42a4c4 VMOVSD	(%RAX,%R12,1),%XMM8

  (173) 0x42a4ca VMOVHPD	(%R12,%RCX,8),%XMM8,%XMM3

  (173) 0x42a4d0 MOV	0x470(%RSP),%RCX

  (173) 0x42a4d8 VMOVSD	(%RCX,%R12,1),%XMM5

  (173) 0x42a4de VMOVHPD	(%R12,%RSI,8),%XMM5,%XMM1

  (173) 0x42a4e4 MOV	0x390(%RSP),%RSI

  (173) 0x42a4ec MOV	0x238(%RSP),%R8

  (173) 0x42a4f4 VINSERTF128	$0x1,%XMM3,%YMM1,%YMM2

  (173) 0x42a4fa MOV	0x380(%RSP),%R9

  (173) 0x42a502 MOV	0x2c0(%RSP),%RAX

  (173) 0x42a50a MOV	0x388(%RSP),%RCX

  (173) 0x42a512 VINSERTF64X4	$0x1,%YMM7,%ZMM2,%ZMM5

  (173) 0x42a519 VMOVSD	(%RSI,%R12,1),%XMM7

  (173) 0x42a51f VMOVHPD	(%R12,%RDI,8),%XMM7,%XMM8

  (173) 0x42a525 MOV	0x398(%RSP),%RDI

  (173) 0x42a52d MOV	0x240(%RSP),%RSI

  (173) 0x42a535 VMOVSD	(%RDI,%R12,1),%XMM3

  (173) 0x42a53b VMOVHPD	(%R12,%R13,8),%XMM3,%XMM1

  (173) 0x42a541 MOV	0x3a8(%RSP),%R13

  (173) 0x42a549 MOV	0x340(%RSP),%RDI

  (173) 0x42a551 VINSERTF128	$0x1,%XMM8,%YMM1,%YMM7

  (173) 0x42a557 VMOVSD	(%R13,%R12,1),%XMM2

  (173) 0x42a55e VMOVHPD	(%R12,%RDX,8),%XMM2,%XMM8

  (173) 0x42a564 MOV	0x3b8(%RSP),%RDX

  (173) 0x42a56c MOV	0x2c8(%RSP),%R13

  (173) 0x42a574 VMOVSD	(%RDX,%R12,1),%XMM3

  (173) 0x42a57a VMOVHPD	(%R12,%R11,8),%XMM3,%XMM1

  (173) 0x42a580 MOV	0x338(%RSP),%R11

  (173) 0x42a588 MOV	0x318(%RSP),%RDX

  (173) 0x42a590 VINSERTF128	$0x1,%XMM8,%YMM1,%YMM2

  (173) 0x42a596 VMOVSD	(%R9,%R12,1),%XMM1

  (173) 0x42a59c VINSERTF64X4	$0x1,%YMM7,%ZMM2,%ZMM3

  (173) 0x42a5a3 VMOVHPD	(%R12,%RAX,8),%XMM1,%XMM2

  (173) 0x42a5a9 VMOVSD	(%RDI,%R12,1),%XMM1

  (173) 0x42a5af VMOVSD	(%R11,%R12,1),%XMM7

  (173) 0x42a5b5 MOV	0x228(%RSP),%R11

  (173) 0x42a5bd VMOVHPD	(%R12,%R8,8),%XMM7,%XMM8

  (173) 0x42a5c3 VMOVSD	(%RCX,%R12,1),%XMM7

  (173) 0x42a5c9 VINSERTF128	$0x1,%XMM8,%YMM2,%YMM8

  (173) 0x42a5cf VMOVHPD	(%R12,%RSI,8),%XMM7,%XMM2

  (173) 0x42a5d5 VMOVHPD	(%R12,%R13,8),%XMM1,%XMM7

  (173) 0x42a5db VINSERTF128	$0x1,%XMM2,%YMM7,%YMM2

  (173) 0x42a5e1 VMOVSD	(%RDX,%R12,1),%XMM7

  (173) 0x42a5e7 VINSERTF64X4	$0x1,%YMM8,%ZMM2,%ZMM8

  (173) 0x42a5ee VSUBPD	%ZMM8,%ZMM5,%ZMM1

  (173) 0x42a5f4 VMOVHPD	(%R12,%R11,8),%XMM7,%XMM2

  (173) 0x42a5fa MOV	0x320(%RSP),%R8

  (173) 0x42a602 MOV	0x2b0(%RSP),%R9

  (173) 0x42a60a MOV	0x328(%RSP),%RAX

  (173) 0x42a612 MOV	0x230(%RSP),%RCX

  (173) 0x42a61a MOV	0x330(%RSP),%RSI

  (173) 0x42a622 MOV	0x2b8(%RSP),%RDI

  (173) 0x42a62a MOV	0x2f8(%RSP),%R13

  (173) 0x42a632 MOV	0x220(%RSP),%RDX

  (173) 0x42a63a MOV	0x300(%RSP),%R11

  (173) 0x42a642 VMOVSD	(%R8,%R12,1),%XMM8

  (173) 0x42a648 MOV	0x2a0(%RSP),%R8

  (173) 0x42a650 VMOVHPD	(%R12,%R9,8),%XMM8,%XMM7

  (173) 0x42a656 MOV	0x308(%RSP),%R9

  (173) 0x42a65e VINSERTF128	$0x1,%XMM2,%YMM7,%YMM7

  (173) 0x42a664 VMOVSD	(%RAX,%R12,1),%XMM2

  (173) 0x42a66a VMOVHPD	(%R12,%RCX,8),%XMM2,%XMM8

  (173) 0x42a670 MOV	0x310(%RSP),%RCX

  (173) 0x42a678 VMOVSD	(%RSI,%R12,1),%XMM2

  (173) 0x42a67e MOV	0x2a8(%RSP),%RSI

  (173) 0x42a686 VMOVHPD	(%R12,%RDI,8),%XMM2,%XMM2

  (173) 0x42a68c VMOVQ	%XMM28,%RAX

  (173) 0x42a692 VINSERTF128	$0x1,%XMM8,%YMM2,%YMM8

  (173) 0x42a698 MOV	0x2d8(%RSP),%RDI

  (173) 0x42a6a0 VINSERTF64X4	$0x1,%YMM7,%ZMM8,%ZMM7

  (173) 0x42a6a7 VMOVSD	(%R13,%R12,1),%XMM8

  (173) 0x42a6ae VMOVQ	%XMM26,%R13

  (173) 0x42a6b4 VSUBPD	%ZMM7,%ZMM3,%ZMM2

  (173) 0x42a6ba VMOVHPD	(%R12,%RDX,8),%XMM8,%XMM7

  (173) 0x42a6c0 VMOVSD	(%R11,%R12,1),%XMM8

  (173) 0x42a6c6 MOV	0x2e0(%RSP),%RDX

  (173) 0x42a6ce VMOVHPD	(%R12,%R8,8),%XMM8,%XMM8

  (173) 0x42a6d4 VINSERTF128	$0x1,%XMM7,%YMM8,%YMM8

  (173) 0x42a6da VMOVSD	(%R9,%R12,1),%XMM7

  (173) 0x42a6e0 VMOVHPD	(%R12,%RAX,8),%XMM7,%XMM7

  (173) 0x42a6e6 VMOVQ	%XMM25,%R9

  (173) 0x42a6ec VMOVAPD	%XMM7,%XMM31

  (173) 0x42a6f2 VMOVSD	(%RCX,%R12,1),%XMM7

  (173) 0x42a6f8 VMOVHPD	(%R12,%RSI,8),%XMM7,%XMM7

  (173) 0x42a6fe VINSERTF64X2	$0x1,%XMM31,%YMM7,%YMM7

  (173) 0x42a705 VINSERTF64X4	$0x1,%YMM8,%ZMM7,%ZMM8

  (173) 0x42a70c VSUBPD	%ZMM5,%ZMM8,%ZMM7

  (173) 0x42a712 VMOVSD	(%RDI,%R12,1),%XMM8

  (173) 0x42a718 VMOVHPD	(%R12,%R13,8),%XMM8,%XMM8

  (173) 0x42a71e VMOVSD	(%RDX,%R12,1),%XMM26

  (173) 0x42a725 MOV	0x290(%RSP),%R11

  (173) 0x42a72d MOV	0x2e8(%RSP),%R8

  (173) 0x42a735 MOV	0x2f0(%RSP),%RAX

  (173) 0x42a73d MOV	0x298(%RSP),%RCX

  (173) 0x42a745 MOV	0x200(%RSP),%RSI

  (173) 0x42a74d VCMPPD	$0x2,%ZMM22,%ZMM7,%K7

  (173) 0x42a754 VMOVSD	(%R12,%R11,8),%XMM28

  (173) 0x42a75b VUNPCKLPD	%XMM28,%XMM26,%XMM16

  (173) 0x42a761 VMULPD	%ZMM7,%ZMM1,%ZMM26

  (173) 0x42a767 VANDPD	%ZMM19,%ZMM7,%ZMM7

  (173) 0x42a76d VINSERTF64X2	$0x1,%XMM8,%YMM16,%YMM18

  (173) 0x42a774 VMOVSD	(%R8,%R12,1),%XMM8

  (173) 0x42a77a VMOVHPD	(%R12,%R9,8),%XMM8,%XMM8

  (173) 0x42a780 VMOVAPD	%XMM8,%XMM25

  (173) 0x42a786 VMOVSD	(%RAX,%R12,1),%XMM8

  (173) 0x42a78c VMOVHPD	(%R12,%RCX,8),%XMM8,%XMM8

  (173) 0x42a792 VANDPD	%ZMM19,%ZMM1,%ZMM1

  (173) 0x42a798 VINSERTF64X2	$0x1,%XMM25,%YMM8,%YMM8

  (173) 0x42a79f VMULPD	%ZMM7,%ZMM9,%ZMM9

  (173) 0x42a7a5 VBLENDMPD	%ZMM21,%ZMM24,%ZMM17{%K7}

  (173) 0x42a7ab VCMPPD	$0xe,%ZMM22,%ZMM26,%K1

  (173) 0x42a7b2 VINSERTF64X4	$0x1,%YMM18,%ZMM8,%ZMM8

  (173) 0x42a7b9 VSUBPD	%ZMM3,%ZMM8,%ZMM8

  (173) 0x42a7bf VFMADD231PD	%ZMM1,%ZMM14,%ZMM9

  (173) 0x42a7c5 VMINPD	%ZMM7,%ZMM1,%ZMM1

  (173) 0x42a7cb VMULPD	%ZMM8,%ZMM2,%ZMM28

  (173) 0x42a7d1 VCMPPD	$0x2,%ZMM22,%ZMM8,%K2

  (173) 0x42a7d8 VANDPD	%ZMM19,%ZMM8,%ZMM8

  (173) 0x42a7de VANDPD	%ZMM19,%ZMM2,%ZMM2

  (173) 0x42a7e4 VMULPD	%ZMM8,%ZMM15,%ZMM15

  (173) 0x42a7ea VCMPPD	$0xe,%ZMM22,%ZMM28,%K3

  (173) 0x42a7f1 VFMADD132PD	%ZMM2,%ZMM15,%ZMM6

  (173) 0x42a7f7 VMULPD	%ZMM20,%ZMM9,%ZMM15

  (173) 0x42a7fd VBLENDMPD	%ZMM21,%ZMM24,%ZMM31{%K2}

  (173) 0x42a803 VMINPD	%ZMM1,%ZMM15,%ZMM7

  (173) 0x42a809 VMULPD	%ZMM20,%ZMM6,%ZMM14

  (173) 0x42a80f VMINPD	%ZMM8,%ZMM2,%ZMM6

  (173) 0x42a815 VMULPD	%ZMM17,%ZMM7,%ZMM9

  (173) 0x42a81b VMINPD	%ZMM6,%ZMM14,%ZMM2

  (173) 0x42a821 VANDPD	%ZMM19,%ZMM0,%ZMM14

  (173) 0x42a827 VDIVPD	%ZMM11,%ZMM14,%ZMM13

  (173) 0x42a82d VMULPD	%ZMM31,%ZMM2,%ZMM8

  (173) 0x42a833 VANDPD	%ZMM19,%ZMM4,%ZMM2

  (173) 0x42a839 VDIVPD	%ZMM10,%ZMM2,%ZMM12

  (173) 0x42a83f VSUBPD	%ZMM13,%ZMM24,%ZMM6

  (173) 0x42a845 VFMADD231PD	%ZMM6,%ZMM9,%ZMM5{%K1}

  (173) 0x42a84b VMULPD	%ZMM0,%ZMM5,%ZMM0

  (173) 0x42a851 VSUBPD	%ZMM12,%ZMM24,%ZMM15

  (173) 0x42a857 VMOVUPD	%ZMM0,(%RSI,%R10,1)

  (173) 0x42a85e VFMADD231PD	%ZMM15,%ZMM8,%ZMM3{%K3}

  (173) 0x42a864 VMULPD	%ZMM4,%ZMM3,%ZMM4

  (173) 0x42a86a VMOVUPD	%ZMM4,0x40(%RSI,%R10,1)

  (173) 0x42a872 SUB	$-0x80,%R10

  (173) 0x42a876 CMP	%R10,0x218(%RSP)

  (173) 0x42a87e JNE	429820

0x42a884 MOV	0xe8(%RSP),%R15D

0x42a88c VMOVQ	0xd8(%RSP),%XMM5

0x42a895 VMOVQ	0xd0(%RSP),%XMM8

0x42a89e VMOVQ	0xc8(%RSP),%XMM9

0x42a8a7 VMOVQ	0xc0(%RSP),%XMM11

0x42a8b0 MOV	0xe4(%RSP),%R8D

0x42a8b8 VMOVQ	0xb0(%RSP),%XMM12

0x42a8c1 VMOVQ	0x90(%RSP),%XMM16

0x42a8c9 MOV	0xb8(%RSP),%R11

0x42a8d1 VMOVQ	0x78(%RSP),%XMM1

0x42a8d7 VMOVQ	0x70(%RSP),%XMM14

0x42a8dd MOV	0xa8(%RSP),%RSI

0x42a8e5 VMOVQ	0x68(%RSP),%XMM13

0x42a8eb VMOVQ	0x60(%RSP),%XMM2

0x42a8f1 MOV	0xa0(%RSP),%RCX

0x42a8f9 MOV	%R15D,%EBX

0x42a8fc MOV	0x98(%RSP),%R10

0x42a904 MOV	0x88(%RSP),%RDX

0x42a90c MOV	0x80(%RSP),%RAX

0x42a914 AND	$-0x10,%EBX

0x42a917 ADD	%EBX,0xfc(%RSP)

0x42a91e ADD	%EBX,0xf8(%RSP)

0x42a925 AND	$0xf,%R15D

0x42a929 JE	42aba0

0x42a92f VMOVQ	%XMM5,%R13

0x42a934 VMOVQ	%XMM1,%R15

0x42a939 MOVSXD	0xf8(%RSP),%RDI

0x42a941 VXORPD	%XMM6,%XMM6,%XMM6

0x42a945 LEA	(%R13,%R11,8),%R9

0x42a94a VMOVQ	%XMM14,%R11

0x42a94f VMOVQ	%XMM13,%R13

0x42a954 VMOVSD	0x34d84(%RIP),%XMM5

0x42a95c LEA	(%R15,%R11,8),%RBX

0x42a960 MOV	0xfc(%RSP),%R11D

0x42a968 VMOVQ	%R9,%XMM19

0x42a96e VMOVQ	%XMM2,%R9

0x42a973 LEA	(%R13,%R9,8),%R15

0x42a978 VMOVQ	%RBX,%XMM24

0x42a97e VMOVQ	%R10,%XMM10

0x42a983 VMOVQ	%R15,%XMM23

0x42a989 VMOVDQA64	%XMM24,%XMM13

0x42a98f VMOVQ	%XMM19,%R15

0x42a995 SUB	%EDI,%R11D

0x42a998 MOV	%R11D,0x478(%RSP)

0x42a9a0 JMP	42ab48

  (172) 0x42a9b0 LEA	-0x1(%RDI),%R11

  (172) 0x42a9b4 LEA	-0x2(%RDI),%R13D

  (172) 0x42a9b8 MOV	%RDI,%R10

  (172) 0x42a9bb MOVSXD	%R13D,%RBX

  (172) 0x42a9be MOV	%R11,%R12

  (172) 0x42a9c1 VMOVQ	%XMM16,%R9

  (172) 0x42a9c7 VMOVQ	%XMM10,%R13

  (172) 0x42a9cc VMOVSD	(%R14,%RDI,8),%XMM7

  (172) 0x42a9d2 VDIVSD	(%R14,%R12,8),%XMM7,%XMM15

  (172) 0x42a9d8 ADD	%R11,%R9

  (172) 0x42a9db LEA	(%RCX,%R11,1),%R12

  (172) 0x42a9df VANDPD	%XMM30,%XMM1,%XMM3

  (172) 0x42a9e5 VMOVSD	0x35ceb(%RIP),%XMM14

  (172) 0x42a9ed LEA	(%R13,%R9,8),%R9

  (172) 0x42a9f2 LEA	(%RSI,%R12,8),%R12

  (172) 0x42a9f6 LEA	(%RCX,%RBX,1),%R13

  (172) 0x42a9fa VDIVSD	(%R9),%XMM3,%XMM3

  (172) 0x42a9ff VMOVSD	(%R12),%XMM21

  (172) 0x42aa06 VADDSD	%XMM29,%XMM3,%XMM0

  (172) 0x42aa0c VMULSD	%XMM0,%XMM15,%XMM4

  (172) 0x42aa10 VSUBSD	(%RSI,%R13,8),%XMM21,%XMM15

  (172) 0x42aa17 LEA	(%RCX,%R10,1),%R13

  (172) 0x42aa1b VSUBSD	%XMM3,%XMM14,%XMM2

  (172) 0x42aa1f VMOVSD	(%RSI,%R13,8),%XMM7

  (172) 0x42aa25 VSUBSD	%XMM21,%XMM7,%XMM0

  (172) 0x42aa2b VCMPSD	$0x6,%XMM6,%XMM0,%XMM14

  (172) 0x42aa30 VMOVSD	%XMM29,%XMM29,%XMM7

  (172) 0x42aa36 VBLENDVPD	%XMM14,%XMM7,%XMM5,%XMM14

  (172) 0x42aa3c VMULSD	%XMM0,%XMM15,%XMM7

  (172) 0x42aa40 VCOMISD	%XMM6,%XMM7

  (172) 0x42aa44 VMOVSD	%XMM14,%XMM14,%XMM20

  (172) 0x42aa4a JBE	42aa82

  (172) 0x42aa4c VANDPD	%XMM30,%XMM0,%XMM0

  (172) 0x42aa52 VANDPD	%XMM30,%XMM15,%XMM15

  (172) 0x42aa58 VSUBSD	%XMM3,%XMM29,%XMM3

  (172) 0x42aa5e VMULSD	%XMM2,%XMM0,%XMM14

  (172) 0x42aa62 VFMADD231SD	%XMM4,%XMM15,%XMM14

  (172) 0x42aa67 VMINSD	%XMM0,%XMM15,%XMM15

  (172) 0x42aa6b VMULSD	0x35ccd(%RIP),%XMM14,%XMM7

  (172) 0x42aa73 VMINSD	%XMM15,%XMM7,%XMM0

  (172) 0x42aa78 VMULSD	%XMM3,%XMM0,%XMM14

  (172) 0x42aa7c VFMADD231SD	%XMM14,%XMM20,%XMM21

  (172) 0x42aa82 ADD	%RAX,%R11

  (172) 0x42aa85 VMOVQ	%XMM13,%R13

  (172) 0x42aa8a LEA	(%RAX,%R10,1),%R10

  (172) 0x42aa8e ADD	%RAX,%RBX

  (172) 0x42aa91 VMULSD	%XMM21,%XMM1,%XMM27

  (172) 0x42aa97 VMOVSD	%XMM27,(%R13,%RDI,8)

  (172) 0x42aa9f VMOVSD	(%RDX,%R11,8),%XMM1

  (172) 0x42aaa5 VMOVSD	(%RDX,%R10,8),%XMM7

  (172) 0x42aaab VSUBSD	%XMM1,%XMM7,%XMM0

  (172) 0x42aaaf VCMPSD	$0x6,%XMM6,%XMM0,%XMM15

  (172) 0x42aab4 VSUBSD	(%RDX,%RBX,8),%XMM1,%XMM14

  (172) 0x42aab9 VMOVSD	%XMM29,%XMM29,%XMM3

  (172) 0x42aabf VMOVSD	(%R12),%XMM22

  (172) 0x42aac6 VBLENDVPD	%XMM15,%XMM3,%XMM5,%XMM7

  (172) 0x42aacc VMOVSD	(%R9),%XMM18

  (172) 0x42aad2 VMULSD	%XMM0,%XMM14,%XMM15

  (172) 0x42aad6 VCOMISD	%XMM6,%XMM15

  (172) 0x42aada JBE	42ab23

  (172) 0x42aadc VANDPD	%XMM30,%XMM0,%XMM0

  (172) 0x42aae2 VANDPD	%XMM30,%XMM14,%XMM14

  (172) 0x42aae8 VMULSD	%XMM18,%XMM22,%XMM25

  (172) 0x42aaee VMULSD	%XMM2,%XMM0,%XMM2

  (172) 0x42aaf2 VFMADD231SD	%XMM4,%XMM14,%XMM2

  (172) 0x42aaf7 VANDPD	%XMM30,%XMM27,%XMM4

  (172) 0x42aafd VMULSD	0x35c3b(%RIP),%XMM2,%XMM2

  (172) 0x42ab05 VDIVSD	%XMM25,%XMM4,%XMM3

  (172) 0x42ab0b VMINSD	%XMM0,%XMM14,%XMM14

  (172) 0x42ab0f VSUBSD	%XMM3,%XMM29,%XMM15

  (172) 0x42ab15 VMINSD	%XMM14,%XMM2,%XMM0

  (172) 0x42ab1a VMULSD	%XMM0,%XMM15,%XMM4

  (172) 0x42ab1e VFMADD231SD	%XMM4,%XMM7,%XMM1

  (172) 0x42ab23 MOV	0x478(%RSP),%R11D

  (172) 0x42ab2b VMOVQ	%XMM23,%RBX

  (172) 0x42ab31 VMULSD	%XMM27,%XMM1,%XMM1

  (172) 0x42ab37 VMOVSD	%XMM1,(%RBX,%RDI,8)

  (172) 0x42ab3c INC	%RDI

  (172) 0x42ab3f LEA	(%R11,%RDI,1),%R9D

  (172) 0x42ab43 CMP	%R8D,%R9D

  (172) 0x42ab46 JAE	42aba0

  (172) 0x42ab48 VMOVSD	(%R15,%RDI,8),%XMM1

  (172) 0x42ab4e VCOMISD	%XMM6,%XMM1

  (172) 0x42ab52 JA	42a9b0

  (172) 0x42ab58 MOV	0xec(%RSP),%R12D

  (172) 0x42ab60 LEA	0x1(%RDI),%R10D

  (172) 0x42ab64 MOV	%RDI,%R11

  (172) 0x42ab67 CMP	%R12D,%R10D

  (172) 0x42ab6a CMOVG	%R12D,%R10D

  (172) 0x42ab6e MOVSXD	%R10D,%R12

  (172) 0x42ab71 LEA	-0x1(%RDI),%R10

  (172) 0x42ab75 MOV	%R12,%RBX

  (172) 0x42ab78 JMP	42a9c1

0x42aba0 MOV	%R8D,0xfc(%RSP)

0x42aba8 MOV	0x50(%RSP),%EAX

0x42abac MOV	0x48(%RSP),%ECX

0x42abb0 INCQ	0xf0(%RSP)

0x42abb8 MOV	0xf0(%RSP),%RDX

0x42abc0 SUB	%ECX,%EAX

0x42abc2 ADD	%EDX,%EAX

0x42abc4 CMP	%EAX,0x5c(%RSP)

0x42abc8 JLE	42ab80

0x42abca MOV	0x54(%RSP),%EDI

0x42abce MOV	0xfc(%RSP),%ESI

0x42abd5 MOV	0x58(%RSP),%R8D

0x42abda MOV	0xe0(%RSP),%R15D

0x42abe2 SUB	%ESI,%EDI

0x42abe4 MOV	%R8D,0xf8(%RSP)

0x42abec JMP	4295d0

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 67 - 110

--------------------------------------------------------------------------------

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	1.85
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P5, P6, P7,
Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2
Source	advec_cell.cpp:67-67,advec_cell.cpp:71-72,advec_cell.cpp:77-77,advec_cell.cpp:88-88,advec_cell.cpp:110-110,stl_algobase.h:238-238,context.h:46-46,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	29.67
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	29.67
CQA cycles if fully vectorized	19.27
Front-end cycles	28.33
DIV/SQRT cycles	13.00
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	13.00
P3 cycles	3.00
P4 cycles	29.67
P5 cycles	29.67
P6 cycles	29.67
P7 cycles	0.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	0.50
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	170.00
Nb loads	66.00
Nb stores	32.00
Nb stack references	39.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.85
Bytes prefetched	0.00
Bytes loaded	460.00
Bytes stored	396.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.95
Vectorization ratio load	3.70
Vectorization ratio store	9.38
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.69
Vector-efficiency ratio all	15.70
Vector-efficiency ratio load	14.35
Vector-efficiency ratio store	19.34
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.18

Metric	Value
CQA speedup if no scalar integer	1.85
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P5, P6, P7,
Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2
Source	advec_cell.cpp:67-67,advec_cell.cpp:71-72,advec_cell.cpp:77-77,advec_cell.cpp:88-88,advec_cell.cpp:110-110,stl_algobase.h:238-238,context.h:46-46,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	29.67
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	29.67
CQA cycles if fully vectorized	19.27
Front-end cycles	28.33
DIV/SQRT cycles	13.00
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	13.00
P3 cycles	3.00
P4 cycles	29.67
P5 cycles	29.67
P6 cycles	29.67
P7 cycles	0.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	0.50
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	170.00
Nb loads	66.00
Nb stores	32.00
Nb stack references	39.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.85
Bytes prefetched	0.00
Bytes loaded	460.00
Bytes stored	396.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.95
Vectorization ratio load	3.70
Vectorization ratio store	9.38
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.69
Vector-efficiency ratio all	15.70
Vector-efficiency ratio load	14.35
Vector-efficiency ratio store	19.34
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.18

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2
Source file and lines	advec_cell.cpp:67-110
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:67-110
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:238
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=18
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 18 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.67 to 16.00 cycles (1.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 29.67 to 19.27 cycles (1.54x speedup).

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

3% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences
INC: 1 occurrences
VMOVDQA32: 3 occurrences
VPBROADCASTD: 3 occurrences

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 460 bytes. The binary loop is storing 396 bytes.

General properties

nb instructions	162
nb uops	170
loop length	962
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	10
nb stack references	39

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.33 cycles
front end	28.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	13.00	13.00	13.00	13.00	3.00	29.33	29.33	29.33	0.50	5.50	5.50	0.50	16.00	16.00
cycles	13.00	13.00	13.00	13.00	3.00	29.67	29.67	29.67	0.50	5.50	5.50	0.50	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.33
Dispatch	29.67
Overall L1	29.67

Vectorization ratios

INT

all	6%
load	4%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	7%
load	3%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	15%
load	14%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	14%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 29.67 cycles. At this rate:

16% of peak load performance is reached (15.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (13.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4295d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV 0xfc(%RSP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %R15D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVBE %EDI,%R15D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R15D,0xe8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%RCX,%R15,1),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R8D,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 42aba8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1738>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x38(%RSP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xf0(%RSP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x40(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x30(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%RDX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ 0x10(%R12),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x10(%R13),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV (%R15),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RSI),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R15),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RAX),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R12),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0x10(%RSI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%RDX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVQ %R9,%XMM16	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %XMM11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%R9),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R9),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%RSP),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %R15,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL (%R13),%RDI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %RDI,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
LEA -0x1(%R9),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0xe,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 42a92f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x14bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD 0xf8(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VMOVQ %XMM5,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM16,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPBROADCASTD 0xf8(%RSP),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50
MOV %R10,0x98(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VBROADCASTSD 0x366f5(%RIP),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
VBROADCASTSD 0x36ed3(%RIP),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
VBROADCASTSD 0x37009(%RIP),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
SHR $0x4,%R9D	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R8D,0xe4(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R11,0xb8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RSI,0xa8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVQ %XMM5,0xd8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDX,0x88(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SAL $0x7,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVQ %XMM8,0xd0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VXORPD %XMM22,%XMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R11,%RDI,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,0x218(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $-0x2,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPADDD 0x36fc5(%RIP),%ZMM3,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
LEA (%RBX,%R12,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R14,%RDI,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPBROADCASTD %R9D,%ZMM7	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1
VBROADCASTSD 0x35f8d(%RIP),%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
MOV %R15,0x210(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R10,%R13,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R12,0x288(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VBROADCASTSD 0x36fcf(%RIP),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM9,0xc8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA (%RSI,%RCX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R13,%RDI,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM1,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM11,0xc0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA (%R13,%R12,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVDQA32 %ZMM7,0x180(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM13,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %R12,0x208(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%RDX,%RAX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R13,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMOVQ %XMM12,0xb0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RDI,0x200(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM16,0x90(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPBROADCASTD %EDI,%ZMM6	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1
MOV $0x1,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM1,0x78(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VPBROADCASTD %EDI,%ZMM10	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1
VMOVQ %XMM14,0x70(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM13,0x68(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVDQA32 %ZMM6,0x1c0(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2
VMOVDQA32 %ZMM10,0x140(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2
VMOVQ %XMM2,0x60(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0xe8(%RSP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0xd8(%RSP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0xd0(%RSP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0xc8(%RSP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0xc0(%RSP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xe4(%RSP),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0xb0(%RSP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x90(%RSP),%XMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xb8(%RSP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0x78(%RSP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x70(%RSP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xa8(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0x68(%RSP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x60(%RSP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xa0(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x98(%RSP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x88(%RSP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x80(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
AND $-0x10,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EBX,0xfc(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %EBX,0xf8(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
AND $0xf,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 42aba0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1730>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVQ %XMM5,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM1,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSXD 0xf8(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R13,%R11,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM13,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD 0x34d84(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R11,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0xfc(%RSP),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %R9,%XMM19	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %XMM2,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA (%R13,%R9,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %RBX,%XMM24	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %R10,%XMM10	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %R15,%XMM23	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVDQA64 %XMM24,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM19,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SUB %EDI,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,0x478(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 42ab48 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x16d8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R8D,0xfc(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x50(%RSP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x48(%RSP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INCQ 0xf0(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xf0(%RSP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB %ECX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,0x5c(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 42ab80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1710>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x54(%RSP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xfc(%RSP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x58(%RSP),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe0(%RSP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB %ESI,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8D,0xf8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 4295d0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2
Source file and lines	advec_cell.cpp:67-110
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:67-110
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:238
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=18
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

3% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences
INC: 1 occurrences
VMOVDQA32: 3 occurrences
VPBROADCASTD: 3 occurrences

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 460 bytes. The binary loop is storing 396 bytes.

General properties

nb instructions	162
nb uops	170
loop length	962
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	10
nb stack references	39

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.33 cycles
front end	28.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	13.00	13.00	13.00	13.00	3.00	29.33	29.33	29.33	0.50	5.50	5.50	0.50	16.00	16.00
cycles	13.00	13.00	13.00	13.00	3.00	29.67	29.67	29.67	0.50	5.50	5.50	0.50	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.33
Dispatch	29.67
Overall L1	29.67

Vectorization ratios

INT

all	6%
load	4%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	7%
load	3%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	15%
load	14%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	14%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 29.67 cycles. At this rate:

16% of peak load performance is reached (15.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (13.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4295d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV 0xfc(%RSP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %R15D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVBE %EDI,%R15D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R15D,0xe8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%RCX,%R15,1),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R8D,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 42aba8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1738>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x38(%RSP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xf0(%RSP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x40(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x30(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%RDX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ 0x10(%R12),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x10(%R13),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV (%R15),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RSI),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R15),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x8(%RAX),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%R12),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0x10(%RSI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x10(%RDX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVQ %R9,%XMM16	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %XMM11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%R9),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R9),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe8(%RSP),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %R15,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL (%R13),%RDI	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %RDI,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
LEA -0x1(%R9),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0xe,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 42a92f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x14bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD 0xf8(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VMOVQ %XMM5,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM16,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPBROADCASTD 0xf8(%RSP),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50
MOV %R10,0x98(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VBROADCASTSD 0x366f5(%RIP),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
VBROADCASTSD 0x36ed3(%RIP),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
VBROADCASTSD 0x37009(%RIP),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
SHR $0x4,%R9D	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R8D,0xe4(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R11,0xb8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RSI,0xa8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVQ %XMM5,0xd8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RDX,0x88(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SAL $0x7,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVQ %XMM8,0xd0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VXORPD %XMM22,%XMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R11,%RDI,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,0x218(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $-0x2,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPADDD 0x36fc5(%RIP),%ZMM3,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
LEA (%RBX,%R12,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R14,%RDI,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPBROADCASTD %R9D,%ZMM7	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1
VBROADCASTSD 0x35f8d(%RIP),%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
MOV %R15,0x210(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%R10,%R13,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R12,0x288(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VBROADCASTSD 0x36fcf(%RIP),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM9,0xc8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA (%RSI,%RCX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R13,%RDI,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM1,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM11,0xc0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA (%R13,%R12,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVDQA32 %ZMM7,0x180(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM13,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV %R12,0x208(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
LEA (%RDX,%RAX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R13,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMOVQ %XMM12,0xb0(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RDI,0x200(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM16,0x90(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPBROADCASTD %EDI,%ZMM6	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1
MOV $0x1,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM1,0x78(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VPBROADCASTD %EDI,%ZMM10	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1
VMOVQ %XMM14,0x70(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM13,0x68(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVDQA32 %ZMM6,0x1c0(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2
VMOVDQA32 %ZMM10,0x140(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2
VMOVQ %XMM2,0x60(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0xe8(%RSP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0xd8(%RSP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0xd0(%RSP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0xc8(%RSP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0xc0(%RSP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xe4(%RSP),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0xb0(%RSP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x90(%RSP),%XMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xb8(%RSP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0x78(%RSP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x70(%RSP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xa8(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ 0x68(%RSP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ 0x60(%RSP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xa0(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x98(%RSP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x88(%RSP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x80(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
AND $-0x10,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EBX,0xfc(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %EBX,0xf8(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
AND $0xf,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 42aba0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1730>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVQ %XMM5,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM1,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSXD 0xf8(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R13,%R11,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM13,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD 0x34d84(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R15,%R11,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0xfc(%RSP),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %R9,%XMM19	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %XMM2,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA (%R13,%R9,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %RBX,%XMM24	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %R10,%XMM10	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVQ %R15,%XMM23	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
VMOVDQA64 %XMM24,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVQ %XMM19,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SUB %EDI,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,0x478(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 42ab48 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x16d8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R8D,0xfc(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x50(%RSP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x48(%RSP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INCQ 0xf0(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0xf0(%RSP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB %ECX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,0x5c(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 42ab80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1710>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x54(%RSP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xfc(%RSP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x58(%RSP),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xe0(%RSP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB %ESI,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8D,0xf8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 4295d0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	0.5	0.01	1	0	1	0	0.06	0.01	0.04	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.03	0.01
2x2	4	1	2	2	0.03	0.01
2x4	8	1	4	4	0.02	0.01
2x8	16	0.5	4	8	0.01	0.01
2x16	32	1	1	16	0.01	0.01
2x32	64	1	1	32	0.02	0.01
2x64	128	0.06	4	64	0.02	0.01
2x96	190	0.04	4	96	0.02	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency