OV - - Loop 197

	Loop Id: 197	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage: 0.01%

0x4306f0 CMP	%ECX,%ESI

0x4306f2 CMOVA	%ECX,%ESI

0x4306f5 LEA	(%R13,%RSI,1),%R15D

0x4306fa MOV	%R15D,-0x34(%RBP)

0x4306fe CMP	%R15D,%R13D

0x430701 JAE	4308f0

0x430707 VMOVQ	%XMM13,%R10

0x43070c LEA	0x1(%RDX),%EAX

0x43070f LEA	-0x1(%RSI),%ESI

0x430712 MOVSXD	%EDX,%RDX

0x430715 VMOVQ	%XMM8,%RCX

0x43071a MOV	(%R10),%R11

0x43071d LEA	0x2(%RDX,%RSI,1),%R8

0x430722 VMOVQ	%XMM11,%RDX

0x430727 MOV	0x10(%RCX),%R9

0x43072b MOV	(%RCX),%R15

0x43072e MOV	(%RDX),%RCX

0x430731 VMOVQ	%XMM10,%R13

0x430736 MOV	0x10(%R10),%RBX

0x43073a MOV	0x10(%R13),%R12

0x43073e MOV	0x10(%RDX),%R10

0x430742 VMOVQ	%XMM6,%R14

0x430747 MOV	(%R13),%R13

0x43074b MOV	%RDI,-0x40(%RBP)

0x43074f MOV	0x8(%R14),%R14

0x430753 CLTQ

0x430755 VXORPD	%XMM7,%XMM7,%XMM7

0x430759 VMOVDDUP	0x2f64f(%RIP),%XMM14

0x430761 IMUL	%RDI,%R11

0x430765 IMUL	%RDI,%RCX

0x430769 IMUL	%RDI,%R15

0x43076d LEA	(%RBX,%R11,8),%RSI

0x430771 IMUL	%RDI,%R13

0x430775 MOV	%R9,%RBX

0x430778 LEA	(%R10,%RCX,8),%R11

0x43077c MOV	%RSI,%RDI

0x43077f JMP	430863

  (198) 0x430790 LEA	-0x2(%RAX),%EDX

  (198) 0x430793 MOV	%RAX,%R10

  (198) 0x430796 MOVSXD	%EDX,%R9

  (198) 0x430799 MOVSXD	%EDX,%RDX

  (198) 0x43079c LEA	(%R15,%RCX,1),%RSI

  (198) 0x4307a0 LEA	(%R13,%R10,1),%R10

  (198) 0x4307a5 ADD	%R13,%RCX

  (198) 0x4307a8 ADD	%R13,%RDX

  (198) 0x4307ab VMOVSD	(%R12,%RCX,8),%XMM0

  (198) 0x4307b1 VMOVSD	(%R12,%R10,8),%XMM1

  (198) 0x4307b7 VMOVSD	(%RBX,%RSI,8),%XMM12

  (198) 0x4307bc VSUBSD	(%R12,%RDX,8),%XMM0,%XMM2

  (198) 0x4307c2 VSUBSD	%XMM0,%XMM1,%XMM1

  (198) 0x4307c6 VMOVSD	-0x8(%R14,%RAX,8),%XMM3

  (198) 0x4307cd VMULSD	%XMM2,%XMM1,%XMM5

  (198) 0x4307d1 VCOMISD	%XMM7,%XMM5

  (198) 0x4307d5 JBE	430850

  (198) 0x4307d7 VCOMISD	%XMM1,%XMM7

  (198) 0x4307db JAE	4308a0

  (198) 0x4307e1 VMOVSD	%XMM15,%XMM15,%XMM22

  (198) 0x4307e7 VMOVSD	%XMM15,%XMM15,%XMM23

  (198) 0x4307ed VANDPD	%XMM17,%XMM4,%XMM24

  (198) 0x4307f3 VUNPCKLPD	%XMM2,%XMM1,%XMM2

  (198) 0x4307f7 VMOVHPD	(%R14,%R9,8),%XMM3,%XMM5

  (198) 0x4307fd VMULSD	%XMM16,%XMM3,%XMM3

  (198) 0x430803 VDIVSD	%XMM12,%XMM24,%XMM18

  (198) 0x430809 VMOVDDUP	%XMM18,%XMM12

  (198) 0x43080f VADDSUBPD	%XMM12,%XMM9,%XMM1

  (198) 0x430814 VANDPD	%XMM14,%XMM2,%XMM2

  (198) 0x430819 VSUBSD	%XMM18,%XMM22,%XMM19

  (198) 0x43081f VMULSD	%XMM23,%XMM19,%XMM26

  (198) 0x430825 VMULPD	%XMM2,%XMM1,%XMM12

  (198) 0x430829 VDIVPD	%XMM5,%XMM12,%XMM1

  (198) 0x43082d VUNPCKHPD	%XMM1,%XMM1,%XMM25

  (198) 0x430833 VADDPD	%XMM1,%XMM25,%XMM12

  (198) 0x430839 VUNPCKHPD	%XMM2,%XMM2,%XMM1

  (198) 0x43083d VMINSD	%XMM2,%XMM1,%XMM2

  (198) 0x430841 VMULSD	%XMM12,%XMM3,%XMM5

  (198) 0x430846 VMINSD	%XMM2,%XMM5,%XMM12

  (198) 0x43084a VFMADD231SD	%XMM26,%XMM12,%XMM0

  (198) 0x430850 VMULSD	%XMM4,%XMM0,%XMM4

  (198) 0x430854 VMOVSD	%XMM4,-0x8(%R11,%RAX,8)

  (198) 0x43085b INC	%RAX

  (198) 0x43085e CMP	%RAX,%R8

  (198) 0x430861 JE	4308c0

  (198) 0x430863 VMOVSD	-0x8(%RDI,%RAX,8),%XMM4

  (198) 0x430869 LEA	-0x1(%RAX),%RCX

  (198) 0x43086d VCOMISD	%XMM4,%XMM7

  (198) 0x430871 JBE	430790

  (198) 0x430877 MOV	%RCX,%R10

  (198) 0x43087a MOVSXD	%EAX,%R9

  (198) 0x43087d LEA	0x1(%RAX),%EDX

  (198) 0x430880 MOV	%RAX,%RCX

  (198) 0x430883 JMP	430799

  (198) 0x4308a0 MOV	0x2ff31(%RIP),%RCX

  (198) 0x4308a7 VMOVSD	%XMM20,%XMM20,%XMM23

  (198) 0x4308ad VMOVQ	%RCX,%XMM22

  (198) 0x4308b3 JMP	4307ed

0x4308c0 MOV	-0x40(%RBP),%RDI

0x4308c4 MOV	-0x50(%RBP),%R14D

0x4308c8 MOV	-0x58(%RBP),%R12D

0x4308cc INC	%RDI

0x4308cf SUB	%R12D,%R14D

0x4308d2 ADD	%EDI,%R14D

0x4308d5 CMP	%R14D,-0x38(%RBP)

0x4308d9 JLE	430890

0x4308db MOV	-0x4c(%RBP),%ESI

0x4308de MOV	-0x34(%RBP),%R13D

0x4308e2 MOV	-0x48(%RBP),%ECX

0x4308e5 MOV	-0x44(%RBP),%EDX

0x4308e8 SUB	%R13D,%ESI

0x4308eb JMP	4306f0

0x4308f0 MOV	%R13D,-0x34(%RBP)

0x4308f4 JMP	4308c4

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	3.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.73
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6
Source	advec_mom.cpp:110-110,advec_mom.cpp:114-114,advec_mom.cpp:132-134,advec_mom.cpp:139-139,context.h:46-46,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	1.31
Front-end cycles	8.83
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	2.50
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	18.00
Nb stores	3.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.94
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.55
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	9.09
Vector-efficiency ratio all	11.36
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.93

Metric	Value
CQA speedup if no scalar integer	3.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.73
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6
Source	advec_mom.cpp:110-110,advec_mom.cpp:114-114,advec_mom.cpp:132-134,advec_mom.cpp:139-139,context.h:46-46,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	1.31
Front-end cycles	8.83
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	2.50
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	18.00
Nb stores	3.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.94
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.55
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	9.09
Vector-efficiency ratio all	11.36
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6
Source file and lines	advec_mom.cpp:108-139
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:108-139
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.83 to 2.50 cycles (3.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.83 to 1.31 cycles (6.73x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	53
nb uops	53
loop length	202
used x86 registers	15
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	5.50	5.25	5.25	2.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50
cycles	5.50	5.50	5.25	5.25	2.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	7.33
Overall L1	8.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	10%
load	10%
store	8%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	10%
store	8%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

13% of peak load performance is reached (13.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.83 to 7.33 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 4306f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
CMP %ECX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVA %ECX,%ESI	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%R13,%RSI,1),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %R15D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 4308f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVQ %XMM13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA 0x1(%RDX),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1(%RSI),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%R10),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDX,%RSI,1),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVQ %XMM11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x10(%RCX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RCX),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RDX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM10,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x10(%R10),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R13),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%R13),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x8(%R14),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTQ
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDDUP 0x2f64f(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RDI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RBX,%R11,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RDI,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R10,%RCX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 430863 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x293>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x50(%RBP),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x58(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB %R12D,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14D,-0x38(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 430890 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x2c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x34(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x48(%RBP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x44(%RBP),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB %R13D,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 4306f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x120>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R13D,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 4308c4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x2f4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6
Source file and lines	advec_mom.cpp:108-139
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:108-139
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.83 to 2.50 cycles (3.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	53
nb uops	53
loop length	202
used x86 registers	15
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	5.50	5.25	5.25	2.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50
cycles	5.50	5.50	5.25	5.25	2.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	7.33
Overall L1	8.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	10%
load	10%
store	8%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	10%
store	8%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

13% of peak load performance is reached (13.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4306f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
CMP %ECX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVA %ECX,%ESI	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%R13,%RSI,1),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %R15D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 4308f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVQ %XMM13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA 0x1(%RDX),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1(%RSI),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%R10),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDX,%RSI,1),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
VMOVQ %XMM11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x10(%RCX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RCX),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RDX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM10,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x10(%R10),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R13),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV (%R13),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x8(%R14),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTQ
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDDUP 0x2f64f(%RIP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
IMUL %RDI,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %RDI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RBX,%R11,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %RDI,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R10,%RCX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 430863 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x293>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x50(%RBP),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x58(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB %R12D,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14D,-0x38(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 430890 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x2c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x34(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x48(%RBP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x44(%RBP),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB %R13D,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 4306f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x120>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %R13D,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 4308c4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x2f4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.5	0	0.75	0	0.75	0	1	0	0.19	0.01	0.09	0.03	0.06	0.03

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.06	0.01
2x2	4	1.5	3	2	0.03	0.01
2x4	8	0.75	3	4	0.04	0.01
2x8	16	0.75	6	8	0.02	0.01
2x16	32	1	1	16	0.01	0.01
2x32	64	0.19	6	32	0.03	0.01
2x64	128	0.09	6	64	0.03	0.03
2x96	192	0.06	6	96	0.05	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency