OV - - Loop 240

	Loop Id: 240	Module: exec	Source: ideal_gas.cpp:40-45	Coverage: 3.1%

0x439f51 VDIVPD	(%R10,%RCX,1),%ZMM4,%ZMM25    [2]

0x439f58 VMOVUPD	(%R12,%RCX,1),%ZMM9    [4]

0x439f5f VMULPD	(%R10,%RCX,1),%ZMM9,%ZMM12    [2]

0x439f66 VMULPD	%ZMM3,%ZMM12,%ZMM7

0x439f6c VMOVUPD	%ZMM7,(%RBX,%RCX,1)    [1]

0x439f73 VMULPD	(%R10,%RCX,1),%ZMM2,%ZMM0    [2]

0x439f7a VMULPD	%ZMM25,%ZMM25,%ZMM26

0x439f80 VMULPD	%ZMM26,%ZMM0,%ZMM1

0x439f86 VMULPD	%ZMM7,%ZMM1,%ZMM8

0x439f8c VSQRTPD	%ZMM8,%ZMM9

0x439f92 VMOVUPD	%ZMM9,(%RAX,%RCX,1)    [3]

0x439f99 VDIVPD	0x40(%R10,%RCX,1),%ZMM4,%ZMM27    [2]

0x439fa1 VMOVUPD	0x40(%R12,%RCX,1),%ZMM12    [4]

0x439fa9 VMULPD	0x40(%R10,%RCX,1),%ZMM12,%ZMM7    [2]

0x439fb1 VMULPD	%ZMM3,%ZMM7,%ZMM1

0x439fb7 VMOVUPD	%ZMM1,0x40(%RBX,%RCX,1)    [1]

0x439fbf VMULPD	0x40(%R10,%RCX,1),%ZMM2,%ZMM0    [2]

0x439fc7 VMULPD	%ZMM27,%ZMM27,%ZMM28

0x439fcd VMULPD	%ZMM28,%ZMM0,%ZMM8

0x439fd3 VMULPD	%ZMM1,%ZMM8,%ZMM9

0x439fd9 VSQRTPD	%ZMM9,%ZMM12

0x439fdf VMOVUPD	%ZMM12,0x40(%RAX,%RCX,1)    [3]

0x439fe7 VDIVPD	0x80(%R10,%RCX,1),%ZMM4,%ZMM29    [2]

0x439fef VMOVUPD	0x80(%R12,%RCX,1),%ZMM7    [4]

0x439ff7 VMULPD	0x80(%R10,%RCX,1),%ZMM7,%ZMM1    [2]

0x439fff VMULPD	%ZMM3,%ZMM1,%ZMM8

0x43a005 VMOVUPD	%ZMM8,0x80(%RBX,%RCX,1)    [1]

0x43a00d VMULPD	0x80(%R10,%RCX,1),%ZMM2,%ZMM0    [2]

0x43a015 VMULPD	%ZMM29,%ZMM29,%ZMM30

0x43a01b VMULPD	%ZMM30,%ZMM0,%ZMM9

0x43a021 VMULPD	%ZMM8,%ZMM9,%ZMM12

0x43a027 VSQRTPD	%ZMM12,%ZMM7

0x43a02d VMOVUPD	%ZMM7,0x80(%RAX,%RCX,1)    [3]

0x43a035 VDIVPD	0xc0(%R10,%RCX,1),%ZMM4,%ZMM31    [2]

0x43a03d VMOVUPD	0xc0(%R12,%RCX,1),%ZMM1    [4]

0x43a045 VMULPD	0xc0(%R10,%RCX,1),%ZMM1,%ZMM8    [2]

0x43a04d VMULPD	%ZMM3,%ZMM8,%ZMM9

0x43a053 VMOVUPD	%ZMM9,0xc0(%RBX,%RCX,1)    [1]

0x43a05b VMULPD	0xc0(%R10,%RCX,1),%ZMM2,%ZMM0    [2]

0x43a063 VMULPD	%ZMM31,%ZMM31,%ZMM22

0x43a069 VMULPD	%ZMM22,%ZMM0,%ZMM12

0x43a06f VMULPD	%ZMM9,%ZMM12,%ZMM7

0x43a075 VSQRTPD	%ZMM7,%ZMM1

0x43a07b VMOVUPD	%ZMM1,0xc0(%RAX,%RCX,1)    [3]

0x43a083 ADD	$0x100,%RCX

0x43a08a CMP	%R9,%RCX

0x43a08d JNE	439f51

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp: 40 - 45

--------------------------------------------------------------------------------

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.13
Bottlenecks	P8, P9,
Function	_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source	ideal_gas.cpp:40-45
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	100.00
CQA cycles if no scalar integer	100.00
CQA cycles if FP arith vectorized	100.00
CQA cycles if fully vectorized	100.00
Front-end cycles	9.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	13.33
P5 cycles	13.33
P6 cycles	13.33
P7 cycles	32.00
P8 cycles	32.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	100.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	54.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.56
Nb FLOP add-sub	0.00
Nb FLOP mul	192.00
Nb FLOP fma	0.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	32.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.36
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	3.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.13
Bottlenecks	P8, P9,
Function	_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source	ideal_gas.cpp:40-45
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	100.00
CQA cycles if no scalar integer	100.00
CQA cycles if FP arith vectorized	100.00
CQA cycles if fully vectorized	100.00
Front-end cycles	9.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	13.33
P5 cycles	13.33
P6 cycles	13.33
P7 cycles	32.00
P8 cycles	32.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	100.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	54.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.56
Nb FLOP add-sub	0.00
Nb FLOP mul	192.00
Nb FLOP fma	0.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	32.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.36
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	3.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source file and lines	ideal_gas.cpp:40-45
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:40-45.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 100.00 to 32.00 cycles (3.13x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 100.00 to 24.00 cycles (4.17x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

32 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 256 FP arithmetical operations:

192: multiply
32: divide
32: square root

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	54
loop length	322
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	17
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	16.00	16.00	0.00	0.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	32.00	32.00	0.00	0.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	100.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	32.00
DIV/SQRT	100.00
Data deps.	1.00
Overall L1	100.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 100.00 cycles. At this rate:

10% of peak load performance is reached (10.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.12 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 439f51

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VDIVPD (%R10,%RCX,1),%ZMM4,%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD (%R12,%RCX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD (%R10,%RCX,1),%ZMM9,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM7,(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD (%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM25,%ZMM25,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM26,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM7,%ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM9,(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VDIVPD 0x40(%R10,%RCX,1),%ZMM4,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD 0x40(%R12,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD 0x40(%R10,%RCX,1),%ZMM12,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM1,0x40(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD 0x40(%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM27,%ZMM27,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM28,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM1,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM12,0x40(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VDIVPD 0x80(%R10,%RCX,1),%ZMM4,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD 0x80(%R12,%RCX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD 0x80(%R10,%RCX,1),%ZMM7,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM8,0x80(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD 0x80(%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM29,%ZMM29,%ZMM30	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM30,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM8,%ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM7,0x80(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VDIVPD 0xc0(%R10,%RCX,1),%ZMM4,%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD 0xc0(%R12,%RCX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD 0xc0(%R10,%RCX,1),%ZMM1,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM9,0xc0(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD 0xc0(%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM31,%ZMM31,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM22,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM9,%ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM1,0xc0(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x100,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 439f51 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x2d1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source file and lines	ideal_gas.cpp:40-45
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 100.00 to 24.00 cycles (4.17x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

32 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 256 FP arithmetical operations:

192: multiply
32: divide
32: square root

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	54
loop length	322
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	17
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	16.00	16.00	0.00	0.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	32.00	32.00	0.00	0.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	100.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	32.00
DIV/SQRT	100.00
Data deps.	1.00
Overall L1	100.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 100.00 cycles. At this rate:

10% of peak load performance is reached (10.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.12 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 439f51

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VDIVPD (%R10,%RCX,1),%ZMM4,%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD (%R12,%RCX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD (%R10,%RCX,1),%ZMM9,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM7,(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD (%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM25,%ZMM25,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM26,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM7,%ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM9,(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VDIVPD 0x40(%R10,%RCX,1),%ZMM4,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD 0x40(%R12,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD 0x40(%R10,%RCX,1),%ZMM12,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM1,0x40(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD 0x40(%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM27,%ZMM27,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM28,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM1,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM12,0x40(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VDIVPD 0x80(%R10,%RCX,1),%ZMM4,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD 0x80(%R12,%RCX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD 0x80(%R10,%RCX,1),%ZMM7,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM8,0x80(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD 0x80(%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM29,%ZMM29,%ZMM30	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM30,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM8,%ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM7,0x80(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VDIVPD 0xc0(%R10,%RCX,1),%ZMM4,%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	9
VMOVUPD 0xc0(%R12,%RCX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMULPD 0xc0(%R10,%RCX,1),%ZMM1,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM3,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM9,0xc0(%RBX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMULPD 0xc0(%R10,%RCX,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMULPD %ZMM31,%ZMM31,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM22,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM9,%ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMOVUPD %ZMM1,0xc0(%RAX,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x100,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 439f51 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x2d1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	-0	1	0.01	0.79	0.76	0.45	2.27	0.23	3.79	0.11	4.44	0.07	5.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	19.26	3.1
2x2	4	1	2	2	9.63	3.1
2x4	8	1	3.99	4	4.86	3.09
2x8	16	0.79	6.29	8	3.1	3.55
2x16	32	0.45	7.16	16	3.15	4.11
2x32	64	0.23	7.38	32	2.81	4.93
2x64	128	0.11	7.27	64	2.87	5.01
2x96	192	0.07	7.03	96	2.78	5.41

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency