OV - - Loop 273

	Loop Id: 273	Module: exec	Source: PdV.cpp:72-83	Coverage: 5.21%

0x4416a0 VMOVQ	%XMM7,%RCX

0x4416a5 VMOVUPD	(%RBX,%RAX,1),%ZMM4    [7]

0x4416ac VADDPD	(%R12,%RAX,1),%ZMM4,%ZMM1    [5]

0x4416b3 VMOVUPD	(%RCX,%RAX,1),%ZMM2    [20]

0x4416ba VADDPD	(%R10,%RAX,1),%ZMM2,%ZMM5    [16]

0x4416c1 VMOVQ	%XMM20,%RCX

0x4416c7 VMOVUPD	(%RCX,%RAX,1),%ZMM6    [11]

0x4416ce VMOVQ	%XMM19,%RCX

0x4416d4 VADDPD	(%R14,%RAX,1),%ZMM6,%ZMM3    [1]

0x4416db VMOVUPD	(%RCX,%RAX,1),%ZMM4    [26]

0x4416e2 VMOVQ	%XMM21,%RCX

0x4416e8 VADDPD	%ZMM5,%ZMM1,%ZMM15

0x4416ee VADDPD	(%R11,%RAX,1),%ZMM4,%ZMM1    [23]

0x4416f5 VADDPD	%ZMM1,%ZMM3,%ZMM2

0x4416fb VMULPD	(%RCX,%RAX,1),%ZMM2,%ZMM1    [25]

0x441702 VMOVQ	%XMM25,%RCX

0x441708 VMOVUPD	(%RCX,%RAX,1),%ZMM5    [3]

0x44170f VMOVQ	%XMM23,%RCX

0x441715 VADDPD	(%R15,%RAX,1),%ZMM5,%ZMM4    [6]

0x44171c VMOVUPD	(%RCX,%RAX,1),%ZMM6    [28]

0x441723 VADDPD	(%R13,%RAX,1),%ZMM6,%ZMM3    [4]

0x44172b VMOVQ	%XMM22,%RCX

0x441731 VMOVUPD	(%RCX,%RAX,1),%ZMM5    [14]

0x441738 VMOVQ	%XMM24,%RCX

0x44173e VMOVUPD	(%RCX,%RAX,1),%ZMM6    [18]

0x441745 VMOVQ	%XMM18,%RCX

0x44174b VADDPD	%ZMM3,%ZMM4,%ZMM2

0x441751 VADDPD	(%RDI,%RAX,1),%ZMM6,%ZMM3    [19]

0x441758 VADDPD	(%RSI,%RAX,1),%ZMM5,%ZMM4    [21]

0x44175f VADDPD	%ZMM3,%ZMM4,%ZMM5

0x441765 VMULPD	(%RCX,%RAX,1),%ZMM5,%ZMM4    [12]

0x44176c MOV	0x1a8(%RSP),%RCX    [27]

0x441774 VMOVUPD	(%R8,%RAX,1),%ZMM3    [24]

0x44177b VFMADD132PD	(%RCX,%RAX,1),%ZMM4,%ZMM2    [13]

0x441782 VMOVQ	%XMM17,%RCX

0x441788 VFMADD132PD	(%RCX,%RAX,1),%ZMM1,%ZMM15    [22]

0x44178f VSUBPD	%ZMM15,%ZMM2,%ZMM15

0x441795 VMOVQ	%XMM13,%RCX

0x44179a VMOVUPD	(%RCX,%RAX,1),%ZMM2    [8]

0x4417a1 VADDPD	(%R9,%RAX,1),%ZMM2,%ZMM4    [2]

0x4417a8 VMOVQ	%XMM10,%RCX

0x4417ad VMULPD	%ZMM12,%ZMM15,%ZMM6

0x4417b3 VADDPD	(%R8,%RAX,1),%ZMM6,%ZMM1    [24]

0x4417ba VDIVPD	(%RDX,%RAX,1),%ZMM4,%ZMM15    [10]

0x4417c1 VDIVPD	%ZMM1,%ZMM3,%ZMM5

0x4417c7 VDIVPD	%ZMM3,%ZMM11,%ZMM1

0x4417cd VMULPD	%ZMM1,%ZMM15,%ZMM3

0x4417d3 VFNMADD213PD	(%RCX,%RAX,1),%ZMM3,%ZMM6    [17]

0x4417da VMOVQ	%XMM8,%RCX

0x4417df VMOVUPD	%ZMM6,(%RCX,%RAX,1)    [15]

0x4417e6 VMULPD	(%RDX,%RAX,1),%ZMM5,%ZMM6    [10]

0x4417ed VMOVQ	%XMM27,%RCX

0x4417f3 VMOVUPD	%ZMM6,(%RCX,%RAX,1)    [9]

0x4417fa MOV	0x1b0(%RSP),%RCX    [27]

0x441802 ADD	$0x40,%RAX

0x441806 CMP	%RCX,%RAX

0x441809 JNE	4416a0

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 72 - 83

--------------------------------------------------------------------------------

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P8, P9,
Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1
Source	PdV.cpp:72-83
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	27.00
Front-end cycles	9.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	19.33
P5 cycles	19.33
P6 cycles	19.33
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	15.00
P10 cycles	15.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	27.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	58.00
Nb loads	29.00
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	8.59
Nb FLOP add-sub	120.00
Nb FLOP mul	40.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	69.33
Bytes prefetched	0.00
Bytes loaded	1744.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	10.00
Stride n	2.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	73.08
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	76.44
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P8, P9,
Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1
Source	PdV.cpp:72-83
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	27.00
Front-end cycles	9.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	19.33
P5 cycles	19.33
P6 cycles	19.33
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	15.00
P10 cycles	15.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	27.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	58.00
Nb loads	29.00
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	8.59
Nb FLOP add-sub	120.00
Nb FLOP mul	40.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	69.33
Bytes prefetched	0.00
Bytes loaded	1744.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	10.00
Stride n	2.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	73.08
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	76.44
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1
Source file and lines	PdV.cpp:72-83
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:72-83.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 76% of vector register length is used (average across all SSE/AVX instructions).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 19.33 cycles (1.40x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 18.67 cycles (1.45x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 232 FP arithmetical operations:

144: addition or subtraction (24 inside FMA instructions)
64: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1744 bytes (218 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	58
loop length	367
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	9
nb stack references	2
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	10.33	10.33	10.33	5.50	5.50	7.50	7.50	9.00	9.00
cycles	0.50	0.50	0.25	0.25	0.50	19.33	19.33	19.33	11.00	11.00	15.00	15.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	27.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	19.33
DIV/SQRT	27.00
Data deps.	1.00
Overall L1	27.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	76%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

67% of peak load performance is reached (64.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.74 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4416a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RBX,%RAX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R12,%RAX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R10,%RAX,1),%ZMM2,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM19,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R14,%RAX,1),%ZMM6,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM21,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM5,%ZMM1,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%R11,%RAX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM1,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD (%RCX,%RAX,1),%ZMM2,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM25,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM23,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R15,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R13,%RAX,1),%ZMM6,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM22,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM24,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM18,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM3,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%RDI,%RAX,1),%ZMM6,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%RSI,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM3,%ZMM4,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD (%RCX,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
MOV 0x1a8(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVUPD (%R8,%RAX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD132PD (%RCX,%RAX,1),%ZMM4,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVQ %XMM17,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VFMADD132PD (%RCX,%RAX,1),%ZMM1,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM15,%ZMM2,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R9,%RAX,1),%ZMM2,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD %ZMM12,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VADDPD (%R8,%RAX,1),%ZMM6,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD (%RDX,%RAX,1),%ZMM4,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM1,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM3,%ZMM11,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMULPD %ZMM1,%ZMM15,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFNMADD213PD (%RCX,%RAX,1),%ZMM3,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVQ %XMM8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RCX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD (%RDX,%RAX,1),%ZMM5,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM27,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RCX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
MOV 0x1b0(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 4416a0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x630>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1
Source file and lines	PdV.cpp:72-83
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 76% of vector register length is used (average across all SSE/AVX instructions).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 18.67 cycles (1.45x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 232 FP arithmetical operations:

144: addition or subtraction (24 inside FMA instructions)
64: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1744 bytes (218 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	58
loop length	367
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	9
nb stack references	2
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	10.33	10.33	10.33	5.50	5.50	7.50	7.50	9.00	9.00
cycles	0.50	0.50	0.25	0.25	0.50	19.33	19.33	19.33	11.00	11.00	15.00	15.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	27.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	19.33
DIV/SQRT	27.00
Data deps.	1.00
Overall L1	27.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	76%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

67% of peak load performance is reached (64.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.74 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4416a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RBX,%RAX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R12,%RAX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R10,%RAX,1),%ZMM2,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM19,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R14,%RAX,1),%ZMM6,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM21,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM5,%ZMM1,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%R11,%RAX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM1,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD (%RCX,%RAX,1),%ZMM2,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM25,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM23,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R15,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R13,%RAX,1),%ZMM6,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM22,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM24,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM18,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM3,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%RDI,%RAX,1),%ZMM6,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%RSI,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM3,%ZMM4,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD (%RCX,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
MOV 0x1a8(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVUPD (%R8,%RAX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD132PD (%RCX,%RAX,1),%ZMM4,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVQ %XMM17,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VFMADD132PD (%RCX,%RAX,1),%ZMM1,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM15,%ZMM2,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RCX,%RAX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R9,%RAX,1),%ZMM2,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD %ZMM12,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VADDPD (%R8,%RAX,1),%ZMM6,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD (%RDX,%RAX,1),%ZMM4,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM1,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM3,%ZMM11,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMULPD %ZMM1,%ZMM15,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFNMADD213PD (%RCX,%RAX,1),%ZMM3,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVQ %XMM8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RCX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD (%RDX,%RAX,1),%ZMM5,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM27,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RCX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
MOV 0x1b0(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 4416a0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x630>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	-0	0.93	0.37	0.58	2.23	0.32	3.99	0.16	5.05	0.1	5.82

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	32.36	5.21
2x2	4	1	2.01	2	16.17	5.18
2x4	8	1	4	4	8.18	5.17
2x8	16	0.93	7.42	8	4.39	5.07
2x16	32	0.58	9.3	16	3.88	5.33
2x32	64	0.32	10.37	32	3.39	5.9
2x64	128	0.16	10.17	64	3.57	6.01
2x96	192	0.1	9.86	96	3.4	6.49

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency