OV - - Loop 170

	Loop Id: 170	Module: exec	Source: advec_cell.cpp:211-216	Coverage: 2.09%

0x428ffb VMOVUPD	(%RBX,%RDX,1),%ZMM15    [3]

0x429002 VMULPD	(%R10,%RDX,1),%ZMM15,%ZMM9    [2]

0x429009 VMOVUPD	(%R12,%RDX,1),%ZMM3    [10]

0x429010 VADDPD	(%R10,%RDX,1),%ZMM3,%ZMM2    [2]

0x429017 VMOVUPD	(%RAX,%RDX,1),%ZMM10    [6]

0x42901e VSUBPD	(%R14,%RDX,1),%ZMM10,%ZMM27    [7]

0x429025 VSUBPD	(%RCX,%RDX,1),%ZMM9,%ZMM25    [1]

0x42902c VSUBPD	(%R15,%RDX,1),%ZMM2,%ZMM6    [9]

0x429033 VFMADD231PD	(%R11,%RDX,1),%ZMM9,%ZMM27    [4]

0x42903a VADDPD	(%R9,%RDX,1),%ZMM25,%ZMM26    [8]

0x429041 VDIVPD	%ZMM26,%ZMM27,%ZMM1

0x429047 VDIVPD	%ZMM6,%ZMM26,%ZMM0

0x42904d VMOVUPD	%ZMM0,(%RBX,%RDX,1)    [3]

0x429054 VMOVUPD	%ZMM1,(%R11,%RDX,1)    [4]

0x42905b VMOVUPD	0x40(%RBX,%RDX,1),%ZMM4    [3]

0x429063 VMULPD	0x40(%R10,%RDX,1),%ZMM4,%ZMM1    [2]

0x42906b VMOVUPD	0x40(%R12,%RDX,1),%ZMM7    [10]

0x429073 VADDPD	0x40(%R10,%RDX,1),%ZMM7,%ZMM8    [2]

0x42907b VMOVUPD	0x40(%RAX,%RDX,1),%ZMM5    [6]

0x429083 VSUBPD	0x40(%R14,%RDX,1),%ZMM5,%ZMM30    [7]

0x42908b VSUBPD	0x40(%RCX,%RDX,1),%ZMM1,%ZMM28    [1]

0x429093 VSUBPD	0x40(%R15,%RDX,1),%ZMM8,%ZMM11    [9]

0x42909b VFMADD132PD	0x40(%R11,%RDX,1),%ZMM30,%ZMM1    [4]

0x4290a3 VADDPD	0x40(%R9,%RDX,1),%ZMM28,%ZMM29    [8]

0x4290ab VDIVPD	%ZMM11,%ZMM29,%ZMM15

0x4290b1 VDIVPD	%ZMM29,%ZMM1,%ZMM9

0x4290b7 VMOVUPD	%ZMM15,0x40(%RBX,%RDX,1)    [3]

0x4290bf VMOVUPD	%ZMM9,0x40(%R11,%RDX,1)    [4]

0x4290c7 SUB	$-0x80,%RDX

0x4290cb CMP	%RDX,0x38(%RSP)    [5]

0x4290d0 JNE	428ffb

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 211 - 216

--------------------------------------------------------------------------------

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P8, P9,
Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7
Source	advec_cell.cpp:211-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	36.00
CQA cycles if no scalar integer	36.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	36.00
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	15.00
P5 cycles	15.00
P6 cycles	15.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	10.00
P10 cycles	10.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	36.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	4.44
Nb FLOP add-sub	80.00
Nb FLOP mul	16.00
Nb FLOP fma	16.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.89
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	8.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P8, P9,
Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7
Source	advec_cell.cpp:211-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	36.00
CQA cycles if no scalar integer	36.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	36.00
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	15.00
P5 cycles	15.00
P6 cycles	15.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	10.00
P10 cycles	10.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	36.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	4.44
Nb FLOP add-sub	80.00
Nb FLOP mul	16.00
Nb FLOP fma	16.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.89
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	8.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7
Source file and lines	advec_cell.cpp:211-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:211-216.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 36.00 to 15.00 cycles (2.40x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 36.00 to 15.00 cycles (2.40x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

18 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)
32: divide

The binary loop is loading 1288 bytes (161 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	34
loop length	219
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	19
nb stack references	1
ADD-SUB / MUL ratio	5.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.33	8.33	8.33	4.00	4.00	5.00	5.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	15.00	15.00	15.00	8.00	8.00	10.00	10.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	36.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	15.00
DIV/SQRT	36.00
Data deps.	1.00
Overall L1	36.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.00 cycles. At this rate:

37% of peak load performance is reached (35.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.11 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 428ffb

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%RBX,%RDX,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD (%R10,%RDX,1),%ZMM15,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVUPD (%R12,%RDX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R10,%RDX,1),%ZMM3,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RAX,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VSUBPD (%R14,%RDX,1),%ZMM10,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD (%RCX,%RDX,1),%ZMM9,%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD (%R15,%RDX,1),%ZMM2,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VFMADD231PD (%R11,%RDX,1),%ZMM9,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD (%R9,%RDX,1),%ZMM25,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD %ZMM26,%ZMM27,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM6,%ZMM26,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMOVUPD %ZMM0,(%RBX,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM1,(%R11,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%RBX,%RDX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD 0x40(%R10,%RDX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%RDX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%R10,%RDX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD 0x40(%RAX,%RDX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VSUBPD 0x40(%R14,%RDX,1),%ZMM5,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x40(%RCX,%RDX,1),%ZMM1,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x40(%R15,%RDX,1),%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VFMADD132PD 0x40(%R11,%RDX,1),%ZMM30,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD 0x40(%R9,%RDX,1),%ZMM28,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD %ZMM11,%ZMM29,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM29,%ZMM1,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMOVUPD %ZMM15,0x40(%RBX,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM9,0x40(%R11,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,0x38(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 428ffb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2fb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7
Source file and lines	advec_cell.cpp:211-216
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 36.00 to 15.00 cycles (2.40x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

18 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)
32: divide

The binary loop is loading 1288 bytes (161 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	34
loop length	219
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	19
nb stack references	1
ADD-SUB / MUL ratio	5.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.33	8.33	8.33	4.00	4.00	5.00	5.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	15.00	15.00	15.00	8.00	8.00	10.00	10.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	36.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	15.00
DIV/SQRT	36.00
Data deps.	1.00
Overall L1	36.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.00 cycles. At this rate:

37% of peak load performance is reached (35.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.11 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 428ffb

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%RBX,%RDX,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD (%R10,%RDX,1),%ZMM15,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVUPD (%R12,%RDX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R10,%RDX,1),%ZMM3,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RAX,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VSUBPD (%R14,%RDX,1),%ZMM10,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD (%RCX,%RDX,1),%ZMM9,%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD (%R15,%RDX,1),%ZMM2,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VFMADD231PD (%R11,%RDX,1),%ZMM9,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD (%R9,%RDX,1),%ZMM25,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD %ZMM26,%ZMM27,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM6,%ZMM26,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMOVUPD %ZMM0,(%RBX,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM1,(%R11,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%RBX,%RDX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD 0x40(%R10,%RDX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%RDX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%R10,%RDX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD 0x40(%RAX,%RDX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VSUBPD 0x40(%R14,%RDX,1),%ZMM5,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x40(%RCX,%RDX,1),%ZMM1,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x40(%R15,%RDX,1),%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VFMADD132PD 0x40(%R11,%RDX,1),%ZMM30,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD 0x40(%R9,%RDX,1),%ZMM28,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD %ZMM11,%ZMM29,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM29,%ZMM1,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMOVUPD %ZMM15,0x40(%RBX,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM9,0x40(%R11,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,0x38(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 428ffb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2fb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.81	0.45	0.63	0.93	0.28	2.05	0.23	2.43	0.08	2.96	0.05	2.99	0.04	2.78

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	13.09	2.09
2x2	4	0.81	1.62	2	8.08	2.34
2x4	8	0.63	2.53	4	5.5	2.53
2x8	16	0.28	2.27	8	6.83	2.86
2x16	32	0.23	3.71	16	3.72	3.17
2x32	64	0.08	2.6	32	5.45	3.22
2x64	128	0.05	3.31	64	4.18	3.15
2x96	192	0.04	3.43	96	3.52	2.88

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency