OV - - Loop 182

	Loop Id: 182	Module: exec	Source: advec_mom.cpp:65-66	Coverage: 1.44%

0x42d817 VMOVUPD	(%R12,%RAX,1),%ZMM0    [4]

0x42d81e VMOVUPD	%ZMM0,(%RBX,%RAX,1)    [3]

0x42d825 VADDPD	(%R11,%RAX,1),%ZMM0,%ZMM2    [1]

0x42d82c VSUBPD	(%R10,%RAX,1),%ZMM2,%ZMM7    [2]

0x42d833 VMOVUPD	%ZMM7,(%RDX,%RAX,1)    [5]

0x42d83a VMOVUPD	0x40(%R12,%RAX,1),%ZMM8    [4]

0x42d842 VMOVUPD	%ZMM8,0x40(%RBX,%RAX,1)    [3]

0x42d84a VADDPD	0x40(%R11,%RAX,1),%ZMM8,%ZMM9    [1]

0x42d852 VSUBPD	0x40(%R10,%RAX,1),%ZMM9,%ZMM10    [2]

0x42d85a VMOVUPD	%ZMM10,0x40(%RDX,%RAX,1)    [5]

0x42d862 VMOVUPD	0x80(%R12,%RAX,1),%ZMM11    [4]

0x42d86a VMOVUPD	%ZMM11,0x80(%RBX,%RAX,1)    [3]

0x42d872 VADDPD	0x80(%R11,%RAX,1),%ZMM11,%ZMM14    [1]

0x42d87a VSUBPD	0x80(%R10,%RAX,1),%ZMM14,%ZMM15    [2]

0x42d882 VMOVUPD	%ZMM15,0x80(%RDX,%RAX,1)    [5]

0x42d88a VMOVUPD	0xc0(%R12,%RAX,1),%ZMM6    [4]

0x42d892 VMOVUPD	%ZMM6,0xc0(%RBX,%RAX,1)    [3]

0x42d89a VADDPD	0xc0(%R11,%RAX,1),%ZMM6,%ZMM0    [1]

0x42d8a2 VSUBPD	0xc0(%R10,%RAX,1),%ZMM0,%ZMM2    [2]

0x42d8aa VMOVUPD	%ZMM2,0xc0(%RDX,%RAX,1)    [5]

0x42d8b2 VMOVUPD	0x100(%R12,%RAX,1),%ZMM7    [4]

0x42d8ba VMOVUPD	%ZMM7,0x100(%RBX,%RAX,1)    [3]

0x42d8c2 VADDPD	0x100(%R11,%RAX,1),%ZMM7,%ZMM8    [1]

0x42d8ca VSUBPD	0x100(%R10,%RAX,1),%ZMM8,%ZMM9    [2]

0x42d8d2 VMOVUPD	%ZMM9,0x100(%RDX,%RAX,1)    [5]

0x42d8da VMOVUPD	0x140(%R12,%RAX,1),%ZMM10    [4]

0x42d8e2 VMOVUPD	%ZMM10,0x140(%RBX,%RAX,1)    [3]

0x42d8ea VADDPD	0x140(%R11,%RAX,1),%ZMM10,%ZMM11    [1]

0x42d8f2 VSUBPD	0x140(%R10,%RAX,1),%ZMM11,%ZMM14    [2]

0x42d8fa VMOVUPD	%ZMM14,0x140(%RDX,%RAX,1)    [5]

0x42d902 VMOVUPD	0x180(%R12,%RAX,1),%ZMM15    [4]

0x42d90a VMOVUPD	%ZMM15,0x180(%RBX,%RAX,1)    [3]

0x42d912 VADDPD	0x180(%R11,%RAX,1),%ZMM15,%ZMM6    [1]

0x42d91a VSUBPD	0x180(%R10,%RAX,1),%ZMM6,%ZMM0    [2]

0x42d922 VMOVUPD	%ZMM0,0x180(%RDX,%RAX,1)    [5]

0x42d92a VMOVUPD	0x1c0(%R12,%RAX,1),%ZMM2    [4]

0x42d932 VMOVUPD	%ZMM2,0x1c0(%RBX,%RAX,1)    [3]

0x42d93a VADDPD	0x1c0(%R11,%RAX,1),%ZMM2,%ZMM7    [1]

0x42d942 VSUBPD	0x1c0(%R10,%RAX,1),%ZMM7,%ZMM8    [2]

0x42d94a VMOVUPD	%ZMM8,0x1c0(%RDX,%RAX,1)    [5]

0x42d952 ADD	$0x200,%RAX

0x42d958 CMP	%R14,%RAX

0x42d95b JNE	42d817

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 65 - 66

--------------------------------------------------------------------------------

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P5, P6, P7,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2
Source	advec_mom.cpp:65-66
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.33
CQA cycles if no scalar integer	21.33
CQA cycles if FP arith vectorized	21.33
CQA cycles if fully vectorized	21.33
Front-end cycles	9.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	21.33
P5 cycles	21.33
P6 cycles	21.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	58.00
Nb loads	24.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	6.00
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	120.00
Bytes prefetched	0.00
Bytes loaded	1536.00
Bytes stored	1024.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P5, P6, P7,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2
Source	advec_mom.cpp:65-66
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.33
CQA cycles if no scalar integer	21.33
CQA cycles if FP arith vectorized	21.33
CQA cycles if fully vectorized	21.33
Front-end cycles	9.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	21.33
P5 cycles	21.33
P6 cycles	21.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	58.00
Nb loads	24.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	6.00
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	120.00
Bytes prefetched	0.00
Bytes loaded	1536.00
Bytes stored	1024.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2
Source file and lines	advec_mom.cpp:65-66
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:65-66.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 21.33 to 16.00 cycles (1.33x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 16 occurrences

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 1536 bytes (192 double precision FP elements). The binary loop is storing 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	43
nb uops	58
loop length	330
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	10
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	0.00	0.00	8.00	8.00	16.00	16.00
cycles	0.50	0.50	0.25	0.25	0.50	21.33	21.33	21.33	0.00	0.00	16.00	16.00	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	21.33
Data deps.	1.00
Overall L1	21.33

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.33 cycles. At this rate:

75% of peak load performance is reached (72.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
75% of peak store performance is reached (48.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42d817

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%RAX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM0,(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD (%R11,%RAX,1),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD (%R10,%RAX,1),%ZMM2,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM7,(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%R12,%RAX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM8,0x40(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x40(%R11,%RAX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x40(%R10,%RAX,1),%ZMM9,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM10,0x40(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%R12,%RAX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM11,0x80(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x80(%R11,%RAX,1),%ZMM11,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x80(%R10,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM15,0x80(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R12,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM6,0xc0(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0xc0(%R11,%RAX,1),%ZMM6,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0xc0(%R10,%RAX,1),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM2,0xc0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x100(%R12,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM7,0x100(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x100(%R11,%RAX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x100(%R10,%RAX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM9,0x100(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x140(%R12,%RAX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM10,0x140(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x140(%R11,%RAX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x140(%R10,%RAX,1),%ZMM11,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM14,0x140(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x180(%R12,%RAX,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM15,0x180(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x180(%R11,%RAX,1),%ZMM15,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x180(%R10,%RAX,1),%ZMM6,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM0,0x180(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x1c0(%R12,%RAX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM2,0x1c0(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x1c0(%R11,%RAX,1),%ZMM2,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x1c0(%R10,%RAX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM8,0x1c0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x200,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 42d817 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x307>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2
Source file and lines	advec_mom.cpp:65-66
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 21.33 to 16.00 cycles (1.33x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 16 occurrences

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 1536 bytes (192 double precision FP elements). The binary loop is storing 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	43
nb uops	58
loop length	330
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	10
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	0.00	0.00	8.00	8.00	16.00	16.00
cycles	0.50	0.50	0.25	0.25	0.50	21.33	21.33	21.33	0.00	0.00	16.00	16.00	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	21.33
Data deps.	1.00
Overall L1	21.33

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.33 cycles. At this rate:

75% of peak load performance is reached (72.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
75% of peak store performance is reached (48.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42d817

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%RAX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM0,(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD (%R11,%RAX,1),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD (%R10,%RAX,1),%ZMM2,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM7,(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%R12,%RAX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM8,0x40(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x40(%R11,%RAX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x40(%R10,%RAX,1),%ZMM9,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM10,0x40(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%R12,%RAX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM11,0x80(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x80(%R11,%RAX,1),%ZMM11,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x80(%R10,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM15,0x80(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R12,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM6,0xc0(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0xc0(%R11,%RAX,1),%ZMM6,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0xc0(%R10,%RAX,1),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM2,0xc0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x100(%R12,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM7,0x100(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x100(%R11,%RAX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x100(%R10,%RAX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM9,0x100(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x140(%R12,%RAX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM10,0x140(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x140(%R11,%RAX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x140(%R10,%RAX,1),%ZMM11,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM14,0x140(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x180(%R12,%RAX,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM15,0x180(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x180(%R11,%RAX,1),%ZMM15,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x180(%R10,%RAX,1),%ZMM6,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM0,0x180(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x1c0(%R12,%RAX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM2,0x1c0(%RBX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VADDPD 0x1c0(%R11,%RAX,1),%ZMM2,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VSUBPD 0x1c0(%R10,%RAX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1
VMOVUPD %ZMM8,0x1c0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x200,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 42d817 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x307>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.76	0.42	0.59	0.75	0.27	1.54	0.22	1.84	0.07	2.23	0.05	2.35	0.03	2.13

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	9	1.44
2x2	4	0.76	1.52	2	5.97	1.72
2x4	8	0.59	2.38	4	4.1	1.85
2x8	16	0.27	2.12	8	4.96	2.1
2x16	32	0.22	3.44	16	2.72	2.35
2x32	64	0.07	2.38	32	4.12	2.41
2x64	128	0.05	2.92	64	3.24	2.46
2x96	192	0.03	3.08	96	2.71	2.2

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency