OV - - Loop 188

	Loop Id: 188	Module: exec	Source: advec_mom.cpp:88-88	Coverage: 0.84%

0x42ebd9 VMOVUPD	(%R12,%RSI,1),%ZMM9    [4]

0x42ebe0 VMOVUPD	(%RDX,%RSI,1),%ZMM14    [3]

0x42ebe7 VADDPD	(%RBX,%RSI,1),%ZMM9,%ZMM13    [2]

0x42ebee VADDPD	(%R13,%RSI,1),%ZMM14,%ZMM15    [1]

0x42ebf6 VADDPD	%ZMM15,%ZMM13,%ZMM7

0x42ebfc VMULPD	%ZMM6,%ZMM7,%ZMM1

0x42ec02 VMOVUPD	%ZMM1,(%R11,%RSI,1)    [5]

0x42ec09 VMOVUPD	0x40(%R12,%RSI,1),%ZMM5    [4]

0x42ec11 VMOVUPD	0x40(%RDX,%RSI,1),%ZMM12    [3]

0x42ec19 VADDPD	0x40(%RBX,%RSI,1),%ZMM5,%ZMM2    [2]

0x42ec21 VADDPD	0x40(%R13,%RSI,1),%ZMM12,%ZMM0    [1]

0x42ec29 VADDPD	%ZMM0,%ZMM2,%ZMM8

0x42ec2f VMULPD	%ZMM6,%ZMM8,%ZMM9

0x42ec35 VMOVUPD	%ZMM9,0x40(%R11,%RSI,1)    [5]

0x42ec3d VMOVUPD	0x80(%R12,%RSI,1),%ZMM13    [4]

0x42ec45 VMOVUPD	0x80(%RDX,%RSI,1),%ZMM15    [3]

0x42ec4d VADDPD	0x80(%RBX,%RSI,1),%ZMM13,%ZMM14    [2]

0x42ec55 VADDPD	0x80(%R13,%RSI,1),%ZMM15,%ZMM7    [1]

0x42ec5d VADDPD	%ZMM7,%ZMM14,%ZMM1

0x42ec63 VMULPD	%ZMM6,%ZMM1,%ZMM5

0x42ec69 VMOVUPD	%ZMM5,0x80(%R11,%RSI,1)    [5]

0x42ec71 VMOVUPD	0xc0(%R12,%RSI,1),%ZMM2    [4]

0x42ec79 VMOVUPD	0xc0(%RDX,%RSI,1),%ZMM12    [3]

0x42ec81 VADDPD	0xc0(%RBX,%RSI,1),%ZMM2,%ZMM0    [2]

0x42ec89 VADDPD	0xc0(%R13,%RSI,1),%ZMM12,%ZMM8    [1]

0x42ec91 VADDPD	%ZMM8,%ZMM0,%ZMM9

0x42ec97 VMULPD	%ZMM6,%ZMM9,%ZMM13

0x42ec9d VMOVUPD	%ZMM13,0xc0(%R11,%RSI,1)    [5]

0x42eca5 ADD	$0x100,%RSI

0x42ecac CMP	%RSI,%R9

0x42ecaf JNE	42ebd9

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 88 - 88

--------------------------------------------------------------------------------

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.12
Bottlenecks	P5, P6, P7, P10, P11,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4
Source	advec_mom.cpp:88-88
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	16.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	10.67
Nb FLOP add-sub	96.00
Nb FLOP mul	32.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	106.67
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.12
Bottlenecks	P5, P6, P7, P10, P11,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4
Source	advec_mom.cpp:88-88
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	16.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	10.67
Nb FLOP add-sub	96.00
Nb FLOP mul	32.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	106.67
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4
Source file and lines	advec_mom.cpp:88-88
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:88.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 5.67 cycles (2.12x speedup).

Workaround

Reduce the number of FP add instructions
Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

96: addition or subtraction
32: multiply

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	31
nb uops	34
loop length	220
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	6.67	6.67	6.67	2.00	2.00	6.00	6.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	12.00	12.00	12.00	4.00	4.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

88% of peak load performance is reached (85.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (21.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ebd9

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%RSI,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RDX,%RSI,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%RBX,%RSI,1),%ZMM9,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%R13,%RSI,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM15,%ZMM13,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM1,(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%R12,%RSI,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%RDX,%RSI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%RBX,%RSI,1),%ZMM5,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R13,%RSI,1),%ZMM12,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM9,0x40(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x80(%R12,%RSI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%RDX,%RSI,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x80(%RBX,%RSI,1),%ZMM13,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%R13,%RSI,1),%ZMM15,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM7,%ZMM14,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM1,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM5,0x80(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0xc0(%R12,%RSI,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%RDX,%RSI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0xc0(%RBX,%RSI,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R13,%RSI,1),%ZMM12,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM8,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM9,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM13,0xc0(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x100,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 42ebd9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x239>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4
Source file and lines	advec_mom.cpp:88-88
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 5.67 cycles (2.12x speedup).

Workaround

Reduce the number of FP add instructions
Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

96: addition or subtraction
32: multiply

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	31
nb uops	34
loop length	220
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	6.67	6.67	6.67	2.00	2.00	6.00	6.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	12.00	12.00	12.00	4.00	4.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

88% of peak load performance is reached (85.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (21.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ebd9

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%RSI,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RDX,%RSI,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%RBX,%RSI,1),%ZMM9,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%R13,%RSI,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM15,%ZMM13,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM1,(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%R12,%RSI,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%RDX,%RSI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%RBX,%RSI,1),%ZMM5,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R13,%RSI,1),%ZMM12,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM9,0x40(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x80(%R12,%RSI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%RDX,%RSI,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x80(%RBX,%RSI,1),%ZMM13,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%R13,%RSI,1),%ZMM15,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM7,%ZMM14,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM1,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM5,0x80(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0xc0(%R12,%RSI,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%RDX,%RSI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0xc0(%RBX,%RSI,1),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R13,%RSI,1),%ZMM12,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM8,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM9,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM13,0xc0(%R11,%RSI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x100,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 42ebd9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x239>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.81	0.18	0.65	0.35	0.3	0.75	0.25	0.89	0.09	1.1	0.05	1.17	0.04	1.08

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	5.26	0.84
2x2	4	0.81	1.61	2	3.27	0.94
2x4	8	0.65	2.59	4	2.16	1
2x8	16	0.3	2.42	8	2.49	1.07
2x16	32	0.25	3.98	16	1.39	1.19
2x32	64	0.09	2.79	32	2.05	1.21
2x64	128	0.05	3.39	64	1.65	1.24
2x96	192	0.04	3.55	96	1.39	1.12

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency