OV - - Loop 200

	Loop Id: 200	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage: 6.83%

0x430ad0 MOV	-0x38(%RBP),%RSI    [7]

0x430ad4 MOVSXD	%R10D,%RAX

0x430ad7 MOV	%RBX,%R9

0x430ada MOVSXD	%R10D,%RDI

0x430add VMOVQ	%XMM13,%R12

0x430ae2 IMUL	%R15,%RAX

0x430ae6 VMOVQ	%XMM17,%R11

0x430aec IMUL	%RSI,%R12

0x430af0 IMUL	%R15,%R9

0x430af4 IMUL	%R15,%RSI

0x430af8 ADD	%RDX,%RAX

0x430afb ADD	%RDX,%R12

0x430afe ADD	%RDX,%R9

0x430b01 VMOVSD	(%R11,%R12,8),%XMM19    [5]

0x430b08 VMOVQ	%XMM20,%R12

0x430b0e ADD	%RDX,%RSI

0x430b11 VMOVSD	(%R14,%R9,8),%XMM1    [10]

0x430b17 VMOVSD	(%R12),%XMM4    [1]

0x430b1d VMOVSD	(%R14,%RSI,8),%XMM0    [8]

0x430b23 VSUBSD	(%R14,%RAX,8),%XMM0,%XMM2    [9]

0x430b29 VSUBSD	%XMM0,%XMM1,%XMM11

0x430b2d VMULSD	%XMM2,%XMM11,%XMM3

0x430b31 VCOMISD	%XMM5,%XMM3

0x430b35 JBE	430bc6

0x430b3b VCOMISD	%XMM11,%XMM5

0x430b40 JAE	430c20

0x430b46 VMOVSD	%XMM14,%XMM14,%XMM25

0x430b4c VMOVSD	%XMM14,%XMM14,%XMM26

0x430b52 VUNPCKLPD	%XMM2,%XMM11,%XMM1

0x430b56 VANDPD	%XMM16,%XMM23,%XMM28

0x430b5c VMOVDDUP	0x2f24c(%RIP),%XMM2    [6]

0x430b64 VMOVQ	%XMM18,%R9

0x430b6a VANDPD	%XMM2,%XMM1,%XMM11

0x430b6e VDIVSD	%XMM19,%XMM28,%XMM24

0x430b74 VMOVDDUP	%XMM24,%XMM3

0x430b7a VADDSUBPD	%XMM3,%XMM6,%XMM1

0x430b7e VMOVHPD	(%R9,%RDI,8),%XMM4,%XMM3    [3]

0x430b84 VSUBSD	%XMM24,%XMM25,%XMM30

0x430b8a VMULSD	%XMM15,%XMM4,%XMM4

0x430b8f VMULSD	%XMM26,%XMM30,%XMM31

0x430b95 VUNPCKHPD	%XMM11,%XMM11,%XMM19

0x430b9b VMULPD	%XMM1,%XMM11,%XMM2

0x430b9f VMINSD	%XMM11,%XMM19,%XMM11

0x430ba5 VDIVPD	%XMM3,%XMM2,%XMM1

0x430ba9 VUNPCKHPD	%XMM1,%XMM1,%XMM27

0x430baf VADDPD	%XMM1,%XMM27,%XMM29

0x430bb5 VMULSD	%XMM29,%XMM4,%XMM3

0x430bbb VMINSD	%XMM11,%XMM3,%XMM1

0x430bc0 VFMADD231SD	%XMM1,%XMM31,%XMM0

0x430bc6 VMOVQ	%XMM12,%RSI

0x430bcb VMULSD	%XMM23,%XMM0,%XMM0

0x430bd1 VMOVSD	%XMM0,(%R8,%RDX,8)    [4]

0x430bd7 MOV	%RCX,%RDX

0x430bda CMP	%RSI,%RCX

0x430bdd JE	430c40

0x430bdf INC	%RCX

0x430be2 VMOVSD	(%R13,%RDX,8),%XMM23    [2]

0x430bea VCOMISD	%XMM23,%XMM5

0x430bf0 JBE	430ad0

0x430bf6 MOVSXD	-0x40(%RBP),%RAX    [7]

0x430bfa MOV	-0x38(%RBP),%R9    [7]

0x430bfe MOVSXD	-0x3c(%RBP),%RDI    [7]

0x430c02 MOV	%RBX,%RSI

0x430c05 JMP	430add

0x430c20 MOV	0x2fbb1(%RIP),%RAX    [6]

0x430c27 VMOVSD	%XMM21,%XMM21,%XMM26

0x430c2d VMOVQ	%RAX,%XMM25

0x430c33 JMP	430b52

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

[...]

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	2.80
CQA speedup if fully vectorized	3.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10
Source	advec_mom.cpp:180-180,advec_mom.cpp:186-211,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.83
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	4.23
CQA cycles if fully vectorized	3.75
Front-end cycles	11.83
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	4.50
P3 cycles	3.00
P4 cycles	4.67
P5 cycles	4.67
P6 cycles	4.67
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.17
P10 cycles	7.33
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	10.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	71.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.61
Nb FLOP add-sub	7.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.79
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	13.95
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	16.67
Vectorization ratio add_sub	40.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	9.52
Vector-efficiency ratio all	14.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	14.58
Vector-efficiency ratio add_sub	17.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	18.75
Vector-efficiency ratio other	13.69

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	2.80
CQA speedup if fully vectorized	3.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10
Source	advec_mom.cpp:180-180,advec_mom.cpp:186-211,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.83
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	4.23
CQA cycles if fully vectorized	3.75
Front-end cycles	11.83
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	4.50
P3 cycles	3.00
P4 cycles	4.67
P5 cycles	4.67
P6 cycles	4.67
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.17
P10 cycles	7.33
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	10.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	71.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.61
Nb FLOP add-sub	7.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.79
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	13.95
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	16.67
Vectorization ratio add_sub	40.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	9.52
Vector-efficiency ratio all	14.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	14.58
Vector-efficiency ratio add_sub	17.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	18.75
Vector-efficiency ratio other	13.69

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10
Source file and lines	advec_mom.cpp:180-211
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:180,186-211
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.83 to 10.00 cycles (1.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.83 to 3.75 cycles (3.16x speedup).

Details

13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
40% of SSE/AVX addition or subtraction instructions are used in vector version.
16% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX divide and square root instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 3 occurrences

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

8: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
3: divide

The binary loop is loading 96 bytes (12 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	71
loop length	338
used x86 registers	15
used mmx registers	0
used xmm registers	27
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.83

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.83 cycles
front end	11.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.50	4.50	3.00	4.67	4.67	4.67	7.25	7.25	7.17	7.33	4.50	4.50
cycles	4.50	4.50	4.50	4.50	3.00	4.67	4.67	4.67	7.25	7.25	7.17	7.33	4.50	4.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	11.83
Dispatch	7.33
DIV/SQRT	10.00
Overall L1	11.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	16%
load	0%
store	0%
mul	16%
add-sub	40%
fma	0%
div/sqrt	50%
other	14%

INT+FP

all	13%
load	0%
store	0%
mul	16%
add-sub	40%
fma	0%
div/sqrt	50%
other	9%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	14%
add-sub	17%
fma	12%
div/sqrt	18%
other	14%

INT+FP

all	14%
load	12%
store	12%
mul	14%
add-sub	17%
fma	12%
div/sqrt	18%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.83 cycles. At this rate:

8% of peak load performance is reached (8.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.68 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 430be2

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %R10D,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %R10D,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
IMUL %R15,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVQ %XMM17,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
IMUL %RSI,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R15,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11,%R12,8),%XMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM20,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R14,%R9,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R12),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R14,%RSI,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R14,%RAX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM0,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM2,%XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VCOMISD %XMM5,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 430bc6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VCOMISD %XMM11,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JAE 430c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM14,%XMM14,%XMM25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD %XMM14,%XMM14,%XMM26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VUNPCKLPD %XMM2,%XMM11,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VANDPD %XMM16,%XMM23,%XMM28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVDDUP 0x2f24c(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM18,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VANDPD %XMM2,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VDIVSD %XMM19,%XMM28,%XMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVDDUP %XMM24,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSUBPD %XMM3,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVHPD (%R9,%RDI,8),%XMM4,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VSUBSD %XMM24,%XMM25,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM15,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM26,%XMM30,%XMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VUNPCKHPD %XMM11,%XMM11,%XMM19	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMULPD %XMM1,%XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMINSD %XMM11,%XMM19,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VDIVPD %XMM3,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VUNPCKHPD %XMM1,%XMM1,%XMM27	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM1,%XMM27,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM29,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMINSD %XMM11,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VFMADD231SD %XMM1,%XMM31,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVQ %XMM12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULSD %XMM23,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM0,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 430c40 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R13,%RDX,8),%XMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VCOMISD %XMM23,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 430ad0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD -0x40(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD -0x3c(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 430add <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x1dd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x2fbb1(%RIP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM21,%XMM21,%XMM26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %RAX,%XMM25	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
JMP 430b52 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x252>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10
Source file and lines	advec_mom.cpp:180-211
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:180,186-211
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
40% of SSE/AVX addition or subtraction instructions are used in vector version.
16% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX divide and square root instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 3 occurrences

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

8: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
3: divide

The binary loop is loading 96 bytes (12 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	71
loop length	338
used x86 registers	15
used mmx registers	0
used xmm registers	27
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.83

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.83 cycles
front end	11.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.50	4.50	3.00	4.67	4.67	4.67	7.25	7.25	7.17	7.33	4.50	4.50
cycles	4.50	4.50	4.50	4.50	3.00	4.67	4.67	4.67	7.25	7.25	7.17	7.33	4.50	4.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	11.83
Dispatch	7.33
DIV/SQRT	10.00
Overall L1	11.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	16%
load	0%
store	0%
mul	16%
add-sub	40%
fma	0%
div/sqrt	50%
other	14%

INT+FP

all	13%
load	0%
store	0%
mul	16%
add-sub	40%
fma	0%
div/sqrt	50%
other	9%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	14%
add-sub	17%
fma	12%
div/sqrt	18%
other	14%

INT+FP

all	14%
load	12%
store	12%
mul	14%
add-sub	17%
fma	12%
div/sqrt	18%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.83 cycles. At this rate:

8% of peak load performance is reached (8.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.68 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 430be2

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %R10D,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %R10D,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
IMUL %R15,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
VMOVQ %XMM17,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
IMUL %RSI,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R15,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11,%R12,8),%XMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM20,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R14,%R9,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R12),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R14,%RSI,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R14,%RAX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM0,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM2,%XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VCOMISD %XMM5,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 430bc6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VCOMISD %XMM11,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JAE 430c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM14,%XMM14,%XMM25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD %XMM14,%XMM14,%XMM26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VUNPCKLPD %XMM2,%XMM11,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VANDPD %XMM16,%XMM23,%XMM28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVDDUP 0x2f24c(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM18,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VANDPD %XMM2,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VDIVSD %XMM19,%XMM28,%XMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVDDUP %XMM24,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSUBPD %XMM3,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVHPD (%R9,%RDI,8),%XMM4,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VSUBSD %XMM24,%XMM25,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM15,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM26,%XMM30,%XMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VUNPCKHPD %XMM11,%XMM11,%XMM19	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMULPD %XMM1,%XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMINSD %XMM11,%XMM19,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VDIVPD %XMM3,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VUNPCKHPD %XMM1,%XMM1,%XMM27	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM1,%XMM27,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM29,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMINSD %XMM11,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VFMADD231SD %XMM1,%XMM31,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVQ %XMM12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULSD %XMM23,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM0,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 430c40 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R13,%RDX,8),%XMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VCOMISD %XMM23,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 430ad0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD -0x40(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD -0x3c(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 430add <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x1dd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x2fbb1(%RIP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM21,%XMM21,%XMM26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %RAX,%XMM25	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
JMP 430b52 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x252>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.99	0.04	0.95	0.27	0.66	1.38	0.6	1.6	0.21	3.15	0.14	3.3	0.09	3.34

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	42.76	6.83
2x2	4	0.99	1.99	2	21.56	6.21
2x4	8	0.95	3.8	4	10.84	5.5
2x8	16	0.66	5.26	8	8.58	4.02
2x16	32	0.6	9.6	16	4.66	4.01
2x32	64	0.21	6.82	32	6.83	4
2x64	128	0.14	8.9	64	5.3	3.83
2x96	192	0.09	8.76	96	4.49	3.68

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency