OV - - Loop 230

	Loop Id: 230	Module: exec	Source: flux_calc.cpp:39-40	Coverage: 2.77%

0x43829e VMOVUPD	(%R11,%RDX,1),%ZMM10    [5]

0x4382a5 VMOVUPD	(%R14,%RDX,1),%ZMM11    [15]

0x4382ac VADDPD	(%R12,%RDX,1),%ZMM10,%ZMM30    [7]

0x4382b3 VMOVQ	%XMM9,%R9

0x4382b8 VADDPD	(%R8,%RDX,1),%ZMM11,%ZMM5    [13]

0x4382bf VMULPD	(%RCX,%RDX,1),%ZMM1,%ZMM18    [9]

0x4382c6 VMOVQ	%XMM4,%RSI

0x4382cb VADDPD	%ZMM5,%ZMM30,%ZMM7

0x4382d1 VMULPD	%ZMM18,%ZMM7,%ZMM0

0x4382d7 VMOVUPD	%ZMM0,(%R9,%RDX,1)    [1]

0x4382de VMOVUPD	(%RSI,%RDX,1),%ZMM8    [6]

0x4382e5 VMOVUPD	(%R13,%RDX,1),%ZMM10    [12]

0x4382ed VADDPD	(%RAX,%RDX,1),%ZMM8,%ZMM31    [3]

0x4382f4 VADDPD	(%RDI,%RDX,1),%ZMM10,%ZMM11    [4]

0x4382fb VMOVQ	%XMM3,%R9

0x438300 VMULPD	(%R9,%RDX,1),%ZMM1,%ZMM19    [10]

0x438307 VMOVQ	%XMM2,%RSI

0x43830c VMOVQ	%XMM9,%R9

0x438311 VADDPD	%ZMM11,%ZMM31,%ZMM5

0x438317 VMULPD	%ZMM19,%ZMM5,%ZMM7

0x43831d VMOVUPD	%ZMM7,(%RSI,%RDX,1)    [2]

0x438324 VMOVUPD	0x40(%R11,%RDX,1),%ZMM0    [5]

0x43832c VMOVUPD	0x40(%R14,%RDX,1),%ZMM8    [15]

0x438334 VADDPD	0x40(%R12,%RDX,1),%ZMM0,%ZMM20    [7]

0x43833c VADDPD	0x40(%R8,%RDX,1),%ZMM8,%ZMM10    [13]

0x438344 VMULPD	0x40(%RCX,%RDX,1),%ZMM1,%ZMM21    [9]

0x43834c VMOVQ	%XMM4,%RSI

0x438351 VADDPD	%ZMM10,%ZMM20,%ZMM11

0x438357 VMULPD	%ZMM21,%ZMM11,%ZMM5

0x43835d VMOVUPD	%ZMM5,0x40(%R9,%RDX,1)    [14]

0x438365 VMOVUPD	0x40(%RSI,%RDX,1),%ZMM7    [16]

0x43836d VMOVUPD	0x40(%R13,%RDX,1),%ZMM0    [12]

0x438375 VADDPD	0x40(%RAX,%RDX,1),%ZMM7,%ZMM30    [3]

0x43837d VADDPD	0x40(%RDI,%RDX,1),%ZMM0,%ZMM8    [4]

0x438385 VMOVQ	%XMM3,%R9

0x43838a VMULPD	0x40(%R9,%RDX,1),%ZMM1,%ZMM18    [17]

0x438392 VMOVQ	%XMM2,%RSI

0x438397 VADDPD	%ZMM8,%ZMM30,%ZMM10

0x43839d VMULPD	%ZMM18,%ZMM10,%ZMM11

0x4383a3 VMOVUPD	%ZMM11,0x40(%RSI,%RDX,1)    [11]

0x4383ab SUB	$-0x80,%RDX

0x4383af CMP	%RDX,0x20(%RSP)    [8]

0x4383b4 JNE	43829e

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp: 39 - 40

--------------------------------------------------------------------------------

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P5, P6, P7,
Function	_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source	flux_calc.cpp:39-40
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	15.00
Front-end cycles	7.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	15.00
P5 cycles	15.00
P6 cycles	15.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	46.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	10.67
Nb FLOP add-sub	96.00
Nb FLOP mul	64.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	102.93
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	10.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	82.50
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P5, P6, P7,
Function	_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source	flux_calc.cpp:39-40
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	15.00
Front-end cycles	7.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	15.00
P5 cycles	15.00
P6 cycles	15.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	46.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	10.67
Nb FLOP add-sub	96.00
Nb FLOP mul	64.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	102.93
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	10.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	82.50
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source file and lines	flux_calc.cpp:39-40
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:39-40.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all SSE/AVX instructions).

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 12.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction
64: multiply

The binary loop is loading 1288 bytes (161 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	43
nb uops	46
loop length	284
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	13
nb stack references	1
ADD-SUB / MUL ratio	1.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.33	8.33	8.33	4.00	4.00	6.00	6.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	15.00	15.00	15.00	8.00	8.00	12.00	12.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	15.00
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	80%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	82%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

89% of peak load performance is reached (85.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (17.07 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43829e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R11,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R14,%RDX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R12,%RDX,1),%ZMM10,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R8,%RDX,1),%ZMM11,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMULPD (%RCX,%RDX,1),%ZMM1,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM5,%ZMM30,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM18,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM0,(%R9,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD (%RSI,%RDX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R13,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%RAX,%RDX,1),%ZMM8,%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%RDI,%RDX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM3,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD (%R9,%RDX,1),%ZMM1,%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM2,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM11,%ZMM31,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM19,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM7,(%RSI,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%R11,%RDX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%R14,%RDX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%R12,%RDX,1),%ZMM0,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R8,%RDX,1),%ZMM8,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMULPD 0x40(%RCX,%RDX,1),%ZMM1,%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM10,%ZMM20,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM21,%ZMM11,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM5,0x40(%R9,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%R13,%RDX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%RAX,%RDX,1),%ZMM7,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%RDI,%RDX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM3,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD 0x40(%R9,%RDX,1),%ZMM1,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM2,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM8,%ZMM30,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM18,%ZMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM11,0x40(%RSI,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,0x20(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 43829e <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source file and lines	flux_calc.cpp:39-40
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all SSE/AVX instructions).

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 12.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction
64: multiply

The binary loop is loading 1288 bytes (161 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	43
nb uops	46
loop length	284
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	13
nb stack references	1
ADD-SUB / MUL ratio	1.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.33	8.33	8.33	4.00	4.00	6.00	6.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	15.00	15.00	15.00	8.00	8.00	12.00	12.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	15.00
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	80%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	82%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

89% of peak load performance is reached (85.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (17.07 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43829e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R11,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R14,%RDX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R12,%RDX,1),%ZMM10,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R8,%RDX,1),%ZMM11,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMULPD (%RCX,%RDX,1),%ZMM1,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM5,%ZMM30,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM18,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM0,(%R9,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD (%RSI,%RDX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R13,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%RAX,%RDX,1),%ZMM8,%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%RDI,%RDX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM3,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD (%R9,%RDX,1),%ZMM1,%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM2,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM11,%ZMM31,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM19,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM7,(%RSI,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%R11,%RDX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%R14,%RDX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%R12,%RDX,1),%ZMM0,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R8,%RDX,1),%ZMM8,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMULPD 0x40(%RCX,%RDX,1),%ZMM1,%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM10,%ZMM20,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM21,%ZMM11,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM5,0x40(%R9,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%R13,%RDX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD 0x40(%RAX,%RDX,1),%ZMM7,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%RDI,%RDX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM3,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD 0x40(%R9,%RDX,1),%ZMM1,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM2,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM8,%ZMM30,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM18,%ZMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD %ZMM11,0x40(%RSI,%RDX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,0x20(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 43829e <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.86	0.42	0.67	1.02	0.3	2.5	0.25	2.95	0.09	3.59	0.06	3.35	0.04	3.06

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	17.36	2.77
2x2	4	0.86	1.71	2	10.11	2.92
2x4	8	0.67	2.7	4	6.76	3.14
2x8	16	0.3	2.4	8	8.54	3.57
2x16	32	0.25	3.97	16	4.58	3.92
2x32	64	0.09	2.81	32	6.67	3.94
2x64	128	0.06	3.86	64	4.96	3.57
2x96	192	0.04	4.07	96	4.05	3.2

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency