OV - - Loop 270

	Loop Id: 270	Module: exec	Source: PdV.cpp:55-63 [...]	Coverage: 3.98%

0x440a00 VMOVQ	%XMM13,%RSI

0x440a05 VMOVUPD	(%R12,%RAX,1),%ZMM3    [5]

0x440a0c VMOVUPD	(%R15,%RAX,1),%ZMM7    [13]

0x440a13 VMOVUPD	(%R8,%RAX,1),%ZMM5    [11]

0x440a1a VMOVUPD	(%RSI,%RAX,1),%ZMM1    [8]

0x440a21 VADDPD	(%R11,%RAX,1),%ZMM1,%ZMM2    [16]

0x440a28 VADDPD	(%R10,%RAX,1),%ZMM5,%ZMM4    [6]

0x440a2f VMOVQ	%XMM24,%RSI

0x440a35 VMOVUPD	(%RSI,%RAX,1),%ZMM5    [14]

0x440a3c VMOVQ	%XMM23,%RSI

0x440a42 VADDPD	(%R14,%RAX,1),%ZMM5,%ZMM1    [12]

0x440a49 VADDPD	%ZMM3,%ZMM3,%ZMM6

0x440a4f VADDPD	%ZMM7,%ZMM7,%ZMM3

0x440a55 VMOVUPD	(%RBX,%RAX,1),%ZMM7    [2]

0x440a5c VMULPD	%ZMM6,%ZMM2,%ZMM2

0x440a62 VMOVUPD	(%RSI,%RAX,1),%ZMM6    [1]

0x440a69 VADDPD	(%R13,%RAX,1),%ZMM6,%ZMM5    [3]

0x440a71 VMOVQ	%XMM15,%RSI

0x440a76 VADDPD	%ZMM7,%ZMM7,%ZMM6

0x440a7c VMULPD	%ZMM6,%ZMM5,%ZMM7

0x440a82 VMOVUPD	(%RSI,%RAX,1),%ZMM5    [7]

0x440a89 VMOVQ	%XMM9,%RSI

0x440a8e VFMADD231PD	%ZMM1,%ZMM3,%ZMM7

0x440a94 VMOVUPD	(%R9,%RAX,1),%ZMM3    [15]

0x440a9b VADDPD	%ZMM3,%ZMM3,%ZMM1

0x440aa1 VADDPD	(%RDI,%RAX,1),%ZMM5,%ZMM3    [17]

0x440aa8 VFMADD132PD	%ZMM4,%ZMM2,%ZMM1

0x440aae VSUBPD	%ZMM1,%ZMM7,%ZMM4

0x440ab4 VMOVUPD	(%RCX,%RAX,1),%ZMM7    [10]

0x440abb VDIVPD	(%RDX,%RAX,1),%ZMM3,%ZMM1    [9]

0x440ac2 VMULPD	%ZMM12,%ZMM4,%ZMM6

0x440ac8 VADDPD	(%RCX,%RAX,1),%ZMM6,%ZMM2    [10]

0x440acf VDIVPD	%ZMM2,%ZMM7,%ZMM4

0x440ad5 VDIVPD	%ZMM7,%ZMM11,%ZMM2

0x440adb VMULPD	%ZMM2,%ZMM1,%ZMM7

0x440ae1 VFNMADD213PD	(%RSI,%RAX,1),%ZMM7,%ZMM6    [4]

0x440ae8 VMOVQ	%XMM8,%RSI

0x440aed VMOVUPD	%ZMM6,(%RSI,%RAX,1)    [19]

0x440af4 VMULPD	(%RDX,%RAX,1),%ZMM4,%ZMM6    [9]

0x440afb VMOVQ	%XMM26,%RSI

0x440b01 VMOVUPD	%ZMM6,(%RSI,%RAX,1)    [18]

0x440b08 MOV	0x130(%RSP),%RSI    [20]

0x440b10 ADD	$0x40,%RAX

0x440b14 CMP	%RSI,%RAX

0x440b17 JNE	440a00

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 55 - 63

--------------------------------------------------------------------------------

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.98
Bottlenecks	P8, P9,
Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source	context.h:69-69,PdV.cpp:55-63
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	27.00
Front-end cycles	7.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	13.67
P5 cycles	13.67
P6 cycles	13.67
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	5.50
P12 cycles	5.50
P13 cycles	27.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	46.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	7.41
Nb FLOP add-sub	88.00
Nb FLOP mul	40.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	50.07
Bytes prefetched	0.00
Bytes loaded	1224.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	10.00
Stride n	2.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	82.93
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	85.06
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.98
Bottlenecks	P8, P9,
Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source	context.h:69-69,PdV.cpp:55-63
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	27.00
Front-end cycles	7.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	13.67
P5 cycles	13.67
P6 cycles	13.67
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	5.50
P12 cycles	5.50
P13 cycles	27.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	46.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	7.41
Nb FLOP add-sub	88.00
Nb FLOP mul	40.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	50.07
Bytes prefetched	0.00
Bytes loaded	1224.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	10.00
Stride n	2.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	82.93
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	85.06
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source file and lines	PdV.cpp:55-63
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:55-63

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all SSE/AVX instructions).

Details

82% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 13.67 cycles (1.98x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 13.00 cycles (2.08x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

112: addition or subtraction (24 inside FMA instructions)
64: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1224 bytes (153 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	46
loop length	285
used x86 registers	15
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	9
nb stack references	1
ADD-SUB / MUL ratio	2.20

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	7.33	7.33	7.33	5.50	5.50	5.50	5.50	5.50	5.50
cycles	0.50	0.50	0.25	0.25	0.50	13.67	13.67	13.67	11.00	11.00	11.00	11.00	5.50	5.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	27.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	13.67
DIV/SQRT	27.00
Data deps.	1.00
Overall L1	27.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	82%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

47% of peak load performance is reached (45.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.74 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 440a00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%R12,%RAX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R15,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R8,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RSI,%RAX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R11,%RAX,1),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%R10,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM24,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RSI,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM23,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R14,%RAX,1),%ZMM5,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM3,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM7,%ZMM7,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RBX,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM6,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD (%RSI,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R13,%RAX,1),%ZMM6,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM7,%ZMM7,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD (%RSI,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VFMADD231PD %ZMM1,%ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVUPD (%R9,%RAX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD %ZMM3,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%RDI,%RAX,1),%ZMM5,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VFMADD132PD %ZMM4,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM1,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VDIVPD (%RDX,%RAX,1),%ZMM3,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	9
VMULPD %ZMM12,%ZMM4,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VADDPD (%RCX,%RAX,1),%ZMM6,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD %ZMM2,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM7,%ZMM11,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMULPD %ZMM2,%ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFNMADD213PD (%RSI,%RAX,1),%ZMM7,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RSI,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD (%RDX,%RAX,1),%ZMM4,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM26,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RSI,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
MOV 0x130(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 440a00 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0
Source file and lines	PdV.cpp:55-63
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:55-63

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all SSE/AVX instructions).

Details

82% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 13.00 cycles (2.08x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

112: addition or subtraction (24 inside FMA instructions)
64: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1224 bytes (153 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	46
loop length	285
used x86 registers	15
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	9
nb stack references	1
ADD-SUB / MUL ratio	2.20

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	7.33	7.33	7.33	5.50	5.50	5.50	5.50	5.50	5.50
cycles	0.50	0.50	0.25	0.25	0.50	13.67	13.67	13.67	11.00	11.00	11.00	11.00	5.50	5.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	27.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	13.67
DIV/SQRT	27.00
Data deps.	1.00
Overall L1	27.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	82%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

47% of peak load performance is reached (45.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.74 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 440a00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%R12,%RAX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R15,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R8,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RSI,%RAX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R11,%RAX,1),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%R10,%RAX,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM24,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD (%RSI,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM23,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD (%R14,%RAX,1),%ZMM5,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM3,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM7,%ZMM7,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RBX,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM6,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD (%RSI,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD (%R13,%RAX,1),%ZMM6,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VADDPD %ZMM7,%ZMM7,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM6,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVUPD (%RSI,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VFMADD231PD %ZMM1,%ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVUPD (%R9,%RAX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VADDPD %ZMM3,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD (%RDI,%RAX,1),%ZMM5,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VFMADD132PD %ZMM4,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM1,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD (%RCX,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VDIVPD (%RDX,%RAX,1),%ZMM3,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	9
VMULPD %ZMM12,%ZMM4,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VADDPD (%RCX,%RAX,1),%ZMM6,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VDIVPD %ZMM2,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VDIVPD %ZMM7,%ZMM11,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VMULPD %ZMM2,%ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFNMADD213PD (%RSI,%RAX,1),%ZMM7,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RSI,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD (%RDX,%RAX,1),%ZMM4,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM26,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVUPD %ZMM6,(%RSI,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
MOV 0x130(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 440a00 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.9	0.38	0.72	1.17	0.33	3.19	0.27	3.72	0.1	4.6	0.07	4.2	0.05	3.88

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	24.87	3.98
2x2	4	0.9	1.81	2	13.8	3.98
2x4	8	0.72	2.89	4	8.94	4.22
2x8	16	0.33	2.6	8	11.34	4.73
2x16	32	0.27	4.38	16	6.07	5.12
2x32	64	0.1	3.12	32	8.64	5.1
2x64	128	0.07	4.41	64	6.34	4.51
2x96	192	0.05	4.6	96	5.28	4.08

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency