OV - - Loop 282

	Loop Id: 282	Module: exec	Source: revert.cpp:37-38	Coverage: 1.44%

0x44333e VMOVUPD	(%R11,%RAX,1),%ZMM7    [2]

0x443345 VMOVUPD	%ZMM7,(%R10,%RAX,1)    [3]

0x44334c VMOVUPD	(%R9,%RAX,1),%ZMM0    [4]

0x443353 VMOVUPD	%ZMM0,(%RDX,%RAX,1)    [1]

0x44335a VMOVUPD	0x40(%R11,%RAX,1),%ZMM8    [2]

0x443362 VMOVUPD	%ZMM8,0x40(%R10,%RAX,1)    [3]

0x44336a VMOVUPD	0x40(%R9,%RAX,1),%ZMM9    [4]

0x443372 VMOVUPD	%ZMM9,0x40(%RDX,%RAX,1)    [1]

0x44337a VMOVUPD	0x80(%R11,%RAX,1),%ZMM10    [2]

0x443382 VMOVUPD	%ZMM10,0x80(%R10,%RAX,1)    [3]

0x44338a VMOVUPD	0x80(%R9,%RAX,1),%ZMM11    [4]

0x443392 VMOVUPD	%ZMM11,0x80(%RDX,%RAX,1)    [1]

0x44339a VMOVUPD	0xc0(%R11,%RAX,1),%ZMM12    [2]

0x4433a2 VMOVUPD	%ZMM12,0xc0(%R10,%RAX,1)    [3]

0x4433aa VMOVUPD	0xc0(%R9,%RAX,1),%ZMM13    [4]

0x4433b2 VMOVUPD	%ZMM13,0xc0(%RDX,%RAX,1)    [1]

0x4433ba VMOVUPD	0x100(%R11,%RAX,1),%ZMM14    [2]

0x4433c2 VMOVUPD	%ZMM14,0x100(%R10,%RAX,1)    [3]

0x4433ca VMOVUPD	0x100(%R9,%RAX,1),%ZMM15    [4]

0x4433d2 VMOVUPD	%ZMM15,0x100(%RDX,%RAX,1)    [1]

0x4433da VMOVUPD	0x140(%R11,%RAX,1),%ZMM5    [2]

0x4433e2 VMOVUPD	%ZMM5,0x140(%R10,%RAX,1)    [3]

0x4433ea VMOVUPD	0x140(%R9,%RAX,1),%ZMM6    [4]

0x4433f2 VMOVUPD	%ZMM6,0x140(%RDX,%RAX,1)    [1]

0x4433fa VMOVUPD	0x180(%R11,%RAX,1),%ZMM7    [2]

0x443402 VMOVUPD	%ZMM7,0x180(%R10,%RAX,1)    [3]

0x44340a VMOVUPD	0x180(%R9,%RAX,1),%ZMM0    [4]

0x443412 VMOVUPD	%ZMM0,0x180(%RDX,%RAX,1)    [1]

0x44341a VMOVUPD	0x1c0(%R11,%RAX,1),%ZMM8    [2]

0x443422 VMOVUPD	%ZMM8,0x1c0(%R10,%RAX,1)    [3]

0x44342a VMOVUPD	0x1c0(%R9,%RAX,1),%ZMM9    [4]

0x443432 VMOVUPD	%ZMM9,0x1c0(%RDX,%RAX,1)    [1]

0x44343a ADD	$0x200,%RAX

0x443440 CMP	%RAX,%R15

0x443443 JNE	44333e

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 37 - 38

--------------------------------------------------------------------------------

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.92
Bottlenecks	P5, P6, P7, P12, P13,
Function	_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source	revert.cpp:37-38
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	8.33
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	16.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	50.00
Nb loads	16.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	128.00
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	1024.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.92
Bottlenecks	P5, P6, P7, P12, P13,
Function	_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source	revert.cpp:37-38
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	8.33
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	16.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	50.00
Nb loads	16.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	128.00
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	1024.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source file and lines	revert.cpp:37-38
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp:37-38.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 16 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 1024 bytes. The binary loop is storing 1024 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	35
nb uops	50
loop length	267
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	16.00	16.00
cycles	0.50	0.50	0.25	0.25	0.50	16.00	16.00	16.00	0.00	0.00	0.00	0.00	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.33
Dispatch	16.00
Data deps.	1.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

66% of peak load performance is reached (64.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (64.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44333e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R11,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM7,(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD (%R9,%RAX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM0,(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x40(%R11,%RAX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM8,0x40(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x40(%R9,%RAX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM9,0x40(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x80(%R11,%RAX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM10,0x80(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x80(%R9,%RAX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM11,0x80(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0xc0(%R11,%RAX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM12,0xc0(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0xc0(%R9,%RAX,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x100(%R11,%RAX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM14,0x100(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x100(%R9,%RAX,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM15,0x100(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x140(%R11,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM5,0x140(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x140(%R9,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM6,0x140(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x180(%R11,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM7,0x180(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x180(%R9,%RAX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM0,0x180(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM8,0x1c0(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM9,0x1c0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
ADD $0x200,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 44333e <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x2be>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0
Source file and lines	revert.cpp:37-38
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 16 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 1024 bytes. The binary loop is storing 1024 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	35
nb uops	50
loop length	267
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	16.00	16.00
cycles	0.50	0.50	0.25	0.25	0.50	16.00	16.00	16.00	0.00	0.00	0.00	0.00	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.33
Dispatch	16.00
Data deps.	1.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

66% of peak load performance is reached (64.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (64.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44333e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R11,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM7,(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD (%R9,%RAX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM0,(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x40(%R11,%RAX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM8,0x40(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x40(%R9,%RAX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM9,0x40(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x80(%R11,%RAX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM10,0x80(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x80(%R9,%RAX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM11,0x80(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0xc0(%R11,%RAX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM12,0xc0(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0xc0(%R9,%RAX,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x100(%R11,%RAX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM14,0x100(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x100(%R9,%RAX,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM15,0x100(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x140(%R11,%RAX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM5,0x140(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x140(%R9,%RAX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM6,0x140(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x180(%R11,%RAX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM7,0x180(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x180(%R9,%RAX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM0,0x180(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM8,0x1c0(%R10,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD %ZMM9,0x1c0(%RDX,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	1	1	5	2
ADD $0x200,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 44333e <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x2be>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.75	0.43	0.58	0.79	0.26	1.61	0.21	1.91	0.07	2.29	0.04	2.4	0.03	2.18

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	8.99	1.44
2x2	4	0.75	1.5	2	6.02	1.73
2x4	8	0.58	2.34	4	4.21	1.89
2x8	16	0.26	2.05	8	5.15	2.17
2x16	32	0.21	3.34	16	2.83	2.42
2x32	64	0.07	2.33	32	4.18	2.47
2x64	128	0.04	2.86	64	3.32	2.51
2x96	192	0.03	3.02	96	2.77	2.25

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency