OV - - Loop 586

	Loop Id: 586	Module: exec	Source: viscosity.cpp:39-64 [...]	Coverage: 13.13%

0x45eb20 VANDPD	%XMM14,%XMM4,%XMM5

0x45eb25 VCOMISD	%XMM4,%XMM9

0x45eb29 VMAXSD	%XMM13,%XMM5,%XMM0

0x45eb2e JA	45ed30

0x45eb34 VMOVSD	%XMM19,%XMM19,%XMM4

0x45eb3a MOV	-0x48(%RBP),%R8    [14]

0x45eb3e VANDPD	%XMM14,%XMM1,%XMM1

0x45eb43 IMUL	(%R14),%R8    [3]

0x45eb47 VMAXSD	%XMM13,%XMM1,%XMM6

0x45eb4c VMULSD	%XMM4,%XMM6,%XMM8

0x45eb50 VMULSD	%XMM8,%XMM8,%XMM5

0x45eb55 VFMADD231SD	%XMM0,%XMM0,%XMM5

0x45eb5a VSQRTSD	%XMM5,%XMM5,%XMM5

0x45eb5e VMULSD	%XMM3,%XMM5,%XMM3

0x45eb62 VMULSD	%XMM7,%XMM5,%XMM7

0x45eb66 VDIVSD	%XMM8,%XMM3,%XMM4

0x45eb6b VDIVSD	%XMM0,%XMM7,%XMM0

0x45eb6f VANDPD	%XMM14,%XMM4,%XMM1

0x45eb74 VANDPD	%XMM14,%XMM0,%XMM6

0x45eb79 ADD	%RAX,%R8

0x45eb7c MOV	0x10(%R14),%RAX    [3]

0x45eb80 VMINSD	%XMM6,%XMM1,%XMM8

0x45eb84 VMULSD	%XMM2,%XMM8,%XMM2

0x45eb88 VMULSD	%XMM2,%XMM2,%XMM3

0x45eb8c VMOVSD	(%RAX,%R8,8),%XMM5    [5]

0x45eb92 MOV	%RDX,%RAX

0x45eb95 VADDSD	%XMM5,%XMM5,%XMM4

0x45eb99 VMULSD	%XMM3,%XMM4,%XMM1

0x45eb9d VMOVSD	%XMM1,(%R10)    [15]

0x45eba2 CMP	%RDX,-0x38(%RBP)    [14]

0x45eba6 JE	45ecf7

0x45ebac INC	%RDX

0x45ebaf VMOVSD	0x8(%R15,%RAX,8),%XMM0    [6]

0x45ebb6 VMOVSD	(%RCX,%RAX,8),%XMM6    [7]

0x45ebbb VMOVSD	(%R15,%RAX,8),%XMM1    [6]

0x45ebc1 VMOVSD	0x8(%RDI,%RAX,8),%XMM7    [11]

0x45ebc7 VADDSD	%XMM0,%XMM1,%XMM27

0x45ebcd VADDSD	%XMM6,%XMM1,%XMM5

0x45ebd1 VMOVSD	0x8(%RCX,%RAX,8),%XMM4    [7]

0x45ebd7 VMOVSD	(%R9,%RAX,8),%XMM1    [8]

0x45ebdd VADDSD	%XMM4,%XMM0,%XMM3

0x45ebe1 VMOVSD	0x8(%R9,%RAX,8),%XMM2    [8]

0x45ebe8 VSUBSD	%XMM5,%XMM3,%XMM0

0x45ebec VADDSD	%XMM2,%XMM7,%XMM8

0x45ebf0 VMOVSD	(%RDI,%RAX,8),%XMM5    [11]

0x45ebf5 VADDSD	%XMM4,%XMM6,%XMM4

0x45ebf9 VADDSD	%XMM1,%XMM2,%XMM2

0x45ebfd VSUBSD	%XMM4,%XMM27,%XMM31

0x45ec03 VADDSD	%XMM1,%XMM5,%XMM6

0x45ec07 VSUBSD	%XMM6,%XMM8,%XMM1

0x45ec0b VUNPCKLPD	%XMM1,%XMM31,%XMM17

0x45ec11 VADDSD	%XMM5,%XMM7,%XMM3

0x45ec15 VMULPD	%XMM15,%XMM17,%XMM16

0x45ec1b VMOVSD	(%RBX,%RAX,8),%XMM7    [2]

0x45ec20 VSUBSD	%XMM3,%XMM2,%XMM2

0x45ec24 VMOVSD	(%R13),%XMM3    [10]

0x45ec2a VUNPCKLPD	%XMM7,%XMM3,%XMM25

0x45ec30 MOV	-0x40(%RBP),%R10    [14]

0x45ec34 VMULSD	%XMM2,%XMM3,%XMM18

0x45ec3a VMOVSD	0x8(%RSI,%RAX,8),%XMM8    [1]

0x45ec40 VFMADD231SD	%XMM0,%XMM7,%XMM18

0x45ec46 VSUBSD	-0x8(%RSI,%RAX,8),%XMM8,%XMM4    [1]

0x45ec4c VADDSD	0x8(%RBX,%RAX,8),%XMM7,%XMM1    [2]

0x45ec52 VMULSD	%XMM10,%XMM0,%XMM0

0x45ec57 VDIVPD	%XMM25,%XMM16,%XMM27

0x45ec5d VDIVSD	%XMM1,%XMM4,%XMM4

0x45ec61 VDIVSD	%XMM7,%XMM0,%XMM0

0x45ec65 VADDSD	(%R11),%XMM3,%XMM1    [9]

0x45ec6a VMULSD	%XMM10,%XMM2,%XMM2

0x45ec6f VDIVSD	%XMM3,%XMM2,%XMM2

0x45ec73 VMOVQ	%XMM11,%R8

0x45ec78 ADD	%RAX,%R8

0x45ec7b VCOMISD	%XMM9,%XMM18

0x45ec81 VUNPCKHPD	%XMM27,%XMM27,%XMM5

0x45ec87 VADDPD	%XMM27,%XMM5,%XMM6

0x45ec8d VMOVSD	(%R12,%RAX,8),%XMM5    [4]

0x45ec93 VSUBSD	(%R10,%RAX,8),%XMM5,%XMM8    [13]

0x45ec99 VDIVSD	%XMM1,%XMM8,%XMM1

0x45ec9d VMULSD	%XMM4,%XMM4,%XMM8

0x45eca1 VMULSD	%XMM4,%XMM1,%XMM25

0x45eca7 VMULSD	%XMM1,%XMM1,%XMM5

0x45ecab VMOVQ	%XMM12,%R10

0x45ecb0 LEA	(%R10,%R8,8),%R10

0x45ecb4 VMULSD	%XMM6,%XMM25,%XMM31

0x45ecba VFMADD132SD	%XMM8,%XMM31,%XMM0

0x45ecc0 VADDSD	%XMM8,%XMM5,%XMM6

0x45ecc5 VMAXSD	%XMM13,%XMM6,%XMM8

0x45ecca VFMADD231SD	%XMM5,%XMM2,%XMM0

0x45eccf VDIVSD	%XMM8,%XMM0,%XMM2

0x45ecd4 JAE	45ece1

0x45ecd6 VCOMISD	%XMM9,%XMM2

0x45ecdb JBE	45eb20

0x45ece1 VXORPD	%XMM1,%XMM1,%XMM1

0x45ece5 MOV	%RDX,%RAX

0x45ece8 VMOVSD	%XMM1,(%R10)    [15]

0x45eced CMP	%RDX,-0x38(%RBP)    [14]

0x45ecf1 JNE	45ebac

0x45ed30 VXORPD	%XMM23,%XMM0,%XMM5

0x45ed36 VCOMISD	%XMM9,%XMM0

0x45ed3b VMOVSD	%XMM5,%XMM5,%XMM0

0x45ed3f JBE	45ed69

0x45ed41 VMOVSD	%XMM22,%XMM22,%XMM4

0x45ed47 JMP	45eb3a

0x45ed69 VMOVSD	0x1827(%RIP),%XMM4    [12]

0x45ed71 JMP	45eb3a

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 39 - 64

--------------------------------------------------------------------------------

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.63
CQA speedup if fully vectorized	3.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P8, P9,
Function	_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0
Source	viscosity.cpp:39-64,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.50
CQA cycles if no scalar integer	48.50
CQA cycles if FP arith vectorized	13.38
CQA cycles if fully vectorized	13.38
Front-end cycles	18.17
DIV/SQRT cycles	4.00
P0 cycles	2.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	4.00
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	16.50
P8 cycles	16.42
P9 cycles	16.58
P10 cycles	16.50
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	48.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	109.00
Nb loads	24.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	1.11
Nb FLOP add-sub	20.00
Nb FLOP mul	16.00
Nb FLOP fma	4.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.29
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.47
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	6.67
Vectorization ratio add_sub	5.26
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	11.11
Vectorization ratio other	26.09
Vector-efficiency ratio all	13.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	13.33
Vector-efficiency ratio add_sub	13.16
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	13.89
Vector-efficiency ratio other	15.76

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.63
CQA speedup if fully vectorized	3.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P8, P9,
Function	_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0
Source	viscosity.cpp:39-64,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.50
CQA cycles if no scalar integer	48.50
CQA cycles if FP arith vectorized	13.38
CQA cycles if fully vectorized	13.38
Front-end cycles	18.17
DIV/SQRT cycles	4.00
P0 cycles	2.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	4.00
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	16.50
P8 cycles	16.42
P9 cycles	16.58
P10 cycles	16.50
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	48.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	109.00
Nb loads	24.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	1.11
Nb FLOP add-sub	20.00
Nb FLOP mul	16.00
Nb FLOP fma	4.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.29
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.47
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	6.67
Vectorization ratio add_sub	5.26
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	11.11
Vectorization ratio other	26.09
Vector-efficiency ratio all	13.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	13.33
Vector-efficiency ratio add_sub	13.16
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	13.89
Vector-efficiency ratio other	15.76

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0
Source file and lines	viscosity.cpp:39-64
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:39-64
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 48.50 to 13.37 cycles (3.63x speedup).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
5% of SSE/AVX addition or subtraction instructions are used in vector version.
6% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
11% of SSE/AVX divide and square root instructions are used in vector version.
26% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 48.50 to 18.17 cycles (2.67x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.50 to 18.17 cycles (2.67x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 4 occurrences

Type of elements and instruction set

52 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 54 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
20: multiply (4 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	109
loop length	512
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.17 cycles
front end	18.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	2.50	2.25	2.25	4.00	8.67	8.67	8.67	16.50	16.42	16.58	16.50	4.00	4.00
cycles	4.00	2.50	2.25	2.25	4.00	8.67	8.67	8.67	16.50	16.42	16.58	16.50	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

48.50

Cycles summary

Front-end	18.17
Dispatch	16.58
DIV/SQRT	48.50
Overall L1	48.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	10%
load	0%
store	0%
mul	6%
add-sub	5%
fma	0%
div/sqrt	11%
other	30%

INT+FP

all	10%
load	0%
store	0%
mul	6%
add-sub	5%
fma	0%
div/sqrt	11%
other	26%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	13%
add-sub	13%
fma	12%
div/sqrt	13%
other	16%

INT+FP

all	13%
load	12%
store	12%
mul	13%
add-sub	13%
fma	12%
div/sqrt	13%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.50 cycles. At this rate:

4% of peak load performance is reached (3.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45ebaf

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VANDPD %XMM14,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCOMISD %XMM4,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMAXSD %XMM13,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
JA 45ed30 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x470>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM19,%XMM19,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOV -0x48(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VANDPD %XMM14,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
IMUL (%R14),%R8	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMAXSD %XMM13,%XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VMULSD %XMM4,%XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM8,%XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM0,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VSQRTSD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
VMULSD %XMM3,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM7,%XMM5,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM8,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VDIVSD %XMM0,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VANDPD %XMM14,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VANDPD %XMM14,%XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADD %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x10(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMINSD %XMM6,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VMULSD %XMM2,%XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD (%RAX,%R8,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD %XMM5,%XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM3,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM1,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %RDX,-0x38(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JE 45ecf7 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x437>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8(%R15,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RCX,%RAX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R15,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD 0x8(%RDI,%RAX,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM0,%XMM1,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM6,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD 0x8(%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R9,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM4,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD 0x8(%R9,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM5,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM2,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%RDI,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM4,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM1,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM4,%XMM27,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM1,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM6,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM1,%XMM31,%XMM17	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM5,%XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %XMM15,%XMM17,%XMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD (%RBX,%RAX,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%R13),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUNPCKLPD %XMM7,%XMM3,%XMM25	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOV -0x40(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD %XMM2,%XMM3,%XMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD 0x8(%RSI,%RAX,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231SD %XMM0,%XMM7,%XMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VSUBSD -0x8(%RSI,%RAX,8),%XMM8,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDSD 0x8(%RBX,%RAX,8),%XMM7,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM10,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVPD %XMM25,%XMM16,%XMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VDIVSD %XMM1,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VDIVSD %XMM7,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VADDSD (%R11),%XMM3,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM10,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVQ %XMM11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCOMISD %XMM9,%XMM18	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VUNPCKHPD %XMM27,%XMM27,%XMM5	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM27,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%R12,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R10,%RAX,8),%XMM5,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VDIVSD %XMM1,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM4,%XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM4,%XMM1,%XMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVQ %XMM12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA (%R10,%R8,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULSD %XMM6,%XMM25,%XMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD132SD %XMM8,%XMM31,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM8,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMAXSD %XMM13,%XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VFMADD231SD %XMM5,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VDIVSD %XMM8,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
JAE 45ece1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x421>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VCOMISD %XMM9,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 45eb20 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM1,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %RDX,-0x38(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 45ebac <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2ec>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM23,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCOMISD %XMM9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
JBE 45ed69 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x4a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM22,%XMM22,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
JMP 45eb3a <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x27a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VMOVSD 0x1827(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
JMP 45eb3a <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x27a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0
Source file and lines	viscosity.cpp:39-64
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:39-64
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
5% of SSE/AVX addition or subtraction instructions are used in vector version.
6% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
11% of SSE/AVX divide and square root instructions are used in vector version.
26% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.50 to 18.17 cycles (2.67x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 4 occurrences

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 54 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
20: multiply (4 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	109
loop length	512
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.17 cycles
front end	18.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	2.50	2.25	2.25	4.00	8.67	8.67	8.67	16.50	16.42	16.58	16.50	4.00	4.00
cycles	4.00	2.50	2.25	2.25	4.00	8.67	8.67	8.67	16.50	16.42	16.58	16.50	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

48.50

Cycles summary

Front-end	18.17
Dispatch	16.58
DIV/SQRT	48.50
Overall L1	48.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	10%
load	0%
store	0%
mul	6%
add-sub	5%
fma	0%
div/sqrt	11%
other	30%

INT+FP

all	10%
load	0%
store	0%
mul	6%
add-sub	5%
fma	0%
div/sqrt	11%
other	26%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	13%
add-sub	13%
fma	12%
div/sqrt	13%
other	16%

INT+FP

all	13%
load	12%
store	12%
mul	13%
add-sub	13%
fma	12%
div/sqrt	13%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.50 cycles. At this rate:

4% of peak load performance is reached (3.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45ebaf

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VANDPD %XMM14,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCOMISD %XMM4,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMAXSD %XMM13,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
JA 45ed30 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x470>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM19,%XMM19,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOV -0x48(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VANDPD %XMM14,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
IMUL (%R14),%R8	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMAXSD %XMM13,%XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VMULSD %XMM4,%XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM8,%XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM0,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VSQRTSD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
VMULSD %XMM3,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM7,%XMM5,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM8,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VDIVSD %XMM0,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VANDPD %XMM14,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VANDPD %XMM14,%XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADD %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x10(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMINSD %XMM6,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VMULSD %XMM2,%XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD (%RAX,%R8,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD %XMM5,%XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM3,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM1,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %RDX,-0x38(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JE 45ecf7 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x437>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8(%R15,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RCX,%RAX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R15,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD 0x8(%RDI,%RAX,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM0,%XMM1,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM6,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD 0x8(%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R9,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM4,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD 0x8(%R9,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM5,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM2,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%RDI,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VADDSD %XMM4,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM1,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM4,%XMM27,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM1,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM6,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKLPD %XMM1,%XMM31,%XMM17	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM5,%XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %XMM15,%XMM17,%XMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD (%RBX,%RAX,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%R13),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUNPCKLPD %XMM7,%XMM3,%XMM25	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOV -0x40(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD %XMM2,%XMM3,%XMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD 0x8(%RSI,%RAX,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231SD %XMM0,%XMM7,%XMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VSUBSD -0x8(%RSI,%RAX,8),%XMM8,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDSD 0x8(%RBX,%RAX,8),%XMM7,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM10,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVPD %XMM25,%XMM16,%XMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VDIVSD %XMM1,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VDIVSD %XMM7,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VADDSD (%R11),%XMM3,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM10,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VDIVSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVQ %XMM11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADD %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCOMISD %XMM9,%XMM18	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VUNPCKHPD %XMM27,%XMM27,%XMM5	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM27,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%R12,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R10,%RAX,8),%XMM5,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VDIVSD %XMM1,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMULSD %XMM4,%XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM4,%XMM1,%XMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVQ %XMM12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA (%R10,%R8,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULSD %XMM6,%XMM25,%XMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD132SD %XMM8,%XMM31,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM8,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMAXSD %XMM13,%XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
VFMADD231SD %XMM5,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VDIVSD %XMM8,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
JAE 45ece1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x421>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VCOMISD %XMM9,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 45eb20 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM1,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %RDX,-0x38(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 45ebac <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2ec>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM23,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCOMISD %XMM9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
JBE 45ed69 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x4a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM22,%XMM22,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
JMP 45eb3a <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x27a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VMOVSD 0x1827(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
JMP 45eb3a <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x27a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> MPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/run/oneview_runs/compilers/gcc_6/oneview_run_1708556066OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0.03	0.95	0.49	0.79	1.37	0.97	0.16	0.7	0.71	0.47	1.16	0.33	1.28

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	82.08	13.13
2x2	4	1	2	2	41.18	11.89
2x4	8	0.95	3.81	4	20.62	10.53
2x8	16	0.79	6.3	8	10.35	6.45
2x16	32	0.97	15.47	16	5.23	4.78
2x32	64	0.7	22.34	32	3.66	2.35
2x64	128	0.47	30.03	64	3	2.19
2x96	192	0.33	32.15	96	2.41	1.92

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency