	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/oneview_runs/compilers/aocc_7/oneview_results_1790700589 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/oneview_runs/compilers/aocc_7/oneview_results_1790700589


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/binaries/aocc_7/exec
  Timestamp:			2026-09-29 18:49:49
  Universal Timestamp:		1790700589
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			ins01.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V4
  Model Name:			AMD EPYC 9654 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 --driver-mode=g++ -D USE_OMP -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/omp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/aocc_7/generated -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/driver -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp -O2 -march=znver4 -mprefer-vector-width=512 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -D NDEBUG -std=c++17 -Wall -Wno-unused-parameter -Wno-unused-function -Wno-unused-variable -fopenmp=libomp -MD -MT CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o -MF CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o.d -o CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp -I /cluster/hpcx/2.50/ompi5-aocc-mt/include -I /cluster/hpcx/2.50/ompi5-aocc-mt/include/openmpi 
  Number of processes observed:	8
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				57.70 s
  Max (Thread Active Time):		57.42 s
  Average Active Time:			51.77 s
  Activity Ratio:			99.9 %
  Average number of active threads:	172.280
  Affinity Stability:			99.8 %
  Time spent in analyzed loops:		94.4 %
  Time spent in analyzed innermost loops: 94.4 %
  Time spent in user code:		94.4 %
  Compilation Options Score:		100
  Array Access Efficiency:		17.2 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.05
  Perfect OpenMP/MPI/Pthread/TBB:	1.06
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.16
  If No Scalar Integer:
      Potential Speedup:		1.64
      Nb Loops to get 80%:		22
  If FP Vectorized:
      Potential Speedup:		1.02
      Nb Loops to get 80%:		2
  If Fully Vectorized:
      Potential Speedup:		2.64
      Nb Loops to get 80%:		25
  If Only FP Arithmetic:
      Potential Speedup:		5.53
      Nb Loops to get 80%:		28




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0370 | 1.2472 | 1.4675 | 1.6037 | 1.6374 | 
  Top 5 loops:
    exec - 223:	1.037
    exec - 161:	1.0664
    exec - 169:	1.0975
    exec - 160:	1.1254
    exec - 168:	1.1546

  If FP Vectorized:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0084 | 1.0165 | 1.0165 | 1.0165 | 1.0165 | 
  Top 5 loops:
    exec - 277:	1.0084
    exec - 128:	1.0161
    exec - 211:	1.0165
    exec - 131:	1.0165
    exec - 651:	1.0165

  If Fully Vectorized:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0467 | 1.4065 | 1.9514 | 2.4469 | 2.6353 | 
  Top 5 loops:
    exec - 277:	1.0467
    exec - 128:	1.0928
    exec - 276:	1.1338
    exec - 223:	1.1751
    exec - 213:	1.2191

  If Only FP Arithmetic:
      Number of loops   | 1      | 9      | 19     | 27     | 37     | 
      Cumulated Speedup | 1.0566 | 1.5793 | 2.7446 | 4.4973 | 5.5313 | 
  Top 5 loops:
    exec - 277:	1.0566
    exec - 276:	1.1083
    exec - 128:	1.165
    exec - 223:	1.2239
    exec - 213:	1.2838



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (57.42 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9985768285547 / 3] Most of time spent in analyzed modules (99.95%) comes from functions compiled with architecture specialization option
-march=znver4


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.19 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (94.36%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [3 / 4] A significant amount of threads are idle (10.27%)
On average, more than 10% of observed threads are idle. Such threads are probably IO/sync waiting. Some hints: use
faster filesystems to read/write data, improve parallel load balancing and/or scheduling.

  [4 / 4] CPU activity is good
CPU cores are active 99.91% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (6.38%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (94.36%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.79%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (14.04%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (0.00%) lower than cumulative innermost loop coverage (94.36%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 277 :
     analysis: Execution Time: 6 % - Vectorization Ratio: 36.18 % - Vector Length Use: 21.87 %
     Loop Computation Issues: 8
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
     Data Access Issues: 232
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [56] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 14 issues ( = indirect data accesses) costing 4 point each.
        [174] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 174 issues (= instructions) costing 1
            point each.
     Vectorization Roadblocks: 58
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [56] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 14 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 174
        [174] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 174 issues (= instructions) costing 1
            point each.

   + exec - 276 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 36.36 % - Vector Length Use: 21.85 %
     Loop Computation Issues: 8
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
     Data Access Issues: 172
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [44] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 11 issues ( = indirect data accesses) costing 4 point each.
        [126] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 126 issues (= instructions) costing 1
            point each.
     Vectorization Roadblocks: 46
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [44] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 11 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 126
        [126] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 126 issues (= instructions) costing 1
            point each.

   + exec - 223 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 36.84 % - Vector Length Use: 31.58 %
     Loop Computation Issues: 14
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 78
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
        [8] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 2 issues (=
            instructions) costing 4 points each.
        [54] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 54 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 16
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 62
        [8] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 2 issues (=
            instructions) costing 4 points each.
        [54] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 54 issues (= instructions) costing 1 point each.

   + exec - 128 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 30.77 % - Vector Length Use: 20.09 %
     Loop Computation Issues: 6
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 273
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [68] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 17 issues ( = indirect data accesses) costing 4 point each.
        [201] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 201 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 70
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [68] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 17 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 201
        [201] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 201 issues (= instructions) costing 1
            point each.

   + exec - 168 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 41.28 % - Vector Length Use: 33.43 %
     Loop Computation Issues: 10
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 2
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
     Data Access Issues: 119
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.
        [8] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 2 issues (=
            instructions) costing 4 points each.
        [91] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 91 issues (= instructions) costing 1
            point each.
     Vectorization Roadblocks: 22
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 101
        [8] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 2 issues (=
            instructions) costing 4 points each.
        [91] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 91 issues (= instructions) costing 1
            point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 94.41  | 0.86    | 0.19    | 0.00   | 0.00   | 0.26  | 0.00  | 4.27  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 9                         | 42.89                     | 42.89                     |
   2% to 4%                   | 17                        | 47.14                     | 90.02                     |
   1% to 2%                   | 6                         | 7.85                      | 97.87                     |
   0.5% to 1%                 | 1                         | 0.68                      | 98.56                     |
   0.25% to 0.5%              | 1                         | 0.29                      | 98.85                     |
   0.125% to 0.25%            | 1                         | 0.17                      | 99.02                     |
   < 0.125%                   | 68                        | 0.91                      | 99.93                     |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 9                         | 42.88                     | 42.88                     |
   2% to 4%                   | 15                        | 43.00                     | 85.88                     |
   1% to 2%                   | 6                         | 7.85                      | 93.73                     |
   0.5% to 1%                 | 0                         | 0.00                      | 93.73                     |
   0.25% to 0.5%              | 1                         | 0.29                      | 94.03                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 94.03                     |
   < 0.125%                   | 28                        | 0.33                      | 94.36                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 6.38           | 3.31           |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 5.33           | 2.76           |
   ideal_gas_kernel(int, int, int, int, clover::Buffer... | exec                | 5.21           | 2.70           |
   accelerate_kernel(int, int, int, int, double, clove... | exec                | 5.17           | 2.68           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.23           | 2.19           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.22           | 2.19           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.12           | 2.13           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.10           | 2.13           |
   flux_calc_kernel(int, int, int, int, double, clover... | exec                | 4.10           | 2.12           |
   advec_cell_kernel(int, int, int, int, int, int, clo... | exec                | 3.40           | 1.76           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   277            | exec                | PdV.cpp:70-83,context.h:69-69                          | 6.38           |
   276            | exec                | PdV.cpp:49-63,context.h:69-69                          | 5.33           |
   223            | exec                | context.h:69-69,ideal_gas.cpp:38-45                    | 5.21           |
   128            | exec                | context.h:69-69,accelerate.cpp:41-53                   | 5.17           |
   168            | exec                | context.h:69-69,advec_mom.cpp:181-186,advec_mom.cpp... | 4.23           |
   160            | exec                | context.h:69-69,advec_mom.cpp:109-114,advec_mom.cpp... | 4.22           |
   169            | exec                | context.h:69-69,advec_mom.cpp:219-221                  | 4.12           |
   161            | exec                | context.h:69-69,advec_mom.cpp:147-149                  | 4.10           |
   213            | exec                | context.h:69-69,flux_calc.cpp:37-40                    | 4.10           |
   144            | exec                | advec_cell.cpp:158-202,context.h:46-46,context.h:69-69 | 3.40           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 277 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
6% of peak computational performance is used (1.46 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 21% of vector register length is used (average across all SSE/AVX instructions).


Details
36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 4% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 96% of SSE/AVX multiply instructions are used in vector version.
 - 33% of SSE/AVX divide and square root instructions are used in vector version.
 - 33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.01x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 4 occurrences<<list_path_1_complex_1>>
 - VMOVHPD: 4 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 58 occurrences<<list_path_1_complex_3>>



      6.1.1.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 14 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.1.1.7  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 13 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 2 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF128: 11 occurrences<<list_path_1_vec_align_2>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.1.1.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 4 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.1.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
25 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 113 FP arithmetical operations:
 - 72: addition or subtraction (12 inside FMA instructions)
 - 33: multiply (12 inside FMA instructions)
 - 8: divide
The binary loop is loading 1064 bytes (133 double precision FP elements).
The binary loop is storing 88 bytes (11 double precision FP elements).


      6.1.1.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.2  -  Loop 276 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
5% of peak computational performance is used (1.40 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 58.00 to 54.50 cycles (1.06x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 21% of vector register length is used (average across all SSE/AVX instructions).


Details
36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 9% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 95% of SSE/AVX multiply instructions are used in vector version.
 - 33% of SSE/AVX divide and square root instructions are used in vector version.
 - 33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.2.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.2.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 4 occurrences<<list_path_1_complex_1>>
 - VMOVHPD: 4 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 42 occurrences<<list_path_1_complex_3>>



      6.1.2.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 11 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.2.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 9 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 2 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF128: 7 occurrences<<list_path_1_vec_align_2>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.2.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 4 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.2.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
17 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.2.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 81 FP arithmetical operations:
 - 40: addition or subtraction (12 inside FMA instructions)
 - 33: multiply (12 inside FMA instructions)
 - 8: divide
The binary loop is loading 864 bytes (108 double precision FP elements).
The binary loop is storing 72 bytes (9 double precision FP elements).


      6.1.2.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.3  -  Loop 223 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
1% of peak computational performance is used (0.46 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 121.00 to 38.17 cycles (3.17x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.3.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 31% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 121.00 to 49.00 cycles (2.47x speedup).

Details
36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 34% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.3.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 121.00 to 41.67 cycles (2.90x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.3.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 121.00 to 40.33 cycles (3.00x speedup).




      6.1.3.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VPEXTRQ: 16 occurrences<<list_path_1_complex_2>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_3>>



      6.1.3.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.3.1.7  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.3.1.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.3.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 56 FP arithmetical operations:
 - 40: multiply
 - 8: divide
 - 8: square root
The binary loop is loading 200 bytes (25 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.3.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.4  -  Loop 128 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41-53


It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
6% of peak computational performance is used (1.49 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 99.17 to 80.33 cycles (1.23x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 20% of vector register length is used (average across all SSE/AVX instructions).


Details
30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 3% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 38% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.4.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.4.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 44 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.01x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 4 occurrences<<list_path_1_complex_1>>
 - VMOVHPD: 8 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 52 occurrences<<list_path_1_complex_3>>



      6.1.4.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 17 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.4.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 20 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 4 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF128: 16 occurrences<<list_path_1_vec_align_2>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 4 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.4.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

26 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 148 FP arithmetical operations:
 - 76: addition or subtraction (44 inside FMA instructions)
 - 68: multiply (44 inside FMA instructions)
 - 4: divide
The binary loop is loading 1760 bytes (220 double precision FP elements).
The binary loop is storing 488 bytes (61 double precision FP elements).


      6.1.4.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.







      6.1.5  -  Loop 168 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-186,197-211


It is main loop of related source loop which is unrolled by 8 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
4% of peak computational performance is used (1.11 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 123.00 to 62.83 cycles (1.96x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 36% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 123.00 to 51.00 cycles (2.41x speedup).

Details
43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 10% of SSE/AVX loads are used in vector version.
 - 27% of SSE/AVX divide and square root instructions are used in vector version.
 - 44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 123.00 to 66.83 cycles (1.84x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.5.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 123.00 to 65.50 cycles (1.88x speedup).


      6.1.5.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.5.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - KORTESTB: 1 occurrences<<list_path_1_complex_2>>
 - VGATHERDPD: 1 occurrences<<list_path_1_complex_3>>
 - VGATHERQPD: 1 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 28 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_complex_6>>



      6.1.5.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.5.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERDPD: 1 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 1 occurrences<<list_path_1_gather_scatter_2>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_gather_scatter_3>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.5.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.5.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 136 FP arithmetical operations:
 - 56: addition or subtraction (16 inside FMA instructions)
 - 56: multiply (16 inside FMA instructions)
 - 24: divide
The binary loop is loading 492 bytes (61 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.5.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.




      6.1.5.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
2% of peak computational performance is used (0.61 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.2.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 105.00 to 44.00 cycles (2.39x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 30% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 105.00 to 33.00 cycles (3.18x speedup).

Details
38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 2% of SSE/AVX loads are used in vector version.
 - 11% of SSE/AVX divide and square root instructions are used in vector version.
 - 39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 105.00 to 47.33 cycles (2.22x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.5.2.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 105.00 to 46.00 cycles (2.28x speedup).


      6.1.5.2.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.5.2.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.2.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_2_complex_1>>
 - KORTESTB: 1 occurrences<<list_path_2_complex_2>>
 - VPEXTRQ: 28 occurrences<<list_path_2_complex_3>>
 - VSCATTERQPD: 1 occurrences<<list_path_2_complex_4>>



      6.1.5.2.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.5.2.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VSCATTERQPD: 1 occurrences<<list_path_2_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.5.2.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_2_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_2_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.5.2.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

9 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.2.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 64 FP arithmetical operations:
 - 32: addition or subtraction (8 inside FMA instructions)
 - 24: multiply (8 inside FMA instructions)
 - 8: divide
The binary loop is loading 332 bytes (41 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.5.2.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.







      6.1.6  -  Loop 160 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-114,125-139


It is main loop of related source loop which is unrolled by 8 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
4% of peak computational performance is used (1.11 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 123.00 to 62.50 cycles (1.97x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.6.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 35% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 123.00 to 51.00 cycles (2.41x speedup).

Details
43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 10% of SSE/AVX loads are used in vector version.
 - 27% of SSE/AVX divide and square root instructions are used in vector version.
 - 44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 123.00 to 66.50 cycles (1.85x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.6.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 123.00 to 65.17 cycles (1.89x speedup).


      6.1.6.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.6.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - KORTESTB: 1 occurrences<<list_path_1_complex_2>>
 - VGATHERDPD: 1 occurrences<<list_path_1_complex_3>>
 - VGATHERQPD: 1 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 28 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_complex_6>>



      6.1.6.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERDPD: 1 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 1 occurrences<<list_path_1_gather_scatter_2>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_gather_scatter_3>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.6.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.6.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 136 FP arithmetical operations:
 - 56: addition or subtraction (16 inside FMA instructions)
 - 56: multiply (16 inside FMA instructions)
 - 24: divide
The binary loop is loading 492 bytes (61 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.6.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.




      6.1.6.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
2% of peak computational performance is used (0.61 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.2.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 105.00 to 43.67 cycles (2.40x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.6.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 30% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 105.00 to 33.00 cycles (3.18x speedup).

Details
38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 2% of SSE/AVX loads are used in vector version.
 - 11% of SSE/AVX divide and square root instructions are used in vector version.
 - 39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 105.00 to 47.00 cycles (2.23x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.6.2.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 105.00 to 45.67 cycles (2.30x speedup).


      6.1.6.2.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.6.2.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.2.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_2_complex_1>>
 - KORTESTB: 1 occurrences<<list_path_2_complex_2>>
 - VPEXTRQ: 28 occurrences<<list_path_2_complex_3>>
 - VSCATTERQPD: 1 occurrences<<list_path_2_complex_4>>



      6.1.6.2.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.2.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VSCATTERQPD: 1 occurrences<<list_path_2_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.6.2.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_2_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_2_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.6.2.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

9 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.2.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 64 FP arithmetical operations:
 - 32: addition or subtraction (8 inside FMA instructions)
 - 24: multiply (8 inside FMA instructions)
 - 8: divide
The binary loop is loading 332 bytes (41 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.6.2.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.







      6.1.7  -  Loop 169 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:219-221


It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
1% of peak computational performance is used (0.30 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 53.00 to 18.83 cycles (2.81x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 21% of vector register length is used (average across all SSE/AVX instructions).


Details
35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.7.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 53.00 to 20.50 cycles (2.59x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.7.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.7.1.5  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 53.00 to 19.83 cycles (2.67x speedup).


      6.1.7.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.7.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 4 occurrences<<list_path_1_complex_1>>
 - VMOVHPD: 2 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 14 occurrences<<list_path_1_complex_3>>



      6.1.7.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.9  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF128: 3 occurrences<<list_path_1_vec_align_2>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.7.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 4 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.7.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.7.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 16 FP arithmetical operations:
 - 8: addition or subtraction (4 inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
 - 4: divide
The binary loop is loading 168 bytes (21 double precision FP elements).
The binary loop is storing 40 bytes (5 double precision FP elements).


      6.1.7.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.8  -  Loop 161 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147-149


It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
1% of peak computational performance is used (0.30 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 53.00 to 18.67 cycles (2.84x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.8.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 20% of vector register length is used (average across all SSE/AVX instructions).


Details
34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.8.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 53.00 to 20.33 cycles (2.61x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.8.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.8.1.5  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 53.00 to 19.67 cycles (2.69x speedup).


      6.1.8.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.8.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 4 occurrences<<list_path_1_complex_1>>
 - VMOVHPD: 2 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 14 occurrences<<list_path_1_complex_3>>



      6.1.8.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.8.1.9  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF128: 3 occurrences<<list_path_1_vec_align_2>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.8.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 4 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.8.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.8.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 16 FP arithmetical operations:
 - 8: addition or subtraction (4 inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
 - 4: divide
The binary loop is loading 168 bytes (21 double precision FP elements).
The binary loop is storing 40 bytes (5 double precision FP elements).


      6.1.8.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.9  -  Loop 213 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37-40


It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [CQTO] is unknown
3% of peak computational performance is used (0.88 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 48.00 to 36.67 cycles (1.31x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 21% of vector register length is used (average across all SSE/AVX instructions).


Details
36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 88% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX divide and square root instructions are used in vector version.
 - 31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 48.00 to 39.17 cycles (1.23x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.9.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.9.1.5  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 38.50 cycles (1.25x speedup).


      6.1.9.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.9.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 4 occurrences<<list_path_1_complex_1>>
 - VMOVHPD: 4 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 28 occurrences<<list_path_1_complex_3>>



      6.1.9.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.9.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 4 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.9.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.9.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 42 FP arithmetical operations:
 - 24: addition or subtraction
 - 18: multiply
The binary loop is loading 360 bytes (45 double precision FP elements).
The binary loop is storing 72 bytes (9 double precision FP elements).


      6.1.9.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.10  -  Loop 144 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158-202
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69


It is main loop of related source loop which is unrolled by 16 (including vectorization).
Warnings:
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=16
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [CQTO] is unknown
 - The number of fused uops of the instruction [VPCMPEQD	%YMM1,%YMM1,%YMM1] is unknown

7% of peak computational performance is used (1.89 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 246.00 to 179.50 cycles (1.37x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 35% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 246.00 to 103.06 cycles (2.39x speedup).

Details
46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 23% of SSE/AVX loads are used in vector version.
 - 54% of SSE/AVX stores are used in vector version.
 - 27% of SSE/AVX divide and square root instructions are used in vector version.
 - 48% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 246.00 to 196.17 cycles (1.25x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.10.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 246.00 to 193.50 cycles (1.27x speedup).


      6.1.10.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.10.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 48 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 16 occurrences<<list_path_1_complex_1>>
 - KORTESTW: 4 occurrences<<list_path_1_complex_2>>
 - VMOVAPD: 5 occurrences<<list_path_1_complex_3>>
 - VMOVDQA64: 6 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 92 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 4 occurrences<<list_path_1_complex_6>>



      6.1.10.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 25 suboptimal vector unaligned load/store instructions.


Details
 - VINSERTF128: 25 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.10.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VSCATTERQPD: 4 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.10.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 16 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 4 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.10.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

70 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.10.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 464 FP arithmetical operations:
 - 192: addition or subtraction (48 inside FMA instructions)
 - 224: multiply (48 inside FMA instructions)
 - 48: divide
The binary loop is loading 3684 bytes (460 double precision FP elements).
The binary loop is storing 1512 bytes (189 double precision FP elements).


      6.1.10.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/oneview_runs/compilers/aocc_7/oneview_run_1790700589"
[MAQAO] Info: 
