	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_5/oneview_results_1790708432 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: -> OPEN THE MAIN APPLICATION BINARY ...
[MAQAO] Info: ---> ALL LOOPS HAVE BEEN ANALYZED
[MAQAO] Info: ---> ALL FUNCTIONS HAVE BEEN ANALYZED
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_5/oneview_results_1790708432


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/binaries/gcc_5/exec
  Timestamp:			2026-09-29 21:00:32
  Universal Timestamp:		1790708432
  Experiment Type:		MPI; Throughput; 
  Machine:			ins01.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V4
  Model Name:			AMD EPYC 9654 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: GNU C++17 11.5.0 20240719 (Red Hat 11.5.0-14) -march=znver4 -g -O3 -O3 -std=c++17 -fno-tree-vectorize -fno-openmp-simd -funroll-loops -ffast-math -fno-omit-frame-pointer -fcf-protection=none -fopenmp 
  Number of processes observed:	8
  Number of threads observed:	8
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				193.92 s
  Max (Thread Active Time):		193.72 s
  Average Active Time:			193.69 s
  Activity Ratio:			99.9 %
  Average number of active threads:	7.991
  Affinity Stability:			99.9 %
  Time spent in analyzed loops:		98.9 %
  Time spent in analyzed innermost loops: 98.8 %
  Time spent in user code:		99.0 %
  Compilation Options Score:		100
  Array Access Efficiency:		71.3 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.10
  Perfect OpenMP/MPI/Pthread/TBB:	1.00
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.01
  If No Scalar Integer:
      Potential Speedup:		1.02
      Nb Loops to get 80%:		6
  If FP Vectorized:
      Potential Speedup:		1.28
      Nb Loops to get 80%:		5
  If Fully Vectorized:
      Potential Speedup:		1.59
      Nb Loops to get 80%:		6
  If Only FP Arithmetic:
      Potential Speedup:		1.56
      Nb Loops to get 80%:		9




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0052 | 1.0237 | 1.0237 | 1.0237 | 1.0237 | 
  Top 5 loops:
    exec - 184:	1.0052
    exec - 244:	1.0094
    exec - 261:	1.0131
    exec - 227:	1.0159
    exec - 225:	1.0187

  If FP Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0981 | 1.2750 | 1.2761 | 1.2761 | 1.2761 | 
  Top 5 loops:
    exec - 573:	1.0981
    exec - 227:	1.1362
    exec - 225:	1.1689
    exec - 200:	1.2015
    exec - 244:	1.2356

  If Fully Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0981 | 1.5391 | 1.5869 | 1.5924 | 1.5924 | 
  Top 5 loops:
    exec - 573:	1.0981
    exec - 244:	1.1919
    exec - 203:	1.2591
    exec - 227:	1.3327
    exec - 200:	1.4136

  If Only FP Arithmetic:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0820 | 1.4749 | 1.5573 | 1.5608 | 1.5608 | 
  Top 5 loops:
    exec - 244:	1.082
    exec - 203:	1.1521
    exec - 200:	1.2239
    exec - 227:	1.2933
    exec - 225:	1.3605



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (193.72 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9990806216498 / 3] Most of time spent in analyzed modules (99.97%) comes from functions compiled with architecture specialization option
-march=znver4


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (98.90%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 99.88% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.86% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (13.07%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (98.84%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.90%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (0.00%)

  [3 / 3] Cumulative Outermost/In between loops coverage (0.06%) lower than cumulative innermost loop coverage (98.84%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 244 :
     analysis: Execution Time: 13 % - Vectorization Ratio: 100.00 % - Vector Length Use: 49.22 %
     Loop Computation Issues: 56
        [56] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 14
            issues (= instructions) costing 4 points each.
     Data Access Issues: 287
        [140] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 35 issues ( = indirect data accesses) costing 4 point each.
        [140] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 35 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 140
        [140] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 35 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 147
        [140] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 35 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 573 :
     analysis: Execution Time: 11 % - Vectorization Ratio: 5.95 % - Vector Length Use: 13.24 %
     Loop Computation Issues: 40
        [40] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 10
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 9
        [9] [SA] Too many paths (5 paths) - Simplify control structure. There are 5 issues ( = paths) costing 1 point
            each with a malus of 4 points.
     Vectorization Roadblocks: 9
        [9] [SA] Too many paths (5 paths) - Simplify control structure. There are 5 issues ( = paths) costing 1 point
            each with a malus of 4 points.

   + exec - 227 :
     analysis: Execution Time: 8 % - Vectorization Ratio: 96.40 % - Vector Length Use: 47.07 %
     Loop Computation Issues: 24
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
     Data Access Issues: 60
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [40] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 10 issues (=
            instructions) costing 4 points each.
        [12] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE,
            SHUFFLE/PERM, BROADCAST) - Simplify data access and try to get stride 1 access. There are 12 issues (=
            instructions) costing 1 point each.
     Vectorization Roadblocks: 8
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 54
        [40] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 10 issues (=
            instructions) costing 4 points each.
        [12] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE,
            SHUFFLE/PERM, BROADCAST) - Simplify data access and try to get stride 1 access. There are 12 issues (=
            instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 225 :
     analysis: Execution Time: 8 % - Vectorization Ratio: 100.00 % - Vector Length Use: 47.34 %
     Loop Computation Issues: 24
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
     Data Access Issues: 56
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [40] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 10 issues (=
            instructions) costing 4 points each.
        [6] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE,
            SHUFFLE/PERM) - Simplify data access and try to get stride 1 access. There are 6 issues (= instructions)
            costing 1 point each.
     Vectorization Roadblocks: 10
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 48
        [40] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 10 issues (=
            instructions) costing 4 points each.
        [6] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE,
            SHUFFLE/PERM) - Simplify data access and try to get stride 1 access. There are 6 issues (= instructions)
            costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 203 :
     analysis: Execution Time: 7 % - Vectorization Ratio: 99.44 % - Vector Length Use: 49.37 %
     Loop Computation Issues: 24
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
     Data Access Issues: 112
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [80] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 20 issues (=
            instructions) costing 4 points each.
        [14] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 14 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 16
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 96
        [80] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 20 issues (=
            instructions) costing 4 points each.
        [14] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 14 issues (= instructions) costing 1
            point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 99.02  | 0.37    | 0.00    | 0.00   | 0.09   | 0.50  | 0.00  | 0.01  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 4                         | 42.11                     | 42.11                     |
   4% to 8%                   | 4                         | 23.70                     | 65.80                     |
   2% to 4%                   | 5                         | 13.02                     | 78.83                     |
   1% to 2%                   | 11                        | 15.14                     | 93.96                     |
   0.5% to 1%                 | 7                         | 4.90                      | 98.86                     |
   0.25% to 0.5%              | 1                         | 0.37                      | 99.22                     |
   0.125% to 0.25%            | 1                         | 0.24                      | 99.46                     |
   < 0.125%                   | 18                        | 0.45                      | 99.92                     |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 4                         | 42.09                     | 42.09                     |
   4% to 8%                   | 4                         | 23.67                     | 65.76                     |
   2% to 4%                   | 5                         | 13.01                     | 78.77                     |
   1% to 2%                   | 11                        | 15.11                     | 93.88                     |
   0.5% to 1%                 | 7                         | 4.88                      | 98.77                     |
   0.25% to 0.5%              | 0                         | 0.00                      | 98.77                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 98.77                     |
   < 0.125%                   | 7                         | 0.07                      | 98.84                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   calc_dt_kernel(int, int, int, int, double, double, ... | exec                | 13.07          | 25.31          |
   viscosity_kernel(int, int, int, int, clover::Buffer... | exec                | 11.92          | 23.08          |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 8.93           | 17.29          |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 8.19           | 15.87          |
   advec_cell_kernel(int, int, int, int, int, int, clo... | exec                | 7.72           | 14.96          |
   advec_cell_kernel(int, int, int, int, int, int, clo... | exec                | 7.31           | 14.17          |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 4.50           | 8.71           |
   accelerate_kernel(int, int, int, int, double, clove... | exec                | 4.16           | 8.06           |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 3.31           | 6.42           |
   ideal_gas_kernel(int, int, int, int, clover::Buffer... | exec                | 2.82           | 5.45           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   244            | exec                | calc_dt.cpp:52-75,context.h:46-46,context.h:69-69      | 13.07          |
   573            | exec                | viscosity.cpp:39-64,context.h:69-69                    | 11.92          |
   227            | exec                | context.h:46-46,context.h:69-69,advec_mom.cpp:186-1... | 8.92           |
   225            | exec                | context.h:69-69,advec_mom.cpp:114-115,advec_mom.cpp... | 8.19           |
   203            | exec                | advec_cell.cpp:163-163,advec_cell.cpp:172-202,conte... | 7.72           |
   200            | exec                | advec_cell.cpp:71-72,advec_cell.cpp:79-110             | 7.31           |
   320            | exec                | PdV.cpp:72-83                                          | 4.49           |
   184            | exec                | accelerate.cpp:43-53                                   | 4.16           |
   318            | exec                | PdV.cpp:55-63,context.h:69-69                          | 3.31           |
   274            | exec                | ideal_gas.cpp:40-45                                    | 2.81           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 244 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52-75
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (1.18 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 49% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.1.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.1.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.01x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCMPPD: 2 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 35 occurrences<<list_path_1_complex_2>>



      6.1.1.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 35 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.1.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 183.33 to 77.00 cycles (2.38x speedup).

Details
 - VGATHERQPD: 35 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.1.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

76 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 216 FP arithmetical operations:
 - 72: addition or subtraction (8 inside FMA instructions)
 - 88: multiply (8 inside FMA instructions)
 - 48: divide
 - 8: square root
The binary loop is loading 2112 bytes (264 double precision FP elements).
The binary loop is storing 160 bytes (20 double precision FP elements).


      6.1.1.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.2  -  Loop 573 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39-64
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=5
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (0.99 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 53.50 to 13.37 cycles (4.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 53.50 to 17.50 cycles (3.06x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.2.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 53.50 to 18.50 cycles (2.89x speedup).


      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 4 occurrences<<list_path_1_complex_1>>



      6.1.2.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

57 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.2.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 53 FP arithmetical operations:
 - 23: addition or subtraction (4 inside FMA instructions)
 - 20: multiply (4 inside FMA instructions)
 - 9: divide
 - 1: square root
The binary loop is loading 200 bytes (25 double precision FP elements).
The binary loop is storing 16 bytes (2 double precision FP elements).


      6.1.2.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.







      6.1.3  -  Loop 227 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,195-211


The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (2.32 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 47% of vector register length is used (average across all SSE/AVX instructions).


Details
96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 88% of SSE/AVX loads are used in vector version.
 - 95% of SSE/AVX multiply instructions are used in vector version.
 - 96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.3.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.3.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.3.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.04x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERDPD: 2 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 8 occurrences<<list_path_1_complex_2>>



      6.1.3.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.3.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 4 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.3.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 59.00 to 30.00 cycles (1.97x speedup).

Details
 - VGATHERDPD: 2 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 8 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.3.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
48 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.3.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 137 FP arithmetical operations:
 - 56: addition or subtraction (8 inside FMA instructions)
 - 57: multiply (8 inside FMA instructions)
 - 24: divide
The binary loop is loading 496 bytes (62 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.3.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.







      6.1.4  -  Loop 225 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114-115,123-139


The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

10% of peak computational performance is used (2.56 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 47% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.4.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.4.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.4.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.4.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.04x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERDPD: 4 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 6 occurrences<<list_path_1_complex_2>>



      6.1.4.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.4.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 4 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 56.17 to 30.00 cycles (1.87x speedup).

Details
 - VGATHERDPD: 4 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 6 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.4.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

50 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 144 FP arithmetical operations:
 - 56: addition or subtraction (8 inside FMA instructions)
 - 64: multiply (8 inside FMA instructions)
 - 24: divide
The binary loop is loading 512 bytes (64 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.4.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.







      6.1.5  -  Loop 203 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163,172-202
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (2.25 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 49% of vector register length is used (average across all SSE/AVX instructions).


Details
99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 97% of SSE/AVX loads are used in vector version.
 - 98% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.5.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.5.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.5.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.5.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.02x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCMPPD: 2 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 20 occurrences<<list_path_1_complex_2>>



      6.1.5.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.5.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 6 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 6 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.5.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 110.33 to 37.50 cycles (2.94x speedup).

Details
 - VGATHERQPD: 20 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.5.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

74 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.5.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 248 FP arithmetical operations:
 - 96: addition or subtraction (32 inside FMA instructions)
 - 128: multiply (32 inside FMA instructions)
 - 24: divide
The binary loop is loading 1544 bytes (193 double precision FP elements).
The binary loop is storing 320 bytes (40 double precision FP elements).


      6.1.5.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.







      6.1.6  -  Loop 200 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71-72,79-110.

It is main loop of related source loop which is unrolled by 11 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (2.35 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 47% register length (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.6.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.6.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.6.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.03x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCMPPD: 1 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 20 occurrences<<list_path_1_complex_2>>



      6.1.6.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 8 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 8 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.6.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 105.67 to 32.75 cycles (3.23x speedup).

Details
 - VGATHERQPD: 20 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.6.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

74 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.6.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 248 FP arithmetical operations:
 - 96: addition or subtraction (32 inside FMA instructions)
 - 128: multiply (32 inside FMA instructions)
 - 24: divide
The binary loop is loading 1088 bytes (136 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.6.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.







      6.1.7  -  Loop 320 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:72-83.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

32% of peak computational performance is used (7.73 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 39% of vector register length is used (average across all SSE/AVX instructions).


Details
73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 10.00 cycles (1.50x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.7.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.7.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 9.67 cycles (1.55x speedup).


      6.1.7.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 12 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 12 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.7.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

26 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.7.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 116 FP arithmetical operations:
 - 72: addition or subtraction (12 inside FMA instructions)
 - 32: multiply (12 inside FMA instructions)
 - 12: divide
The binary loop is loading 848 bytes (106 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.7.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.


      6.1.7.1.10  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N







      6.1.8  -  Loop 184 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:43-53.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

37% of peak computational performance is used (9.00 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 16.00 to 14.00 cycles (1.14x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.8.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 44% of vector register length is used (average across all SSE/AVX instructions).


Details
84% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.8.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 9.83 cycles (1.63x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.8.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.8.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 40 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.8.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 16 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 16 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.8.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

26 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.8.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 144 FP arithmetical operations:
 - 76: addition or subtraction (40 inside FMA instructions)
 - 64: multiply (40 inside FMA instructions)
 - 4: divide
The binary loop is loading 1208 bytes (151 double precision FP elements).
The binary loop is storing 160 bytes (20 double precision FP elements).


      6.1.8.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.


      6.1.8.1.10  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N







      6.1.9  -  Loop 318 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:55-63
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

27% of peak computational performance is used (6.67 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 43% of vector register length is used (average across all SSE/AVX instructions).


Details
82% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.9.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 7.17 cycles (2.09x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.9.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.9.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 7.17 cycles (2.09x speedup).


      6.1.9.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 12 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 12 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.9.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.9.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 100 FP arithmetical operations:
 - 56: addition or subtraction (12 inside FMA instructions)
 - 32: multiply (12 inside FMA instructions)
 - 12: divide
The binary loop is loading 584 bytes (73 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.9.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.







      6.1.10  -  Loop 274 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:40-45.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (2.37 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.10.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 54.00 to 16.00 cycles (3.38x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.10.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.10.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 54.00 to 12.00 cycles (4.50x speedup).




      6.1.10.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 12 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 12 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

32 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 128 FP arithmetical operations:
 - 96: multiply
 - 16: divide
 - 16: square root
The binary loop is loading 512 bytes (64 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.10.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/179-069-4349/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_5/oneview_run_1790708432"
[MAQAO] Info: 
