| Loop Id: 135 | Module: exec | Source: advec_mom_kernel.f90:131-131 | Coverage: 0.87% |
|---|
| Loop Id: 135 | Module: exec | Source: advec_mom_kernel.f90:131-131 | Coverage: 0.87% |
|---|
0x42630d VMOVUPD (%RBX,%RAX,1),%YMM0 [1] |
0x426312 VMOVUPD (%RDI,%RAX,1),%YMM9 [4] |
0x426317 VADDPD (%R12,%RAX,1),%YMM0,%YMM5 [5] |
0x42631d VADDPD (%R8,%RAX,1),%YMM9,%YMM6 [2] |
0x426323 VADDPD %YMM6,%YMM5,%YMM12 |
0x426327 VMULPD %YMM14,%YMM12,%YMM15 |
0x42632c VMOVUPD %YMM15,(%R11,%RAX,1) [3] |
0x426332 VMOVUPD 0x20(%RBX,%RAX,1),%YMM11 [1] |
0x426338 VMOVUPD 0x20(%RDI,%RAX,1),%YMM3 [4] |
0x42633e VADDPD 0x20(%R12,%RAX,1),%YMM11,%YMM13 [5] |
0x426345 VADDPD 0x20(%R8,%RAX,1),%YMM3,%YMM1 [2] |
0x42634c VADDPD %YMM1,%YMM13,%YMM4 |
0x426350 VMULPD %YMM14,%YMM4,%YMM7 |
0x426355 VMOVUPD %YMM7,0x20(%R11,%RAX,1) [3] |
0x42635c VMOVUPD 0x40(%RBX,%RAX,1),%YMM2 [1] |
0x426362 VMOVUPD 0x40(%RDI,%RAX,1),%YMM5 [4] |
0x426368 VADDPD 0x40(%R12,%RAX,1),%YMM2,%YMM0 [5] |
0x42636f VADDPD 0x40(%R8,%RAX,1),%YMM5,%YMM9 [2] |
0x426376 VADDPD %YMM9,%YMM0,%YMM6 |
0x42637b VMULPD %YMM14,%YMM6,%YMM12 |
0x426380 VMOVUPD %YMM12,0x40(%R11,%RAX,1) [3] |
0x426387 VMOVUPD 0x60(%RBX,%RAX,1),%YMM15 [1] |
0x42638d VMOVUPD 0x60(%RDI,%RAX,1),%YMM13 [4] |
0x426393 VADDPD 0x60(%R12,%RAX,1),%YMM15,%YMM11 [5] |
0x42639a VADDPD 0x60(%R8,%RAX,1),%YMM13,%YMM3 [2] |
0x4263a1 VADDPD %YMM3,%YMM11,%YMM1 |
0x4263a5 VMULPD %YMM14,%YMM1,%YMM4 |
0x4263aa VMOVUPD %YMM4,0x60(%R11,%RAX,1) [3] |
0x4263b1 SUB $-0x80,%RAX |
0x4263b5 CMP %R10,%RAX |
0x4263b8 JNE 42630d |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 131 - 131 |
-------------------------------------------------------------------------------- |
131: +mass_flux_x(j+1,k-1)+mass_flux_x(j+1,k)) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.50 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | P1, |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:131-131 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 4.00 |
| P0 cycles | 8.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 2.00 |
| P4 cycles | 6.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 6.56 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 31.00 |
| Nb uops | 30.00 |
| Nb loads | 16.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 8.00 |
| Nb FLOP add-sub | 48.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 80.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.50 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | P1, |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:131-131 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 4.00 |
| P0 cycles | 8.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 2.00 |
| P4 cycles | 6.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 6.56 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 31.00 |
| Nb uops | 30.00 |
| Nb loads | 16.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 8.00 |
| Nb FLOP add-sub | 48.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 80.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:131-131 |
| Module | exec |
| nb instructions | 31 |
| nb uops | 30 |
| loop length | 177 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 14 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 6.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
| cycles | 4.00 | 8.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 6.56 |
| Stall cycles | 0.00 |
| Front-end | 6.33 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RBX,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%RDI,%RAX,1),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%R12,%RAX,1),%YMM0,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%R8,%RAX,1),%YMM9,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM6,%YMM5,%YMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM12,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM15,(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RBX,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%RDI,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R12,%RAX,1),%YMM11,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x20(%R8,%RAX,1),%YMM3,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM1,%YMM13,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM4,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM7,0x20(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RBX,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x40(%RDI,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%R12,%RAX,1),%YMM2,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x40(%R8,%RAX,1),%YMM5,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM9,%YMM0,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM6,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM12,0x40(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RBX,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x60(%RDI,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%R12,%RAX,1),%YMM15,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x60(%R8,%RAX,1),%YMM13,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM3,%YMM11,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM4,0x60(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 42630d <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3a1d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:131-131 |
| Module | exec |
| nb instructions | 31 |
| nb uops | 30 |
| loop length | 177 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 14 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 6.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
| cycles | 4.00 | 8.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 6.56 |
| Stall cycles | 0.00 |
| Front-end | 6.33 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RBX,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%RDI,%RAX,1),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%R12,%RAX,1),%YMM0,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%R8,%RAX,1),%YMM9,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM6,%YMM5,%YMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM12,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM15,(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RBX,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%RDI,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R12,%RAX,1),%YMM11,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x20(%R8,%RAX,1),%YMM3,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM1,%YMM13,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM4,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM7,0x20(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RBX,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x40(%RDI,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%R12,%RAX,1),%YMM2,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x40(%R8,%RAX,1),%YMM5,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM9,%YMM0,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM6,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM12,0x40(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RBX,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x60(%RDI,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%R12,%RAX,1),%YMM15,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x60(%R8,%RAX,1),%YMM13,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM3,%YMM11,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM14,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM4,0x60(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 42630d <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3a1d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
