| Loop Id: 137 | Module: exec | Source: advec_mom_kernel.f90:86-87 | Coverage: 2.46% |
|---|
| Loop Id: 137 | Module: exec | Source: advec_mom_kernel.f90:86-87 | Coverage: 2.46% |
|---|
0x4237ad VMOVUPD (%R8,%RAX,1),%YMM15 [2] |
0x4237b3 VADDPD (%R15,%RAX,1),%YMM15,%YMM1 [5] |
0x4237b9 VSUBPD (%R12,%RAX,1),%YMM1,%YMM0 [3] |
0x4237bf VMOVUPD %YMM0,(%RBX,%RAX,1) [7] |
0x4237c4 VMOVUPD (%R9,%RAX,1),%YMM2 [1] |
0x4237ca VSUBPD (%R11,%RAX,1),%YMM2,%YMM3 [6] |
0x4237d0 VADDPD %YMM0,%YMM3,%YMM4 |
0x4237d4 VMOVUPD %YMM4,(%R10,%RAX,1) [4] |
0x4237da VMOVUPD 0x20(%R8,%RAX,1),%YMM5 [2] |
0x4237e1 VADDPD 0x20(%R15,%RAX,1),%YMM5,%YMM6 [5] |
0x4237e8 VSUBPD 0x20(%R12,%RAX,1),%YMM6,%YMM7 [3] |
0x4237ef VMOVUPD %YMM7,0x20(%RBX,%RAX,1) [7] |
0x4237f5 VMOVUPD 0x20(%RAX,%R9,1),%YMM8 [9] |
0x4237fc VSUBPD 0x20(%R11,%RAX,1),%YMM8,%YMM9 [6] |
0x423803 VADDPD %YMM7,%YMM9,%YMM10 |
0x423807 VMOVUPD %YMM10,0x20(%R10,%RAX,1) [4] |
0x42380e VMOVUPD 0x40(%R8,%RAX,1),%YMM11 [2] |
0x423815 VADDPD 0x40(%R15,%RAX,1),%YMM11,%YMM12 [5] |
0x42381c VSUBPD 0x40(%R12,%RAX,1),%YMM12,%YMM13 [3] |
0x423823 VMOVUPD %YMM13,0x40(%RBX,%RAX,1) [7] |
0x423829 VMOVUPD 0x40(%RAX,%R9,1),%YMM14 [9] |
0x423830 VSUBPD 0x40(%R11,%RAX,1),%YMM14,%YMM15 [6] |
0x423837 VADDPD %YMM13,%YMM15,%YMM1 |
0x42383c VMOVUPD %YMM1,0x40(%R10,%RAX,1) [4] |
0x423843 VMOVUPD 0x60(%R8,%RAX,1),%YMM0 [2] |
0x42384a VADDPD 0x60(%R15,%RAX,1),%YMM0,%YMM2 [5] |
0x423851 VSUBPD 0x60(%R12,%RAX,1),%YMM2,%YMM3 [3] |
0x423858 VMOVUPD %YMM3,0x60(%RBX,%RAX,1) [7] |
0x42385e VMOVUPD 0x60(%RAX,%R9,1),%YMM4 [9] |
0x423865 VSUBPD 0x60(%R11,%RAX,1),%YMM4,%YMM5 [6] |
0x42386c VADDPD %YMM3,%YMM5,%YMM6 |
0x423870 VMOVUPD %YMM6,0x60(%R10,%RAX,1) [4] |
0x423877 SUB $-0x80,%RAX |
0x42387b CMP %RAX,0x180(%RSP) [8] |
0x423883 JNE 4237ad |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 86 - 87 |
-------------------------------------------------------------------------------- |
86: post_vol(j,k)= volume(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
87: pre_vol(j,k)=post_vol(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.17 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.04 |
| Bottlenecks | P1, P5, |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:86-87 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 6.83 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 7.67 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 8.00 |
| P1 cycles | 7.00 |
| P2 cycles | 7.00 |
| P3 cycles | 4.00 |
| P4 cycles | 8.00 |
| P5 cycles | 0.50 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 0.00 |
| P10 cycles | 7.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.53 |
| Stall cycles (UFS) | 0.17 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 21.00 |
| Nb stores | 8.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 8.00 |
| Nb FLOP add-sub | 64.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 113.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 648.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 6.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.17 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.04 |
| Bottlenecks | P1, P5, |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:86-87 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 6.83 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 7.67 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 8.00 |
| P1 cycles | 7.00 |
| P2 cycles | 7.00 |
| P3 cycles | 4.00 |
| P4 cycles | 8.00 |
| P5 cycles | 0.50 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 0.00 |
| P10 cycles | 7.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.53 |
| Stall cycles (UFS) | 0.17 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 21.00 |
| Nb stores | 8.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 8.00 |
| Nb FLOP add-sub | 64.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 113.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 648.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 6.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:86-87 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 220 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 7.67 cycles |
| front end | 7.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 8.00 | 7.00 | 7.00 | 4.00 | 8.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 7.00 |
| cycles | 0.50 | 8.00 | 7.00 | 7.00 | 4.00 | 8.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.53 |
| Stall cycles | 0.17 |
| RS full (events) | 0.82 |
| LB full (events) | 0.04 |
| Front-end | 7.67 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R8,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%R15,%RAX,1),%YMM15,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%R12,%RAX,1),%YMM1,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM0,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD (%R9,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD (%R11,%RAX,1),%YMM2,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM0,%YMM3,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM4,(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%R8,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R15,%RAX,1),%YMM5,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x20(%R12,%RAX,1),%YMM6,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM7,0x20(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RAX,%R9,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD 0x20(%R11,%RAX,1),%YMM8,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM7,%YMM9,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM10,0x20(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R8,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%R15,%RAX,1),%YMM11,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x40(%R12,%RAX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM13,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RAX,%R9,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD 0x40(%R11,%RAX,1),%YMM14,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM13,%YMM15,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM1,0x40(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%R8,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%R15,%RAX,1),%YMM0,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x60(%R12,%RAX,1),%YMM2,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM3,0x60(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RAX,%R9,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD 0x60(%R11,%RAX,1),%YMM4,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM3,%YMM5,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM6,0x60(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RAX,0x180(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 4237ad <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xebd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:86-87 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 220 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 7.67 cycles |
| front end | 7.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 8.00 | 7.00 | 7.00 | 4.00 | 8.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 7.00 |
| cycles | 0.50 | 8.00 | 7.00 | 7.00 | 4.00 | 8.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.53 |
| Stall cycles | 0.17 |
| RS full (events) | 0.82 |
| LB full (events) | 0.04 |
| Front-end | 7.67 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R8,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%R15,%RAX,1),%YMM15,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%R12,%RAX,1),%YMM1,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM0,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD (%R9,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD (%R11,%RAX,1),%YMM2,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM0,%YMM3,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM4,(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%R8,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R15,%RAX,1),%YMM5,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x20(%R12,%RAX,1),%YMM6,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM7,0x20(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RAX,%R9,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD 0x20(%R11,%RAX,1),%YMM8,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM7,%YMM9,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM10,0x20(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R8,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%R15,%RAX,1),%YMM11,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x40(%R12,%RAX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM13,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RAX,%R9,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD 0x40(%R11,%RAX,1),%YMM14,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM13,%YMM15,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM1,0x40(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%R8,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%R15,%RAX,1),%YMM0,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x60(%R12,%RAX,1),%YMM2,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM3,0x60(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RAX,%R9,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VSUBPD 0x60(%R11,%RAX,1),%YMM4,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD %YMM3,%YMM5,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM6,0x60(%R10,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RAX,0x180(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 4237ad <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xebd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
