| Loop Id: 286 | Module: exec | Source: calc_dt_kernel.f90:99-129 | Coverage: 8.14% |
|---|
| Loop Id: 286 | Module: exec | Source: calc_dt_kernel.f90:99-129 | Coverage: 8.14% |
|---|
0x43aff8 MOV -0x40(%RBP),%RDX [14] |
0x43affc VMINSD (%RDX),%XMM21,%XMM26 [11] |
0x43b002 LEA 0x1(%RAX),%RDX |
0x43b006 VMINSD %XMM9,%XMM26,%XMM27 |
0x43b00c VMINSD %XMM27,%XMM6,%XMM6 |
0x43b012 CMP %RAX,-0x38(%RBP) [14] |
0x43b016 JE 43b145 |
0x43b01c MOV %RDX,%RAX |
0x43b01f VMOVSD %XMM15,%XMM15,%XMM9 |
0x43b024 VMOVSD %XMM22,%XMM22,%XMM2 |
0x43b02a VMOVSD (%R13,%RAX,8),%XMM1 [9] |
0x43b031 VMOVSD (%R14,%RAX,8),%XMM19 [12] |
0x43b038 VMOVSD 0x8(%RCX,%RAX,8),%XMM22 [15] |
0x43b040 VADDSD %XMM1,%XMM1,%XMM15 |
0x43b044 VADDSD %XMM22,%XMM2,%XMM2 |
0x43b04a VDIVSD (%R12,%RAX,8),%XMM15,%XMM0 [13] |
0x43b050 VFMADD132SD %XMM19,%XMM0,%XMM19 |
0x43b056 VMOVSD %XMM3,%XMM3,%XMM0 |
0x43b05a VMOVSD 0x8(%R8,%RAX,8),%XMM3 [10] |
0x43b061 VMULSD (%R10,%RAX,8),%XMM2,%XMM2 [5] |
0x43b067 VANDPD %XMM4,%XMM0,%XMM15 |
0x43b06b VADDSD 0x8(%R9,%RAX,8),%XMM3,%XMM1 [3] |
0x43b072 VMULSD 0x8(%RDI,%RAX,8),%XMM1,%XMM3 [1] |
0x43b078 VMOVSD (%RBX,%RAX,8),%XMM1 [8] |
0x43b07d VSQRTSD %XMM19,%XMM19,%XMM19 |
0x43b083 VSUBSD %XMM0,%XMM2,%XMM0 |
0x43b087 VANDPD %XMM4,%XMM2,%XMM2 |
0x43b08b VMULSD %XMM1,%XMM5,%XMM18 |
0x43b091 VMULSD %XMM1,%XMM8,%XMM17 |
0x43b097 VMAXSD %XMM19,%XMM5,%XMM24 |
0x43b09d VMULSD %XMM1,%XMM7,%XMM23 |
0x43b0a3 VADDSD %XMM1,%XMM1,%XMM1 |
0x43b0a7 VANDPD %XMM4,%XMM3,%XMM16 |
0x43b0ad VMAXSD %XMM18,%XMM15,%XMM15 |
0x43b0b3 VMAXSD %XMM16,%XMM15,%XMM15 |
0x43b0b9 VDIVSD %XMM15,%XMM17,%XMM21 |
0x43b0bf VMOVSD 0x8(%RSI,%RAX,8),%XMM15 [6] |
0x43b0c5 VADDSD %XMM15,%XMM9,%XMM9 |
0x43b0ca VMULSD (%R11,%RAX,8),%XMM9,%XMM9 [4] |
0x43b0d0 VSUBSD %XMM9,%XMM3,%XMM20 |
0x43b0d6 VANDPD %XMM4,%XMM9,%XMM9 |
0x43b0da VMAXSD %XMM9,%XMM2,%XMM2 |
0x43b0df VADDSD %XMM20,%XMM0,%XMM0 |
0x43b0e5 VMAXSD %XMM18,%XMM2,%XMM9 |
0x43b0eb VMINSD (%R15,%RAX,8),%XMM14,%XMM2 [7] |
0x43b0f1 VMULSD %XMM10,%XMM2,%XMM2 |
0x43b0f6 VDIVSD %XMM1,%XMM0,%XMM0 |
0x43b0fa VDIVSD %XMM9,%XMM23,%XMM9 |
0x43b100 VCOMISD %XMM0,%XMM11 |
0x43b104 VDIVSD %XMM24,%XMM2,%XMM25 |
0x43b10a VMINSD %XMM25,%XMM9,%XMM9 |
0x43b110 JBE 43aff8 |
0x43b116 VDIVSD %XMM0,%XMM13,%XMM2 |
0x43b11a MOV -0x48(%RBP),%RDX [14] |
0x43b11e VXORPD %XMM12,%XMM2,%XMM1 |
0x43b123 VMULSD (%RDX),%XMM1,%XMM0 [2] |
0x43b127 LEA 0x1(%RAX),%RDX |
0x43b12b VMINSD %XMM21,%XMM0,%XMM2 |
0x43b131 VMINSD %XMM9,%XMM2,%XMM9 |
0x43b136 VMINSD %XMM9,%XMM6,%XMM6 |
0x43b13b CMP %RAX,-0x38(%RBP) [14] |
0x43b13f JNE 43b01c |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 99 - 129 |
-------------------------------------------------------------------------------- |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
124: dtdivt=dtdiv_safe*(-1.0_8/div) |
125: ELSE |
126: dtdivt=g_big |
127: ENDIF |
128: |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.90 |
| Bottlenecks | |
| Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
| Source | calc_dt_kernel.f90:99-129 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 26.50 |
| CQA cycles if no scalar integer | 26.50 |
| CQA cycles if FP arith vectorized | 13.25 |
| CQA cycles if fully vectorized | 13.25 |
| Front-end cycles | 9.83 |
| DIV/SQRT cycles | 13.92 |
| P0 cycles | 13.75 |
| P1 cycles | 5.00 |
| P2 cycles | 5.00 |
| P3 cycles | 0.00 |
| P4 cycles | 13.83 |
| P5 cycles | 2.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.50 |
| P10 cycles | 5.00 |
| P11 cycles | 26.50 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 28.08 - 27.64 |
| Stall cycles (UFS) | 17.54 - 17.10 |
| Nb insns | 53.50 |
| Nb uops | 53.00 |
| Nb loads | 15.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.91 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 7.50 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 5.50 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 1.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.55 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 120.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 12.00 |
| Vectorization ratio all | 9.45 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 24.27 |
| Vector-efficiency ratio all | 13.68 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 15.53 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.99 |
| Bottlenecks | P0, |
| Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
| Source | calc_dt_kernel.f90:99-129 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 28.50 |
| CQA cycles if no scalar integer | 28.50 |
| CQA cycles if FP arith vectorized | 14.25 |
| CQA cycles if fully vectorized | 14.25 |
| Front-end cycles | 10.00 |
| DIV/SQRT cycles | 14.33 |
| P0 cycles | 14.33 |
| P1 cycles | 5.00 |
| P2 cycles | 5.00 |
| P3 cycles | 0.00 |
| P4 cycles | 14.33 |
| P5 cycles | 2.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.00 |
| P11 cycles | 28.50 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 30.51 - 29.61 |
| Stall cycles (UFS) | 19.82 - 18.92 |
| Nb insns | 55.00 |
| Nb uops | 54.00 |
| Nb loads | 15.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.88 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 6.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 1.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.21 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 120.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 12.00 |
| Vectorization ratio all | 10.20 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 26.32 |
| Vector-efficiency ratio all | 13.78 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 15.79 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.81 |
| Bottlenecks | P0, |
| Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
| Source | calc_dt_kernel.f90:99-129 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.50 |
| CQA cycles if no scalar integer | 24.50 |
| CQA cycles if FP arith vectorized | 12.25 |
| CQA cycles if fully vectorized | 12.25 |
| Front-end cycles | 9.67 |
| DIV/SQRT cycles | 13.50 |
| P0 cycles | 13.17 |
| P1 cycles | 5.00 |
| P2 cycles | 5.00 |
| P3 cycles | 0.00 |
| P4 cycles | 13.33 |
| P5 cycles | 2.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.00 |
| P11 cycles | 24.50 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 25.65 - 25.66 |
| Stall cycles (UFS) | 15.27 - 15.28 |
| Nb insns | 52.00 |
| Nb uops | 52.00 |
| Nb loads | 15.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.94 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 7.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 5.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 1.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.90 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 120.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 12.00 |
| Vectorization ratio all | 8.70 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 22.22 |
| Vector-efficiency ratio all | 13.59 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 15.28 |
| Path / |
| Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
| Source file and lines | calc_dt_kernel.f90:99-129 |
| Module | exec |
| nb instructions | 53.50 |
| nb uops | 53 |
| loop length | 291.50 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 26 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.07 |
| micro-operation queue | 9.83 cycles |
| front end | 9.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.92 | 13.75 | 5.00 | 5.00 | 0.00 | 13.83 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 5.00 |
| cycles | 13.92 | 13.75 | 5.00 | 5.00 | 0.00 | 13.83 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 5.00 |
| Cycles executing div or sqrt instructions | 26.50 |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 28.08-27.63 |
| Stall cycles | 17.54-17.10 |
| PRF_FLOAT full (events) | 19.35-18.80 |
| Front-end | 9.83 |
| Dispatch | 13.92 |
| DIV/SQRT | 26.50 |
| Data deps. | 4.00 |
| Overall L1 | 26.50 |
| all | 9% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 24% |
| all | 13% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 15% |
| Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
| Source file and lines | calc_dt_kernel.f90:99-129 |
| Module | exec |
| nb instructions | 55 |
| nb uops | 54 |
| loop length | 297 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 26 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 10.00 cycles |
| front end | 10.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.33 | 14.33 | 5.00 | 5.00 | 0.00 | 14.33 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.00 |
| cycles | 14.33 | 14.33 | 5.00 | 5.00 | 0.00 | 14.33 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.00 |
| Cycles executing div or sqrt instructions | 28.50 |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 30.51-29.61 |
| Stall cycles | 19.82-18.92 |
| PRF_FLOAT full (events) | 20.83-19.92 |
| Front-end | 10.00 |
| Dispatch | 14.33 |
| DIV/SQRT | 28.50 |
| Data deps. | 4.00 |
| Overall L1 | 28.50 |
| all | 10% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 26% |
| all | 13% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMOVSD %XMM15,%XMM15,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD %XMM22,%XMM22,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD (%R13,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%R14,%RAX,8),%XMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x8(%RCX,%RAX,8),%XMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM1,%XMM1,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM22,%XMM2,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VDIVSD (%R12,%RAX,8),%XMM15,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VFMADD132SD %XMM19,%XMM0,%XMM19 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM3,%XMM3,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%R8,%RAX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD (%R10,%RAX,8),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VANDPD %XMM4,%XMM0,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VADDSD 0x8(%R9,%RAX,8),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMULSD 0x8(%RDI,%RAX,8),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD (%RBX,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VSQRTSD %XMM19,%XMM19,%XMM19 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VSUBSD %XMM0,%XMM2,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM4,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMULSD %XMM1,%XMM5,%XMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM1,%XMM8,%XMM17 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMAXSD %XMM19,%XMM5,%XMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM1,%XMM7,%XMM23 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM4,%XMM3,%XMM16 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM18,%XMM15,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMAXSD %XMM16,%XMM15,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM15,%XMM17,%XMM21 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VMOVSD 0x8(%RSI,%RAX,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM15,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD (%R11,%RAX,8),%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBSD %XMM9,%XMM3,%XMM20 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM4,%XMM9,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM9,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM20,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMAXSD %XMM18,%XMM2,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD (%R15,%RAX,8),%XMM14,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM10,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM1,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VDIVSD %XMM9,%XMM23,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VCOMISD %XMM0,%XMM11 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VDIVSD %XMM24,%XMM2,%XMM25 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VMINSD %XMM25,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| JBE 43aff8 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x3b8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VDIVSD %XMM0,%XMM13,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VXORPD %XMM12,%XMM2,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VMULSD (%RDX),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMINSD %XMM21,%XMM0,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD %XMM9,%XMM2,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD %XMM9,%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RAX,-0x38(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 43b01c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x3dc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
| Source file and lines | calc_dt_kernel.f90:99-129 |
| Module | exec |
| nb instructions | 52 |
| nb uops | 52 |
| loop length | 286 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 26 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.14 |
| micro-operation queue | 9.67 cycles |
| front end | 9.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.50 | 13.17 | 5.00 | 5.00 | 0.00 | 13.33 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| cycles | 13.50 | 13.17 | 5.00 | 5.00 | 0.00 | 13.33 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| Cycles executing div or sqrt instructions | 24.50 |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 25.65-25.66 |
| Stall cycles | 15.27-15.28 |
| PRF_FLOAT full (events) | 17.87-17.67 |
| Front-end | 9.67 |
| Dispatch | 13.50 |
| DIV/SQRT | 24.50 |
| Data deps. | 4.00 |
| Overall L1 | 24.50 |
| all | 8% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 22% |
| all | 13% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMINSD (%RDX),%XMM21,%XMM26 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMINSD %XMM9,%XMM26,%XMM27 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD %XMM27,%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RAX,-0x38(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JE 43b145 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x505> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMOVSD %XMM15,%XMM15,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD %XMM22,%XMM22,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD (%R13,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%R14,%RAX,8),%XMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x8(%RCX,%RAX,8),%XMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM1,%XMM1,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM22,%XMM2,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VDIVSD (%R12,%RAX,8),%XMM15,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VFMADD132SD %XMM19,%XMM0,%XMM19 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM3,%XMM3,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%R8,%RAX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD (%R10,%RAX,8),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VANDPD %XMM4,%XMM0,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VADDSD 0x8(%R9,%RAX,8),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMULSD 0x8(%RDI,%RAX,8),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD (%RBX,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VSQRTSD %XMM19,%XMM19,%XMM19 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VSUBSD %XMM0,%XMM2,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM4,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMULSD %XMM1,%XMM5,%XMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM1,%XMM8,%XMM17 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMAXSD %XMM19,%XMM5,%XMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM1,%XMM7,%XMM23 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM4,%XMM3,%XMM16 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM18,%XMM15,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMAXSD %XMM16,%XMM15,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM15,%XMM17,%XMM21 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VMOVSD 0x8(%RSI,%RAX,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM15,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD (%R11,%RAX,8),%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBSD %XMM9,%XMM3,%XMM20 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM4,%XMM9,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM9,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM20,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMAXSD %XMM18,%XMM2,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD (%R15,%RAX,8),%XMM14,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM10,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM1,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VDIVSD %XMM9,%XMM23,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VCOMISD %XMM0,%XMM11 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VDIVSD %XMM24,%XMM2,%XMM25 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VMINSD %XMM25,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| JBE 43aff8 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x3b8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
