| Loop Id: 121 | Module: exec | Source: advec_mom_kernel.f90:248-248 | Coverage: 3.35% |
|---|
| Loop Id: 121 | Module: exec | Source: advec_mom_kernel.f90:248-248 | Coverage: 3.35% |
|---|
0x424574 VMOVUPD (%R12,%RAX,1),%YMM5 [5] |
0x42457a VMOVUPD (%RCX,%RAX,1),%YMM0 [3] |
0x42457f VMOVUPD 0x20(%RCX,%RAX,1),%YMM12 [3] |
0x424585 VMOVUPD 0x40(%RCX,%RAX,1),%YMM10 [3] |
0x42458b VFMSUB132PD (%R13,%RAX,1),%YMM5,%YMM0 [1] |
0x424592 VMOVUPD 0x60(%RCX,%RAX,1),%YMM3 [3] |
0x424598 VADDPD (%RBX,%RAX,1),%YMM0,%YMM6 [2] |
0x42459d VDIVPD (%R11,%RAX,1),%YMM6,%YMM9 [4] |
0x4245a3 VMOVUPD %YMM9,(%RCX,%RAX,1) [3] |
0x4245a8 VMOVUPD 0x20(%R12,%RAX,1),%YMM15 [5] |
0x4245af VFMSUB132PD 0x20(%R13,%RAX,1),%YMM15,%YMM12 [1] |
0x4245b6 VADDPD 0x20(%RBX,%RAX,1),%YMM12,%YMM11 [2] |
0x4245bc VDIVPD 0x20(%R11,%RAX,1),%YMM11,%YMM13 [4] |
0x4245c3 VMOVUPD %YMM13,0x20(%RCX,%RAX,1) [3] |
0x4245c9 VMOVUPD 0x40(%R12,%RAX,1),%YMM8 [5] |
0x4245d0 VFMSUB132PD 0x40(%R13,%RAX,1),%YMM8,%YMM10 [1] |
0x4245d7 VADDPD 0x40(%RBX,%RAX,1),%YMM10,%YMM1 [2] |
0x4245dd VDIVPD 0x40(%R11,%RAX,1),%YMM1,%YMM14 [4] |
0x4245e4 VMOVUPD %YMM14,0x40(%RCX,%RAX,1) [3] |
0x4245ea VMOVUPD 0x60(%R12,%RAX,1),%YMM4 [5] |
0x4245f1 VFMSUB132PD 0x60(%R13,%RAX,1),%YMM4,%YMM3 [1] |
0x4245f8 VADDPD 0x60(%RBX,%RAX,1),%YMM3,%YMM7 [2] |
0x4245fe VDIVPD 0x60(%R11,%RAX,1),%YMM7,%YMM2 [4] |
0x424605 VMOVUPD %YMM2,0x60(%RCX,%RAX,1) [3] |
0x42460b SUB $-0x80,%RAX |
0x42460f CMP %R8,%RAX |
0x424612 JNE 424574 |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 248 - 248 |
-------------------------------------------------------------------------------- |
248: vel1 (j,k)=(vel1(j,k)*node_mass_pre(j,k)+mom_flux(j,k-1)-mom_flux(j,k))/node_mass_post(j,k) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.80 |
| Bottlenecks | P0, |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:248-248 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 32.00 |
| CQA cycles if fully vectorized | 32.00 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 4.00 |
| P0 cycles | 4.00 |
| P1 cycles | 6.67 |
| P2 cycles | 6.67 |
| P3 cycles | 2.00 |
| P4 cycles | 4.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 6.67 |
| P11 cycles | 32.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 32.26 - 32.28 |
| Stall cycles (UFS) | 25.32 - 25.34 |
| Nb insns | 27.00 |
| Nb uops | 26.00 |
| Nb loads | 20.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.00 |
| Nb FLOP add-sub | 16.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 16.00 |
| Nb FLOP div | 16.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 24.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 640.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | 50.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.80 |
| Bottlenecks | P0, |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:248-248 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 32.00 |
| CQA cycles if fully vectorized | 32.00 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 4.00 |
| P0 cycles | 4.00 |
| P1 cycles | 6.67 |
| P2 cycles | 6.67 |
| P3 cycles | 2.00 |
| P4 cycles | 4.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 6.67 |
| P11 cycles | 32.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 32.26 - 32.28 |
| Stall cycles (UFS) | 25.32 - 25.34 |
| Nb insns | 27.00 |
| Nb uops | 26.00 |
| Nb loads | 20.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.00 |
| Nb FLOP add-sub | 16.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 16.00 |
| Nb FLOP div | 16.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 24.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 640.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | 50.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:248-248 |
| Module | exec |
| nb instructions | 27 |
| nb uops | 26 |
| loop length | 164 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
| cycles | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 32.26-32.28 |
| Stall cycles | 25.32-25.34 |
| LB full (events) | 29.58-29.60 |
| LM full (events) | 0.13-0.12 |
| Front-end | 6.33 |
| Dispatch | 6.67 |
| DIV/SQRT | 32.00 |
| Data deps. | 1.00 |
| Overall L1 | 32.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | 50% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R12,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%RCX,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%RCX,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x40(%RCX,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD (%R13,%RAX,1),%YMM5,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x60(%RCX,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RBX,%RAX,1),%YMM0,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD (%R11,%RAX,1),%YMM6,%YMM9 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM9,(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%R12,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD 0x20(%R13,%RAX,1),%YMM15,%YMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD 0x20(%RBX,%RAX,1),%YMM12,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD 0x20(%R11,%RAX,1),%YMM11,%YMM13 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM13,0x20(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R12,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD 0x40(%R13,%RAX,1),%YMM8,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD 0x40(%RBX,%RAX,1),%YMM10,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD 0x40(%R11,%RAX,1),%YMM1,%YMM14 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM14,0x40(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%R12,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD 0x60(%R13,%RAX,1),%YMM4,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD 0x60(%RBX,%RAX,1),%YMM3,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD 0x60(%R11,%RAX,1),%YMM7,%YMM2 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM2,0x60(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 424574 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1c84> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:248-248 |
| Module | exec |
| nb instructions | 27 |
| nb uops | 26 |
| loop length | 164 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
| cycles | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 32.26-32.28 |
| Stall cycles | 25.32-25.34 |
| LB full (events) | 29.58-29.60 |
| LM full (events) | 0.13-0.12 |
| Front-end | 6.33 |
| Dispatch | 6.67 |
| DIV/SQRT | 32.00 |
| Data deps. | 1.00 |
| Overall L1 | 32.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | 50% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R12,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%RCX,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%RCX,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x40(%RCX,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD (%R13,%RAX,1),%YMM5,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x60(%RCX,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RBX,%RAX,1),%YMM0,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD (%R11,%RAX,1),%YMM6,%YMM9 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM9,(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%R12,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD 0x20(%R13,%RAX,1),%YMM15,%YMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD 0x20(%RBX,%RAX,1),%YMM12,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD 0x20(%R11,%RAX,1),%YMM11,%YMM13 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM13,0x20(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R12,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD 0x40(%R13,%RAX,1),%YMM8,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD 0x40(%RBX,%RAX,1),%YMM10,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD 0x40(%R11,%RAX,1),%YMM1,%YMM14 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM14,0x40(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%R12,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMSUB132PD 0x60(%R13,%RAX,1),%YMM4,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD 0x60(%RBX,%RAX,1),%YMM3,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD 0x60(%R11,%RAX,1),%YMM7,%YMM2 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
| VMOVUPD %YMM2,0x60(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 424574 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1c84> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
