| Loop Id: 225 | Module: exec | Source: accelerate_kernel.f90:62-76 | Coverage: 4.68% |
|---|
| Loop Id: 225 | Module: exec | Source: accelerate_kernel.f90:62-76 | Coverage: 4.68% |
|---|
0x42c430 VMOVUPD -0x8(%RBX,%R8,8),%ZMM0 [12] |
0x42c43b VMOVUPD (%RBX,%R8,8),%ZMM3 [12] |
0x42c442 VMULPD -0x8(%R14,%R8,8),%ZMM0,%ZMM0 [8] |
0x42c44d VFMADD231PD (%R14,%R8,8),%ZMM3,%ZMM0 [8] |
0x42c454 VMOVUPD -0x8(%R9,%R8,8),%ZMM3 [15] |
0x42c45f VMOVUPD (%R9,%R8,8),%ZMM4 [15] |
0x42c466 VFMADD132PD (%R11,%R8,8),%ZMM0,%ZMM4 [4] |
0x42c46d VFMADD231PD -0x8(%R11,%R8,8),%ZMM3,%ZMM4 [4] |
0x42c478 VMULPD %ZMM1,%ZMM4,%ZMM0 |
0x42c47e VDIVPD %ZMM0,%ZMM2,%ZMM0 |
0x42c484 VMOVUPD (%RDX,%R8,8),%ZMM3 [13] |
0x42c48b VMOVUPD -0x8(%RAX,%R8,8),%ZMM4 [3] |
0x42c496 VMOVUPD (%RAX,%R8,8),%ZMM17 [3] |
0x42c49d VSUBPD %ZMM17,%ZMM4,%ZMM18 |
0x42c4a3 VMULPD %ZMM3,%ZMM18,%ZMM18 |
0x42c4a9 VMOVUPD (%RDI,%R8,8),%ZMM19 [16] |
0x42c4b0 VMOVUPD -0x8(%R13,%R8,8),%ZMM20 [9] |
0x42c4bb VMOVUPD (%R13,%R8,8),%ZMM25 [9] |
0x42c4c3 VSUBPD %ZMM25,%ZMM20,%ZMM26 |
0x42c4c9 VFMADD213PD %ZMM18,%ZMM19,%ZMM26 |
0x42c4cf VMOVUPD -0x8(%RSI,%R8,8),%ZMM18 [1] |
0x42c4da VMOVUPD (%RSI,%R8,8),%ZMM27 [1] |
0x42c4e1 VSUBPD %ZMM17,%ZMM25,%ZMM17 |
0x42c4e7 VMULPD %ZMM17,%ZMM27,%ZMM17 |
0x42c4ed VSUBPD %ZMM4,%ZMM20,%ZMM4 |
0x42c4f3 VFMADD213PD %ZMM17,%ZMM18,%ZMM4 |
0x42c4f9 VMOVUPD -0x8(%R12,%R8,8),%ZMM17 [7] |
0x42c504 VMOVUPD (%R12,%R8,8),%ZMM20 [7] |
0x42c50b VSUBPD %ZMM20,%ZMM17,%ZMM25 |
0x42c511 VMOVUPD -0x8(%R10,%R8,8),%ZMM28 [2] |
0x42c51c VMOVUPD (%R10,%R8,8),%ZMM29 [2] |
0x42c523 VSUBPD %ZMM29,%ZMM28,%ZMM30 |
0x42c529 VFMADD213PD %ZMM26,%ZMM3,%ZMM25 |
0x42c52f VFMADD231PD %ZMM30,%ZMM19,%ZMM25 |
0x42c535 VFMADD213PD (%R15,%R8,8),%ZMM0,%ZMM25 [10] |
0x42c53c MOV 0x128(%RSP),%RCX [14] |
0x42c544 VMOVUPD %ZMM25,(%RCX,%R8,8) [6] |
0x42c54b VSUBPD %ZMM20,%ZMM29,%ZMM3 |
0x42c551 VSUBPD %ZMM17,%ZMM28,%ZMM17 |
0x42c557 VFMADD213PD %ZMM4,%ZMM27,%ZMM3 |
0x42c55d VFMADD231PD %ZMM17,%ZMM18,%ZMM3 |
0x42c563 MOV 0x130(%RSP),%RCX [14] |
0x42c56b VFMADD213PD (%RCX,%R8,8),%ZMM0,%ZMM3 [5] |
0x42c572 MOV 0x138(%RSP),%RCX [14] |
0x42c57a VMOVUPD %ZMM3,(%RCX,%R8,8) [11] |
0x42c581 ADD $0x8,%R8 |
0x42c585 CMP 0x88(%RSP),%R8 [14] |
0x42c58d JB 42c430 |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 62 - 76 |
-------------------------------------------------------------------------------- |
62: DO j=x_min,x_max+1 |
63: stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1) & |
64: +density0(j ,k-1)*volume(j ,k-1) & |
65: +density0(j ,k )*volume(j ,k ) & |
66: +density0(j-1,k )*volume(j-1,k )) & |
67: *0.25_8) |
68: |
69: xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j ,k )*(pressure(j ,k )-pressure(j-1,k )) & |
70: +xarea(j ,k-1)*(pressure(j ,k-1)-pressure(j-1,k-1))) |
71: yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j ,k )*(pressure(j ,k )-pressure(j ,k-1)) & |
72: +yarea(j-1,k )*(pressure(j-1,k )-pressure(j-1,k-1))) |
73: xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j ,k )*(viscosity(j ,k )-viscosity(j-1,k )) & |
74: +xarea(j ,k-1)*(viscosity(j ,k-1)-viscosity(j-1,k-1))) |
75: yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j ,k )*(viscosity(j ,k )-viscosity(j ,k-1)) & |
76: +yarea(j-1,k )*(viscosity(j-1,k )-viscosity(j-1,k-1))) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P0, |
| Function | accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source | accelerate_kernel.f90:62-76 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 16.00 |
| Front-end cycles | 9.17 |
| DIV/SQRT cycles | 13.00 |
| P0 cycles | 11.50 |
| P1 cycles | 8.67 |
| P2 cycles | 8.67 |
| P3 cycles | 1.00 |
| P4 cycles | 13.00 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 8.67 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 16.47 - 17.10 |
| Stall cycles (UFS) | 6.65 - 7.28 |
| Nb insns | 48.00 |
| Nb uops | 49.00 |
| Nb loads | 26.00 |
| Nb stores | 2.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 17.50 |
| Nb FLOP add-sub | 64.00 |
| Nb FLOP mul | 32.00 |
| Nb FLOP fma | 88.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 98.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1440.00 |
| Bytes stored | 128.00 |
| Stride 0 | 1.00 |
| Stride 1 | 3.00 |
| Stride n | 9.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P0, |
| Function | accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source | accelerate_kernel.f90:62-76 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 16.00 |
| Front-end cycles | 9.17 |
| DIV/SQRT cycles | 13.00 |
| P0 cycles | 11.50 |
| P1 cycles | 8.67 |
| P2 cycles | 8.67 |
| P3 cycles | 1.00 |
| P4 cycles | 13.00 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 8.67 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 16.47 - 17.10 |
| Stall cycles (UFS) | 6.65 - 7.28 |
| Nb insns | 48.00 |
| Nb uops | 49.00 |
| Nb loads | 26.00 |
| Nb stores | 2.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 17.50 |
| Nb FLOP add-sub | 64.00 |
| Nb FLOP mul | 32.00 |
| Nb FLOP fma | 88.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 98.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1440.00 |
| Bytes stored | 128.00 |
| Stride 0 | 1.00 |
| Stride 1 | 3.00 |
| Stride n | 9.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | accelerate_kernel.f90:62-76 |
| Module | exec |
| nb instructions | 48 |
| nb uops | 49 |
| loop length | 355 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 15 |
| nb stack references | 4 |
| ADD-SUB / MUL ratio | 2.00 |
| micro-operation queue | 9.17 cycles |
| front end | 9.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.00 | 0.00 | 8.67 | 8.67 | 1.00 | 13.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| cycles | 13.00 | 11.50 | 8.67 | 8.67 | 1.00 | 13.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 16.47-17.10 |
| Stall cycles | 6.65-7.28 |
| LB full (events) | 7.30-7.93 |
| Front-end | 9.17 |
| Dispatch | 13.00 |
| DIV/SQRT | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0x8(%RBX,%R8,8),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RBX,%R8,8),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD -0x8(%R14,%R8,8),%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%R14,%R8,8),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD -0x8(%R9,%R8,8),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R9,%R8,8),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFMADD132PD (%R11,%R8,8),%ZMM0,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD -0x8(%R11,%R8,8),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD %ZMM1,%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM0,%ZMM2,%ZMM0 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VMOVUPD (%RDX,%R8,8),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD -0x8(%RAX,%R8,8),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RAX,%R8,8),%ZMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM17,%ZMM4,%ZMM18 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM3,%ZMM18,%ZMM18 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%RDI,%R8,8),%ZMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD -0x8(%R13,%R8,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R13,%R8,8),%ZMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM25,%ZMM20,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM18,%ZMM19,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD -0x8(%RSI,%R8,8),%ZMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RSI,%R8,8),%ZMM27 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM17,%ZMM25,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM17,%ZMM27,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VSUBPD %ZMM4,%ZMM20,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM17,%ZMM18,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD -0x8(%R12,%R8,8),%ZMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R12,%R8,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM20,%ZMM17,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD -0x8(%R10,%R8,8),%ZMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R10,%R8,8),%ZMM29 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM29,%ZMM28,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM26,%ZMM3,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM30,%ZMM19,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD (%R15,%R8,8),%ZMM0,%ZMM25 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x128(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD %ZMM25,(%RCX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VSUBPD %ZMM20,%ZMM29,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM17,%ZMM28,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM4,%ZMM27,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM17,%ZMM18,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV 0x130(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD213PD (%RCX,%R8,8),%ZMM0,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x138(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD %ZMM3,(%RCX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP 0x88(%RSP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JB 42c430 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | accelerate_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | accelerate_kernel.f90:62-76 |
| Module | exec |
| nb instructions | 48 |
| nb uops | 49 |
| loop length | 355 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 15 |
| nb stack references | 4 |
| ADD-SUB / MUL ratio | 2.00 |
| micro-operation queue | 9.17 cycles |
| front end | 9.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.00 | 0.00 | 8.67 | 8.67 | 1.00 | 13.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| cycles | 13.00 | 11.50 | 8.67 | 8.67 | 1.00 | 13.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 8.67 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 16.47-17.10 |
| Stall cycles | 6.65-7.28 |
| LB full (events) | 7.30-7.93 |
| Front-end | 9.17 |
| Dispatch | 13.00 |
| DIV/SQRT | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0x8(%RBX,%R8,8),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RBX,%R8,8),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD -0x8(%R14,%R8,8),%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%R14,%R8,8),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD -0x8(%R9,%R8,8),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R9,%R8,8),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFMADD132PD (%R11,%R8,8),%ZMM0,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD -0x8(%R11,%R8,8),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD %ZMM1,%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM0,%ZMM2,%ZMM0 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VMOVUPD (%RDX,%R8,8),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD -0x8(%RAX,%R8,8),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RAX,%R8,8),%ZMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM17,%ZMM4,%ZMM18 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM3,%ZMM18,%ZMM18 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%RDI,%R8,8),%ZMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD -0x8(%R13,%R8,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R13,%R8,8),%ZMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM25,%ZMM20,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM18,%ZMM19,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD -0x8(%RSI,%R8,8),%ZMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RSI,%R8,8),%ZMM27 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM17,%ZMM25,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM17,%ZMM27,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VSUBPD %ZMM4,%ZMM20,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM17,%ZMM18,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD -0x8(%R12,%R8,8),%ZMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R12,%R8,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM20,%ZMM17,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD -0x8(%R10,%R8,8),%ZMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R10,%R8,8),%ZMM29 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM29,%ZMM28,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM26,%ZMM3,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM30,%ZMM19,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD (%R15,%R8,8),%ZMM0,%ZMM25 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x128(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD %ZMM25,(%RCX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VSUBPD %ZMM20,%ZMM29,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM17,%ZMM28,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM4,%ZMM27,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM17,%ZMM18,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV 0x130(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD213PD (%RCX,%R8,8),%ZMM0,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x138(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD %ZMM3,(%RCX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP 0x88(%RSP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JB 42c430 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
