| Loop Id: 102 | Module: exec | Source: advec_cell_kernel.f90:192-193 | Coverage: 1.04% |
|---|
| Loop Id: 102 | Module: exec | Source: advec_cell_kernel.f90:192-193 | Coverage: 1.04% |
|---|
0x41d463 VMOVUPD (%RDX,%RAX,1),%YMM12 [3] |
0x41d468 MOV 0xe8(%RSP),%RSI [6] |
0x41d470 VADDPD (%R15,%RAX,1),%YMM12,%YMM13 [1] |
0x41d476 VSUBPD (%RCX,%RAX,1),%YMM13,%YMM14 [5] |
0x41d47b VMOVUPD %YMM14,(%R12,%RAX,1) [2] |
0x41d481 VMOVUPD (%RDX,%RAX,1),%YMM15 [3] |
0x41d486 VMOVUPD %YMM15,(%RBX,%RAX,1) [4] |
0x41d48b VMOVUPD 0x20(%RDX,%RAX,1),%YMM5 [3] |
0x41d491 VADDPD 0x20(%R15,%RAX,1),%YMM5,%YMM0 [1] |
0x41d498 VSUBPD 0x20(%RCX,%RAX,1),%YMM0,%YMM1 [5] |
0x41d49e VMOVUPD %YMM1,0x20(%R12,%RAX,1) [2] |
0x41d4a5 VMOVUPD 0x20(%RDX,%RAX,1),%YMM6 [3] |
0x41d4ab VMOVUPD %YMM6,0x20(%RBX,%RAX,1) [4] |
0x41d4b1 VMOVUPD 0x40(%RDX,%RAX,1),%YMM7 [3] |
0x41d4b7 VADDPD 0x40(%R15,%RAX,1),%YMM7,%YMM2 [1] |
0x41d4be VSUBPD 0x40(%RCX,%RAX,1),%YMM2,%YMM3 [5] |
0x41d4c4 VMOVUPD %YMM3,0x40(%R12,%RAX,1) [2] |
0x41d4cb VMOVUPD 0x40(%RDX,%RAX,1),%YMM4 [3] |
0x41d4d1 VMOVUPD %YMM4,0x40(%RBX,%RAX,1) [4] |
0x41d4d7 VMOVUPD 0x60(%RDX,%RAX,1),%YMM8 [3] |
0x41d4dd VADDPD 0x60(%R15,%RAX,1),%YMM8,%YMM9 [1] |
0x41d4e4 VSUBPD 0x60(%RCX,%RAX,1),%YMM9,%YMM10 [5] |
0x41d4ea VMOVUPD %YMM10,0x60(%R12,%RAX,1) [2] |
0x41d4f1 VMOVUPD 0x60(%RDX,%RAX,1),%YMM11 [3] |
0x41d4f7 VMOVUPD %YMM11,0x60(%RBX,%RAX,1) [4] |
0x41d4fd SUB $-0x80,%RAX |
0x41d501 CMP %RSI,%RAX |
0x41d504 JNE 41d463 |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 192 - 193 |
-------------------------------------------------------------------------------- |
192: pre_vol(j,k)=volume(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
193: post_vol(j,k)=volume(j,k) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.06 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | micro-operation queue, |
| Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
| Source | advec_cell_kernel.f90:192-193 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.83 |
| CQA cycles if no scalar integer | 5.83 |
| CQA cycles if FP arith vectorized | 5.50 |
| CQA cycles if fully vectorized | 2.92 |
| Front-end cycles | 5.83 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 4.00 |
| P1 cycles | 5.67 |
| P2 cycles | 5.67 |
| P3 cycles | 4.00 |
| P4 cycles | 4.00 |
| P5 cycles | 0.50 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.67 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 6.02 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 28.00 |
| Nb uops | 27.00 |
| Nb loads | 17.00 |
| Nb stores | 8.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 5.49 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 133.03 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 520.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 4.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.06 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | micro-operation queue, |
| Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
| Source | advec_cell_kernel.f90:192-193 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.83 |
| CQA cycles if no scalar integer | 5.83 |
| CQA cycles if FP arith vectorized | 5.50 |
| CQA cycles if fully vectorized | 2.92 |
| Front-end cycles | 5.83 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 4.00 |
| P1 cycles | 5.67 |
| P2 cycles | 5.67 |
| P3 cycles | 4.00 |
| P4 cycles | 4.00 |
| P5 cycles | 0.50 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.67 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 6.02 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 28.00 |
| Nb uops | 27.00 |
| Nb loads | 17.00 |
| Nb stores | 8.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 5.49 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 133.03 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 520.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 4.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
| Source file and lines | advec_cell_kernel.f90:192-193 |
| Module | exec |
| nb instructions | 28 |
| nb uops | 27 |
| loop length | 167 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 5.83 cycles |
| front end | 5.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 4.00 | 5.67 | 5.67 | 4.00 | 4.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 5.67 |
| cycles | 0.50 | 4.00 | 5.67 | 5.67 | 4.00 | 4.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 5.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 6.02 |
| Stall cycles | 0.00 |
| Front-end | 5.83 |
| Dispatch | 5.67 |
| Data deps. | 1.00 |
| Overall L1 | 5.83 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RDX,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| MOV 0xe8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R15,%RAX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%RCX,%RAX,1),%YMM13,%YMM14 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM14,(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD (%RDX,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM15,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RDX,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R15,%RAX,1),%YMM5,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x20(%RCX,%RAX,1),%YMM0,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM1,0x20(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RDX,%RAX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM6,0x20(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RDX,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%R15,%RAX,1),%YMM7,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x40(%RCX,%RAX,1),%YMM2,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM3,0x40(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RDX,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM4,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RDX,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%R15,%RAX,1),%YMM8,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x60(%RCX,%RAX,1),%YMM9,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM10,0x60(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RDX,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM11,0x60(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 41d463 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x453> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
| Source file and lines | advec_cell_kernel.f90:192-193 |
| Module | exec |
| nb instructions | 28 |
| nb uops | 27 |
| loop length | 167 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 5.83 cycles |
| front end | 5.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 4.00 | 5.67 | 5.67 | 4.00 | 4.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 5.67 |
| cycles | 0.50 | 4.00 | 5.67 | 5.67 | 4.00 | 4.00 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 5.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 6.02 |
| Stall cycles | 0.00 |
| Front-end | 5.83 |
| Dispatch | 5.67 |
| Data deps. | 1.00 |
| Overall L1 | 5.83 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RDX,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| MOV 0xe8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R15,%RAX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%RCX,%RAX,1),%YMM13,%YMM14 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM14,(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD (%RDX,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM15,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RDX,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R15,%RAX,1),%YMM5,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x20(%RCX,%RAX,1),%YMM0,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM1,0x20(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%RDX,%RAX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM6,0x20(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RDX,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%R15,%RAX,1),%YMM7,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x40(%RCX,%RAX,1),%YMM2,%YMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM3,0x40(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RDX,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM4,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RDX,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%R15,%RAX,1),%YMM8,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD 0x60(%RCX,%RAX,1),%YMM9,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM10,0x60(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%RDX,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD %YMM11,0x60(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 41d463 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x453> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
