| Loop Id: 173 | Module: exec | Source: flux_calc_kernel.f90:58-60 | Coverage: 3.46% |
|---|
| Loop Id: 173 | Module: exec | Source: flux_calc_kernel.f90:58-60 | Coverage: 3.46% |
|---|
0x42bb51 VMULSD (%RCX),%XMM3,%XMM8 [9] |
0x42bb55 VMOVUPD (%R12,%RAX,1),%YMM0 [1] |
0x42bb5b VMOVUPD (%R8,%RAX,1),%YMM4 [17] |
0x42bb61 VADDPD (%R15,%RAX,1),%YMM0,%YMM9 [4] |
0x42bb67 VADDPD (%R14,%RAX,1),%YMM4,%YMM10 [8] |
0x42bb6d VBROADCASTSD %XMM8,%YMM6 |
0x42bb72 VMULPD (%RSI,%RAX,1),%YMM6,%YMM12 [5] |
0x42bb77 VADDPD %YMM10,%YMM9,%YMM11 |
0x42bb7c VMULPD %YMM12,%YMM11,%YMM5 |
0x42bb81 VMOVUPD %YMM5,(%R11,%RAX,1) [6] |
0x42bb87 VMULSD (%RCX),%XMM3,%XMM13 [9] |
0x42bb8b VMOVUPD (%RBX,%RAX,1),%YMM14 [3] |
0x42bb90 VMOVUPD (%R9,%RAX,1),%YMM2 [15] |
0x42bb96 VADDPD (%RDI,%RAX,1),%YMM14,%YMM15 [11] |
0x42bb9b VADDPD (%RDX,%RAX,1),%YMM2,%YMM7 [7] |
0x42bba0 VBROADCASTSD %XMM13,%YMM0 |
0x42bba5 VMULPD (%R10,%RAX,1),%YMM0,%YMM9 [10] |
0x42bbab VADDPD %YMM7,%YMM15,%YMM8 |
0x42bbaf VMULPD %YMM9,%YMM8,%YMM4 |
0x42bbb4 VMOVUPD %YMM4,(%R13,%RAX,1) [14] |
0x42bbbb VMULSD (%RCX),%XMM3,%XMM10 [9] |
0x42bbbf VMOVUPD 0x20(%RAX,%R12,1),%YMM11 [13] |
0x42bbc6 VMOVUPD 0x20(%R8,%RAX,1),%YMM12 [17] |
0x42bbcd VADDPD 0x20(%R15,%RAX,1),%YMM11,%YMM6 [4] |
0x42bbd4 VADDPD 0x20(%R14,%RAX,1),%YMM12,%YMM5 [8] |
0x42bbdb VBROADCASTSD %XMM10,%YMM14 |
0x42bbe0 VMULPD 0x20(%RSI,%RAX,1),%YMM14,%YMM15 [5] |
0x42bbe6 VADDPD %YMM5,%YMM6,%YMM13 |
0x42bbea VMULPD %YMM15,%YMM13,%YMM2 |
0x42bbef VMOVUPD %YMM2,0x20(%R11,%RAX,1) [6] |
0x42bbf6 VMULSD (%RCX),%XMM3,%XMM7 [9] |
0x42bbfa VMOVUPD 0x20(%RAX,%RBX,1),%YMM8 [12] |
0x42bc00 VMOVUPD 0x20(%R9,%RAX,1),%YMM9 [15] |
0x42bc07 VADDPD 0x20(%RDI,%RAX,1),%YMM8,%YMM0 [11] |
0x42bc0d VADDPD 0x20(%RDX,%RAX,1),%YMM9,%YMM4 [7] |
0x42bc13 VBROADCASTSD %XMM7,%YMM11 |
0x42bc18 VMULPD 0x20(%R10,%RAX,1),%YMM11,%YMM6 [10] |
0x42bc1f VADDPD %YMM4,%YMM0,%YMM10 |
0x42bc23 ADD $0x40,%RAX |
0x42bc27 VMULPD %YMM6,%YMM10,%YMM12 |
0x42bc2b VMOVUPD %YMM12,-0x20(%RAX,%R13,1) [2] |
0x42bc32 CMP %RAX,0x1d8(%RSP) [16] |
0x42bc3a JNE 42bb51 |
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 58 - 60 |
-------------------------------------------------------------------------------- |
58: *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1)) |
59: vol_flux_y(j,k)=0.25_8*dt*yarea(j,k) & |
60: *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k)) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.49 |
| CQA speedup if fully vectorized | 2.29 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | P1, |
| Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
| Source | flux_calc_kernel.f90:58-60 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 8.04 |
| CQA cycles if fully vectorized | 5.25 |
| Front-end cycles | 9.00 |
| DIV/SQRT cycles | 9.50 |
| P0 cycles | 12.00 |
| P1 cycles | 8.33 |
| P2 cycles | 8.33 |
| P3 cycles | 2.00 |
| P4 cycles | 9.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 8.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 9.74 |
| Stall cycles (UFS) | 0.06 |
| Nb insns | 43.00 |
| Nb uops | 42.00 |
| Nb loads | 25.00 |
| Nb stores | 4.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 7.00 |
| Nb FLOP add-sub | 48.00 |
| Nb FLOP mul | 36.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 67.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 680.00 |
| Bytes stored | 128.00 |
| Stride 0 | 2.00 |
| Stride 1 | 9.00 |
| Stride n | 6.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 80.00 |
| Vectorization ratio load | 83.33 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 42.50 |
| Vector-efficiency ratio load | 43.75 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 37.50 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.49 |
| CQA speedup if fully vectorized | 2.29 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | P1, |
| Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
| Source | flux_calc_kernel.f90:58-60 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 8.04 |
| CQA cycles if fully vectorized | 5.25 |
| Front-end cycles | 9.00 |
| DIV/SQRT cycles | 9.50 |
| P0 cycles | 12.00 |
| P1 cycles | 8.33 |
| P2 cycles | 8.33 |
| P3 cycles | 2.00 |
| P4 cycles | 9.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 8.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 9.74 |
| Stall cycles (UFS) | 0.06 |
| Nb insns | 43.00 |
| Nb uops | 42.00 |
| Nb loads | 25.00 |
| Nb stores | 4.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 7.00 |
| Nb FLOP add-sub | 48.00 |
| Nb FLOP mul | 36.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 67.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 680.00 |
| Bytes stored | 128.00 |
| Stride 0 | 2.00 |
| Stride 1 | 9.00 |
| Stride n | 6.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 80.00 |
| Vectorization ratio load | 83.33 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 42.50 |
| Vector-efficiency ratio load | 43.75 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 37.50 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
| Source file and lines | flux_calc_kernel.f90:58-60 |
| Module | exec |
| nb instructions | 43 |
| nb uops | 42 |
| loop length | 239 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 5 |
| used ymm registers | 14 |
| used zmm registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 9.00 cycles |
| front end | 9.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 9.50 | 9.50 | 8.33 | 8.33 | 2.00 | 9.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 8.33 |
| cycles | 9.50 | 12.00 | 8.33 | 8.33 | 2.00 | 9.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 8.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 9.74 |
| Stall cycles | 0.06 |
| RS full (events) | 0.24 |
| Front-end | 9.00 |
| Dispatch | 12.00 |
| Data deps. | 1.00 |
| Overall L1 | 12.00 |
| all | 80% |
| load | 83% |
| store | 100% |
| mul | 66% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 42% |
| load | 43% |
| store | 50% |
| mul | 37% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMULSD (%RCX),%XMM3,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD (%R12,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R8,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%R15,%RAX,1),%YMM0,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%R14,%RAX,1),%YMM4,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM8,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD (%RSI,%RAX,1),%YMM6,%YMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM10,%YMM9,%YMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM12,%YMM11,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM5,(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD (%RCX),%XMM3,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD (%RBX,%RAX,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R9,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RDI,%RAX,1),%YMM14,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%RDX,%RAX,1),%YMM2,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM13,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD (%R10,%RAX,1),%YMM0,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM7,%YMM15,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM9,%YMM8,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM4,(%R13,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD (%RCX),%XMM3,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x20(%RAX,%R12,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%R8,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R15,%RAX,1),%YMM11,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x20(%R14,%RAX,1),%YMM12,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM10,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD 0x20(%RSI,%RAX,1),%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM5,%YMM6,%YMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM15,%YMM13,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM2,0x20(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD (%RCX),%XMM3,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x20(%RAX,%RBX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%R9,%RAX,1),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%RDI,%RAX,1),%YMM8,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x20(%RDX,%RAX,1),%YMM9,%YMM4 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM7,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD 0x20(%R10,%RAX,1),%YMM11,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM4,%YMM0,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMULPD %YMM6,%YMM10,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM12,-0x20(%RAX,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| CMP %RAX,0x1d8(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 42bb51 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0+0x7a1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
| Source file and lines | flux_calc_kernel.f90:58-60 |
| Module | exec |
| nb instructions | 43 |
| nb uops | 42 |
| loop length | 239 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 5 |
| used ymm registers | 14 |
| used zmm registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 9.00 cycles |
| front end | 9.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 9.50 | 9.50 | 8.33 | 8.33 | 2.00 | 9.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 8.33 |
| cycles | 9.50 | 12.00 | 8.33 | 8.33 | 2.00 | 9.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 8.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 9.74 |
| Stall cycles | 0.06 |
| RS full (events) | 0.24 |
| Front-end | 9.00 |
| Dispatch | 12.00 |
| Data deps. | 1.00 |
| Overall L1 | 12.00 |
| all | 80% |
| load | 83% |
| store | 100% |
| mul | 66% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 42% |
| load | 43% |
| store | 50% |
| mul | 37% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMULSD (%RCX),%XMM3,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD (%R12,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R8,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%R15,%RAX,1),%YMM0,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%R14,%RAX,1),%YMM4,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM8,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD (%RSI,%RAX,1),%YMM6,%YMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM10,%YMM9,%YMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM12,%YMM11,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM5,(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD (%RCX),%XMM3,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD (%RBX,%RAX,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R9,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RDI,%RAX,1),%YMM14,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%RDX,%RAX,1),%YMM2,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM13,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD (%R10,%RAX,1),%YMM0,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM7,%YMM15,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM9,%YMM8,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM4,(%R13,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD (%RCX),%XMM3,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x20(%RAX,%R12,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%R8,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%R15,%RAX,1),%YMM11,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x20(%R14,%RAX,1),%YMM12,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM10,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD 0x20(%RSI,%RAX,1),%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM5,%YMM6,%YMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %YMM15,%YMM13,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM2,0x20(%R11,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD (%RCX),%XMM3,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x20(%RAX,%RBX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x20(%R9,%RAX,1),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%RDI,%RAX,1),%YMM8,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD 0x20(%RDX,%RAX,1),%YMM9,%YMM4 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VBROADCASTSD %XMM7,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD 0x20(%R10,%RAX,1),%YMM11,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %YMM4,%YMM0,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMULPD %YMM6,%YMM10,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM12,-0x20(%RAX,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| CMP %RAX,0x1d8(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 42bb51 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0+0x7a1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
