Function: setVcm._omp_fn.0 | Module: exec | Source: initAtoms.c:123-133 | Coverage: 0.02% |
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Function: setVcm._omp_fn.0 | Module: exec | Source: initAtoms.c:123-133 | Coverage: 0.02% |
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/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 123 - 133 |
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123: #pragma omp parallel for |
124: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
125: { |
126: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
127: { |
128: int iSpecies = s->atoms->iSpecies[iOff]; |
129: real_t mass = s->species[iSpecies].mass; |
130: |
131: s->atoms->p[iOff][0] += mass * vShift[0]; |
132: s->atoms->p[iOff][1] += mass * vShift[1]; |
133: s->atoms->p[iOff][2] += mass * vShift[2]; |
0x404e80 PUSH %RBP |
0x404e81 MOV %RSP,%RBP |
0x404e84 PUSH %R14 |
0x404e86 PUSH %R13 |
0x404e88 MOV %RDI,%R13 |
0x404e8b PUSH %R12 |
0x404e8d PUSH %RBX |
0x404e8e MOV (%RDI),%RBX |
0x404e91 CALL 403060 <omp_get_num_threads@plt> |
0x404e96 MOV 0x18(%RBX),%R14 |
0x404e9a MOV %EAX,%R12D |
0x404e9d CALL 403150 <omp_get_thread_num@plt> |
0x404ea2 MOV %EAX,%R8D |
0x404ea5 MOV 0xc(%R14),%EAX |
0x404ea9 CLTD |
0x404eaa IDIV %R12D |
0x404ead CMP %EDX,%R8D |
0x404eb0 JL 405142 |
0x404eb6 IMUL %EAX,%R8D |
0x404eba ADD %EDX,%R8D |
0x404ebd ADD %R8D,%EAX |
0x404ec0 CMP %EAX,%R8D |
0x404ec3 JGE 405139 |
0x404ec9 MOVSXD %R8D,%R9 |
0x404ecc MOV 0x78(%R14),%R12 |
0x404ed0 MOV 0x8(%R13),%RCX |
0x404ed4 SAL $0x6,%R8D |
0x404ed8 LEA (%R9,%R9,2),%R11 |
0x404edc SAL $0x9,%R11 |
(10) 0x404ee0 MOVSXD (%R12,%R9,4),%R10 |
(10) 0x404ee4 TEST %R10D,%R10D |
(10) 0x404ee7 JLE 405122 |
(10) 0x404eed MOV 0x20(%RBX),%R14 |
(10) 0x404ef1 MOVSXD %R8D,%RSI |
(10) 0x404ef4 MOV 0x28(%RBX),%RDI |
(10) 0x404ef8 MOV 0x10(%R14),%R13 |
(10) 0x404efc MOV 0x20(%R14),%RDX |
(10) 0x404f00 MOV %R9,%R14 |
(10) 0x404f03 SAL $0x6,%R14 |
(10) 0x404f07 ADD %R14,%R10 |
(10) 0x404f0a LEA (%R13,%RSI,4),%RSI |
(10) 0x404f0f ADD %R11,%RDX |
(10) 0x404f12 LEA (%R13,%R10,4),%R10 |
(10) 0x404f17 MOV %R10,%R13 |
(10) 0x404f1a SUB %RSI,%R13 |
(10) 0x404f1d SUB $0x4,%R13 |
(10) 0x404f21 SHR $0x2,%R13 |
(10) 0x404f25 INC %R13 |
(10) 0x404f28 AND $0x3,%R13D |
(10) 0x404f2c JE 40501a |
(10) 0x404f32 CMP $0x1,%R13 |
(10) 0x404f36 JE 404fcc |
(10) 0x404f3c CMP $0x2,%R13 |
(10) 0x404f40 JE 404f87 |
(10) 0x404f42 MOVSXD (%RSI),%R14 |
(10) 0x404f45 VMOVSD (%RCX),%XMM1 |
(10) 0x404f49 ADD $0x4,%RSI |
(10) 0x404f4d ADD $0x18,%RDX |
(10) 0x404f51 VMOVSD -0x8(%RDX),%XMM7 |
(10) 0x404f56 SAL $0x4,%R14 |
(10) 0x404f5a VMOVSD 0x8(%RDI,%R14,1),%XMM0 |
(10) 0x404f61 VFMADD213SD -0x18(%RDX),%XMM0,%XMM1 |
(10) 0x404f67 VMOVSD %XMM1,-0x18(%RDX) |
(10) 0x404f6c VMOVSD 0x8(%RCX),%XMM2 |
(10) 0x404f71 VFMADD213SD -0x10(%RDX),%XMM0,%XMM2 |
(10) 0x404f77 VMOVSD %XMM2,-0x10(%RDX) |
(10) 0x404f7c VFMADD132SD 0x10(%RCX),%XMM7,%XMM0 |
(10) 0x404f82 VMOVSD %XMM0,-0x8(%RDX) |
(10) 0x404f87 MOVSXD (%RSI),%R13 |
(10) 0x404f8a VMOVSD (%RCX),%XMM4 |
(10) 0x404f8e ADD $0x4,%RSI |
(10) 0x404f92 ADD $0x18,%RDX |
(10) 0x404f96 VMOVSD -0x8(%RDX),%XMM6 |
(10) 0x404f9b SAL $0x4,%R13 |
(10) 0x404f9f VMOVSD 0x8(%RDI,%R13,1),%XMM3 |
(10) 0x404fa6 VFMADD213SD -0x18(%RDX),%XMM3,%XMM4 |
(10) 0x404fac VMOVSD %XMM4,-0x18(%RDX) |
(10) 0x404fb1 VMOVSD 0x8(%RCX),%XMM5 |
(10) 0x404fb6 VFMADD213SD -0x10(%RDX),%XMM3,%XMM5 |
(10) 0x404fbc VMOVSD %XMM5,-0x10(%RDX) |
(10) 0x404fc1 VFMADD132SD 0x10(%RCX),%XMM6,%XMM3 |
(10) 0x404fc7 VMOVSD %XMM3,-0x8(%RDX) |
(10) 0x404fcc MOVSXD (%RSI),%R14 |
(10) 0x404fcf VMOVSD (%RCX),%XMM9 |
(10) 0x404fd3 ADD $0x4,%RSI |
(10) 0x404fd7 ADD $0x18,%RDX |
(10) 0x404fdb VMOVSD -0x8(%RDX),%XMM11 |
(10) 0x404fe0 SAL $0x4,%R14 |
(10) 0x404fe4 VMOVSD 0x8(%RDI,%R14,1),%XMM8 |
(10) 0x404feb VFMADD213SD -0x18(%RDX),%XMM8,%XMM9 |
(10) 0x404ff1 VMOVSD %XMM9,-0x18(%RDX) |
(10) 0x404ff6 VMOVSD 0x8(%RCX),%XMM10 |
(10) 0x404ffb VFMADD213SD -0x10(%RDX),%XMM8,%XMM10 |
(10) 0x405001 VMOVSD %XMM10,-0x10(%RDX) |
(10) 0x405006 VFMADD132SD 0x10(%RCX),%XMM11,%XMM8 |
(10) 0x40500c VMOVSD %XMM8,-0x8(%RDX) |
(10) 0x405011 CMP %RSI,%R10 |
(10) 0x405014 JE 405122 |
(11) 0x40501a MOVSXD (%RSI),%R13 |
(11) 0x40501d VMOVSD (%RCX),%XMM13 |
(11) 0x405021 ADD $0x10,%RSI |
(11) 0x405025 ADD $0x60,%RDX |
(11) 0x405029 VMOVSD -0x50(%RDX),%XMM15 |
(11) 0x40502e MOVSXD -0xc(%RSI),%R14 |
(11) 0x405032 SAL $0x4,%R13 |
(11) 0x405036 VMOVSD -0x38(%RDX),%XMM7 |
(11) 0x40503b VMOVSD -0x20(%RDX),%XMM6 |
(11) 0x405040 VMOVSD 0x8(%RDI,%R13,1),%XMM12 |
(11) 0x405047 SAL $0x4,%R14 |
(11) 0x40504b MOVSXD -0x8(%RSI),%R13 |
(11) 0x40504f VFMADD213SD -0x60(%RDX),%XMM12,%XMM13 |
(11) 0x405055 SAL $0x4,%R13 |
(11) 0x405059 VMOVSD %XMM13,-0x60(%RDX) |
(11) 0x40505e VMOVSD 0x8(%RCX),%XMM14 |
(11) 0x405063 VFMADD213SD -0x58(%RDX),%XMM12,%XMM14 |
(11) 0x405069 VMOVSD %XMM14,-0x58(%RDX) |
(11) 0x40506e VFMADD132SD 0x10(%RCX),%XMM15,%XMM12 |
(11) 0x405074 VMOVSD %XMM12,-0x50(%RDX) |
(11) 0x405079 VMOVSD 0x8(%RDI,%R14,1),%XMM0 |
(11) 0x405080 VMOVSD (%RCX),%XMM1 |
(11) 0x405084 VFMADD213SD -0x48(%RDX),%XMM0,%XMM1 |
(11) 0x40508a VMOVSD %XMM1,-0x48(%RDX) |
(11) 0x40508f VMOVSD 0x8(%RCX),%XMM2 |
(11) 0x405094 VFMADD213SD -0x40(%RDX),%XMM0,%XMM2 |
(11) 0x40509a VMOVSD %XMM2,-0x40(%RDX) |
(11) 0x40509f VFMADD132SD 0x10(%RCX),%XMM7,%XMM0 |
(11) 0x4050a5 VMOVSD %XMM0,-0x38(%RDX) |
(11) 0x4050aa VMOVSD 0x8(%RDI,%R13,1),%XMM3 |
(11) 0x4050b1 VMOVSD (%RCX),%XMM4 |
(11) 0x4050b5 VFMADD213SD -0x30(%RDX),%XMM3,%XMM4 |
(11) 0x4050bb VMOVSD %XMM4,-0x30(%RDX) |
(11) 0x4050c0 VMOVSD 0x8(%RCX),%XMM5 |
(11) 0x4050c5 VFMADD213SD -0x28(%RDX),%XMM3,%XMM5 |
(11) 0x4050cb VMOVSD %XMM5,-0x28(%RDX) |
(11) 0x4050d0 VFMADD132SD 0x10(%RCX),%XMM6,%XMM3 |
(11) 0x4050d6 VMOVSD %XMM3,-0x20(%RDX) |
(11) 0x4050db MOVSXD -0x4(%RSI),%R14 |
(11) 0x4050df VMOVSD (%RCX),%XMM9 |
(11) 0x4050e3 VMOVSD -0x8(%RDX),%XMM11 |
(11) 0x4050e8 SAL $0x4,%R14 |
(11) 0x4050ec VMOVSD 0x8(%RDI,%R14,1),%XMM8 |
(11) 0x4050f3 VFMADD213SD -0x18(%RDX),%XMM8,%XMM9 |
(11) 0x4050f9 VMOVSD %XMM9,-0x18(%RDX) |
(11) 0x4050fe VMOVSD 0x8(%RCX),%XMM10 |
(11) 0x405103 VFMADD213SD -0x10(%RDX),%XMM8,%XMM10 |
(11) 0x405109 VMOVSD %XMM10,-0x10(%RDX) |
(11) 0x40510e VFMADD132SD 0x10(%RCX),%XMM11,%XMM8 |
(11) 0x405114 VMOVSD %XMM8,-0x8(%RDX) |
(11) 0x405119 CMP %RSI,%R10 |
(11) 0x40511c JNE 40501a |
(10) 0x405122 INC %R9 |
(10) 0x405125 ADD $0x40,%R8D |
(10) 0x405129 ADD $0x600,%R11 |
(10) 0x405130 CMP %R9D,%EAX |
(10) 0x405133 JG 404ee0 |
0x405139 POP %RBX |
0x40513a POP %R12 |
0x40513c POP %R13 |
0x40513e POP %R14 |
0x405140 POP %RBP |
0x405141 RET |
0x405142 INC %EAX |
0x405144 XOR %EDX,%EDX |
0x405146 JMP 404eb6 |
0x40514b NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | initAtoms.c:123-133 |
Module | exec |
nb instructions | 39 |
nb uops | 44 |
loop length | 119 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
cycles | 3.00 | 5.33 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.09-7.14 |
Stall cycles | 0.00 |
Front-end | 7.33 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 7.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 405142 <setVcm._omp_fn.0+0x2c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 405139 <setVcm._omp_fn.0+0x2b9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R14),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%R8D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x9,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 404eb6 <setVcm._omp_fn.0+0x36> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:123-133 |
Module | exec |
nb instructions | 39 |
nb uops | 44 |
loop length | 119 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
cycles | 3.00 | 5.33 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.09-7.14 |
Stall cycles | 0.00 |
Front-end | 7.33 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 7.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 405142 <setVcm._omp_fn.0+0x2c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 405139 <setVcm._omp_fn.0+0x2b9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R14),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%R8D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x9,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 404eb6 <setVcm._omp_fn.0+0x36> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼setVcm._omp_fn.0– | 0.02 | 0 |
▼Loop 10 - initAtoms.c:126-133 - exec– | 0 | 0 |
○Loop 11 - initAtoms.c:126-133 - exec | 0.01 | 0 |