Function: updateLinkCells | Module: exec | Source: linkCells.c:209-385 [...] | Coverage: 0.3% |
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Function: updateLinkCells | Module: exec | Source: linkCells.c:209-385 [...] | Coverage: 0.3% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385 |
-------------------------------------------------------------------------------- |
209: if (iz == gridSize[2]) |
210: { |
211: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) + |
212: (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1); |
213: } |
214: // Halo in Z- |
215: else if (iz == -1) |
216: { |
217: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) + |
218: (gridSize[0]+2)*(iy+1) + (ix+1); |
219: } |
220: // Halo in Y+ |
221: else if (iy == gridSize[1]) |
[...] |
227: else if (iy == -1) |
228: { |
229: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1); |
230: } |
231: // Halo in X+ |
232: else if (ix == gridSize[0]) |
233: { |
234: iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy; |
235: } |
236: // Halo in X- |
237: else if (ix == -1) |
238: { |
239: iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy; |
240: } |
241: // local link celll. |
242: else |
243: { |
244: iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz; |
245: } |
246: assert(iBox >= 0); |
247: assert(iBox < boxes->nTotalBoxes); |
[...] |
258: int nj = boxes->nAtoms[jBox]; |
259: copyAtom(boxes, atoms, iId, iBox, nj, jBox); |
260: boxes->nAtoms[jBox]++; |
261: |
262: assert(boxes->nAtoms[jBox] < MAXATOMS); |
263: |
264: boxes->nAtoms[iBox]--; |
265: int ni = boxes->nAtoms[iBox]; |
266: if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox); |
267: |
268: if (jBox > boxes->nLocalBoxes) |
269: --atoms->nLocal; |
[...] |
288: { |
289: emptyHaloCells(boxes); |
290: |
291: for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox) |
292: { |
293: int iOff = iBox*MAXATOMS; |
294: int ii=0; |
295: while (ii < boxes->nAtoms[iBox]) |
296: { |
297: int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]); |
298: if (jBox != iBox) |
299: moveAtom(boxes, atoms, ii, iBox, jBox); |
300: else |
301: ++ii; |
302: } |
303: } |
304: } |
[...] |
327: const int iOff = MAXATOMS*iBox+iAtom; |
328: const int jOff = MAXATOMS*jBox+jAtom; |
329: atoms->gid[jOff] = atoms->gid[iOff]; |
330: atoms->iSpecies[jOff] = atoms->iSpecies[iOff]; |
331: memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3)); |
332: memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3)); |
333: memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3)); |
334: memcpy(atoms->U+jOff, atoms->U+iOff, sizeof(real_t)); |
[...] |
352: int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0])); |
353: int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1])); |
[...] |
359: if (rr[0] < localMax[0]) |
360: { |
361: if (ix == gridSize[0]) ix = gridSize[0] - 1; |
362: } |
363: else |
364: ix = gridSize[0]; // assign to halo cell |
365: if (rr[1] < localMax[1]) |
[...] |
371: if (rr[2] < localMax[2]) |
[...] |
384: for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii) |
385: boxes->nAtoms[ii] = 0; |
0x40ac10 PUSH %RBP |
0x40ac11 MOV %RSP,%RBP |
0x40ac14 PUSH %R15 |
0x40ac16 PUSH %R14 |
0x40ac18 PUSH %R13 |
0x40ac1a PUSH %R12 |
0x40ac1c PUSH %RBX |
0x40ac1d SUB $0x78,%RSP |
0x40ac21 MOV %RSI,-0x48(%RBP) |
0x40ac25 MOV 0xc(%RDI),%R14D |
0x40ac29 MOV %RDI,-0x40(%RBP) |
0x40ac2d MOV 0x14(%RDI),%EDI |
0x40ac30 CMP %EDI,%R14D |
0x40ac33 MOV %EDI,-0x38(%RBP) |
0x40ac36 JGE 40ac62 |
0x40ac38 MOV %EDI,%ECX |
0x40ac3a MOVSXD %R14D,%RDI |
0x40ac3d SAL $0x2,%RDI |
0x40ac41 MOV -0x40(%RBP),%RAX |
0x40ac45 ADD 0x78(%RAX),%RDI |
0x40ac49 MOV %R14D,%EAX |
0x40ac4c NOT %EAX |
0x40ac4e ADD %ECX,%EAX |
0x40ac50 LEA 0x4(,%RAX,4),%RDX |
0x40ac58 XOR %ESI,%ESI |
0x40ac5a CALL 412d60 <_intel_fast_memset> |
0x40ac5f MOV -0x38(%RBP),%EDI |
0x40ac62 TEST %R14D,%R14D |
0x40ac65 JLE 40b037 |
0x40ac6b MOV -0x40(%RBP),%RAX |
0x40ac6f MOV 0x78(%RAX),%RAX |
0x40ac73 LEA 0x1(%R14),%ECX |
0x40ac77 MOV %ECX,-0x2c(%RBP) |
0x40ac7a XOR %R9D,%R9D |
0x40ac7d VPCMPEQD %XMM0,%XMM0,%XMM0 |
0x40ac81 MOV %RAX,-0x60(%RBP) |
0x40ac85 MOV %R14,-0xa0(%RBP) |
0x40ac8c JMP 40ac9c |
0x40ac8e XCHG %AX,%AX |
(81) 0x40ac90 INC %R9 |
(81) 0x40ac93 CMP %R14,%R9 |
(81) 0x40ac96 JE 40b037 |
(81) 0x40ac9c CMPL $0,(%RAX,%R9,4) |
(81) 0x40aca1 JLE 40ac90 |
(81) 0x40aca3 MOVSXD %R9D,%RCX |
(81) 0x40aca6 SAL $0x6,%RCX |
(81) 0x40acaa MOV %RCX,-0x88(%RBP) |
(81) 0x40acb1 MOV -0x48(%RBP),%RCX |
(81) 0x40acb5 MOV 0x18(%RCX),%R11 |
(81) 0x40acb9 MOV -0x40(%RBP),%RAX |
(81) 0x40acbd VMOVSD 0x30(%RAX),%XMM1 |
(81) 0x40acc2 MOV (%RAX),%R13D |
(81) 0x40acc5 LEA -0x1(%R13),%ECX |
(81) 0x40acc9 MOV %ECX,-0x64(%RBP) |
(81) 0x40accc VMOVUPD 0x38(%RAX),%XMM2 |
(81) 0x40acd1 VMOVUPD 0x20(%RAX),%XMM3 |
(81) 0x40acd6 VMOVUPD 0x68(%RAX),%XMM4 |
(81) 0x40acdb MOV 0x4(%RAX),%RBX |
(81) 0x40acdf MOV -0x60(%RBP),%RAX |
(81) 0x40ace3 VMOVQ %RBX,%XMM5 |
(81) 0x40ace8 MOV %RBX,%RCX |
(81) 0x40aceb SHR $0x20,%RCX |
(81) 0x40acef VPADDD %XMM0,%XMM5,%XMM6 |
(81) 0x40acf3 MOV %RCX,-0x98(%RBP) |
(81) 0x40acfa LEA (%RCX,%RCX,1),%EDX |
(81) 0x40acfd MOV %RDX,%RCX |
(81) 0x40ad00 MOV %RDX,-0x78(%RBP) |
(81) 0x40ad04 IMUL %EBX,%ECX |
(81) 0x40ad07 MOV %ECX,-0x34(%RBP) |
(81) 0x40ad0a LEA 0x2(%R13),%ECX |
(81) 0x40ad0e MOV %ECX,-0x30(%RBP) |
(81) 0x40ad11 VPINSRD $0,%R14D,%XMM5,%XMM7 |
(81) 0x40ad17 XOR %R15D,%R15D |
(81) 0x40ad1a MOV %R13,-0x70(%RBP) |
(81) 0x40ad1e MOV %RBX,-0x58(%RBP) |
(81) 0x40ad22 MOV %R9,-0x50(%RBP) |
(81) 0x40ad26 JMP 40ad41 |
0x40ad28 NOPL (%RAX,%RAX,1) |
(82) 0x40ad30 INC %R15D |
(82) 0x40ad33 MOV -0x58(%RBP),%RBX |
(82) 0x40ad37 CMP (%RAX,%R9,4),%R15D |
(82) 0x40ad3b JGE 40ac90 |
(82) 0x40ad41 MOV -0x88(%RBP),%RCX |
(82) 0x40ad48 ADD %R15D,%ECX |
(82) 0x40ad4b MOVSXD %ECX,%RCX |
(82) 0x40ad4e MOV %RCX,-0x90(%RBP) |
(82) 0x40ad55 LEA (%RCX,%RCX,2),%R12 |
(82) 0x40ad59 VMOVSD (%R11,%R12,8),%XMM8 |
(82) 0x40ad5f VUCOMISD %XMM8,%XMM1 |
(82) 0x40ad64 MOV %R13D,%ECX |
(82) 0x40ad67 JBE 40ad8d |
(82) 0x40ad69 MOV -0x40(%RBP),%RAX |
(82) 0x40ad6d VSUBSD 0x18(%RAX),%XMM8,%XMM8 |
(82) 0x40ad72 VMULSD 0x60(%RAX),%XMM8,%XMM8 |
(82) 0x40ad77 MOV -0x60(%RBP),%RAX |
(82) 0x40ad7b VROUNDSD $0x9,%XMM8,%XMM8,%XMM8 |
(82) 0x40ad81 VCVTTSD2SI %XMM8,%ECX |
(82) 0x40ad86 CMP %ECX,%R13D |
(82) 0x40ad89 CMOVE -0x64(%RBP),%ECX |
(82) 0x40ad8d VMOVUPD 0x8(%R11,%R12,8),%XMM9 |
(82) 0x40ad94 VSUBPD %XMM3,%XMM9,%XMM8 |
(82) 0x40ad98 VMULPD %XMM4,%XMM8,%XMM8 |
(82) 0x40ad9c VROUNDPD $0x9,%XMM8,%XMM8 |
(82) 0x40ada2 VCVTTPD2DQ %XMM8,%XMM8 |
(82) 0x40ada7 VPCMPEQD %XMM8,%XMM5,%K1 |
(82) 0x40adad VCMPPD $0x2,%XMM9,%XMM2,%K0 |
(82) 0x40adb4 KSHIFTRB $0x1,%K0,%K2 |
(82) 0x40adba KMOVD %K2,%R10D |
(82) 0x40adbe KMOVD %K0,%EDX |
(82) 0x40adc2 VMOVDQA32 %XMM6,%XMM8{%K1} |
(82) 0x40adc8 VMOVD %XMM8,%ESI |
(82) 0x40adcc TEST $0x1,%DL |
(82) 0x40adcf MOV %ESI,%R8D |
(82) 0x40add2 CMOVNE %EBX,%R8D |
(82) 0x40add6 TEST $0x1,%R10B |
(82) 0x40adda JE 40ae00 |
(82) 0x40addc ADD %EBX,%R8D |
(82) 0x40addf MOV -0x78(%RBP),%RDX |
(82) 0x40ade3 LEA 0x3(%RDX,%R8,1),%EDX |
(82) 0x40ade8 IMUL -0x30(%RBP),%EDX |
(82) 0x40adec ADD -0x2c(%RBP),%ECX |
(82) 0x40adef ADD -0x34(%RBP),%ECX |
(82) 0x40adf2 ADD %EDX,%ECX |
(82) 0x40adf4 JMP 40ae71 |
0x40adf6 NOPW %CS:(%RAX,%RAX,1) |
(82) 0x40ae00 MOV %R15,%R10 |
(82) 0x40ae03 VPEXTRD $0x1,%XMM8,%R15D |
(82) 0x40ae09 CMP $-0x1,%R15D |
(82) 0x40ae0d JE 40ae1d |
(82) 0x40ae0f TEST $0x1,%DL |
(82) 0x40ae12 JE 40ae34 |
(82) 0x40ae14 ADD -0x98(%RBP),%R15D |
(82) 0x40ae1b JMP 40ae60 |
(82) 0x40ae1d MOV -0x78(%RBP),%RDX |
(82) 0x40ae21 LEA 0x1(%R8,%RDX,1),%EDX |
(82) 0x40ae26 IMUL -0x30(%RBP),%EDX |
(82) 0x40ae2a ADD -0x2c(%RBP),%ECX |
(82) 0x40ae2d ADD -0x34(%RBP),%ECX |
(82) 0x40ae30 ADD %EDX,%ECX |
(82) 0x40ae32 JMP 40ae6e |
(82) 0x40ae34 CMP $-0x1,%ESI |
(82) 0x40ae37 JE 40ae60 |
(82) 0x40ae39 CMP %ECX,%R13D |
(82) 0x40ae3c JNE 40b015 |
(82) 0x40ae42 VPADDD %XMM7,%XMM8,%XMM8 |
(82) 0x40ae46 VPEXTRD $0x1,%XMM8,%EDX |
(82) 0x40ae4c IMUL %EBX,%EDX |
(82) 0x40ae4f VMOVD %XMM8,%ECX |
(82) 0x40ae53 ADD %EDX,%ECX |
(82) 0x40ae55 JMP 40ae6e |
0x40ae57 NOPW (%RAX,%RAX,1) |
(82) 0x40ae60 IMUL -0x30(%RBP),%R15D |
(82) 0x40ae65 ADD -0x2c(%RBP),%ECX |
(82) 0x40ae68 ADD -0x34(%RBP),%ECX |
(82) 0x40ae6b ADD %R15D,%ECX |
(82) 0x40ae6e MOV %R10,%R15 |
(82) 0x40ae71 TEST %ECX,%ECX |
(82) 0x40ae73 JS 40b046 |
(82) 0x40ae79 CMP %EDI,%ECX |
(82) 0x40ae7b JGE 40b05f |
(82) 0x40ae81 MOV %ECX,%EBX |
(82) 0x40ae83 CMP %RBX,%R9 |
(82) 0x40ae86 JE 40ad30 |
(82) 0x40ae8c MOV %R15,-0x80(%RBP) |
(82) 0x40ae90 MOVSXD (%RAX,%RBX,4),%RSI |
(82) 0x40ae94 MOVSXD %ECX,%RDX |
(82) 0x40ae97 SAL $0x6,%RDX |
(82) 0x40ae9b ADD %RSI,%RDX |
(82) 0x40ae9e MOV -0x48(%RBP),%RAX |
(82) 0x40aea2 MOV 0x8(%RAX),%R14 |
(82) 0x40aea6 MOV -0x90(%RBP),%R13 |
(82) 0x40aead MOV (%R14,%R13,4),%ESI |
(82) 0x40aeb1 MOV %ESI,(%R14,%RDX,4) |
(82) 0x40aeb5 MOV %R11,%R8 |
(82) 0x40aeb8 MOV 0x10(%RAX),%R11 |
(82) 0x40aebc MOV (%R11,%R13,4),%ESI |
(82) 0x40aec0 MOV %ESI,(%R11,%RDX,4) |
(82) 0x40aec4 LEA (%R8,%R12,8),%R12 |
(82) 0x40aec8 LEA (,%RDX,8),%RSI |
(82) 0x40aed0 LEA (%RSI,%RSI,2),%R10 |
(82) 0x40aed4 MOV 0x10(%R12),%RSI |
(82) 0x40aed9 MOV %RSI,0x10(%R8,%R10,1) |
(82) 0x40aede VMOVUPS (%R12),%XMM8 |
(82) 0x40aee4 MOV %R8,%RDI |
(82) 0x40aee7 VMOVUPS %XMM8,(%R8,%R10,1) |
(82) 0x40aeed MOV 0x20(%RAX),%RSI |
(82) 0x40aef1 LEA (,%R13,8),%R8 |
(82) 0x40aef9 LEA (%R8,%R8,2),%R15 |
(82) 0x40aefd MOV 0x10(%RSI,%R15,1),%R8 |
(82) 0x40af02 MOV %R8,0x10(%RSI,%R10,1) |
(82) 0x40af07 VMOVUPS (%RSI,%R15,1),%XMM8 |
(82) 0x40af0d VMOVUPS %XMM8,(%RSI,%R10,1) |
(82) 0x40af13 MOV 0x28(%RAX),%R8 |
(82) 0x40af17 MOV 0x10(%R8,%R15,1),%R9 |
(82) 0x40af1c MOV %R9,0x10(%R8,%R10,1) |
(82) 0x40af21 VMOVDQU (%R8,%R15,1),%XMM8 |
(82) 0x40af27 VMOVDQU %XMM8,(%R8,%R10,1) |
(82) 0x40af2d MOV 0x30(%RAX),%R10 |
(82) 0x40af31 MOV -0x60(%RBP),%RAX |
(82) 0x40af35 MOV (%R10,%R13,8),%R9 |
(82) 0x40af39 MOV %R9,(%R10,%RDX,8) |
(82) 0x40af3d MOV (%RAX,%RBX,4),%EDX |
(82) 0x40af40 LEA 0x1(%RDX),%R9D |
(82) 0x40af44 MOV %R9D,(%RAX,%RBX,4) |
(82) 0x40af48 CMP $0x3f,%EDX |
(82) 0x40af4b JGE 40b078 |
(82) 0x40af51 MOV -0x50(%RBP),%RDX |
(82) 0x40af55 MOVSXD (%RAX,%RDX,4),%RBX |
(82) 0x40af59 DEC %RBX |
(82) 0x40af5c MOV %EBX,(%RAX,%RDX,4) |
(82) 0x40af5f TEST %EBX,%EBX |
(82) 0x40af61 JE 40afdc |
(82) 0x40af63 LEA (%RSI,%R15,1),%RDX |
(82) 0x40af67 ADD -0x88(%RBP),%RBX |
(82) 0x40af6e MOV (%R14,%RBX,4),%R9D |
(82) 0x40af72 MOV -0x90(%RBP),%R13 |
(82) 0x40af79 MOV %R9D,(%R14,%R13,4) |
(82) 0x40af7d MOV (%R11,%RBX,4),%R9D |
(82) 0x40af81 MOV %R9D,(%R11,%R13,4) |
(82) 0x40af85 ADD %R8,%R15 |
(82) 0x40af88 LEA (,%RBX,8),%R9 |
(82) 0x40af90 LEA (%R9,%R9,2),%R9 |
(82) 0x40af94 MOV %RDI,%R14 |
(82) 0x40af97 MOV 0x10(%RDI,%R9,1),%R11 |
(82) 0x40af9c MOV %R11,0x10(%R12) |
(82) 0x40afa1 VMOVUPS (%RDI,%R9,1),%XMM8 |
(82) 0x40afa7 VMOVUPS %XMM8,(%R12) |
(82) 0x40afad MOV 0x10(%RSI,%R9,1),%R11 |
(82) 0x40afb2 MOV %R11,0x10(%RDX) |
(82) 0x40afb6 VMOVUPS (%RSI,%R9,1),%XMM8 |
(82) 0x40afbc VMOVUPS %XMM8,(%RDX) |
(82) 0x40afc0 MOV 0x10(%R8,%R9,1),%RDX |
(82) 0x40afc5 MOV %RDX,0x10(%R15) |
(82) 0x40afc9 VMOVDQU (%R8,%R9,1),%XMM8 |
(82) 0x40afcf VMOVDQU %XMM8,(%R15) |
(82) 0x40afd4 MOV (%R10,%RBX,8),%RDX |
(82) 0x40afd8 MOV %RDX,(%R10,%R13,8) |
(82) 0x40afdc MOV -0xa0(%RBP),%R14 |
(82) 0x40afe3 CMP %ECX,%R14D |
(82) 0x40afe6 JGE 40afee |
(82) 0x40afe8 MOV -0x48(%RBP),%RCX |
(82) 0x40afec DECL (%RCX) |
(82) 0x40afee MOV -0x38(%RBP),%ECX |
(82) 0x40aff1 MOV -0x50(%RBP),%R9 |
(82) 0x40aff5 MOV %RDI,%R11 |
(82) 0x40aff8 MOV %ECX,%EDI |
(82) 0x40affa MOV -0x70(%RBP),%R13 |
(82) 0x40affe MOV -0x58(%RBP),%RBX |
(82) 0x40b002 MOV -0x80(%RBP),%R15 |
(82) 0x40b006 CMP (%RAX,%R9,4),%R15D |
(82) 0x40b00a JL 40ad41 |
(81) 0x40b010 JMP 40ac90 |
(82) 0x40b015 IMUL %EBX,%R15D |
(82) 0x40b019 CMP $-0x1,%ECX |
(82) 0x40b01c JE 40b02a |
(82) 0x40b01e ADD %ESI,%R15D |
(82) 0x40b021 IMUL %R13D,%R15D |
(82) 0x40b025 JMP 40ae6b |
(82) 0x40b02a ADD %R14D,%ESI |
(82) 0x40b02d ADD %R15D,%ESI |
(82) 0x40b030 MOV %ESI,%ECX |
(82) 0x40b032 JMP 40ae6e |
0x40b037 ADD $0x78,%RSP |
0x40b03b POP %RBX |
0x40b03c POP %R12 |
0x40b03e POP %R13 |
0x40b040 POP %R14 |
0x40b042 POP %R15 |
0x40b044 POP %RBP |
0x40b045 RET |
0x40b046 MOV $0x423a7a,%EDI |
0x40b04b MOV $0x42399f,%ESI |
0x40b050 MOV $0x423a84,%ECX |
0x40b055 MOV $0xf6,%EDX |
0x40b05a CALL 4030b0 <__assert_fail@plt> |
0x40b05f MOV $0x423ab3,%EDI |
0x40b064 MOV $0x42399f,%ESI |
0x40b069 MOV $0x423a84,%ECX |
0x40b06e MOV $0xf7,%EDX |
0x40b073 CALL 4030b0 <__assert_fail@plt> |
0x40b078 MOV $0x423acd,%EDI |
0x40b07d MOV $0x42399f,%ESI |
0x40b082 MOV $0x423aec,%ECX |
0x40b087 MOV $0x106,%EDX |
0x40b08c CALL 4030b0 <__assert_fail@plt> |
0x40b091 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | linkCells.c:209-385 |
Module | exec |
nb instructions | 66 |
nb uops | 70 |
loop length | 260 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 11.67 cycles |
front end | 11.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
cycles | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.13 |
Stall cycles | 0.00 |
Front-end | 11.67 |
Dispatch | 8.00 |
Overall L1 | 11.67 |
all | 4% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x14(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 40ac62 <updateLinkCells+0x52> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD %R14D,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x78(%RAX),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 412d60 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40b037 <updateLinkCells+0x427> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R14),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 40ac9c <updateLinkCells+0x8c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV $0x423a7a,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x42399f,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x423a84,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x423ab3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x42399f,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x423a84,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x423acd,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x42399f,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x423aec,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x106,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | linkCells.c:209-385 |
Module | exec |
nb instructions | 66 |
nb uops | 70 |
loop length | 260 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 11.67 cycles |
front end | 11.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
cycles | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.13 |
Stall cycles | 0.00 |
Front-end | 11.67 |
Dispatch | 8.00 |
Overall L1 | 11.67 |
all | 4% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x14(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 40ac62 <updateLinkCells+0x52> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD %R14D,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x78(%RAX),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 412d60 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40b037 <updateLinkCells+0x427> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R14),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 40ac9c <updateLinkCells+0x8c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV $0x423a7a,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x42399f,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x423a84,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x423ab3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x42399f,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x423a84,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x423acd,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x42399f,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x423aec,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x106,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼updateLinkCells– | 0.3 | 0.04 |
▼Loop 81 - linkCells.c:209-371 - exec– | 0 | 0.02 |
○Loop 82 - linkCells.c:209-371 - exec | 0.29 | 2 |