Loop Id: 93 | Module: exec | Source: timestep.c:71-78 | Coverage: 0.01% |
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Loop Id: 93 | Module: exec | Source: timestep.c:71-78 | Coverage: 0.01% |
---|
0x40ef50 LEA 0x1(%RDI),%R8 |
0x40ef54 ADD $0x40,%ESI |
0x40ef57 CMP %RCX,%RDI |
0x40ef5a MOV %R8,%RDI |
0x40ef5d JE 40eedb |
0x40ef63 LEA (%RDI,%RAX,1),%R8 |
0x40ef67 MOV (%RDX,%R8,4),%R8D |
0x40ef6b TEST %R8D,%R8D |
0x40ef6e JLE 40ef50 |
0x40ef70 MOV %ESI,%R11D |
0x40ef73 SAL $0x3,%R11 |
0x40ef77 LEA (%RDI,%RAX,1),%R15D |
0x40ef7b SAL $0x6,%R15D |
0x40ef7f MOV 0x20(%RBX),%R10 |
0x40ef83 MOV 0x20(%R10),%R9 |
0x40ef87 MOV 0x28(%R10),%R10 |
0x40ef8b LEA -0x1(%R8),%R14D |
0x40ef8f MOVSXD %R14D,%R14 |
0x40ef92 ADD %R15,%R14 |
0x40ef95 SAL $0x3,%R14 |
0x40ef99 LEA (%R14,%R14,2),%R14 |
0x40ef9d LEA 0x10(%R10,%R14,1),%R12 |
0x40efa2 SAL $0x3,%R15 |
0x40efa6 LEA (%R15,%R15,2),%R15 |
0x40efaa LEA (%R9,%R15,1),%R13 |
0x40efae CMP %R13,%R12 |
0x40efb1 JB 40f020 |
0x40efb3 ADD %R10,%R15 |
0x40efb6 LEA 0x10(%R9,%R14,1),%R14 |
0x40efbb CMP %R15,%R14 |
0x40efbe JB 40f020 |
0x40efc0 LEA 0x10(%R11,%R11,2),%R11 |
0x40efc5 NOPW %CS:(%RAX,%RAX,1) |
(96) 0x40efd0 VMOVSD -0x10(%R10,%R11,1),%XMM2 |
(96) 0x40efd7 VFMADD213SD -0x10(%R9,%R11,1),%XMM0,%XMM2 |
(96) 0x40efde VMOVSD %XMM2,-0x10(%R9,%R11,1) |
(96) 0x40efe5 VMOVSD -0x8(%R10,%R11,1),%XMM2 |
(96) 0x40efec VFMADD213SD -0x8(%R9,%R11,1),%XMM0,%XMM2 |
(96) 0x40eff3 VMOVSD %XMM2,-0x8(%R9,%R11,1) |
(96) 0x40effa VMOVSD (%R10,%R11,1),%XMM2 |
(96) 0x40f000 VFMADD213SD (%R9,%R11,1),%XMM0,%XMM2 |
(96) 0x40f006 VMOVSD %XMM2,(%R9,%R11,1) |
(96) 0x40f00c ADD $0x18,%R11 |
(96) 0x40f010 DEC %R8D |
(96) 0x40f013 JNE 40efd0 |
0x40f015 JMP 40ef50 |
0x40f020 LEA (%R11,%R11,2),%R14 |
0x40f024 MOV %R8D,%R15D |
0x40f027 AND $-0x8,%R15D |
0x40f02b JE 40f252 |
0x40f031 LEA -0x1(%R15),%R12D |
0x40f035 XOR %R13D,%R13D |
0x40f038 MOV %R14,%R11 |
0x40f03b NOPL (%RAX,%RAX,1) |
(95) 0x40f040 VMOVUPD 0x80(%R10,%R11,1),%YMM7 |
(95) 0x40f04a VMOVUPD 0x20(%R10,%R11,1),%YMM8 |
(95) 0x40f051 VMOVUPD 0x80(%R9,%R11,1),%YMM9 |
(95) 0x40f05b VMOVUPD 0x20(%R9,%R11,1),%YMM10 |
(95) 0x40f062 VMOVUPD 0x10(%R10,%R11,1),%XMM11 |
(95) 0x40f069 VMOVUPD 0x70(%R10,%R11,1),%XMM12 |
(95) 0x40f070 VBLENDPD $0x3,(%R10,%R11,1),%YMM8,%YMM13 |
(95) 0x40f077 VBLENDPD $0x3,0x60(%R10,%R11,1),%YMM7,%YMM14 |
(95) 0x40f07f VBLENDPD $0x3,(%R9,%R11,1),%YMM10,%YMM15 |
(95) 0x40f086 VMOVUPD 0x10(%R9,%R11,1),%XMM16 |
(95) 0x40f08e VBLENDPD $0x3,0x60(%R9,%R11,1),%YMM9,%YMM2 |
(95) 0x40f096 VMOVUPD 0x20(%R10,%R11,1),%XMM3 |
(95) 0x40f09d VMOVUPD 0x80(%R10,%R11,1),%XMM4 |
(95) 0x40f0a7 VMOVUPD 0x20(%R9,%R11,1),%XMM5 |
(95) 0x40f0ae VINSERTF128 $0x1,0x40(%R10,%R11,1),%YMM11,%YMM11 |
(95) 0x40f0b6 VBLENDPD $0xc,0x40(%R10,%R11,1),%YMM3,%YMM3 |
(95) 0x40f0be VBLENDPD $0xa,%YMM3,%YMM11,%YMM3 |
(95) 0x40f0c4 VBLENDPD $0xa,%YMM11,%YMM13,%YMM11 |
(95) 0x40f0ca VSHUFPD $0x5,%YMM8,%YMM13,%YMM8 |
(95) 0x40f0d0 VINSERTF128 $0x1,0xa0(%R10,%R11,1),%YMM12,%YMM12 |
(95) 0x40f0db VBLENDPD $0xc,0xa0(%R10,%R11,1),%YMM4,%YMM4 |
(95) 0x40f0e6 VBLENDPD $0xa,%YMM4,%YMM12,%YMM4 |
(95) 0x40f0ec VBLENDPD $0xa,%YMM12,%YMM14,%YMM12 |
(95) 0x40f0f2 VSHUFPD $0x5,%YMM7,%YMM14,%YMM13 |
(95) 0x40f0f7 VINSERTF32X4 $0x1,0x40(%R9,%R11,1),%YMM16,%YMM14 |
(95) 0x40f100 VBLENDPD $0xc,0x40(%R9,%R11,1),%YMM5,%YMM5 |
(95) 0x40f108 VMOVUPD 0x70(%R9,%R11,1),%XMM16 |
(95) 0x40f110 VBLENDPD $0xa,%YMM5,%YMM14,%YMM7 |
(95) 0x40f116 VBLENDPD $0xa,%YMM14,%YMM15,%YMM5 |
(95) 0x40f11c VSHUFPD $0x5,%YMM10,%YMM15,%YMM10 |
(95) 0x40f122 VBROADCASTSD 0x50(%R10,%R11,1),%YMM14 |
(95) 0x40f129 VBLENDPD $0x8,%YMM14,%YMM8,%YMM14 |
(95) 0x40f12f VBROADCASTSD 0xb0(%R10,%R11,1),%YMM8 |
(95) 0x40f139 VBLENDPD $0x8,%YMM8,%YMM13,%YMM13 |
(95) 0x40f13f VBROADCASTSD 0x50(%R9,%R11,1),%YMM8 |
(95) 0x40f146 VBLENDPD $0x8,%YMM8,%YMM10,%YMM10 |
(95) 0x40f14c VBROADCASTSD 0xb0(%R9,%R11,1),%YMM8 |
(95) 0x40f156 VSHUFPD $0x5,%YMM9,%YMM2,%YMM9 |
(95) 0x40f15c VBLENDPD $0x8,%YMM8,%YMM9,%YMM9 |
(95) 0x40f162 VINSERTF32X4 $0x1,0xa0(%R9,%R11,1),%YMM16,%YMM15 |
(95) 0x40f16b VBLENDPD $0xa,%YMM15,%YMM2,%YMM8 |
(95) 0x40f171 VFMADD231PD %YMM12,%YMM1,%YMM8 |
(95) 0x40f176 VFMADD231PD %YMM11,%YMM1,%YMM5 |
(95) 0x40f17b VFMADD231PD %YMM13,%YMM1,%YMM9 |
(95) 0x40f180 VFMADD231PD %YMM14,%YMM1,%YMM10 |
(95) 0x40f185 VMOVUPD 0x80(%R9,%R11,1),%XMM2 |
(95) 0x40f18f VBLENDPD $0xc,0xa0(%R9,%R11,1),%YMM2,%YMM2 |
(95) 0x40f19a VBLENDPD $0xa,%YMM2,%YMM15,%YMM2 |
(95) 0x40f1a0 VFMADD231PD %YMM4,%YMM1,%YMM2 |
(95) 0x40f1a5 VFMADD231PD %YMM3,%YMM1,%YMM7 |
(95) 0x40f1aa VMOVAPD %YMM5,%YMM3 |
(95) 0x40f1ae VPERMT2PD %YMM10,%YMM17,%YMM3 |
(95) 0x40f1b4 VMOVAPD %YMM9,%YMM4 |
(95) 0x40f1b8 VPERMT2PD %YMM8,%YMM18,%YMM4 |
(95) 0x40f1be VMOVAPD %YMM9,%YMM11 |
(95) 0x40f1c3 VPERMT2PD %YMM8,%YMM19,%YMM11 |
(95) 0x40f1c9 VPERMT2PD %YMM9,%YMM17,%YMM8 |
(95) 0x40f1cf VMOVAPD %YMM10,%YMM9 |
(95) 0x40f1d4 VPERMT2PD %YMM5,%YMM18,%YMM9 |
(95) 0x40f1da VPERMT2PD %YMM5,%YMM19,%YMM10 |
(95) 0x40f1e0 VPERMT2PD %YMM2,%YMM20,%YMM8 |
(95) 0x40f1e6 VBLENDPD $0x2,%YMM2,%YMM11,%YMM5 |
(95) 0x40f1ec VPERMT2PD %YMM4,%YMM6,%YMM2 |
(95) 0x40f1f2 VBLENDPD $0x2,%YMM7,%YMM10,%YMM4 |
(95) 0x40f1f8 VPERMT2PD %YMM7,%YMM20,%YMM3 |
(95) 0x40f1fe VPERMT2PD %YMM9,%YMM6,%YMM7 |
(95) 0x40f204 VMOVUPD %YMM5,0x80(%R9,%R11,1) |
(95) 0x40f20e VMOVUPD %YMM4,0x20(%R9,%R11,1) |
(95) 0x40f215 VMOVUPD %YMM7,0x40(%R9,%R11,1) |
(95) 0x40f21c VMOVUPD %YMM2,0xa0(%R9,%R11,1) |
(95) 0x40f226 VMOVUPD %YMM8,0x60(%R9,%R11,1) |
(95) 0x40f22d VMOVUPD %YMM3,(%R9,%R11,1) |
(95) 0x40f233 ADD $0x8,%R13D |
(95) 0x40f237 ADD $0xc0,%R11 |
(95) 0x40f23e CMP %R12D,%R13D |
(95) 0x40f241 JLE 40f040 |
0x40f247 CMP %R15D,%R8D |
0x40f24a JE 40ef50 |
0x40f250 JMP 40f255 |
0x40f252 XOR %R15D,%R15D |
0x40f255 SUB %R15D,%R8D |
0x40f258 MOVSXD %R15D,%R11 |
0x40f25b SAL $0x3,%R11 |
0x40f25f LEA (%R11,%R11,2),%R11 |
0x40f263 ADD %R11,%R9 |
0x40f266 ADD %R11,%R10 |
0x40f269 NOPL (%RAX) |
(94) 0x40f270 VMOVUPD (%R10,%R14,1),%XMM2 |
(94) 0x40f276 VFMADD213PD (%R9,%R14,1),%XMM1,%XMM2 |
(94) 0x40f27c VMOVUPD %XMM2,(%R9,%R14,1) |
(94) 0x40f282 VMOVSD 0x10(%R10,%R14,1),%XMM2 |
(94) 0x40f289 VFMADD213SD 0x10(%R9,%R14,1),%XMM0,%XMM2 |
(94) 0x40f290 VMOVSD %XMM2,0x10(%R9,%R14,1) |
(94) 0x40f297 ADD $0x18,%R14 |
(94) 0x40f29b DEC %R8D |
(94) 0x40f29e JNE 40f270 |
0x40f2a0 JMP 40ef50 |
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 15.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.00 |
CQA cycles if no scalar integer | 9.00 |
CQA cycles if FP arith vectorized | 9.00 |
CQA cycles if fully vectorized | 0.59 |
Front-end cycles | 9.00 |
DIV/SQRT cycles | 6.30 |
P0 cycles | 6.67 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 6.20 |
P5 cycles | 6.10 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.20 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 9.15 |
Stall cycles (UFS) | 0.00 |
Nb insns | 54.00 |
Nb uops | 54.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.93 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 15.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.00 |
CQA cycles if no scalar integer | 9.00 |
CQA cycles if FP arith vectorized | 9.00 |
CQA cycles if fully vectorized | 0.59 |
Front-end cycles | 9.00 |
DIV/SQRT cycles | 6.30 |
P0 cycles | 6.67 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 6.20 |
P5 cycles | 6.10 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.20 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 9.15 |
Stall cycles (UFS) | 0.00 |
Nb insns | 54.00 |
Nb uops | 54.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.93 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Path / |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 54 |
nb uops | 54 |
loop length | 211 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.00 cycles |
front end | 9.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 6.20 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
cycles | 6.30 | 6.67 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.15 |
Stall cycles | 0.00 |
Front-end | 9.00 |
Dispatch | 6.67 |
Overall L1 | 9.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40eedb <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDI,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R14D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(%R10,%R14,1),%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R15,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R13,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40f020 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x10(%R9,%R14,1),%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40f020 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x10(%R11,%R11,2),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA (%R11,%R11,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40f252 <advanceVelocity.extracted+0x3e2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%R15),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 40f255 <advanceVelocity.extracted+0x3e5> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R11,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 54 |
nb uops | 54 |
loop length | 211 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.00 cycles |
front end | 9.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 6.20 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
cycles | 6.30 | 6.67 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.15 |
Stall cycles | 0.00 |
Front-end | 9.00 |
Dispatch | 6.67 |
Overall L1 | 9.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40eedb <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDI,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R14D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(%R10,%R14,1),%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R15,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R13,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40f020 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x10(%R9,%R14,1),%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40f020 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x10(%R11,%R11,2),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA (%R11,%R11,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40f252 <advanceVelocity.extracted+0x3e2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%R15),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 40f255 <advanceVelocity.extracted+0x3e5> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R11,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ef50 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |