Function: advanceVelocity.extracted | Module: exec | Source: timestep.c:71-80 | Coverage: 3.57% |
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Function: advanceVelocity.extracted | Module: exec | Source: timestep.c:71-80 | Coverage: 3.57% |
---|
/scratch_na/users/xoserete/qaas_runs/171-416-7289/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 80 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
79: } |
80: } |
0x412880 PUSH %RBP |
0x412881 MOV %RSP,%RBP |
0x412884 PUSH %R15 |
0x412886 PUSH %R14 |
0x412888 PUSH %R13 |
0x41288a PUSH %R12 |
0x41288c PUSH %RBX |
0x41288d SUB $0x18,%RSP |
0x412891 MOV %RCX,%R15 |
0x412894 MOV %RDX,%RBX |
0x412897 MOVL $0,-0x3c(%RBP) |
0x41289e MOV (%RDI),%ESI |
0x4128a0 MOVL $0,-0x30(%RBP) |
0x4128a7 MOV %R9D,-0x2c(%RBP) |
0x4128ab MOVL $0x1,-0x38(%RBP) |
0x4128b2 SUB $0x8,%RSP |
0x4128b6 LEA -0x38(%RBP),%RAX |
0x4128ba LEA -0x3c(%RBP),%RCX |
0x4128be LEA -0x30(%RBP),%R8 |
0x4128c2 LEA -0x2c(%RBP),%R9 |
0x4128c6 MOV $0x6258f0,%EDI |
0x4128cb MOV %ESI,-0x34(%RBP) |
0x4128ce MOV $0x22,%EDX |
0x4128d3 PUSH $0x1 |
0x4128d5 PUSH $0x1 |
0x4128d7 PUSH %RAX |
0x4128d8 CALL 402e50 <__kmpc_for_static_init_4@plt> |
0x4128dd ADD $0x20,%RSP |
0x4128e1 MOV -0x30(%RBP),%EAX |
0x4128e4 MOV -0x2c(%RBP),%ECX |
0x4128e7 CMP %ECX,%EAX |
0x4128e9 JBE 412940 |
0x4128eb MOV $0x625910,%EDI |
0x4128f0 MOV -0x34(%RBP),%ESI |
0x4128f3 ADD $0x18,%RSP |
0x4128f7 POP %RBX |
0x4128f8 POP %R12 |
0x4128fa POP %R13 |
0x4128fc POP %R14 |
0x4128fe POP %R15 |
0x412900 POP %RBP |
0x412901 VZEROUPPER |
0x412904 JMP 402d00 |
0x412909 NOPW %CS:(%RAX,%RAX,1) |
0x412918 NOPW %CS:(%RAX,%RAX,1) |
0x412927 NOPW %CS:(%RAX,%RAX,1) |
0x412936 NOPW %CS:(%RAX,%RAX,1) |
0x412940 VMOVQ %R15,%XMM0 |
0x412945 MOV 0x18(%RBX),%RDX |
0x412949 MOV 0x78(%RDX),%RDX |
0x41294d SUB %RAX,%RCX |
0x412950 VPBROADCASTQ %XMM0,%YMM1 |
0x412955 MOV %EAX,%ESI |
0x412957 SAL $0x6,%ESI |
0x41295a XOR %EDI,%EDI |
0x41295c VPBROADCASTQ %XMM0,%XMM22 |
0x412962 VMOVUPD 0x8114(%RIP),%YMM16 |
0x41296c VMOVUPD 0x806a(%RIP),%YMM17 |
0x412976 VMOVUPD 0x8080(%RIP),%YMM18 |
0x412980 VMOVUPD 0x80b6(%RIP),%YMM19 |
0x41298a VMOVUPD 0x80cc(%RIP),%YMM21 |
0x412994 JMP 4129d0 |
0x412996 NOPW %CS:(%RAX,%RAX,1) |
0x4129a5 NOPW %CS:(%RAX,%RAX,1) |
0x4129b4 NOPW %CS:(%RAX,%RAX,1) |
(104) 0x4129c0 ADD $0x40,%ESI |
(104) 0x4129c3 CMP %RCX,%RDI |
(104) 0x4129c6 LEA 0x1(%RDI),%RDI |
(104) 0x4129ca JE 4128eb |
(104) 0x4129d0 LEA (%RDI,%RAX,1),%R8 |
(104) 0x4129d4 MOV (%RDX,%R8,4),%R8D |
(104) 0x4129d8 TEST %R8D,%R8D |
(104) 0x4129db JLE 4129c0 |
(104) 0x4129dd MOV %ESI,%R11D |
(104) 0x4129e0 SAL $0x3,%R11 |
(104) 0x4129e4 LEA (%RAX,%RDI,1),%R15D |
(104) 0x4129e8 SAL $0x6,%R15D |
(104) 0x4129ec MOV 0x20(%RBX),%R10 |
(104) 0x4129f0 MOV 0x20(%R10),%R9 |
(104) 0x4129f4 MOV 0x28(%R10),%R10 |
(104) 0x4129f8 LEA -0x1(%R8),%R14D |
(104) 0x4129fc MOVSXD %R14D,%R14 |
(104) 0x4129ff ADD %R15,%R14 |
(104) 0x412a02 SAL $0x3,%R14 |
(104) 0x412a06 LEA (%R14,%R14,2),%R14 |
(104) 0x412a0a LEA 0x10(%R10,%R14,1),%R12 |
(104) 0x412a0f SAL $0x3,%R15 |
(104) 0x412a13 LEA (%R15,%R15,2),%R15 |
(104) 0x412a17 LEA (%R9,%R15,1),%R13 |
(104) 0x412a1b CMP %R13,%R12 |
(104) 0x412a1e JB 412ac0 |
(104) 0x412a24 ADD %R10,%R15 |
(104) 0x412a27 LEA 0x10(%R9,%R14,1),%R14 |
(104) 0x412a2c CMP %R15,%R14 |
(104) 0x412a2f JB 412ac0 |
(104) 0x412a35 LEA 0x10(%R11,%R11,2),%R11 |
(104) 0x412a3a NOPW (%RAX,%RAX,1) |
(107) 0x412a40 VMOVSD -0x10(%R10,%R11,1),%XMM2 |
(107) 0x412a47 VFMADD213SD -0x10(%R9,%R11,1),%XMM0,%XMM2 |
(107) 0x412a4e VMOVSD %XMM2,-0x10(%R9,%R11,1) |
(107) 0x412a55 VMOVSD -0x8(%R10,%R11,1),%XMM2 |
(107) 0x412a5c VFMADD213SD -0x8(%R9,%R11,1),%XMM0,%XMM2 |
(107) 0x412a63 VMOVSD %XMM2,-0x8(%R9,%R11,1) |
(107) 0x412a6a VMOVSD (%R10,%R11,1),%XMM2 |
(107) 0x412a70 VFMADD213SD (%R9,%R11,1),%XMM0,%XMM2 |
(107) 0x412a76 VMOVSD %XMM2,(%R9,%R11,1) |
(107) 0x412a7c ADD $0x18,%R11 |
(107) 0x412a80 DEC %R8D |
(107) 0x412a83 JNE 412a40 |
(104) 0x412a85 JMP 4129c0 |
0x412a8a NOPW %CS:(%RAX,%RAX,1) |
0x412a99 NOPW %CS:(%RAX,%RAX,1) |
0x412aa8 NOPW %CS:(%RAX,%RAX,1) |
0x412ab7 NOPW (%RAX,%RAX,1) |
(104) 0x412ac0 LEA (%R11,%R11,2),%R14 |
(104) 0x412ac4 MOV %R8D,%R15D |
(104) 0x412ac7 AND $-0x8,%R15D |
(104) 0x412acb JE 412d00 |
(104) 0x412ad1 LEA -0x1(%R15),%R12D |
(104) 0x412ad5 XOR %R13D,%R13D |
(104) 0x412ad8 MOV %R14,%R11 |
(104) 0x412adb NOPL (%RAX,%RAX,1) |
(106) 0x412ae0 VMOVUPD 0x80(%R10,%R11,1),%YMM8 |
(106) 0x412aea VMOVUPD 0x20(%R10,%R11,1),%YMM11 |
(106) 0x412af1 VMOVUPD 0x80(%R9,%R11,1),%YMM9 |
(106) 0x412afb VMOVUPD 0x20(%R9,%R11,1),%YMM13 |
(106) 0x412b02 VMOVUPD 0x10(%R10,%R11,1),%XMM3 |
(106) 0x412b09 VMOVUPD 0x70(%R10,%R11,1),%XMM12 |
(106) 0x412b10 VBLENDPD $0x3,(%R10,%R11,1),%YMM11,%YMM5 |
(106) 0x412b17 VBLENDPD $0x3,0x60(%R10,%R11,1),%YMM8,%YMM6 |
(106) 0x412b1f VBLENDPD $0x3,(%R9,%R11,1),%YMM13,%YMM4 |
(106) 0x412b26 VMOVUPD 0x10(%R9,%R11,1),%XMM20 |
(106) 0x412b2e VBLENDPD $0x3,0x60(%R9,%R11,1),%YMM9,%YMM15 |
(106) 0x412b36 VMOVUPD 0x20(%R10,%R11,1),%XMM10 |
(106) 0x412b3d VMOVUPD 0x80(%R10,%R11,1),%XMM7 |
(106) 0x412b47 VMOVUPD 0x20(%R9,%R11,1),%XMM2 |
(106) 0x412b4e VINSERTF128 $0x1,0x40(%R10,%R11,1),%YMM3,%YMM3 |
(106) 0x412b56 VBLENDPD $0xc,0x40(%R10,%R11,1),%YMM10,%YMM10 |
(106) 0x412b5e VBLENDPD $0xa,%YMM10,%YMM3,%YMM10 |
(106) 0x412b64 VBLENDPD $0xa,%YMM3,%YMM5,%YMM14 |
(106) 0x412b6a VSHUFPD $0x5,%YMM11,%YMM5,%YMM5 |
(106) 0x412b70 VINSERTF128 $0x1,0xa0(%R10,%R11,1),%YMM12,%YMM3 |
(106) 0x412b7b VBLENDPD $0xc,0xa0(%R10,%R11,1),%YMM7,%YMM7 |
(106) 0x412b86 VBLENDPD $0xa,%YMM7,%YMM3,%YMM11 |
(106) 0x412b8c VBLENDPD $0xa,%YMM3,%YMM6,%YMM3 |
(106) 0x412b92 VSHUFPD $0x5,%YMM8,%YMM6,%YMM6 |
(106) 0x412b98 VINSERTF32X4 $0x1,0x40(%R9,%R11,1),%YMM20,%YMM7 |
(106) 0x412ba1 VBLENDPD $0xc,0x40(%R9,%R11,1),%YMM2,%YMM2 |
(106) 0x412ba9 VMOVUPD 0x70(%R9,%R11,1),%XMM20 |
(106) 0x412bb1 VBLENDPD $0xa,%YMM2,%YMM7,%YMM8 |
(106) 0x412bb7 VBLENDPD $0xa,%YMM7,%YMM4,%YMM12 |
(106) 0x412bbd VSHUFPD $0x5,%YMM13,%YMM4,%YMM2 |
(106) 0x412bc3 VBROADCASTSD 0x50(%R10,%R11,1),%YMM4 |
(106) 0x412bca VBLENDPD $0x8,%YMM4,%YMM5,%YMM4 |
(106) 0x412bd0 VBROADCASTSD 0xb0(%R10,%R11,1),%YMM5 |
(106) 0x412bda VBLENDPD $0x8,%YMM5,%YMM6,%YMM5 |
(106) 0x412be0 VBROADCASTSD 0x50(%R9,%R11,1),%YMM6 |
(106) 0x412be7 VBLENDPD $0x8,%YMM6,%YMM2,%YMM13 |
(106) 0x412bed VBROADCASTSD 0xb0(%R9,%R11,1),%YMM2 |
(106) 0x412bf7 VSHUFPD $0x5,%YMM9,%YMM15,%YMM6 |
(106) 0x412bfd VBLENDPD $0x8,%YMM2,%YMM6,%YMM2 |
(106) 0x412c03 VINSERTF32X4 $0x1,0xa0(%R9,%R11,1),%YMM20,%YMM6 |
(106) 0x412c0c VBLENDPD $0xa,%YMM6,%YMM15,%YMM9 |
(106) 0x412c12 VFMADD231PD %YMM3,%YMM1,%YMM9 |
(106) 0x412c17 VFMADD231PD %YMM14,%YMM1,%YMM12 |
(106) 0x412c1c VFMADD231PD %YMM5,%YMM1,%YMM2 |
(106) 0x412c21 VFMADD231PD %YMM4,%YMM1,%YMM13 |
(106) 0x412c26 VMOVUPD 0x80(%R9,%R11,1),%XMM3 |
(106) 0x412c30 VBLENDPD $0xc,0xa0(%R9,%R11,1),%YMM3,%YMM3 |
(106) 0x412c3b VBLENDPD $0xa,%YMM3,%YMM6,%YMM14 |
(106) 0x412c41 VFMADD231PD %YMM11,%YMM1,%YMM14 |
(106) 0x412c46 VFMADD231PD %YMM10,%YMM1,%YMM8 |
(106) 0x412c4b VMOVAPD %YMM12,%YMM3 |
(106) 0x412c4f VPERMT2PD %YMM13,%YMM16,%YMM3 |
(106) 0x412c55 VMOVAPD %YMM2,%YMM4 |
(106) 0x412c59 VPERMT2PD %YMM9,%YMM17,%YMM4 |
(106) 0x412c5f VMOVAPD %YMM2,%YMM5 |
(106) 0x412c63 VPERMT2PD %YMM9,%YMM18,%YMM5 |
(106) 0x412c69 VPERMT2PD %YMM2,%YMM16,%YMM9 |
(106) 0x412c6f VMOVAPD %YMM13,%YMM2 |
(106) 0x412c73 VPERMT2PD %YMM12,%YMM17,%YMM2 |
(106) 0x412c79 VPERMT2PD %YMM12,%YMM18,%YMM13 |
(106) 0x412c7f VPERMT2PD %YMM14,%YMM19,%YMM9 |
(106) 0x412c85 VBLENDPD $0x2,%YMM14,%YMM5,%YMM5 |
(106) 0x412c8b VPERMT2PD %YMM4,%YMM21,%YMM14 |
(106) 0x412c91 VBLENDPD $0x2,%YMM8,%YMM13,%YMM4 |
(106) 0x412c97 VPERMT2PD %YMM8,%YMM19,%YMM3 |
(106) 0x412c9d VPERMT2PD %YMM2,%YMM21,%YMM8 |
(106) 0x412ca3 VMOVUPD %YMM5,0x80(%R9,%R11,1) |
(106) 0x412cad VMOVUPD %YMM4,0x20(%R9,%R11,1) |
(106) 0x412cb4 VMOVUPD %YMM8,0x40(%R9,%R11,1) |
(106) 0x412cbb VMOVUPD %YMM14,0xa0(%R9,%R11,1) |
(106) 0x412cc5 VMOVUPD %YMM9,0x60(%R9,%R11,1) |
(106) 0x412ccc VMOVUPD %YMM3,(%R9,%R11,1) |
(106) 0x412cd2 ADD $0x8,%R13D |
(106) 0x412cd6 ADD $0xc0,%R11 |
(106) 0x412cdd CMP %R12D,%R13D |
(106) 0x412ce0 JLE 412ae0 |
(104) 0x412ce6 CMP %R15D,%R8D |
(104) 0x412ce9 JE 4129c0 |
(104) 0x412cef JMP 412d03 |
0x412cf1 NOPW %CS:(%RAX,%RAX,1) |
(104) 0x412d00 XOR %R15D,%R15D |
(104) 0x412d03 SUB %R15D,%R8D |
(104) 0x412d06 MOVSXD %R15D,%R11 |
(104) 0x412d09 SAL $0x3,%R11 |
(104) 0x412d0d LEA (%R11,%R11,2),%R11 |
(104) 0x412d11 ADD %R11,%R9 |
(104) 0x412d14 ADD %R11,%R10 |
(104) 0x412d17 NOPW (%RAX,%RAX,1) |
(105) 0x412d20 VMOVUPD (%R10,%R14,1),%XMM2 |
(105) 0x412d26 VFMADD213PD (%R9,%R14,1),%XMM22,%XMM2 |
(105) 0x412d2d VMOVUPD %XMM2,(%R9,%R14,1) |
(105) 0x412d33 VMOVSD 0x10(%R10,%R14,1),%XMM2 |
(105) 0x412d3a VFMADD213SD 0x10(%R9,%R14,1),%XMM0,%XMM2 |
(105) 0x412d41 VMOVSD %XMM2,0x10(%R9,%R14,1) |
(105) 0x412d48 ADD $0x18,%R14 |
(105) 0x412d4c DEC %R8D |
(105) 0x412d4f JNE 412d20 |
(104) 0x412d51 JMP 4129c0 |
0x412d56 NOPW %CS:(%RAX,%RAX,1) |
0x412d60 NOPW %CS:(%RAX,%RAX,1) |
0x412d6a NOPW %CS:(%RAX,%RAX,1) |
0x412d74 NOPW %CS:(%RAX,%RAX,1) |
0x412d7e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | timestep.c:71-80 |
Module | exec |
nb instructions | 75 |
nb uops | 77 |
loop length | 431 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 6 |
used zmm registers | 0 |
nb stack references | 5 |
micro-operation queue | 12.83 cycles |
front end | 12.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.80 | 1.80 | 5.67 | 5.67 | 7.50 | 3.00 | 1.80 | 7.50 | 7.50 | 7.50 | 1.60 | 5.67 |
cycles | 1.80 | 1.80 | 5.67 | 5.67 | 7.50 | 3.00 | 1.80 | 7.50 | 7.50 | 7.50 | 1.60 | 5.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.62-12.67 |
Stall cycles | 0.00 |
Front-end | 12.83 |
Dispatch | 7.50 |
Overall L1 | 12.83 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 25% |
load | 71% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 18% |
load | 37% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x6258f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 402e50 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 412940 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x625910,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402d00 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x18(%RBX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPBROADCASTQ %XMM0,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %XMM0,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD 0x8114(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x806a(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8080(%RIP),%YMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x80b6(%RIP),%YMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x80cc(%RIP),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
JMP 4129d0 <advanceVelocity.extracted+0x150> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:71-80 |
Module | exec |
nb instructions | 75 |
nb uops | 77 |
loop length | 431 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 6 |
used zmm registers | 0 |
nb stack references | 5 |
micro-operation queue | 12.83 cycles |
front end | 12.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.80 | 1.80 | 5.67 | 5.67 | 7.50 | 3.00 | 1.80 | 7.50 | 7.50 | 7.50 | 1.60 | 5.67 |
cycles | 1.80 | 1.80 | 5.67 | 5.67 | 7.50 | 3.00 | 1.80 | 7.50 | 7.50 | 7.50 | 1.60 | 5.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.62-12.67 |
Stall cycles | 0.00 |
Front-end | 12.83 |
Dispatch | 7.50 |
Overall L1 | 12.83 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 25% |
load | 71% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 18% |
load | 37% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x6258f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 402e50 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 412940 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x625910,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402d00 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x18(%RBX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPBROADCASTQ %XMM0,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %XMM0,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD 0x8114(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x806a(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8080(%RIP),%YMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x80b6(%RIP),%YMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x80cc(%RIP),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
JMP 4129d0 <advanceVelocity.extracted+0x150> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advanceVelocity.extracted– | 3.57 | 0.75 |
▼Loop 104 - timestep.c:71-80 - exec– | 0.05 | 0.01 |
○Loop 106 - timestep.c:74-78 - exec | 3.09 | 0.64 |
○Loop 105 - timestep.c:74-78 - exec | 0.43 | 0.09 |
○Loop 107 - timestep.c:74-78 - exec | 0 | 0 |