Loop Id: 104 | Module: exec | Source: timestep.c:71-80 | Coverage: 0.05% |
---|
Loop Id: 104 | Module: exec | Source: timestep.c:71-80 | Coverage: 0.05% |
---|
0x4129c0 ADD $0x40,%ESI |
0x4129c3 CMP %RCX,%RDI |
0x4129c6 LEA 0x1(%RDI),%RDI |
0x4129ca JE 4128eb |
0x4129d0 LEA (%RDI,%RAX,1),%R8 |
0x4129d4 MOV (%RDX,%R8,4),%R8D |
0x4129d8 TEST %R8D,%R8D |
0x4129db JLE 4129c0 |
0x4129dd MOV %ESI,%R11D |
0x4129e0 SAL $0x3,%R11 |
0x4129e4 LEA (%RAX,%RDI,1),%R15D |
0x4129e8 SAL $0x6,%R15D |
0x4129ec MOV 0x20(%RBX),%R10 |
0x4129f0 MOV 0x20(%R10),%R9 |
0x4129f4 MOV 0x28(%R10),%R10 |
0x4129f8 LEA -0x1(%R8),%R14D |
0x4129fc MOVSXD %R14D,%R14 |
0x4129ff ADD %R15,%R14 |
0x412a02 SAL $0x3,%R14 |
0x412a06 LEA (%R14,%R14,2),%R14 |
0x412a0a LEA 0x10(%R10,%R14,1),%R12 |
0x412a0f SAL $0x3,%R15 |
0x412a13 LEA (%R15,%R15,2),%R15 |
0x412a17 LEA (%R9,%R15,1),%R13 |
0x412a1b CMP %R13,%R12 |
0x412a1e JB 412ac0 |
0x412a24 ADD %R10,%R15 |
0x412a27 LEA 0x10(%R9,%R14,1),%R14 |
0x412a2c CMP %R15,%R14 |
0x412a2f JB 412ac0 |
0x412a35 LEA 0x10(%R11,%R11,2),%R11 |
0x412a3a NOPW (%RAX,%RAX,1) |
(107) 0x412a40 VMOVSD -0x10(%R10,%R11,1),%XMM2 |
(107) 0x412a47 VFMADD213SD -0x10(%R9,%R11,1),%XMM0,%XMM2 |
(107) 0x412a4e VMOVSD %XMM2,-0x10(%R9,%R11,1) |
(107) 0x412a55 VMOVSD -0x8(%R10,%R11,1),%XMM2 |
(107) 0x412a5c VFMADD213SD -0x8(%R9,%R11,1),%XMM0,%XMM2 |
(107) 0x412a63 VMOVSD %XMM2,-0x8(%R9,%R11,1) |
(107) 0x412a6a VMOVSD (%R10,%R11,1),%XMM2 |
(107) 0x412a70 VFMADD213SD (%R9,%R11,1),%XMM0,%XMM2 |
(107) 0x412a76 VMOVSD %XMM2,(%R9,%R11,1) |
(107) 0x412a7c ADD $0x18,%R11 |
(107) 0x412a80 DEC %R8D |
(107) 0x412a83 JNE 412a40 |
0x412a85 JMP 4129c0 |
0x412ac0 LEA (%R11,%R11,2),%R14 |
0x412ac4 MOV %R8D,%R15D |
0x412ac7 AND $-0x8,%R15D |
0x412acb JE 412d00 |
0x412ad1 LEA -0x1(%R15),%R12D |
0x412ad5 XOR %R13D,%R13D |
0x412ad8 MOV %R14,%R11 |
0x412adb NOPL (%RAX,%RAX,1) |
(106) 0x412ae0 VMOVUPD 0x80(%R10,%R11,1),%YMM8 |
(106) 0x412aea VMOVUPD 0x20(%R10,%R11,1),%YMM11 |
(106) 0x412af1 VMOVUPD 0x80(%R9,%R11,1),%YMM9 |
(106) 0x412afb VMOVUPD 0x20(%R9,%R11,1),%YMM13 |
(106) 0x412b02 VMOVUPD 0x10(%R10,%R11,1),%XMM3 |
(106) 0x412b09 VMOVUPD 0x70(%R10,%R11,1),%XMM12 |
(106) 0x412b10 VBLENDPD $0x3,(%R10,%R11,1),%YMM11,%YMM5 |
(106) 0x412b17 VBLENDPD $0x3,0x60(%R10,%R11,1),%YMM8,%YMM6 |
(106) 0x412b1f VBLENDPD $0x3,(%R9,%R11,1),%YMM13,%YMM4 |
(106) 0x412b26 VMOVUPD 0x10(%R9,%R11,1),%XMM20 |
(106) 0x412b2e VBLENDPD $0x3,0x60(%R9,%R11,1),%YMM9,%YMM15 |
(106) 0x412b36 VMOVUPD 0x20(%R10,%R11,1),%XMM10 |
(106) 0x412b3d VMOVUPD 0x80(%R10,%R11,1),%XMM7 |
(106) 0x412b47 VMOVUPD 0x20(%R9,%R11,1),%XMM2 |
(106) 0x412b4e VINSERTF128 $0x1,0x40(%R10,%R11,1),%YMM3,%YMM3 |
(106) 0x412b56 VBLENDPD $0xc,0x40(%R10,%R11,1),%YMM10,%YMM10 |
(106) 0x412b5e VBLENDPD $0xa,%YMM10,%YMM3,%YMM10 |
(106) 0x412b64 VBLENDPD $0xa,%YMM3,%YMM5,%YMM14 |
(106) 0x412b6a VSHUFPD $0x5,%YMM11,%YMM5,%YMM5 |
(106) 0x412b70 VINSERTF128 $0x1,0xa0(%R10,%R11,1),%YMM12,%YMM3 |
(106) 0x412b7b VBLENDPD $0xc,0xa0(%R10,%R11,1),%YMM7,%YMM7 |
(106) 0x412b86 VBLENDPD $0xa,%YMM7,%YMM3,%YMM11 |
(106) 0x412b8c VBLENDPD $0xa,%YMM3,%YMM6,%YMM3 |
(106) 0x412b92 VSHUFPD $0x5,%YMM8,%YMM6,%YMM6 |
(106) 0x412b98 VINSERTF32X4 $0x1,0x40(%R9,%R11,1),%YMM20,%YMM7 |
(106) 0x412ba1 VBLENDPD $0xc,0x40(%R9,%R11,1),%YMM2,%YMM2 |
(106) 0x412ba9 VMOVUPD 0x70(%R9,%R11,1),%XMM20 |
(106) 0x412bb1 VBLENDPD $0xa,%YMM2,%YMM7,%YMM8 |
(106) 0x412bb7 VBLENDPD $0xa,%YMM7,%YMM4,%YMM12 |
(106) 0x412bbd VSHUFPD $0x5,%YMM13,%YMM4,%YMM2 |
(106) 0x412bc3 VBROADCASTSD 0x50(%R10,%R11,1),%YMM4 |
(106) 0x412bca VBLENDPD $0x8,%YMM4,%YMM5,%YMM4 |
(106) 0x412bd0 VBROADCASTSD 0xb0(%R10,%R11,1),%YMM5 |
(106) 0x412bda VBLENDPD $0x8,%YMM5,%YMM6,%YMM5 |
(106) 0x412be0 VBROADCASTSD 0x50(%R9,%R11,1),%YMM6 |
(106) 0x412be7 VBLENDPD $0x8,%YMM6,%YMM2,%YMM13 |
(106) 0x412bed VBROADCASTSD 0xb0(%R9,%R11,1),%YMM2 |
(106) 0x412bf7 VSHUFPD $0x5,%YMM9,%YMM15,%YMM6 |
(106) 0x412bfd VBLENDPD $0x8,%YMM2,%YMM6,%YMM2 |
(106) 0x412c03 VINSERTF32X4 $0x1,0xa0(%R9,%R11,1),%YMM20,%YMM6 |
(106) 0x412c0c VBLENDPD $0xa,%YMM6,%YMM15,%YMM9 |
(106) 0x412c12 VFMADD231PD %YMM3,%YMM1,%YMM9 |
(106) 0x412c17 VFMADD231PD %YMM14,%YMM1,%YMM12 |
(106) 0x412c1c VFMADD231PD %YMM5,%YMM1,%YMM2 |
(106) 0x412c21 VFMADD231PD %YMM4,%YMM1,%YMM13 |
(106) 0x412c26 VMOVUPD 0x80(%R9,%R11,1),%XMM3 |
(106) 0x412c30 VBLENDPD $0xc,0xa0(%R9,%R11,1),%YMM3,%YMM3 |
(106) 0x412c3b VBLENDPD $0xa,%YMM3,%YMM6,%YMM14 |
(106) 0x412c41 VFMADD231PD %YMM11,%YMM1,%YMM14 |
(106) 0x412c46 VFMADD231PD %YMM10,%YMM1,%YMM8 |
(106) 0x412c4b VMOVAPD %YMM12,%YMM3 |
(106) 0x412c4f VPERMT2PD %YMM13,%YMM16,%YMM3 |
(106) 0x412c55 VMOVAPD %YMM2,%YMM4 |
(106) 0x412c59 VPERMT2PD %YMM9,%YMM17,%YMM4 |
(106) 0x412c5f VMOVAPD %YMM2,%YMM5 |
(106) 0x412c63 VPERMT2PD %YMM9,%YMM18,%YMM5 |
(106) 0x412c69 VPERMT2PD %YMM2,%YMM16,%YMM9 |
(106) 0x412c6f VMOVAPD %YMM13,%YMM2 |
(106) 0x412c73 VPERMT2PD %YMM12,%YMM17,%YMM2 |
(106) 0x412c79 VPERMT2PD %YMM12,%YMM18,%YMM13 |
(106) 0x412c7f VPERMT2PD %YMM14,%YMM19,%YMM9 |
(106) 0x412c85 VBLENDPD $0x2,%YMM14,%YMM5,%YMM5 |
(106) 0x412c8b VPERMT2PD %YMM4,%YMM21,%YMM14 |
(106) 0x412c91 VBLENDPD $0x2,%YMM8,%YMM13,%YMM4 |
(106) 0x412c97 VPERMT2PD %YMM8,%YMM19,%YMM3 |
(106) 0x412c9d VPERMT2PD %YMM2,%YMM21,%YMM8 |
(106) 0x412ca3 VMOVUPD %YMM5,0x80(%R9,%R11,1) |
(106) 0x412cad VMOVUPD %YMM4,0x20(%R9,%R11,1) |
(106) 0x412cb4 VMOVUPD %YMM8,0x40(%R9,%R11,1) |
(106) 0x412cbb VMOVUPD %YMM14,0xa0(%R9,%R11,1) |
(106) 0x412cc5 VMOVUPD %YMM9,0x60(%R9,%R11,1) |
(106) 0x412ccc VMOVUPD %YMM3,(%R9,%R11,1) |
(106) 0x412cd2 ADD $0x8,%R13D |
(106) 0x412cd6 ADD $0xc0,%R11 |
(106) 0x412cdd CMP %R12D,%R13D |
(106) 0x412ce0 JLE 412ae0 |
0x412ce6 CMP %R15D,%R8D |
0x412ce9 JE 4129c0 |
0x412cef JMP 412d03 |
0x412d00 XOR %R15D,%R15D |
0x412d03 SUB %R15D,%R8D |
0x412d06 MOVSXD %R15D,%R11 |
0x412d09 SAL $0x3,%R11 |
0x412d0d LEA (%R11,%R11,2),%R11 |
0x412d11 ADD %R11,%R9 |
0x412d14 ADD %R11,%R10 |
0x412d17 NOPW (%RAX,%RAX,1) |
(105) 0x412d20 VMOVUPD (%R10,%R14,1),%XMM2 |
(105) 0x412d26 VFMADD213PD (%R9,%R14,1),%XMM22,%XMM2 |
(105) 0x412d2d VMOVUPD %XMM2,(%R9,%R14,1) |
(105) 0x412d33 VMOVSD 0x10(%R10,%R14,1),%XMM2 |
(105) 0x412d3a VFMADD213SD 0x10(%R9,%R14,1),%XMM0,%XMM2 |
(105) 0x412d41 VMOVSD %XMM2,0x10(%R9,%R14,1) |
(105) 0x412d48 ADD $0x18,%R14 |
(105) 0x412d4c DEC %R8D |
(105) 0x412d4f JNE 412d20 |
0x412d51 JMP 4129c0 |
/scratch_na/users/xoserete/qaas_runs/171-416-7289/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 80 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
79: } |
80: } |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 15.14 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.32 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-80 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.83 |
CQA cycles if no scalar integer | 8.83 |
CQA cycles if FP arith vectorized | 8.83 |
CQA cycles if fully vectorized | 0.58 |
Front-end cycles | 8.83 |
DIV/SQRT cycles | 6.30 |
P0 cycles | 6.67 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 6.20 |
P5 cycles | 6.10 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.20 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 8.99 - 8.98 |
Stall cycles (UFS) | 0.00 |
Nb insns | 53.00 |
Nb uops | 53.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.93 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 15.14 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.32 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-80 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.83 |
CQA cycles if no scalar integer | 8.83 |
CQA cycles if FP arith vectorized | 8.83 |
CQA cycles if fully vectorized | 0.58 |
Front-end cycles | 8.83 |
DIV/SQRT cycles | 6.30 |
P0 cycles | 6.67 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 6.20 |
P5 cycles | 6.10 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.20 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 8.99 - 8.98 |
Stall cycles (UFS) | 0.00 |
Nb insns | 53.00 |
Nb uops | 53.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.93 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Path / |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-80 |
Module | exec |
nb instructions | 53 |
nb uops | 53 |
loop length | 213 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 8.83 cycles |
front end | 8.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 6.20 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
cycles | 6.30 | 6.67 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 8.99-8.98 |
Stall cycles | 0.00 |
Front-end | 8.83 |
Dispatch | 6.67 |
Overall L1 | 8.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RDI),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 4128eb <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RAX,%RDI,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R14D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(%R10,%R14,1),%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R15,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R13,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 412ac0 <advanceVelocity.extracted+0x240> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x10(%R9,%R14,1),%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 412ac0 <advanceVelocity.extracted+0x240> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x10(%R11,%R11,2),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA (%R11,%R11,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 412d00 <advanceVelocity.extracted+0x480> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%R15),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 412d03 <advanceVelocity.extracted+0x483> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R11,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-80 |
Module | exec |
nb instructions | 53 |
nb uops | 53 |
loop length | 213 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 8.83 cycles |
front end | 8.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 6.20 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
cycles | 6.30 | 6.67 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 8.99-8.98 |
Stall cycles | 0.00 |
Front-end | 8.83 |
Dispatch | 6.67 |
Overall L1 | 8.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RDI),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 4128eb <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RAX,%RDI,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R14D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(%R10,%R14,1),%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R15,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R13,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 412ac0 <advanceVelocity.extracted+0x240> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x10(%R9,%R14,1),%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 412ac0 <advanceVelocity.extracted+0x240> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x10(%R11,%R11,2),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA (%R11,%R11,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 412d00 <advanceVelocity.extracted+0x480> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%R15),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 412d03 <advanceVelocity.extracted+0x483> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R11,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4129c0 <advanceVelocity.extracted+0x140> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |