Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 57.48% |
---|
Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 57.48% |
---|
/scratch_na/users/xoserete/qaas_runs/171-416-1926/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216 |
-------------------------------------------------------------------------------- |
172: #pragma omp parallel for reduction(+:ePot) |
173: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
174: { |
175: int nIBox = s->boxes->nAtoms[iBox]; |
176: |
177: // loop over neighbors of iBox |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
0x40b200 PUSH %RBP |
0x40b201 MOV %RSP,%RBP |
0x40b204 PUSH %R15 |
0x40b206 PUSH %R14 |
0x40b208 PUSH %R13 |
0x40b20a PUSH %R12 |
0x40b20c MOV %RDI,%R12 |
0x40b20f PUSH %RBX |
0x40b210 SUB $0x68,%RSP |
0x40b214 VMOVSD 0x18(%RDI),%XMM10 |
0x40b219 VMOVSD 0x10(%RDI),%XMM9 |
0x40b21e MOV 0x30(%RDI),%EAX |
0x40b221 VMOVSD 0x20(%RDI),%XMM5 |
0x40b226 VMOVSD 0x8(%RDI),%XMM8 |
0x40b22b MOV (%RDI),%R15 |
0x40b22e VMOVSD %XMM10,-0x50(%RBP) |
0x40b233 VMOVSD %XMM9,-0x48(%RBP) |
0x40b238 VMOVSD %XMM5,-0x38(%RBP) |
0x40b23d MOV 0x18(%R15),%R13 |
0x40b241 VMOVSD %XMM8,-0x40(%RBP) |
0x40b246 MOV %EAX,-0x68(%RBP) |
0x40b249 CALL 403070 <omp_get_num_threads@plt> |
0x40b24e MOV %EAX,%EBX |
0x40b250 CALL 403160 <omp_get_thread_num@plt> |
0x40b255 VMOVSD -0x40(%RBP),%XMM0 |
0x40b25a VMOVSD -0x48(%RBP),%XMM9 |
0x40b25f MOV %EAX,%ECX |
0x40b261 MOV 0xc(%R13),%EAX |
0x40b265 VMOVSD -0x50(%RBP),%XMM10 |
0x40b26a CLTD |
0x40b26b IDIV %EBX |
0x40b26d CMP %EDX,%ECX |
0x40b26f JL 40b659 |
0x40b275 IMUL %EAX,%ECX |
0x40b278 ADD %ECX,%EDX |
0x40b27a ADD %EDX,%EAX |
0x40b27c MOV %EAX,-0x6c(%RBP) |
0x40b27f CMP %EAX,%EDX |
0x40b281 JGE 40b66f |
0x40b287 MOVSXD -0x68(%RBP),%RSI |
0x40b28b MOVSXD %EDX,%RAX |
0x40b28e MOV 0x78(%R13),%R14 |
0x40b292 SAL $0x6,%EDX |
0x40b295 VMULSD 0x5ddb(%RIP),%XMM0,%XMM8 |
0x40b29d MOV %EDX,%ECX |
0x40b29f VXORPD %XMM5,%XMM5,%XMM5 |
0x40b2a3 VMOVSD 0x548d(%RIP),%XMM7 |
0x40b2ab LEA (,%RSI,4),%RDI |
0x40b2b3 VMOVSD 0x581d(%RIP),%XMM6 |
0x40b2bb VMOVSD 0x5dbd(%RIP),%XMM11 |
0x40b2c3 MOV %RDI,-0x78(%RBP) |
(80) 0x40b2c7 MOV -0x68(%RBP),%R9D |
(80) 0x40b2cb MOV (%R14,%RAX,4),%R8D |
(80) 0x40b2cf TEST %R9D,%R9D |
(80) 0x40b2d2 JLE 40b60f |
(80) 0x40b2d8 MOV 0x80(%R13),%R11 |
(80) 0x40b2df MOV %EAX,%ESI |
(80) 0x40b2e1 MOV -0x78(%RBP),%RBX |
(80) 0x40b2e5 MOV %ECX,-0x70(%RBP) |
(80) 0x40b2e8 SAL $0x6,%ESI |
(80) 0x40b2eb LEA (%R8,%RCX,1),%R10D |
(80) 0x40b2ef MOV %R13,-0x80(%RBP) |
(80) 0x40b2f3 VMOVSD 0x5d8d(%RIP),%XMM12 |
(80) 0x40b2fb MOV (%R11,%RAX,8),%RDX |
(80) 0x40b2ff MOVSXD %ESI,%R9 |
(80) 0x40b302 MOV %R10D,-0x50(%RBP) |
(80) 0x40b306 LEA -0x1(%R10),%R10D |
(80) 0x40b30a LEA (,%R9,8),%RDI |
(80) 0x40b312 SUB %ESI,%R10D |
(80) 0x40b315 MOV %R14,-0x48(%RBP) |
(80) 0x40b319 LEA (%RDX,%RBX,1),%R8 |
(80) 0x40b31d MOV %RDI,-0x58(%RBP) |
(80) 0x40b321 LEA 0x1(%R9,%R10,1),%RBX |
(80) 0x40b326 MOV %R12,%R9 |
(80) 0x40b329 MOV %R8,-0x60(%RBP) |
(80) 0x40b32d SAL $0x3,%RBX |
(80) 0x40b331 MOV %RAX,-0x88(%RBP) |
(80) 0x40b338 MOV %ESI,-0x64(%RBP) |
(82) 0x40b33b MOV (%RDX),%R11D |
(82) 0x40b33e TEST %R11D,%R11D |
(82) 0x40b341 JS 40b675 |
(82) 0x40b347 MOV -0x48(%RBP),%R13 |
(82) 0x40b34b MOVSXD %R11D,%R12 |
(82) 0x40b34e MOV -0x64(%RBP),%EAX |
(82) 0x40b351 MOV (%R13,%R12,4),%R14D |
(82) 0x40b356 CMP %EAX,-0x50(%RBP) |
(82) 0x40b359 JLE 40b5e9 |
(82) 0x40b35f LEA (%R12,%R12,2),%R12 |
(82) 0x40b363 MOV %RDX,-0x40(%RBP) |
(82) 0x40b367 SAL $0x6,%R11D |
(82) 0x40b36b LEA (%R14,%R14,2),%RCX |
(82) 0x40b36f SAL $0x9,%R12 |
(82) 0x40b373 MOV -0x58(%RBP),%R8 |
(82) 0x40b377 LEA (%R14,%R11,1),%R13D |
(82) 0x40b37b VXORPD %XMM4,%XMM4,%XMM4 |
(82) 0x40b37f LEA (%R12,%RCX,8),%R14 |
(82) 0x40b383 NOPL (%RAX,%RAX,1) |
(83) 0x40b388 CMP %R13D,%R11D |
(83) 0x40b38b JGE 40b5d8 |
(83) 0x40b391 MOV 0x20(%R15),%RDI |
(83) 0x40b395 LEA (%R8,%R8,2),%R10 |
(83) 0x40b399 MOV 0x18(%RDI),%RCX |
(83) 0x40b39d LEA (%RCX,%R12,1),%RAX |
(83) 0x40b3a1 LEA (%RCX,%R10,1),%RDX |
(83) 0x40b3a5 ADD %R14,%RCX |
(83) 0x40b3a8 MOV %RCX,%RSI |
(83) 0x40b3ab SUB %RAX,%RSI |
(83) 0x40b3ae AND $0x8,%ESI |
(83) 0x40b3b1 JE 40b470 |
(83) 0x40b3b7 VMOVSD 0x8(%RDX),%XMM2 |
(83) 0x40b3bc VSUBSD 0x8(%RAX),%XMM2,%XMM0 |
(83) 0x40b3c1 VMOVSD (%RDX),%XMM1 |
(83) 0x40b3c5 VSUBSD (%RAX),%XMM1,%XMM1 |
(83) 0x40b3c9 VMOVSD 0x10(%RDX),%XMM13 |
(83) 0x40b3ce VSUBSD 0x10(%RAX),%XMM13,%XMM2 |
(83) 0x40b3d3 VMULSD %XMM0,%XMM0,%XMM3 |
(83) 0x40b3d7 VFMADD231SD %XMM1,%XMM1,%XMM3 |
(83) 0x40b3dc VFMADD231SD %XMM2,%XMM2,%XMM3 |
(83) 0x40b3e1 VCOMISD %XMM3,%XMM9 |
(83) 0x40b3e5 JB 40b461 |
(83) 0x40b3e7 VCOMISD %XMM4,%XMM3 |
(83) 0x40b3eb JBE 40b461 |
(83) 0x40b3ed VDIVSD %XMM3,%XMM7,%XMM15 |
(83) 0x40b3f1 MOV 0x30(%RDI),%RSI |
(83) 0x40b3f5 ADD %R8,%RSI |
(83) 0x40b3f8 VMULSD %XMM15,%XMM15,%XMM13 |
(83) 0x40b3fd VMULSD %XMM15,%XMM10,%XMM3 |
(83) 0x40b402 VMULSD %XMM8,%XMM15,%XMM14 |
(83) 0x40b407 VMULSD %XMM3,%XMM13,%XMM3 |
(83) 0x40b40b VSUBSD %XMM7,%XMM3,%XMM13 |
(83) 0x40b40f VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(83) 0x40b415 VMOVSD %XMM13,%XMM13,%XMM15 |
(83) 0x40b41a VFMADD231SD %XMM6,%XMM13,%XMM5 |
(83) 0x40b41f VMOVSD %XMM3,%XMM3,%XMM13 |
(83) 0x40b423 VFMADD132SD %XMM11,%XMM12,%XMM13 |
(83) 0x40b428 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(83) 0x40b42d VMULSD %XMM13,%XMM3,%XMM3 |
(83) 0x40b432 VMOVSD %XMM15,(%RSI) |
(83) 0x40b436 MOV 0x28(%RDI),%RSI |
(83) 0x40b43a ADD %R10,%RSI |
(83) 0x40b43d VMULSD %XMM14,%XMM3,%XMM14 |
(83) 0x40b442 VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(83) 0x40b447 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(83) 0x40b44d VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(83) 0x40b453 VMOVSD %XMM1,(%RSI) |
(83) 0x40b457 VMOVSD %XMM0,0x8(%RSI) |
(83) 0x40b45c VMOVSD %XMM14,0x10(%RSI) |
(83) 0x40b461 ADD $0x18,%RAX |
(83) 0x40b465 CMP %RAX,%RCX |
(83) 0x40b468 JE 40b5d8 |
(83) 0x40b46e XCHG %AX,%AX |
(84) 0x40b470 VMOVSD 0x8(%RDX),%XMM0 |
(84) 0x40b475 VSUBSD 0x8(%RAX),%XMM0,%XMM0 |
(84) 0x40b47a VMOVSD (%RDX),%XMM1 |
(84) 0x40b47e VSUBSD (%RAX),%XMM1,%XMM1 |
(84) 0x40b482 VMOVSD 0x10(%RDX),%XMM2 |
(84) 0x40b487 VSUBSD 0x10(%RAX),%XMM2,%XMM2 |
(84) 0x40b48c VMULSD %XMM0,%XMM0,%XMM15 |
(84) 0x40b490 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(84) 0x40b495 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(84) 0x40b49a VCOMISD %XMM15,%XMM9 |
(84) 0x40b49f JB 40b51b |
(84) 0x40b4a1 VCOMISD %XMM4,%XMM15 |
(84) 0x40b4a5 JBE 40b51b |
(84) 0x40b4a7 VDIVSD %XMM15,%XMM7,%XMM3 |
(84) 0x40b4ac MOV 0x30(%RDI),%RSI |
(84) 0x40b4b0 ADD %R8,%RSI |
(84) 0x40b4b3 VMULSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b4b7 VMULSD %XMM3,%XMM10,%XMM15 |
(84) 0x40b4bb VMULSD %XMM8,%XMM3,%XMM14 |
(84) 0x40b4c0 VMULSD %XMM15,%XMM13,%XMM3 |
(84) 0x40b4c5 VSUBSD %XMM7,%XMM3,%XMM13 |
(84) 0x40b4c9 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(84) 0x40b4cf VMOVSD %XMM13,%XMM13,%XMM15 |
(84) 0x40b4d4 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(84) 0x40b4d9 VMOVSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b4dd VFMADD132SD %XMM11,%XMM12,%XMM13 |
(84) 0x40b4e2 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(84) 0x40b4e7 VMULSD %XMM13,%XMM3,%XMM3 |
(84) 0x40b4ec VMOVSD %XMM15,(%RSI) |
(84) 0x40b4f0 MOV 0x28(%RDI),%RSI |
(84) 0x40b4f4 ADD %R10,%RSI |
(84) 0x40b4f7 VMULSD %XMM14,%XMM3,%XMM14 |
(84) 0x40b4fc VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(84) 0x40b501 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(84) 0x40b507 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(84) 0x40b50d VMOVSD %XMM1,(%RSI) |
(84) 0x40b511 VMOVSD %XMM0,0x8(%RSI) |
(84) 0x40b516 VMOVSD %XMM14,0x10(%RSI) |
(84) 0x40b51b VMOVSD 0x8(%RDX),%XMM0 |
(84) 0x40b520 VSUBSD 0x20(%RAX),%XMM0,%XMM0 |
(84) 0x40b525 LEA 0x18(%RAX),%RSI |
(84) 0x40b529 VMOVSD (%RDX),%XMM1 |
(84) 0x40b52d VSUBSD 0x18(%RAX),%XMM1,%XMM1 |
(84) 0x40b532 VMOVSD 0x10(%RDX),%XMM2 |
(84) 0x40b537 VSUBSD 0x28(%RAX),%XMM2,%XMM2 |
(84) 0x40b53c VMULSD %XMM0,%XMM0,%XMM15 |
(84) 0x40b540 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(84) 0x40b545 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(84) 0x40b54a VCOMISD %XMM15,%XMM9 |
(84) 0x40b54f JB 40b5cb |
(84) 0x40b551 VCOMISD %XMM4,%XMM15 |
(84) 0x40b555 JBE 40b5cb |
(84) 0x40b557 VDIVSD %XMM15,%XMM7,%XMM3 |
(84) 0x40b55c MOV 0x30(%RDI),%RAX |
(84) 0x40b560 ADD %R8,%RAX |
(84) 0x40b563 VMULSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b567 VMULSD %XMM3,%XMM10,%XMM15 |
(84) 0x40b56b VMULSD %XMM8,%XMM3,%XMM14 |
(84) 0x40b570 VMULSD %XMM15,%XMM13,%XMM3 |
(84) 0x40b575 VSUBSD %XMM7,%XMM3,%XMM13 |
(84) 0x40b579 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(84) 0x40b57f VMOVSD %XMM13,%XMM13,%XMM15 |
(84) 0x40b584 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(84) 0x40b589 VMOVSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b58d VFMADD132SD %XMM11,%XMM12,%XMM13 |
(84) 0x40b592 VFMADD213SD (%RAX),%XMM6,%XMM15 |
(84) 0x40b597 VMULSD %XMM13,%XMM3,%XMM3 |
(84) 0x40b59c VMOVSD %XMM15,(%RAX) |
(84) 0x40b5a0 MOV 0x28(%RDI),%RAX |
(84) 0x40b5a4 ADD %R10,%RAX |
(84) 0x40b5a7 VMULSD %XMM14,%XMM3,%XMM14 |
(84) 0x40b5ac VFNMADD213SD (%RAX),%XMM14,%XMM1 |
(84) 0x40b5b1 VFNMADD213SD 0x8(%RAX),%XMM14,%XMM0 |
(84) 0x40b5b7 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(84) 0x40b5bd VMOVSD %XMM1,(%RAX) |
(84) 0x40b5c1 VMOVSD %XMM0,0x8(%RAX) |
(84) 0x40b5c6 VMOVSD %XMM14,0x10(%RAX) |
(84) 0x40b5cb LEA 0x18(%RSI),%RAX |
(84) 0x40b5cf CMP %RAX,%RCX |
(84) 0x40b5d2 JNE 40b470 |
(83) 0x40b5d8 ADD $0x8,%R8 |
(83) 0x40b5dc CMP %R8,%RBX |
(83) 0x40b5df JNE 40b388 |
(82) 0x40b5e5 MOV -0x40(%RBP),%RDX |
(82) 0x40b5e9 MOV -0x60(%RBP),%R11 |
(82) 0x40b5ed ADD $0x4,%RDX |
(82) 0x40b5f1 CMP %R11,%RDX |
(82) 0x40b5f4 JNE 40b33b |
(80) 0x40b5fa MOV -0x80(%RBP),%R13 |
(80) 0x40b5fe MOV -0x48(%RBP),%R14 |
(80) 0x40b602 MOV %R9,%R12 |
(80) 0x40b605 MOV -0x88(%RBP),%RAX |
(80) 0x40b60c MOV -0x70(%RBP),%ECX |
(80) 0x40b60f INC %RAX |
(80) 0x40b612 ADD $0x40,%ECX |
(80) 0x40b615 CMP %EAX,-0x6c(%RBP) |
(80) 0x40b618 JG 40b2c7 |
0x40b61e MOV 0x28(%R12),%R8 |
0x40b623 LEA 0x28(%R12),%R15 |
(81) 0x40b628 VMOVQ %R8,%XMM9 |
(81) 0x40b62d MOV %R8,%RAX |
(81) 0x40b630 VADDSD %XMM9,%XMM5,%XMM10 |
(81) 0x40b635 VMOVQ %XMM10,%RBX |
(81) 0x40b63a LOCK CMPXCHG %RBX,(%R15) |
(81) 0x40b63f MOV %R8,%R9 |
(81) 0x40b642 MOV %RAX,%R8 |
(81) 0x40b645 CMP %RAX,%R9 |
(81) 0x40b648 JNE 40b628 |
0x40b64a ADD $0x68,%RSP |
0x40b64e POP %RBX |
0x40b64f POP %R12 |
0x40b651 POP %R13 |
0x40b653 POP %R14 |
0x40b655 POP %R15 |
0x40b657 POP %RBP |
0x40b658 RET |
0x40b659 INC %EAX |
0x40b65b XOR %EDX,%EDX |
0x40b65d IMUL %EAX,%ECX |
0x40b660 ADD %ECX,%EDX |
0x40b662 ADD %EDX,%EAX |
0x40b664 MOV %EAX,-0x6c(%RBP) |
0x40b667 CMP %EAX,%EDX |
0x40b669 JL 40b287 |
0x40b66f VXORPD %XMM5,%XMM5,%XMM5 |
0x40b673 JMP 40b61e |
0x40b675 MOV $0x411070,%ECX |
0x40b67a MOV $0xb6,%EDX |
0x40b67f MOV $0x410f80,%ESI |
0x40b684 MOV $0x411068,%EDI |
0x40b689 CALL 4030d0 <__assert_fail@plt> |
0x40b68e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.37 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.63 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 83 |
loop length | 279 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.83 cycles |
front end | 13.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
cycles | 5.10 | 7.73 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.40 |
Stall cycles | 0.00 |
Front-end | 13.83 |
Dispatch | 8.50 |
DIV/SQRT | 6.00 |
Overall L1 | 13.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 7% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 10% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x18(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x20(%RDI),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM9,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM5,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM8,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b659 <ljForce._omp_fn.1+0x459> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b66f <ljForce._omp_fn.1+0x46f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD -0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMULSD 0x5ddb(%RIP),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x548d(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RSI,4),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x581d(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x5dbd(%RIP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b287 <ljForce._omp_fn.1+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40b61e <ljForce._omp_fn.1+0x41e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x411070,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410f80,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x411068,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030d0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 83 |
loop length | 279 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.83 cycles |
front end | 13.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
cycles | 5.10 | 7.73 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.40 |
Stall cycles | 0.00 |
Front-end | 13.83 |
Dispatch | 8.50 |
DIV/SQRT | 6.00 |
Overall L1 | 13.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 7% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 10% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x18(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x20(%RDI),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM9,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM5,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM8,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b659 <ljForce._omp_fn.1+0x459> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b66f <ljForce._omp_fn.1+0x46f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD -0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMULSD 0x5ddb(%RIP),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x548d(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RSI,4),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x581d(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x5dbd(%RIP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b287 <ljForce._omp_fn.1+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40b61e <ljForce._omp_fn.1+0x41e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x411070,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410f80,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x411068,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030d0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼ljForce._omp_fn.1– | 57.48 | 8.9 |
▼Loop 80 - ljForce.c:175-216 - exec– | 0.02 | 0 |
▼Loop 82 - ljForce.c:178-216 - exec– | 0.28 | 0.03 |
▼Loop 83 - ljForce.c:187-216 - exec– | 4.54 | 0.49 |
○Loop 84 - ljForce.c:191-216 - exec | 52.63 | 5.66 |
○Loop 81 - ljForce.c:172-172 - exec | 0 | 0 |