OV - exec - Loop 2

	Loop Id: 2	Module: exec	Source: main.c:142-146	Coverage: 0.02%

0x401750 VMOVSS	0x58ba80(,%R12,4),%XMM0    [1]

0x40175a VMOVSS	%XMM4,-0x58(%RBP)    [3]

0x40175f VMOVSS	0x64ef80(,%R12,4),%XMM2    [1]

0x401769 VMOVSS	0x5ed500(,%R12,4),%XMM1    [1]

0x401773 VMOVSS	-0x48(%RBP),%XMM4    [3]

0x401778 VMOVSS	-0x4c(%RBP),%XMM3    [3]

0x40177d MOV	-0x44(%RBP),%EDI    [3]

0x401780 LEA	0x1(%R12),%R15

0x401785 PUSH	%R14

0x401787 LEA	-0x3c(%RBP),%R9

0x40178b PUSH	%R13

0x40178d MOV	$0x52a000,%R8D

0x401793 MOV	$0x64ef80,%ECX

0x401798 MOV	$0x5ed500,%EDX

0x40179d MOV	$0x58ba80,%ESI

0x4017a2 CALL	401970 <Step10_orig>

0x4017a7 VMOVSS	0x58ba80(,%R15,4),%XMM0    [2]

0x4017b1 VMOVSS	-0x48(%RBP),%XMM4    [3]

0x4017b6 VMOVSS	-0x4c(%RBP),%XMM3    [3]

0x4017bb VMOVSS	0x64ef80(,%R15,4),%XMM2    [2]

0x4017c5 VMOVSS	0x5ed500(,%R15,4),%XMM1    [2]

0x4017cf MOV	$0x52a000,%R8D

0x4017d5 LEA	-0x3c(%RBP),%R9

0x4017d9 MOV	-0x44(%RBP),%EDI    [3]

0x4017dc VMOVSS	-0x58(%RBP),%XMM9    [3]

0x4017e1 VMOVSS	-0x3c(%RBP),%XMM8    [3]

0x4017e6 VFMADD213SS	0x4c8580(,%R12,4),%XMM9,%XMM8    [1]

0x4017f0 VMOVSS	-0x38(%RBP),%XMM10    [3]

0x4017f5 VMOVSS	%XMM8,0x4c8580(,%R12,4)    [1]

0x4017ff VFMADD213SS	0x466b00(,%R12,4),%XMM9,%XMM10    [1]

0x401809 VMOVSS	-0x34(%RBP),%XMM11    [3]

0x40180e VMOVSS	%XMM10,0x466b00(,%R12,4)    [1]

0x401818 VFMADD213SS	0x405080(,%R12,4),%XMM9,%XMM11    [1]

0x401822 MOV	$0x5ed500,%EDX

0x401827 VMOVSS	%XMM11,0x405080(,%R12,4)    [1]

0x401831 POP	%RCX

0x401832 POP	%RSI

0x401833 MOV	$0x64ef80,%ECX

0x401838 PUSH	%R14

0x40183a MOV	$0x58ba80,%ESI

0x40183f PUSH	%R13

0x401841 ADD	$0x2,%R12

0x401845 CALL	401970 <Step10_orig>

0x40184a VMOVSS	-0x58(%RBP),%XMM4    [3]

0x40184f VMOVSS	-0x3c(%RBP),%XMM12    [3]

0x401854 VMOVSS	-0x38(%RBP),%XMM13    [3]

0x401859 VMOVSS	-0x34(%RBP),%XMM14    [3]

0x40185e VFMADD213SS	0x4c8580(,%R15,4),%XMM4,%XMM12    [2]

0x401868 VFMADD213SS	0x466b00(,%R15,4),%XMM4,%XMM13    [2]

0x401872 VMOVSS	%XMM12,0x4c8580(,%R15,4)    [2]

0x40187c VMOVSS	%XMM13,0x466b00(,%R15,4)    [2]

0x401886 VFMADD213SS	0x405080(,%R15,4),%XMM4,%XMM14    [2]

0x401890 VMOVSS	%XMM14,0x405080(,%R15,4)    [2]

0x40189a POP	%RDI

0x40189b POP	%R8

0x40189d CMP	%R12D,%EBX

0x4018a0 JG	401750

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 142 - 146

--------------------------------------------------------------------------------

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	9.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.1
Source	main.c:142-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.67
CQA cycles if no scalar integer	10.33
CQA cycles if FP arith vectorized	11.04
CQA cycles if fully vectorized	1.27
Front-end cycles	9.67
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	1.50
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	11.67
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.50
P13 cycles	3.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	58.00
Nb loads	26.00
Nb stores	7.00
Nb stack references	7.00
FLOP/cycle	1.03
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.31
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	28.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	9.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.1
Source	main.c:142-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.67
CQA cycles if no scalar integer	10.33
CQA cycles if FP arith vectorized	11.04
CQA cycles if fully vectorized	1.27
Front-end cycles	9.67
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	1.50
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	11.67
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.50
P13 cycles	3.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	58.00
Nb loads	26.00
Nb stores	7.00
Nb stack references	7.00
FLOP/cycle	1.03
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.31
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	28.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	main.c:142-146
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142-146.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.67 to 10.33 cycles (1.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 11.67 to 1.27 cycles (9.18x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 11.67 to 9.67 cycles (1.21x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

Step10_orig: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop is loading 104 bytes (26 single precision FP elements). The binary loop is storing 28 bytes (7 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	57
nb uops	58
loop length	342
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	3.50	3.25	3.25	1.50	11.67	11.67	11.67	3.00	3.00	0.00	0.00	3.50	3.50
cycles	3.50	3.50	3.25	3.25	1.50	11.67	11.67	11.67	3.00	3.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	11.67
Data deps.	1.00
Overall L1	11.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.67 cycles. At this rate:

9% of peak load performance is reached (8.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401750

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVSS 0x58ba80(,%R12,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM4,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS 0x64ef80(,%R12,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x5ed500(,%R12,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
MOV -0x44(%RBP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
LEA 0x1(%R12),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x64ef80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x58ba80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 401970 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
VMOVSS 0x58ba80(,%R15,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x64ef80(,%R15,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x5ed500(,%R15,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x44(%RBP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
VMOVSS -0x58(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4c8580(,%R12,4),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM8,0x4c8580(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x466b00(,%R12,4),%XMM9,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM10,0x466b00(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x405080(,%R12,4),%XMM9,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
VMOVSS %XMM11,0x405080(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
POP %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x64ef80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x58ba80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x2,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 401970 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
VMOVSS -0x58(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4c8580(,%R15,4),%XMM4,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x466b00(,%R15,4),%XMM4,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM12,0x4c8580(,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM13,0x466b00(,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x405080(,%R15,4),%XMM4,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM14,0x405080(,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
POP %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP %R12D,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JG 401750 <main._omp_fn.1+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main._omp_fn.1
Source file and lines	main.c:142-146
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142-146.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 11.67 to 1.27 cycles (9.18x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 11.67 to 9.67 cycles (1.21x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Step10_orig: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop is loading 104 bytes (26 single precision FP elements). The binary loop is storing 28 bytes (7 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	57
nb uops	58
loop length	342
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	3.50	3.25	3.25	1.50	11.67	11.67	11.67	3.00	3.00	0.00	0.00	3.50	3.50
cycles	3.50	3.50	3.25	3.25	1.50	11.67	11.67	11.67	3.00	3.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	11.67
Data deps.	1.00
Overall L1	11.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.67 cycles. At this rate:

9% of peak load performance is reached (8.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401750

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVSS 0x58ba80(,%R12,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM4,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS 0x64ef80(,%R12,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x5ed500(,%R12,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
MOV -0x44(%RBP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
LEA 0x1(%R12),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x64ef80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x58ba80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 401970 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
VMOVSS 0x58ba80(,%R15,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x64ef80(,%R15,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x5ed500(,%R15,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x44(%RBP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
VMOVSS -0x58(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4c8580(,%R12,4),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM8,0x4c8580(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x466b00(,%R12,4),%XMM9,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM10,0x466b00(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x405080(,%R12,4),%XMM9,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
VMOVSS %XMM11,0x405080(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
POP %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x64ef80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x58ba80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x2,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 401970 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
VMOVSS -0x58(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4c8580(,%R15,4),%XMM4,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x466b00(,%R15,4),%XMM4,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM12,0x4c8580(,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM13,0x466b00(,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x405080(,%R15,4),%XMM4,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM14,0x405080(,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
POP %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP %R12D,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JG 401750 <main._omp_fn.1+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code