OV - exec - Function main.extracted.8

	Function: main.extracted.8	Module: exec	Source: main.c:139-146	Coverage: 0.05%

/beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

0x402900 PUSH	%RBP

0x402901 MOV	%RSP,%RBP

0x402904 PUSH	%R15

0x402906 PUSH	%R14

0x402908 PUSH	%R13

0x40290a PUSH	%R12

0x40290c PUSH	%RBX

0x40290d SUB	$0x28,%RSP

0x402911 MOV	%R9,%R14

0x402914 MOVL	$0,-0x3c(%RBP)

0x40291b MOV	(%RDI),%ESI

0x40291d MOVL	$0,-0x30(%RBP)

0x402924 MOVL	$0xbb7,-0x2c(%RBP)

0x40292b MOVL	$0x1,-0x38(%RBP)

0x402932 SUB	$0x8,%RSP

0x402936 LEA	-0x38(%RBP),%RAX

0x40293a LEA	-0x3c(%RBP),%RCX

0x40293e LEA	-0x30(%RBP),%R8

0x402942 LEA	-0x2c(%RBP),%R9

0x402946 MOV	$0x40e100,%EDI

0x40294b MOV	%ESI,-0x34(%RBP)

0x40294e MOV	$0x22,%EDX

0x402953 PUSH	$0x1

0x402955 PUSH	$0x1

0x402957 PUSH	%RAX

0x402958 CALL	402130 <__kmpc_for_static_init_4@plt>

0x40295d ADD	$0x20,%RSP

0x402961 MOV	-0x30(%RBP),%R12D

0x402965 MOV	-0x2c(%RBP),%R13D

0x402969 CMP	%R13D,%R12D

0x40296c JA	402a57

0x402972 SUB	%R12,%R13

0x402975 INC	%R13

0x402978 XOR	%EBX,%EBX

0x40297a SAL	$0x2,%R12

0x40297e LEA	-0x40(%RBP),%R15

0x402982 NOPW	%CS:(%RAX,%RAX,1)

(3) 0x402990 MOVSS	0x40e1b0(%R12,%RBX,4),%XMM0

(3) 0x40299a MOVSS	0x46fc30(%R12,%RBX,4),%XMM1

(3) 0x4029a4 MOVSS	0x4d16b0(%R12,%RBX,4),%XMM2

(3) 0x4029ae MOV	$0x40e1b0,%ESI

(3) 0x4029b3 MOV	$0x46fc30,%EDX

(3) 0x4029b8 MOV	$0x4d16b0,%ECX

(3) 0x4029bd MOV	$0x533130,%R8D

(3) 0x4029c3 MOV	%R14D,%EDI

(3) 0x4029c6 MOVSS	0x764e(%RIP),%XMM3

(3) 0x4029ce MOVSS	0x764a(%RIP),%XMM4

(3) 0x4029d6 MOV	%R15,%R9

(3) 0x4029d9 LEA	-0x48(%RBP),%RAX

(3) 0x4029dd PUSH	%RAX

(3) 0x4029de LEA	-0x44(%RBP),%RAX

(3) 0x4029e2 PUSH	%RAX

(3) 0x4029e3 CALL	402100 <@plt>

(3) 0x4029e8 ADD	$0x10,%RSP

(3) 0x4029ec MOVSS	-0x40(%RBP),%XMM0

(3) 0x4029f1 MOVSS	0x762b(%RIP),%XMM2

(3) 0x4029f9 MULSS	%XMM2,%XMM0

(3) 0x4029fd ADDSS	0x594bb0(%R12,%RBX,4),%XMM0

(3) 0x402a07 MOVSS	%XMM0,0x594bb0(%R12,%RBX,4)

(3) 0x402a11 MOVSS	-0x44(%RBP),%XMM0

(3) 0x402a16 MULSS	%XMM2,%XMM0

(3) 0x402a1a ADDSS	0x5f6630(%R12,%RBX,4),%XMM0

(3) 0x402a24 MOVSS	-0x48(%RBP),%XMM1

(3) 0x402a29 MULSS	%XMM2,%XMM1

(3) 0x402a2d ADDSS	0x6580b0(%R12,%RBX,4),%XMM1

(3) 0x402a37 MOVSS	%XMM0,0x5f6630(%R12,%RBX,4)

(3) 0x402a41 MOVSS	%XMM1,0x6580b0(%R12,%RBX,4)

(3) 0x402a4b INC	%RBX

(3) 0x402a4e CMP	%RBX,%R13

(3) 0x402a51 JNE	402990

0x402a57 MOV	$0x40e120,%EDI

0x402a5c MOV	-0x34(%RBP),%ESI

0x402a5f CALL	4020a0 <__kmpc_for_static_fini@plt>

0x402a64 ADD	$0x28,%RSP

0x402a68 POP	%RBX

0x402a69 POP	%R12

0x402a6b POP	%R13

0x402a6d POP	%R14

0x402a6f POP	%R15

0x402a71 POP	%RBP

0x402a72 RET

0x402a73 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	main.c:139-146
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.17 to 0.54 cycles (15.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences
__kmpc_for_static_init_4@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	49
nb uops	49
loop length	185
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.17 cycles
front end	8.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.17
Dispatch	4.50
Overall L1	8.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.17 cycles. At this rate:

2% of peak load performance is reached (1.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.17 to 4.50 cycles (1.81x speedup).

ASM code

In the binary file, the address of the function is: 402900

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0xbb7,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x3c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x40e100,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 402130 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x30(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R13D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JA 402a57 <main.extracted.8+0x157>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
SUB %R12,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
INC %R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25
SAL $0x2,%R12	1	0	0.50	0.50	0	0	0	0	0	1	0.50
LEA -0x40(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV $0x40e120,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 4020a0 <__kmpc_for_static_fini@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	main.c:139-146
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences
__kmpc_for_static_init_4@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	49
nb uops	49
loop length	185
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.17 cycles
front end	8.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.17
Dispatch	4.50
Overall L1	8.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.17 cycles. At this rate:

2% of peak load performance is reached (1.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402900

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0xbb7,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x3c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x40e100,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 402130 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x30(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R13D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JA 402a57 <main.extracted.8+0x157>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
SUB %R12,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
INC %R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25
SAL $0x2,%R12	1	0	0.50	0.50	0	0	0	0	0	1	0.50
LEA -0x40(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV $0x40e120,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 4020a0 <__kmpc_for_static_fini@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼main.extracted.8–	0.05	0.01
○Loop 3 - main.c:139-146 - exec	0.05	0.01

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Matching between your function (in the source code) and the binary function

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