OV - exec - Loop 9

	Loop Id: 9	Module: exec	Source: Step10_orig.c:19-35	Coverage: 63.15%

0x403110 MOVAPS	%XMM13,%XMM1

0x403114 ADDPS	%XMM10,%XMM1

0x403118 CVTPS2PD	%XMM1,%XMM2

0x40311b MOVHLPS	%XMM1,%XMM1

0x40311e CVTPS2PD	%XMM1,%XMM0

0x403121 SQRTPD	%XMM0,%XMM6

0x403125 MULPD	%XMM0,%XMM0

0x403129 MOVAPD	0x726f(%RIP),%XMM7    [3]

0x403131 MOVAPD	%XMM7,%XMM1

0x403135 DIVPD	%XMM0,%XMM1

0x403139 SQRTPD	%XMM2,%XMM0

0x40313d MULPD	%XMM6,%XMM1

0x403141 MULPD	%XMM2,%XMM2

0x403145 DIVPD	%XMM2,%XMM7

0x403149 MULPD	%XMM0,%XMM7

0x40314d MOVAPS	%XMM13,%XMM0

0x403151 MULPS	0x7258(%RIP),%XMM0    [3]

0x403158 ADDPS	0x7261(%RIP),%XMM0    [3]

0x40315f MULPS	%XMM13,%XMM0

0x403163 ADDPS	0x7266(%RIP),%XMM0    [3]

0x40316a MULPS	%XMM13,%XMM0

0x40316e ADDPS	0x726b(%RIP),%XMM0    [3]

0x403175 MULPS	%XMM13,%XMM0

0x403179 ADDPS	0x7270(%RIP),%XMM0    [3]

0x403180 MULPS	%XMM13,%XMM0

0x403184 ADDPS	0x7275(%RIP),%XMM0    [3]

0x40318b CVTPS2PD	%XMM0,%XMM2

0x40318e ADDPD	%XMM7,%XMM2

0x403192 MOVHLPS	%XMM0,%XMM0

0x403195 CVTPS2PD	%XMM0,%XMM0

0x403198 CVTPD2PS	%XMM2,%XMM2

0x40319c ADDPD	%XMM1,%XMM0

0x4031a0 CVTPD2PS	%XMM0,%XMM0

0x4031a4 UNPCKLPD	%XMM0,%XMM2

0x4031a8 MULPS	%XMM3,%XMM2

0x4031ab XORPD	%XMM0,%XMM0

0x4031af CMPPS	$0x1,%XMM13,%XMM0

0x4031b4 ANDPS	%XMM2,%XMM0

0x4031b7 MULPS	%XMM0,%XMM12

0x4031bb ADDPS	%XMM12,%XMM14

0x4031bf MULPS	%XMM0,%XMM15

0x4031c3 ADDPS	%XMM15,%XMM11

0x4031c7 MULPS	%XMM4,%XMM0

0x4031ca ADDPS	%XMM0,%XMM5

0x4031cd ADD	$0x4,%RBX

0x4031d1 CMP	%R11,%RBX

0x4031d4 JAE	40329c

0x4031da MOVUPS	(%RSI,%RBX,4),%XMM12    [2]

0x4031df SUBPS	-0x90(%RBP),%XMM12    [4]

0x4031e7 MOVUPS	(%RDX,%RBX,4),%XMM15    [6]

0x4031ec SUBPS	-0x80(%RBP),%XMM15    [4]

0x4031f1 MOVUPS	(%RCX,%RBX,4),%XMM4    [1]

0x4031f5 SUBPS	%XMM8,%XMM4

0x4031f9 MOVAPS	%XMM12,%XMM1

0x4031fd MULPS	%XMM12,%XMM1

0x403201 MOVAPS	%XMM15,%XMM3

0x403205 MULPS	%XMM15,%XMM3

0x403209 ADDPS	%XMM1,%XMM3

0x40320c MOVAPS	%XMM4,%XMM13

0x403210 MULPS	%XMM4,%XMM13

0x403214 ADDPS	%XMM3,%XMM13

0x403218 LEA	(%R8,%RBX,4),%R14

0x40321c MOVAPS	%XMM13,%XMM1

0x403220 CMPPS	$0x1,%XMM9,%XMM1

0x403225 MOVMSKPS	%XMM1,%R15D

0x403229 XORPS	%XMM3,%XMM3

0x40322c TEST	$0x1,%R15B

0x403230 JNE	403250

0x403232 TEST	$0x2,%R15B

0x403236 JNE	40325b

0x403238 TEST	$0x4,%R15B

0x40323c JNE	403271

0x40323e TEST	$0x8,%R15B

0x403242 JE	403110

0x403248 JMP	403289

0x403250 MOVSS	(%R14),%XMM3    [5]

0x403255 TEST	$0x2,%R15B

0x403259 JE	403238

0x40325b MOVSS	0x4(%R14),%XMM1    [5]

0x403261 MOVLHPS	%XMM3,%XMM1

0x403264 SHUFPS	$-0x1e,%XMM3,%XMM1

0x403268 MOVAPS	%XMM1,%XMM3

0x40326b TEST	$0x4,%R15B

0x40326f JE	40323e

0x403271 MOVSS	0x8(%R14),%XMM1    [5]

0x403277 SHUFPS	$0x30,%XMM3,%XMM1

0x40327b SHUFPS	$-0x7c,%XMM1,%XMM3

0x40327f TEST	$0x8,%R15B

0x403283 JE	403110

0x403289 MOVSS	0xc(%R14),%XMM1    [5]

0x40328f SHUFPS	$-0x1c,%XMM3,%XMM1

0x403293 SHUFPS	$0x24,%XMM1,%XMM3

0x403297 JMP	403110

/beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.74
Bottlenecks	P8, P9,
Function	Step10_orig.A
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	13.50
Front-end cycles	15.50
DIV/SQRT cycles	5.00
P0 cycles	3.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	5.00
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	11.00
P8 cycles	14.33
P9 cycles	14.33
P10 cycles	14.33
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	27.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	4.59
Nb FLOP add-sub	60.00
Nb FLOP mul	56.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.70
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	91.89
Vectorization ratio load	75.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	22.47
Vector-efficiency ratio load	20.31
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	21.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.74
Bottlenecks	P8, P9,
Function	Step10_orig.A
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	13.50
Front-end cycles	15.50
DIV/SQRT cycles	5.00
P0 cycles	3.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	5.00
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	11.00
P8 cycles	14.33
P9 cycles	14.33
P10 cycles	14.33
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	27.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	4.59
Nb FLOP add-sub	60.00
Nb FLOP mul	56.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.70
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	91.89
Vectorization ratio load	75.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	22.47
Vector-efficiency ratio load	20.31
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	21.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig.A
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.00 to 13.50 cycles (2.00x speedup).

Details

91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 15.50 cycles (1.74x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 15.50 cycles (1.74x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTPD2PS (FP64 to FP32, SIMD): 2 occurrences
CVTPS2PD (FP32 to FP64, SIMD): 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 124 FP arithmetical operations:

60: addition or subtraction
56: multiply
4: divide
4: square root

The binary loop is loading 208 bytes (52 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.60 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	93
loop length	390
used x86 registers	9
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.00	3.50	3.25	3.25	5.00	5.33	5.33	5.33	11.00	14.33	14.33	14.33	0.50	0.50
cycles	5.00	3.50	3.25	3.25	5.00	5.33	5.33	5.33	11.00	14.33	14.33	14.33	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

27.00

Cycles summary

Front-end	15.50
Dispatch	14.33
DIV/SQRT	27.00
Overall L1	27.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	93%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	96%

INT+FP

all	91%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	93%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	21%

INT+FP

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

8% of peak load performance is reached (7.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4031da

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVAPS %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADDPS %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTPS2PD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVHLPS %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
CVTPS2PD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
SQRTPD %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
MULPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD 0x726f(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
DIVPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
SQRTPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
MULPD %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DIVPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MULPD %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS 0x7258(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7261(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7266(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x726b(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7270(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7275(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
CVTPS2PD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVHLPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
CVTPS2PD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTPD2PS %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTPD2PS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UNPCKLPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MULPS %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMPPS $0x1,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ANDPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MULPS %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R11,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 40329c <Step10_orig.A+0x21c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVUPS (%RSI,%RBX,4),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPS -0x90(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVUPS (%RDX,%RBX,4),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPS -0x80(%RBP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVUPS (%RCX,%RBX,4),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPS %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPS %XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS %XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPS %XMM15,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS %XMM15,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPS %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LEA (%R8,%RBX,4),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPS %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMPPS $0x1,%XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVMSKPS %XMM1,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
XORPS %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x1,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 403250 <Step10_orig.A+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x2,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40325b <Step10_orig.A+0x1db>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x4,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 403271 <Step10_orig.A+0x1f1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x8,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 403110 <Step10_orig.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 403289 <Step10_orig.A+0x209>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOVSS (%R14),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
TEST $0x2,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 403238 <Step10_orig.A+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSS 0x4(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVLHPS %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPS $-0x1e,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVAPS %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x4,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40323e <Step10_orig.A+0x1be>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSS 0x8(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SHUFPS $0x30,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPS $-0x7c,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
TEST $0x8,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 403110 <Step10_orig.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSS 0xc(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SHUFPS $-0x1c,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPS $0x24,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
JMP 403110 <Step10_orig.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	Step10_orig.A
Source file and lines	Step10_orig.c:19-35
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 15.50 cycles (1.74x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTPD2PS (FP64 to FP32, SIMD): 2 occurrences
CVTPS2PD (FP32 to FP64, SIMD): 4 occurrences

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 124 FP arithmetical operations:

60: addition or subtraction
56: multiply
4: divide
4: square root

The binary loop is loading 208 bytes (52 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.60 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	93
loop length	390
used x86 registers	9
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.00	3.50	3.25	3.25	5.00	5.33	5.33	5.33	11.00	14.33	14.33	14.33	0.50	0.50
cycles	5.00	3.50	3.25	3.25	5.00	5.33	5.33	5.33	11.00	14.33	14.33	14.33	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

27.00

Cycles summary

Front-end	15.50
Dispatch	14.33
DIV/SQRT	27.00
Overall L1	27.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	93%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	96%

INT+FP

all	91%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	93%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	21%

INT+FP

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

8% of peak load performance is reached (7.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4031da

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVAPS %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADDPS %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTPS2PD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVHLPS %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
CVTPS2PD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
SQRTPD %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
MULPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD 0x726f(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
DIVPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
SQRTPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
MULPD %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DIVPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MULPD %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS 0x7258(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7261(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7266(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x726b(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7270(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS 0x7275(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
CVTPS2PD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVHLPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
CVTPS2PD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTPD2PS %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTPD2PS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UNPCKLPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MULPS %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMPPS $0x1,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ANDPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MULPS %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPS %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R11,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 40329c <Step10_orig.A+0x21c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVUPS (%RSI,%RBX,4),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPS -0x90(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVUPS (%RDX,%RBX,4),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPS -0x80(%RBP),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVUPS (%RCX,%RBX,4),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPS %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPS %XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS %XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPS %XMM15,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS %XMM15,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPS %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPS %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPS %XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LEA (%R8,%RBX,4),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPS %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMPPS $0x1,%XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
MOVMSKPS %XMM1,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
XORPS %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x1,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 403250 <Step10_orig.A+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x2,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40325b <Step10_orig.A+0x1db>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x4,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 403271 <Step10_orig.A+0x1f1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x8,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 403110 <Step10_orig.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 403289 <Step10_orig.A+0x209>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOVSS (%R14),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
TEST $0x2,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 403238 <Step10_orig.A+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSS 0x4(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVLHPS %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPS $-0x1e,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVAPS %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
TEST $0x4,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40323e <Step10_orig.A+0x1be>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSS 0x8(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SHUFPS $0x30,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPS $-0x7c,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
TEST $0x8,%R15B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 403110 <Step10_orig.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSS 0xc(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SHUFPS $-0x1c,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPS $0x24,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
JMP 403110 <Step10_orig.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code