OV - exec - Function main.extracted.8

	Function: main.extracted.8	Module: exec	Source: main.c:139-146	Coverage: 0.07%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

0x401950 PUSH	%RBP

0x401951 MOV	%RSP,%RBP

0x401954 PUSH	%R15

0x401956 PUSH	%R14

0x401958 PUSH	%R13

0x40195a PUSH	%R12

0x40195c PUSH	%RBX

0x40195d SUB	$0x28,%RSP

0x401961 MOVL	$0,-0x3c(%RBP)

0x401968 MOV	%R9,%R14

0x40196b MOV	(%RDI),%ESI

0x40196d MOVL	$0,-0x30(%RBP)

0x401974 MOVL	$0xbb7,-0x2c(%RBP)

0x40197b MOVL	$0x1,-0x38(%RBP)

0x401982 SUB	$0x8,%RSP

0x401986 LEA	-0x38(%RBP),%RAX

0x40198a LEA	-0x3c(%RBP),%RCX

0x40198e LEA	-0x30(%RBP),%R8

0x401992 LEA	-0x2c(%RBP),%R9

0x401996 MOV	$0x40c0e0,%EDI

0x40199b MOV	%ESI,-0x34(%RBP)

0x40199e MOV	$0x22,%EDX

0x4019a3 PUSH	$0x1

0x4019a5 PUSH	$0x1

0x4019a7 PUSH	%RAX

0x4019a8 CALL	401100 <__kmpc_for_static_init_4@plt>

0x4019ad ADD	$0x20,%RSP

0x4019b1 MOV	-0x30(%RBP),%R12D

0x4019b5 MOV	-0x2c(%RBP),%R13D

0x4019b9 CMP	%R13D,%R12D

0x4019bc JA	401a9b

0x4019c2 SUB	%R12,%R13

0x4019c5 SAL	$0x2,%R12

0x4019c9 LEA	-0x40(%RBP),%R15

0x4019cd XOR	%EBX,%EBX

0x4019cf INC	%R13

0x4019d2 NOPW	%CS:(%RAX,%RAX,1)

(4) 0x4019e0 VMOVSS	0x40c190(%R12,%RBX,4),%XMM0

(4) 0x4019ea VMOVSS	0x46dc10(%R12,%RBX,4),%XMM1

(4) 0x4019f4 VMOVSS	0x4cf690(%R12,%RBX,4),%XMM2

(4) 0x4019fe VMOVSS	0x661a(%RIP),%XMM3

(4) 0x401a06 VMOVSS	0x6616(%RIP),%XMM4

(4) 0x401a0e LEA	-0x48(%RBP),%RAX

(4) 0x401a12 MOV	$0x40c190,%ESI

(4) 0x401a17 MOV	$0x46dc10,%EDX

(4) 0x401a1c MOV	$0x4cf690,%ECX

(4) 0x401a21 MOV	$0x531110,%R8D

(4) 0x401a27 MOV	%R14D,%EDI

(4) 0x401a2a MOV	%R15,%R9

(4) 0x401a2d PUSH	%RAX

(4) 0x401a2e LEA	-0x44(%RBP),%RAX

(4) 0x401a32 PUSH	%RAX

(4) 0x401a33 CALL	401b20 <Step10_orig>

(4) 0x401a38 ADD	$0x10,%RSP

(4) 0x401a3c VMOVSS	-0x40(%RBP),%XMM0

(4) 0x401a41 VMOVSS	0x65df(%RIP),%XMM1

(4) 0x401a49 VMOVSS	-0x44(%RBP),%XMM3

(4) 0x401a4e VMOVSS	-0x48(%RBP),%XMM2

(4) 0x401a53 VFMADD213SS	0x592b90(%R12,%RBX,4),%XMM1,%XMM0

(4) 0x401a5d VFMADD213SS	0x5f4610(%R12,%RBX,4),%XMM1,%XMM3

(4) 0x401a67 VFMADD213SS	0x656090(%R12,%RBX,4),%XMM1,%XMM2

(4) 0x401a71 VMOVSS	%XMM0,0x592b90(%R12,%RBX,4)

(4) 0x401a7b VMOVSS	%XMM3,0x5f4610(%R12,%RBX,4)

(4) 0x401a85 VMOVSS	%XMM2,0x656090(%R12,%RBX,4)

(4) 0x401a8f INC	%RBX

(4) 0x401a92 CMP	%RBX,%R13

(4) 0x401a95 JNE	4019e0

0x401a9b MOV	-0x34(%RBP),%ESI

0x401a9e MOV	$0x40c100,%EDI

0x401aa3 CALL	401090 <__kmpc_for_static_fini@plt>

0x401aa8 ADD	$0x28,%RSP

0x401aac POP	%RBX

0x401aad POP	%R12

0x401aaf POP	%R13

0x401ab1 POP	%R14

0x401ab3 POP	%R15

0x401ab5 POP	%RBP

0x401ab6 RET

0x401ab7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	main.c:139-146
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.17 to 0.54 cycles (15.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	49
nb uops	49
loop length	181
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.17 cycles
front end	8.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.17
Dispatch	4.50
Overall L1	8.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.17 cycles. At this rate:

2% of peak load performance is reached (1.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.17 to 4.50 cycles (1.81x speedup).

ASM code

In the binary file, the address of the function is: 401950

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0xbb7,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x3c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x40c0e0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 401100 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x30(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
CMP %R13D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
JA 401a9b <main.extracted.8+0x14b>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
SUB %R12,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SAL $0x2,%R12	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
LEA -0x40(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
INC %R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOV $0x40c100,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CALL 401090 <__kmpc_for_static_fini@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Source file and lines	main.c:139-146
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	49
nb uops	49
loop length	181
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.17 cycles
front end	8.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	2.00	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.17
Dispatch	4.50
Overall L1	8.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.17 cycles. At this rate:

2% of peak load performance is reached (1.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401950

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0xbb7,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x3c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x40c0e0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 401100 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x30(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
CMP %R13D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
JA 401a9b <main.extracted.8+0x14b>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
SUB %R12,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SAL $0x2,%R12	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
LEA -0x40(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
INC %R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOV $0x40c100,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CALL 401090 <__kmpc_for_static_fini@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.8–	0.07	0.01
○Loop 4 - main.c:139-146 - exec	0.07	0.01

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Matching between your function (in the source code) and the binary function

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