OV - exec - Loop 5

	Loop Id: 5	Module: exec	Source: Step10_orig.c:19-35	Coverage: 51.86%

0x401d20 VMOVUPS	(%RSI,%RBX,4),%ZMM16    [2]

0x401d27 VMOVUPS	(%RDX,%RBX,4),%ZMM17    [4]

0x401d2e VMOVUPS	(%RCX,%RBX,4),%ZMM18    [1]

0x401d35 VMOVAPS	%ZMM9,%ZMM25

0x401d3b VSUBPS	%ZMM5,%ZMM16,%ZMM16

0x401d41 VSUBPS	%ZMM6,%ZMM17,%ZMM17

0x401d47 VSUBPS	%ZMM1,%ZMM18,%ZMM18

0x401d4d VMULPS	%ZMM16,%ZMM16,%ZMM19

0x401d53 VFMADD231PS	%ZMM17,%ZMM17,%ZMM19

0x401d59 VFMADD231PS	%ZMM18,%ZMM18,%ZMM19

0x401d5f VADDPS	%ZMM2,%ZMM19,%ZMM21

0x401d65 VFMADD213PS	%ZMM10,%ZMM19,%ZMM25

0x401d6b VCMPPS	$0x1,%ZMM0,%ZMM19,%K1

0x401d72 VEXTRACTF64X4	$0x1,%ZMM21,%YMM22

0x401d79 VCVTPS2PD	%YMM21,%ZMM21

0x401d7f VFMADD213PS	%ZMM11,%ZMM19,%ZMM25

0x401d85 VMOVUPS	(%R8,%RBX,4),%ZMM20{%K1}{z}    [3]

0x401d8c VCMPPS	$0x1,%ZMM19,%ZMM3,%K1

0x401d93 ADD	$0x10,%RBX

0x401d97 VSQRTPD	%ZMM21,%ZMM23

0x401d9d VMULPD	%ZMM21,%ZMM21,%ZMM21

0x401da3 VFMADD213PS	%ZMM13,%ZMM19,%ZMM25

0x401da9 VDIVPD	%ZMM21,%ZMM8,%ZMM21

0x401daf VCVTPS2PD	%YMM22,%ZMM22

0x401db5 VFMADD213PS	%ZMM14,%ZMM19,%ZMM25

0x401dbb VSQRTPD	%ZMM22,%ZMM24

0x401dc1 VMULPD	%ZMM22,%ZMM22,%ZMM22

0x401dc7 VFMADD213PS	%ZMM15,%ZMM19,%ZMM25

0x401dcd VDIVPD	%ZMM22,%ZMM8,%ZMM22

0x401dd3 VCVTPS2PD	%YMM25,%ZMM26

0x401dd9 VFMADD231PD	%ZMM21,%ZMM23,%ZMM26

0x401ddf VEXTRACTF64X4	$0x1,%ZMM25,%YMM21

0x401de6 VCVTPS2PD	%YMM21,%ZMM21

0x401dec VFMADD231PD	%ZMM22,%ZMM24,%ZMM21

0x401df2 VCVTPD2PS	%ZMM26,%YMM22

0x401df8 VCVTPD2PS	%ZMM21,%YMM21

0x401dfe VINSERTF64X4	$0x1,%YMM21,%ZMM22,%ZMM21

0x401e05 VMULPS	%ZMM21,%ZMM20,%ZMM19{%K1}{z}

0x401e0b VFMADD231PS	%ZMM16,%ZMM19,%ZMM12

0x401e11 VFMADD231PS	%ZMM17,%ZMM19,%ZMM7

0x401e17 VFMADD231PS	%ZMM18,%ZMM19,%ZMM4

0x401e1d CMP	%RDI,%RBX

0x401e20 JB	401d20

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►100.00+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.27
Bottlenecks	P8, P9,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	2.67
P6 cycles	2.67
P7 cycles	2.67
P8 cycles	22.00
P9 cycles	20.50
P10 cycles	11.25
P11 cycles	11.25
P12 cycles	0.00
P13 cycles	0.00
DIV/SQRT cycles	50.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	48.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.92
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	91.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	70.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.27
Bottlenecks	P8, P9,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	2.67
P6 cycles	2.67
P7 cycles	2.67
P8 cycles	22.00
P9 cycles	20.50
P10 cycles	11.25
P11 cycles	11.25
P12 cycles	0.00
P13 cycles	0.00
DIV/SQRT cycles	50.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	48.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.92
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	91.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	70.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 91% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 50.00 to 22.00 cycles (2.27x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 21.00 cycles (2.38x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPD2PS: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

18 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 256 bytes (64 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.94 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	48
loop length	262
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	27
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.50	11.00	9.25	9.25	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	22.00	20.50	11.25	11.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.00
Dispatch	22.00
DIV/SQRT	50.00
Data deps.	4.00
Overall L1	50.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	91%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	70%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401d20

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPS (%RDX,%RBX,4),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPS (%RCX,%RBX,4),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVAPS %ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VSUBPS %ZMM5,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VSUBPS %ZMM6,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VSUBPS %ZMM1,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMULPS %ZMM16,%ZMM16,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD231PS %ZMM17,%ZMM17,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VFMADD231PS %ZMM18,%ZMM18,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VADDPS %ZMM2,%ZMM19,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VFMADD213PS %ZMM10,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VCMPPS $0x1,%ZMM0,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VCVTPS2PD %YMM21,%ZMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD213PS %ZMM11,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VMOVUPS (%R8,%RBX,4),%ZMM20{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VCMPPS $0x1,%ZMM19,%ZMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
ADD $0x10,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VSQRTPD %ZMM21,%ZMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16	vect (100.0%)
VMULPD %ZMM21,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD213PS %ZMM13,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VDIVPD %ZMM21,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9	vect (100.0%)
VCVTPS2PD %YMM22,%ZMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD213PS %ZMM14,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VSQRTPD %ZMM22,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16	vect (100.0%)
VMULPD %ZMM22,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD213PS %ZMM15,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VDIVPD %ZMM22,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9	vect (100.0%)
VCVTPS2PD %YMM25,%ZMM26	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD231PD %ZMM21,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM25,%YMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VCVTPS2PD %YMM21,%ZMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD231PD %ZMM22,%ZMM24,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VCVTPD2PS %ZMM26,%YMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33	vect (100.0%)
VCVTPD2PS %ZMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33	vect (100.0%)
VINSERTF64X4 $0x1,%YMM21,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	vect (50.0%)
VMULPS %ZMM21,%ZMM20,%ZMM19{%K1}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD231PS %ZMM16,%ZMM19,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VFMADD231PS %ZMM17,%ZMM19,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VFMADD231PS %ZMM18,%ZMM19,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
CMP %RDI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JB 401d20 <Step10_orig+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 91% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 21.00 cycles (2.38x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPD2PS: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 256 bytes (64 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.94 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	48
loop length	262
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	27
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.50	11.00	9.25	9.25	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	22.00	20.50	11.25	11.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.00
Dispatch	22.00
DIV/SQRT	50.00
Data deps.	4.00
Overall L1	50.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	91%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	70%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401d20

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPS (%RDX,%RBX,4),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPS (%RCX,%RBX,4),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVAPS %ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VSUBPS %ZMM5,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VSUBPS %ZMM6,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VSUBPS %ZMM1,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMULPS %ZMM16,%ZMM16,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD231PS %ZMM17,%ZMM17,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VFMADD231PS %ZMM18,%ZMM18,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VADDPS %ZMM2,%ZMM19,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VFMADD213PS %ZMM10,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VCMPPS $0x1,%ZMM0,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VCVTPS2PD %YMM21,%ZMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD213PS %ZMM11,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VMOVUPS (%R8,%RBX,4),%ZMM20{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VCMPPS $0x1,%ZMM19,%ZMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
ADD $0x10,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VSQRTPD %ZMM21,%ZMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16	vect (100.0%)
VMULPD %ZMM21,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD213PS %ZMM13,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VDIVPD %ZMM21,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9	vect (100.0%)
VCVTPS2PD %YMM22,%ZMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD213PS %ZMM14,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VSQRTPD %ZMM22,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16	vect (100.0%)
VMULPD %ZMM22,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD213PS %ZMM15,%ZMM19,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VDIVPD %ZMM22,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9	vect (100.0%)
VCVTPS2PD %YMM25,%ZMM26	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD231PD %ZMM21,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM25,%YMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VCVTPS2PD %YMM21,%ZMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33	vect (50.0%)
VFMADD231PD %ZMM22,%ZMM24,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VCVTPD2PS %ZMM26,%YMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33	vect (100.0%)
VCVTPD2PS %ZMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33	vect (100.0%)
VINSERTF64X4 $0x1,%YMM21,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	vect (50.0%)
VMULPS %ZMM21,%ZMM20,%ZMM19{%K1}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VFMADD231PS %ZMM16,%ZMM19,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VFMADD231PS %ZMM17,%ZMM19,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
VFMADD231PS %ZMM18,%ZMM19,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1	vect (100.0%)
CMP %RDI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JB 401d20 <Step10_orig+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code