OV - exec - Loop 4

	Loop Id: 4	Module: exec	Source: main.c:139-146	Coverage: 0.03%

0x4019e0 VMOVSS	0x40c190(%R12,%RBX,4),%XMM0    [3]

0x4019ea VMOVSS	0x46dc10(%R12,%RBX,4),%XMM1    [3]

0x4019f4 VMOVSS	0x4cf690(%R12,%RBX,4),%XMM2    [3]

0x4019fe VMOVSS	0x661a(%RIP),%XMM3    [1]

0x401a06 VMOVSS	0x6616(%RIP),%XMM4    [1]

0x401a0e LEA	-0x48(%RBP),%RAX

0x401a12 MOV	$0x40c190,%ESI

0x401a17 MOV	$0x46dc10,%EDX

0x401a1c MOV	$0x4cf690,%ECX

0x401a21 MOV	$0x531110,%R8D

0x401a27 MOV	%R14D,%EDI

0x401a2a MOV	%R15,%R9

0x401a2d PUSH	%RAX

0x401a2e LEA	-0x44(%RBP),%RAX

0x401a32 PUSH	%RAX

0x401a33 CALL	401b20 <Step10_orig>

0x401a38 ADD	$0x10,%RSP

0x401a3c VMOVSS	-0x40(%RBP),%XMM0    [2]

0x401a41 VMOVSS	0x65df(%RIP),%XMM1    [1]

0x401a49 VMOVSS	-0x44(%RBP),%XMM3    [2]

0x401a4e VMOVSS	-0x48(%RBP),%XMM2    [2]

0x401a53 VFMADD213SS	0x592b90(%R12,%RBX,4),%XMM1,%XMM0    [3]

0x401a5d VFMADD213SS	0x5f4610(%R12,%RBX,4),%XMM1,%XMM3    [3]

0x401a67 VFMADD213SS	0x656090(%R12,%RBX,4),%XMM1,%XMM2    [3]

0x401a71 VMOVSS	%XMM0,0x592b90(%R12,%RBX,4)    [3]

0x401a7b VMOVSS	%XMM3,0x5f4610(%R12,%RBX,4)    [3]

0x401a85 VMOVSS	%XMM2,0x656090(%R12,%RBX,4)    [3]

0x401a8f INC	%RBX

0x401a92 CMP	%RBX,%R13

0x401a95 JNE	4019e0

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	9.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P5, P6, P7,
Function	main.extracted.8
Source	main.c:139-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.02
CQA cycles if fully vectorized	0.58
Front-end cycles	5.00
P0 cycles	2.25
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	1.00
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	5.33
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.50
P13 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	12.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	1.13
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.25
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	12.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.82
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	9.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P5, P6, P7,
Function	main.extracted.8
Source	main.c:139-146
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.02
CQA cycles if fully vectorized	0.58
Front-end cycles	5.00
P0 cycles	2.25
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	1.00
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	5.33
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.50
P13 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	12.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	1.13
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.25
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	12.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.82
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main.extracted.8
Source file and lines	main.c:139-146
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.33 to 5.00 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 0.58 cycles (9.14x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 5.00 cycles (1.07x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 3 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

Step10_orig: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 48 bytes (12 single precision FP elements). The binary loop is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	30
nb uops	30
loop length	187
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.25	2.25	1.00	5.33	5.33	5.33	1.50	1.50	0.00	0.00	1.50	1.50
cycles	2.25	2.25	2.25	2.25	1.00	5.33	5.33	5.33	1.50	1.50	0.00	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

9% of peak load performance is reached (9.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.25 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4019e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVSS 0x40c190(%R12,%RBX,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x46dc10(%R12,%RBX,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x4cf690(%R12,%RBX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x661a(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x6616(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x40c190,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x46dc10,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x4cf690,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x531110,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %R14D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x44(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 401b20 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
VMOVSS -0x40(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x65df(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x44(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x592b90(%R12,%RBX,4),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x5f4610(%R12,%RBX,4),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x656090(%R12,%RBX,4),%XMM1,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM0,0x592b90(%R12,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM3,0x5f4610(%R12,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM2,0x656090(%R12,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
INC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RBX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 4019e0 <main.extracted.8+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main.extracted.8
Source file and lines	main.c:139-146
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.33 to 5.00 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 5.00 cycles (1.07x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 3 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Step10_orig: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 48 bytes (12 single precision FP elements). The binary loop is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	30
nb uops	30
loop length	187
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.25	2.25	1.00	5.33	5.33	5.33	1.50	1.50	0.00	0.00	1.50	1.50
cycles	2.25	2.25	2.25	2.25	1.00	5.33	5.33	5.33	1.50	1.50	0.00	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

9% of peak load performance is reached (9.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.25 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4019e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVSS 0x40c190(%R12,%RBX,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x46dc10(%R12,%RBX,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x4cf690(%R12,%RBX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x661a(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x6616(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x40c190,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x46dc10,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x4cf690,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x531110,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %R14D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x44(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 401b20 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
VMOVSS -0x40(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x65df(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x44(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x592b90(%R12,%RBX,4),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x5f4610(%R12,%RBX,4),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x656090(%R12,%RBX,4),%XMM1,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM0,0x592b90(%R12,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM3,0x5f4610(%R12,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM2,0x656090(%R12,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (6.3%)
INC %RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RBX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 4019e0 <main.extracted.8+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

▶Scalability Runs Description

Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> MPI Command: mpirun -n <number_processes>Dataset: Run Directory: /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/run/oneview_runs/multicore/icx_3/oneview_run_1722906572OMP_PROC_BIND: spreadOMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x16	Number processes: 1OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x32	Number processes: 1OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x64	Number processes: 1OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x128	Number processes: 1OMP_NUM_THREADS: 128OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x192	Number processes: 1OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads

(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	0.79	0.01	0.77	0.01	0.45	0.03	0.33	0.04	0.21	0.06

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x8	8	1	1	1	0.050000000745058	0.03248630464077
1x16	16	0.79	1.59	2	0.049999989569187	0.040019817650318
1x32	32	0.77	3.06	4	0.02000000141561	0.038173995912075
1x64	64	0.45	3.57	8	0.024999998509884	0.05721914768219
1x128	128	0.33	5.23	16	0.024999996647239	0.060791995376348
1x192	188	0.21	4.99	24	0.029999995604157	0.07969257235527

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency