OV - exec - Loop 5

	Loop Id: 5	Module: exec	Source: Step10_orig.c:19-35	Coverage: 97.04%

0x401bc0 VMOVUPS	(%RSI,%RBX,4),%YMM16    [2]

0x401bc7 VMOVUPS	(%RDX,%RBX,4),%YMM17    [4]

0x401bce VMOVUPS	(%RCX,%RBX,4),%YMM18    [1]

0x401bd5 VMOVAPS	%YMM9,%YMM25

0x401bdb VSUBPS	%YMM6,%YMM16,%YMM16

0x401be1 VSUBPS	%YMM5,%YMM17,%YMM17

0x401be7 VSUBPS	%YMM2,%YMM18,%YMM18

0x401bed VMULPS	%YMM16,%YMM16,%YMM19

0x401bf3 VFMADD231PS	%YMM17,%YMM17,%YMM19

0x401bf9 VFMADD231PS	%YMM18,%YMM18,%YMM19

0x401bff VADDPS	%YMM0,%YMM19,%YMM21

0x401c05 VFMADD213PS	%YMM10,%YMM19,%YMM25

0x401c0b VCMPPS	$0x1,%YMM1,%YMM19,%K1

0x401c12 VMOVUPS	(%R8,%RBX,4),%YMM20{%K1}{z}    [3]

0x401c19 VCMPPS	$0x1,%YMM19,%YMM3,%K1

0x401c20 ADD	$0x8,%RBX

0x401c24 VEXTRACTF32X4	$0x1,%YMM21,%XMM22

0x401c2b VCVTPS2PD	%XMM21,%YMM21

0x401c31 VFMADD213PS	%YMM11,%YMM19,%YMM25

0x401c37 VCVTPS2PD	%XMM22,%YMM22

0x401c3d VSQRTPD	%YMM21,%YMM23

0x401c43 VMULPD	%YMM21,%YMM21,%YMM21

0x401c49 VFMADD213PS	%YMM13,%YMM19,%YMM25

0x401c4f VSQRTPD	%YMM22,%YMM24

0x401c55 VMULPD	%YMM22,%YMM22,%YMM22

0x401c5b VDIVPD	%YMM21,%YMM8,%YMM21

0x401c61 VFMADD213PS	%YMM14,%YMM19,%YMM25

0x401c67 VDIVPD	%YMM22,%YMM8,%YMM22

0x401c6d VFMADD213PS	%YMM15,%YMM19,%YMM25

0x401c73 VCVTPS2PD	%XMM25,%YMM26

0x401c79 VFMADD231PD	%YMM21,%YMM23,%YMM26

0x401c7f VEXTRACTF32X4	$0x1,%YMM25,%XMM21

0x401c86 VCVTPS2PD	%XMM21,%YMM21

0x401c8c VFMADD231PD	%YMM22,%YMM24,%YMM21

0x401c92 VCVTPD2PS	%YMM26,%XMM22

0x401c98 VCVTPD2PS	%YMM21,%XMM21

0x401c9e VINSERTF32X4	$0x1,%XMM21,%YMM22,%YMM21

0x401ca5 VMULPS	%YMM21,%YMM20,%YMM19{%K1}{z}

0x401cab VFMADD231PS	%YMM16,%YMM19,%YMM12

0x401cb1 VFMADD231PS	%YMM17,%YMM19,%YMM7

0x401cb7 VFMADD231PS	%YMM18,%YMM19,%YMM4

0x401cbd CMP	%RDI,%RBX

0x401cc0 JB	401bc0

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►99.99+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►99.96+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►100.00+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Coverage (%)	Name	Source Location	Module
►99.99+	main.extracted.8	main.c:142	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.35
Bottlenecks	P8, P9,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	27.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.33
P8 cycles	11.50
P9 cycles	11.00
P10 cycles	9.25
P11 cycles	9.25
P12 cycles	0.00
P13 cycles	0.00
DIV/SQRT cycles	27.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	48.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.19
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	88.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.74
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	45.63
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	35.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.35
Bottlenecks	P8, P9,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	27.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.33
P8 cycles	11.50
P9 cycles	11.00
P10 cycles	9.25
P11 cycles	9.25
P12 cycles	0.00
P13 cycles	0.00
DIV/SQRT cycles	27.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	48.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.19
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	88.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.74
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	45.63
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	35.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 45% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 11.50 cycles (2.35x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 11.00 cycles (2.45x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPD2PS: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:22
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:23
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:27

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

18 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time). 8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 248 FP arithmetical operations:

120: addition or subtraction (88 inside FMA instructions)
112: multiply (88 inside FMA instructions)
8: divide
8: square root

The binary loop is loading 128 bytes (32 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.94 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	48
loop length	262
used x86 registers	6
used mmx registers	0
used xmm registers	3
used ymm registers	27
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.50	11.00	9.25	9.25	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.50	11.00	9.25	9.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	27.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.00
Dispatch	11.50
DIV/SQRT	27.00
Data deps.	4.00
Overall L1	27.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	35%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

4% of peak load performance is reached (4.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401bc0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%YMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS (%RDX,%RBX,4),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS (%RCX,%RBX,4),%YMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM9,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VSUBPS %YMM6,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VSUBPS %YMM5,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VSUBPS %YMM2,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VMULPS %YMM16,%YMM16,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM17,%YMM17,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM18,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM19,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VFMADD213PS %YMM10,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM1,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPS (%R8,%RBX,4),%YMM20{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VCMPPS $0x1,%YMM19,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
ADD $0x8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VEXTRACTF32X4 $0x1,%YMM21,%XMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	vect (25.0%)
VCVTPS2PD %XMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VFMADD213PS %YMM11,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCVTPS2PD %XMM22,%YMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VSQRTPD %YMM21,%YMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	8.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD213PS %YMM13,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM22,%YMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	8.50	vect (50.0%)
VMULPD %YMM22,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM8,%YMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	5	vect (50.0%)
VFMADD213PS %YMM14,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM22,%YMM8,%YMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	5	vect (50.0%)
VFMADD213PS %YMM15,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCVTPS2PD %XMM25,%YMM26	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VFMADD231PD %YMM21,%YMM23,%YMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM25,%XMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	vect (25.0%)
VCVTPS2PD %XMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VFMADD231PD %YMM22,%YMM24,%YMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCVTPD2PS %YMM26,%XMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	0.67	vect (50.0%)
VCVTPD2PS %YMM21,%XMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	0.67	vect (50.0%)
VINSERTF32X4 $0x1,%XMM21,%YMM22,%YMM21	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VMULPS %YMM21,%YMM20,%YMM19{%K1}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM16,%YMM19,%YMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM17,%YMM19,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM18,%YMM19,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
CMP %RDI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JB 401bc0 <Step10_orig+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 45% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 11.00 cycles (2.45x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPD2PS: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:22
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:23
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:27

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 248 FP arithmetical operations:

120: addition or subtraction (88 inside FMA instructions)
112: multiply (88 inside FMA instructions)
8: divide
8: square root

The binary loop is loading 128 bytes (32 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.94 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	48
loop length	262
used x86 registers	6
used mmx registers	0
used xmm registers	3
used ymm registers	27
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.50	11.00	9.25	9.25	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.50	11.00	9.25	9.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	27.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.00
Dispatch	11.50
DIV/SQRT	27.00
Data deps.	4.00
Overall L1	27.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	35%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

4% of peak load performance is reached (4.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401bc0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%YMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS (%RDX,%RBX,4),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS (%RCX,%RBX,4),%YMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM9,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VSUBPS %YMM6,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VSUBPS %YMM5,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VSUBPS %YMM2,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VMULPS %YMM16,%YMM16,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM17,%YMM17,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM18,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM19,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	vect (50.0%)
VFMADD213PS %YMM10,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM1,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPS (%R8,%RBX,4),%YMM20{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (50.0%)
VCMPPS $0x1,%YMM19,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
ADD $0x8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VEXTRACTF32X4 $0x1,%YMM21,%XMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	vect (25.0%)
VCVTPS2PD %XMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VFMADD213PS %YMM11,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCVTPS2PD %XMM22,%YMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VSQRTPD %YMM21,%YMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	8.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD213PS %YMM13,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM22,%YMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	8.50	vect (50.0%)
VMULPD %YMM22,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM8,%YMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	5	vect (50.0%)
VFMADD213PS %YMM14,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM22,%YMM8,%YMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	5	vect (50.0%)
VFMADD213PS %YMM15,%YMM19,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCVTPS2PD %XMM25,%YMM26	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VFMADD231PD %YMM21,%YMM23,%YMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM25,%XMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	vect (25.0%)
VCVTPS2PD %XMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	4	0.67	vect (25.0%)
VFMADD231PD %YMM22,%YMM24,%YMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VCVTPD2PS %YMM26,%XMM22	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	0.67	vect (50.0%)
VCVTPD2PS %YMM21,%XMM21	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	0.67	vect (50.0%)
VINSERTF32X4 $0x1,%XMM21,%YMM22,%YMM21	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VMULPS %YMM21,%YMM20,%YMM19{%K1}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM16,%YMM19,%YMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM17,%YMM19,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM18,%YMM19,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
CMP %RDI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JB 401bc0 <Step10_orig+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

▶Scalability Runs Description

Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> MPI Command: mpirun -n <number_processes>Dataset: Run Directory: /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/run/oneview_runs/multicore/icx_3/oneview_run_1722906572OMP_PROC_BIND: spreadOMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x16	Number processes: 1OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x32	Number processes: 1OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x64	Number processes: 1OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x128	Number processes: 1OMP_NUM_THREADS: 128OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads
Run 1x192	Number processes: 1OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threads

(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	1	0	0.98	1.63	0.95	3.68	0.88	8.28	0.89	6.4

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x8	8	1	1	1	93.495010375977	97.041786193848
1x16	16	1	2	2	46.764987945557	94.692604064941
1x32	32	0.98	3.93	4	24.049999237061	88.93717956543
1x64	64	0.95	7.63	8	12.470000267029	80.027420043945
1x128	128	0.88	14.04	16	6.9249992370605	67.684600830078
1x192	192	0.89	21.25	24	4.9799995422363	55.922576904297

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency