OV - - Function main._omp

	Function: main._omp_fn.1	Module: exec	Source: main.c:139-146	Coverage: 0.02%

/beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

0x401d60 PUSH	%RBP

0x401d61 MOV	%RSP,%RBP

0x401d64 PUSH	%R15

0x401d66 PUSH	%R14

0x401d68 PUSH	%R13

0x401d6a PUSH	%R12

0x401d6c PUSH	%RBX

0x401d6d MOV	%RDI,%RBX

0x401d70 SUB	$0x38,%RSP

0x401d74 CALL	401050 <omp_get_num_threads@plt>

0x401d79 MOV	%EAX,%R12D

0x401d7c CALL	401080 <omp_get_thread_num@plt>

0x401d81 MOV	%EAX,%ECX

0x401d83 MOV	0x10(%RBX),%EAX

0x401d86 CLTD

0x401d87 IDIV	%R12D

0x401d8a CMP	%EDX,%ECX

0x401d8c JL	402090

0x401d92 IMUL	%EAX,%ECX

0x401d95 ADD	%ECX,%EDX

0x401d97 LEA	(%RAX,%RDX,1),%R13D

0x401d9b CMP	%R13D,%EDX

0x401d9e JGE	40207c

0x401da4 MOVSXD	%EDX,%R10

0x401da7 VMOVSS	0x4(%RBX),%XMM4

0x401dac VMOVSS	0x8(%RBX),%XMM5

0x401db1 VMOVSS	(%RBX),%XMM3

0x401db5 VMOVSS	0x64ef80(,%R10,4),%XMM0

0x401dbf VMOVSS	0x58ba80(,%R10,4),%XMM2

0x401dc9 VMOVSS	0x5ed500(,%R10,4),%XMM1

0x401dd3 LEA	-0x34(%RBP),%R15

0x401dd7 MOV	0xc(%RBX),%EDI

0x401dda LEA	-0x38(%RBP),%R14

0x401dde MOV	$0x58ba80,%ECX

0x401de3 MOV	$0x5ed500,%EDX

0x401de8 MOV	$0x64ef80,%ESI

0x401ded LEA	-0x3c(%RBP),%R9

0x401df1 MOV	$0x52a000,%R8D

0x401df7 MOV	%R10,%R12

0x401dfa NOT	%R12

0x401dfd VMOVSS	%XMM4,-0x44(%RBP)

0x401e02 ADD	%R13D,%R12D

0x401e05 VMOVSS	%XMM5,-0x54(%RBP)

0x401e0a AND	$0x1,%R12D

0x401e0e VMOVSS	%XMM3,-0x48(%RBP)

0x401e13 PUSH	%R15

0x401e15 PUSH	%R14

0x401e17 MOV	%R10,-0x50(%RBP)

0x401e1b CALL	401640 <Step10_orig>

0x401e20 MOV	-0x50(%RBP),%RSI

0x401e24 VMOVSS	-0x54(%RBP),%XMM4

0x401e29 VMOVSS	-0x3c(%RBP),%XMM0

0x401e2e VMOVSS	-0x38(%RBP),%XMM1

0x401e33 VMOVSS	-0x34(%RBP),%XMM2

0x401e38 LEA	0x1(%RSI),%RBX

0x401e3c VFMADD213SS	0x4c8580(,%RSI,4),%XMM4,%XMM0

0x401e46 VFMADD213SS	0x466b00(,%RSI,4),%XMM4,%XMM1

0x401e50 VMOVSS	%XMM0,0x4c8580(,%RSI,4)

0x401e59 VMOVSS	%XMM1,0x466b00(,%RSI,4)

0x401e62 VFMADD213SS	0x405080(,%RSI,4),%XMM4,%XMM2

0x401e6c VMOVSS	%XMM2,0x405080(,%RSI,4)

0x401e75 POP	%RDX

0x401e76 POP	%RCX

0x401e77 CMP	%EBX,%R13D

0x401e7a JLE	40207c

0x401e80 MOV	%RSI,-0x50(%RBP)

0x401e84 TEST	%R12D,%R12D

0x401e87 JE	401f40

0x401e8d VMOVSS	0x64ef80(,%RBX,4),%XMM0

0x401e96 VMOVSS	%XMM4,-0x54(%RBP)

0x401e9b VMOVSS	-0x48(%RBP),%XMM3

0x401ea0 VMOVSS	-0x44(%RBP),%XMM4

0x401ea5 VMOVSS	0x58ba80(,%RBX,4),%XMM2

0x401eae VMOVSS	0x5ed500(,%RBX,4),%XMM1

0x401eb7 PUSH	%R15

0x401eb9 MOV	$0x52a000,%R8D

0x401ebf PUSH	%R14

0x401ec1 MOV	$0x5ed500,%EDX

0x401ec6 LEA	-0x3c(%RBP),%R9

0x401eca MOV	$0x58ba80,%ECX

0x401ecf MOV	$0x64ef80,%ESI

0x401ed4 CALL	401640 <Step10_orig>

0x401ed9 MOV	-0x50(%RBP),%R8

0x401edd VMOVSS	-0x54(%RBP),%XMM4

0x401ee2 VMOVSS	-0x3c(%RBP),%XMM3

0x401ee7 VMOVSS	-0x38(%RBP),%XMM6

0x401eec VFMADD213SS	0x4c8580(,%RBX,4),%XMM4,%XMM3

0x401ef6 VFMADD213SS	0x466b00(,%RBX,4),%XMM4,%XMM6

0x401f00 VMOVSS	%XMM3,0x4c8580(,%RBX,4)

0x401f09 VMOVSS	%XMM6,0x466b00(,%RBX,4)

0x401f12 VMOVSS	-0x34(%RBP),%XMM7

0x401f17 VFMADD213SS	0x405080(,%RBX,4),%XMM4,%XMM7

0x401f21 VMOVSS	%XMM7,0x405080(,%RBX,4)

0x401f2a POP	%RAX

0x401f2b POP	%RDX

0x401f2c LEA	0x2(%R8),%RBX

0x401f30 CMP	%EBX,%R13D

0x401f33 JLE	40207c

0x401f39 NOPL	(%RAX)

(4) 0x401f40 VMOVSS	0x64ef80(,%RBX,4),%XMM0

(4) 0x401f49 VMOVSS	%XMM4,-0x50(%RBP)

(4) 0x401f4e VMOVSS	0x58ba80(,%RBX,4),%XMM2

(4) 0x401f57 VMOVSS	0x5ed500(,%RBX,4),%XMM1

(4) 0x401f60 VMOVSS	-0x44(%RBP),%XMM4

(4) 0x401f65 VMOVSS	-0x48(%RBP),%XMM3

(4) 0x401f6a LEA	0x1(%RBX),%R12

(4) 0x401f6e PUSH	%R15

(4) 0x401f70 LEA	-0x3c(%RBP),%R9

(4) 0x401f74 PUSH	%R14

(4) 0x401f76 MOV	$0x52a000,%R8D

(4) 0x401f7c MOV	$0x58ba80,%ECX

(4) 0x401f81 MOV	$0x5ed500,%EDX

(4) 0x401f86 MOV	$0x64ef80,%ESI

(4) 0x401f8b CALL	401640 <Step10_orig>

(4) 0x401f90 VMOVSS	0x64ef80(,%R12,4),%XMM0

(4) 0x401f9a VMOVSS	-0x44(%RBP),%XMM4

(4) 0x401f9f VMOVSS	0x58ba80(,%R12,4),%XMM2

(4) 0x401fa9 VMOVSS	0x5ed500(,%R12,4),%XMM1

(4) 0x401fb3 VMOVSS	-0x48(%RBP),%XMM3

(4) 0x401fb8 MOV	$0x5ed500,%EDX

(4) 0x401fbd VMOVSS	-0x50(%RBP),%XMM9

(4) 0x401fc2 VMOVSS	-0x3c(%RBP),%XMM8

(4) 0x401fc7 VMOVSS	-0x38(%RBP),%XMM10

(4) 0x401fcc VFMADD213SS	0x4c8580(,%RBX,4),%XMM9,%XMM8

(4) 0x401fd6 VFMADD213SS	0x466b00(,%RBX,4),%XMM9,%XMM10

(4) 0x401fe0 VMOVSS	%XMM8,0x4c8580(,%RBX,4)

(4) 0x401fe9 VMOVSS	-0x34(%RBP),%XMM11

(4) 0x401fee VFMADD213SS	0x405080(,%RBX,4),%XMM9,%XMM11

(4) 0x401ff8 VMOVSS	%XMM10,0x466b00(,%RBX,4)

(4) 0x402001 VMOVSS	%XMM11,0x405080(,%RBX,4)

(4) 0x40200a POP	%RCX

(4) 0x40200b POP	%R10

(4) 0x40200d MOV	$0x58ba80,%ECX

(4) 0x402012 PUSH	%R15

(4) 0x402014 ADD	$0x2,%RBX

(4) 0x402018 PUSH	%R14

(4) 0x40201a CALL	401640 <Step10_orig>

(4) 0x40201f VMOVSS	-0x50(%RBP),%XMM4

(4) 0x402024 VMOVSS	-0x3c(%RBP),%XMM12

(4) 0x402029 VMOVSS	-0x38(%RBP),%XMM13

(4) 0x40202e VFMADD213SS	0x4c8580(,%R12,4),%XMM4,%XMM12

(4) 0x402038 VFMADD213SS	0x466b00(,%R12,4),%XMM4,%XMM13

(4) 0x402042 VMOVSS	%XMM12,0x4c8580(,%R12,4)

(4) 0x40204c VMOVSS	-0x34(%RBP),%XMM14

(4) 0x402051 VMOVSS	%XMM13,0x466b00(,%R12,4)

(4) 0x40205b VFMADD213SS	0x405080(,%R12,4),%XMM4,%XMM14

(4) 0x402065 VMOVSS	%XMM14,0x405080(,%R12,4)

(4) 0x40206f POP	%R11

(4) 0x402071 POP	%R12

(4) 0x402073 CMP	%EBX,%R13D

(4) 0x402076 JG	401f40

0x40207c LEA	-0x28(%RBP),%RSP

0x402080 POP	%RBX

0x402081 POP	%R12

0x402083 POP	%R13

0x402085 POP	%R14

0x402087 POP	%R15

0x402089 POP	%RBP

0x40208a RET

0x40208b NOPL	(%RAX,%RAX,1)

0x402090 INC	%EAX

0x402092 XOR	%EDX,%EDX

0x402094 JMP	401d92

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	main.c:139-146
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.83 to 12.00 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.83 to 1.67 cycles (11.30x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

Step10_orig: 2 occurrences
omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary function is loading 124 bytes (31 single precision FP elements). The binary function is storing 56 bytes (14 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	111
nb uops	113
loop length	509
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.83 cycles
front end	18.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.00	9.00	8.75	8.75	6.50	15.00	15.00	15.00	3.00	3.00	0.00	0.00	5.00	5.00
cycles	9.00	9.00	8.75	8.75	6.50	15.00	15.00	15.00	3.00	3.00	0.00	0.00	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	18.83
Dispatch	15.00
DIV/SQRT	6.00
Overall L1	18.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	12%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	7%
mul	6%
add-sub	9%
fma	6%
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.83 cycles. At this rate:

6% of peak load performance is reached (6.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.97 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.83 to 15.00 cycles (1.26x speedup).

ASM code

In the binary file, the address of the function is: 401d60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 401050 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 401080 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %R12D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 402090 <main._omp_fn.1+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %ECX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RDX,1),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R13D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40207c <main._omp_fn.1+0x31c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS 0x4(%RBX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x8(%RBX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS (%RBX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x64ef80(,%R10,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x58ba80(,%R10,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x5ed500(,%R10,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA -0x34(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0xc(%RBX),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x38(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x58ba80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x64ef80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOT %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM4,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD %R13D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM5,-0x54(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
AND $0x1,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM3,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CALL 401640 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSS -0x54(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x3c(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x38(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%RSI),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD213SS 0x4c8580(,%RSI,4),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SS 0x466b00(,%RSI,4),%XMM4,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM0,0x4c8580(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM1,0x466b00(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SS 0x405080(,%RSI,4),%XMM4,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM2,0x405080(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
CMP %EBX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 40207c <main._omp_fn.1+0x31c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 401f40 <main._omp_fn.1+0x1e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSS 0x64ef80(,%RBX,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS %XMM4,-0x54(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS -0x48(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x44(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x58ba80(,%RBX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x5ed500(,%RBX,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x58ba80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x64ef80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 401640 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV -0x50(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSS -0x54(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x3c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x38(%RBP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SS 0x4c8580(,%RBX,4),%XMM4,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SS 0x466b00(,%RBX,4),%XMM4,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM3,0x4c8580(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM6,0x466b00(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS -0x34(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SS 0x405080(,%RBX,4),%XMM4,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM7,0x405080(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
LEA 0x2(%R8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EBX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 40207c <main._omp_fn.1+0x31c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 401d92 <main._omp_fn.1+0x32>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Source file and lines	main.c:139-146
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Step10_orig: 2 occurrences
omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary function is loading 124 bytes (31 single precision FP elements). The binary function is storing 56 bytes (14 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	111
nb uops	113
loop length	509
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.83 cycles
front end	18.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.00	9.00	8.75	8.75	6.50	15.00	15.00	15.00	3.00	3.00	0.00	0.00	5.00	5.00
cycles	9.00	9.00	8.75	8.75	6.50	15.00	15.00	15.00	3.00	3.00	0.00	0.00	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	18.83
Dispatch	15.00
DIV/SQRT	6.00
Overall L1	18.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	12%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	7%
mul	6%
add-sub	9%
fma	6%
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.83 cycles. At this rate:

6% of peak load performance is reached (6.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.97 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401d60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 401050 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 401080 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %R12D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 402090 <main._omp_fn.1+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %ECX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RDX,1),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R13D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40207c <main._omp_fn.1+0x31c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS 0x4(%RBX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x8(%RBX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS (%RBX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x64ef80(,%R10,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x58ba80(,%R10,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x5ed500(,%R10,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA -0x34(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0xc(%RBX),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x38(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x58ba80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x64ef80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOT %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM4,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD %R13D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM5,-0x54(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
AND $0x1,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM3,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CALL 401640 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSS -0x54(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x3c(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x38(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x1(%RSI),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD213SS 0x4c8580(,%RSI,4),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SS 0x466b00(,%RSI,4),%XMM4,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM0,0x4c8580(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM1,0x466b00(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SS 0x405080(,%RSI,4),%XMM4,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM2,0x405080(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
CMP %EBX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 40207c <main._omp_fn.1+0x31c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 401f40 <main._omp_fn.1+0x1e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSS 0x64ef80(,%RBX,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS %XMM4,-0x54(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS -0x48(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x44(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x58ba80(,%RBX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS 0x5ed500(,%RBX,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x52a000,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x5ed500,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x58ba80,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x64ef80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 401640 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV -0x50(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSS -0x54(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x3c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSS -0x38(%RBP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SS 0x4c8580(,%RBX,4),%XMM4,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SS 0x466b00(,%RBX,4),%XMM4,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM3,0x4c8580(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM6,0x466b00(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS -0x34(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SS 0x405080(,%RBX,4),%XMM4,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM7,0x405080(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
LEA 0x2(%R8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EBX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 40207c <main._omp_fn.1+0x31c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 401d92 <main._omp_fn.1+0x32>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable> MPI Command: mpirun -np <number_processes> -ppn <number_processes_per_node>Dataset: Run Directory: /home/eoseret/tst_HACCmkI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 1x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x128	OMP_NUM_THREADS: 128I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x192	OMP_NUM_THREADS: 192I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	1.08	-0	1.08	-0	0.81	0	0.41	0.02	0.2	0.05	0.2	0.06	0.05	0.18	0.03	0.18

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.13	0.02
1x2	2	1.08	2.17	2	0.07	0.02
1x4	4	1.08	4.33	4	0.05	0.02
1x8	8	0.81	6.5	8	0.03	0.02
1x16	16	0.41	6.5	16	0.03	0.04
1x32	32	0.2	6.5	32	0.03	0.06
1x64	64	0.2	13	64	0.03	0.07
1x128	128	0.05	6.5	128	0.07	0.19
1x192	192	0.03	6.5	192	0.06	0.19

Name	Coverage (%)	Time (s)
▼main._omp_fn.1–	0.02	0.13
○Loop 4 - main.c:142-146 - exec	0.02	0.12

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency