OV - - Loop 0

	Loop Id: 0	Module: exec	Source: main.c:111-116	Coverage: 0.04%

0x401281 VADDSS	%XMM10,%XMM0,%XMM14

0x401286 VADDSS	%XMM7,%XMM2,%XMM15

0x40128a LEA	0x1(%RBX),%RCX

0x40128e LEA	0x2(%RBX),%RSI

0x401292 VADDSS	%XMM11,%XMM1,%XMM3

0x401297 VCVTSI2SS	%EBX,%XMM4,%XMM6

0x40129b LEA	0x3(%RBX),%RDI

0x40129f VCVTSI2SS	%ECX,%XMM4,%XMM5

0x4012a3 VADDSS	%XMM10,%XMM14,%XMM12

0x4012a8 VADDSS	%XMM7,%XMM15,%XMM2

0x4012ac VMOVSS	%XMM14,0x64ef80(,%RBX,4)    [1]

0x4012b5 VFMADD132SS	%XMM8,%XMM14,%XMM6

0x4012ba VADDSS	%XMM11,%XMM3,%XMM1

0x4012bf VMOVSS	%XMM15,0x5ed500(,%RBX,4)    [1]

0x4012c8 VCVTSI2SS	%ESI,%XMM4,%XMM15

0x4012cc VMOVSS	%XMM3,0x58ba80(,%RBX,4)    [1]

0x4012d5 VCVTSI2SS	%EDI,%XMM4,%XMM3

0x4012d9 VADDSS	%XMM10,%XMM12,%XMM0

0x4012de VMOVSS	%XMM12,0x64ef80(,%RCX,4)    [2]

0x4012e7 VADDSS	%XMM7,%XMM2,%XMM13

0x4012eb VFMADD132SS	%XMM8,%XMM12,%XMM5

0x4012f0 VADDSS	%XMM11,%XMM1,%XMM14

0x4012f5 VMOVSS	%XMM2,0x5ed500(,%RCX,4)    [2]

0x4012fe VMOVSS	%XMM1,0x58ba80(,%RCX,4)    [2]

0x401307 VFMADD132SS	%XMM8,%XMM0,%XMM15

0x40130c VMOVSS	%XMM0,0x64ef80(,%RSI,4)    [2]

0x401315 VADDSS	%XMM10,%XMM0,%XMM0

0x40131a VADDSS	%XMM7,%XMM13,%XMM2

0x40131e VADDSS	%XMM11,%XMM14,%XMM1

0x401323 VMOVSS	%XMM6,0x52a000(,%RBX,4)    [1]

0x40132c ADD	$0x4,%RBX

0x401330 VMOVSS	%XMM5,0x52a000(,%RCX,4)    [2]

0x401339 VFMADD132SS	%XMM8,%XMM0,%XMM3

0x40133e VMOVSS	%XMM13,0x5ed500(,%RSI,4)    [2]

0x401347 VMOVSS	%XMM14,0x58ba80(,%RSI,4)    [2]

0x401350 VMOVSS	%XMM15,0x52a000(,%RSI,4)    [2]

0x401359 VMOVSS	%XMM0,0x64ef80(,%RDI,4)    [2]

0x401362 VMOVSS	%XMM2,0x5ed500(,%RDI,4)    [2]

0x40136b VMOVSS	%XMM1,0x58ba80(,%RDI,4)    [2]

0x401374 VMOVSS	%XMM3,0x52a000(,%RDI,4)    [2]

0x40137d CMP	%RDX,%RBX

0x401380 JNE	401281

/beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c: 111 - 116

--------------------------------------------------------------------------------

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	13.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	main
Source	main.c:111-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	0.88
Front-end cycles	7.50
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	45.00
Nb loads	0.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	1.67
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	13.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	main
Source	main.c:111-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	0.88
Front-end cycles	7.50
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	45.00
Nb loads	0.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	1.67
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	main.c:111-116
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/main.c:111-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 0.87 cycles (13.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SS: 4 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SS (INT32/64 to FP32, scalar): 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is storing 64 bytes (16 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	42
nb uops	45
loop length	261
used x86 registers	5
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	5.33	5.33	5.33	2.00	2.00	8.00	8.00	8.00	8.00
cycles	1.25	1.25	1.00	1.00	0.50	5.33	5.33	5.33	2.00	2.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	7.50
Dispatch	8.00
Data deps.	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

8% of peak store performance is reached (5.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401281

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VADDSS %XMM10,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM7,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LEA 0x1(%RBX),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%RBX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDSS %XMM11,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTSI2SS %EBX,%XMM4,%XMM6	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
LEA 0x3(%RBX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SS %ECX,%XMM4,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VADDSS %XMM10,%XMM14,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM7,%XMM15,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM14,0x64ef80(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD132SS %XMM8,%XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSS %XMM11,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM15,0x5ed500(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VCVTSI2SS %ESI,%XMM4,%XMM15	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VMOVSS %XMM3,0x58ba80(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VCVTSI2SS %EDI,%XMM4,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VADDSS %XMM10,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM12,0x64ef80(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDSS %XMM7,%XMM2,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMADD132SS %XMM8,%XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSS %XMM11,%XMM1,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM2,0x5ed500(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM1,0x58ba80(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD132SS %XMM8,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM0,0x64ef80(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDSS %XMM10,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM7,%XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM11,%XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM6,0x52a000(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM5,0x52a000(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD132SS %XMM8,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM13,0x5ed500(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM14,0x58ba80(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM15,0x52a000(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM0,0x64ef80(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM2,0x5ed500(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM1,0x58ba80(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM3,0x52a000(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 401281 <main+0x1e1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	main
Source file and lines	main.c:111-116
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 0.87 cycles (13.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SS: 4 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SS (INT32/64 to FP32, scalar): 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is storing 64 bytes (16 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	42
nb uops	45
loop length	261
used x86 registers	5
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	5.33	5.33	5.33	2.00	2.00	8.00	8.00	8.00	8.00
cycles	1.25	1.25	1.00	1.00	0.50	5.33	5.33	5.33	2.00	2.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	7.50
Dispatch	8.00
Data deps.	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

8% of peak store performance is reached (5.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401281

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VADDSS %XMM10,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM7,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LEA 0x1(%RBX),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%RBX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDSS %XMM11,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTSI2SS %EBX,%XMM4,%XMM6	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
LEA 0x3(%RBX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SS %ECX,%XMM4,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VADDSS %XMM10,%XMM14,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM7,%XMM15,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM14,0x64ef80(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD132SS %XMM8,%XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSS %XMM11,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM15,0x5ed500(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VCVTSI2SS %ESI,%XMM4,%XMM15	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VMOVSS %XMM3,0x58ba80(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VCVTSI2SS %EDI,%XMM4,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VADDSS %XMM10,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM12,0x64ef80(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDSS %XMM7,%XMM2,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMADD132SS %XMM8,%XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSS %XMM11,%XMM1,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM2,0x5ed500(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM1,0x58ba80(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD132SS %XMM8,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM0,0x64ef80(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDSS %XMM10,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM7,%XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSS %XMM11,%XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSS %XMM6,0x52a000(,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSS %XMM5,0x52a000(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD132SS %XMM8,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSS %XMM13,0x5ed500(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM14,0x58ba80(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM15,0x52a000(,%RSI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM0,0x64ef80(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM2,0x5ed500(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM1,0x58ba80(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSS %XMM3,0x52a000(,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 401281 <main+0x1e1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable> MPI Command: mpirun -np <number_processes> -ppn <number_processes_per_node>Dataset: Run Directory: /home/eoseret/tst_HACCmkI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 1x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x128	OMP_NUM_THREADS: 128I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x192	OMP_NUM_THREADS: 192I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	0.06	0.57	0.06	0.57	0.06	0.57	0.06	0.53	0.06	0.48	0.06	0.39	0.05	0.3	0.07	0.22

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.25	0.04
1x2	1	0.06	0.12	2	4.08	0.61
1x4	1	0.06	0.24	4	4.14	0.61
1x8	1	0.06	0.46	8	4.3	0.61
1x16	1	0.06	0.96	16	4.17	0.56
1x32	1	0.06	1.79	32	4.39	0.51
1x64	1	0.06	3.57	64	4.41	0.41
1x128	1	0.05	6.25	128	4.74	0.32
1x192	1	0.07	12.5	192	4.74	0.24

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency