OV - - Loop 3

	Loop Id: 3	Module: exec	Source: Step10_orig.c:19-31	Coverage: 99.87%

0x4016f0 VMOVUPS	(%RDX,%R11,1),%ZMM0    [1]

0x4016f7 VMOVUPS	(%RSI,%R11,1),%ZMM7    [3]

0x4016fe VMOVUPS	(%RCX,%R11,1),%ZMM5    [2]

0x401705 VSUBPS	%ZMM26,%ZMM0,%ZMM8

0x40170b VSUBPS	%ZMM27,%ZMM7,%ZMM9

0x401711 VSUBPS	%ZMM25,%ZMM5,%ZMM7

0x401717 VMULPS	%ZMM8,%ZMM8,%ZMM29

0x40171d VFMADD231PS	%ZMM9,%ZMM9,%ZMM29

0x401723 VFMADD231PS	%ZMM7,%ZMM7,%ZMM29

0x401729 VADDPS	%ZMM23,%ZMM29,%ZMM0

0x40172f VCMPPS	$0xe,%ZMM16,%ZMM29,%K2

0x401736 VCMPPS	$0x1,%ZMM24,%ZMM29,%K1

0x40173d VMOVUPS	(%R8,%R11,1),%ZMM13{%K1}    [4]

0x401744 ADD	$0x40,%R11

0x401748 VCVTPS2PD	%YMM0,%ZMM6

0x40174e VEXTRACTF32X8	$0x1,%ZMM0,%YMM5

0x401755 VMOVAPS	%ZMM29,%ZMM0

0x40175b VFMADD132PS	%ZMM22,%ZMM21,%ZMM0

0x401761 VCVTPS2PD	%YMM5,%ZMM5

0x401767 VMOVAPS	%ZMM13,%ZMM28{%K1}{z}

0x40176d VFMADD132PS	%ZMM29,%ZMM20,%ZMM0

0x401773 VSQRTPD	%ZMM6,%ZMM30

0x401779 VMULPD	%ZMM30,%ZMM6,%ZMM6

0x40177f VSQRTPD	%ZMM5,%ZMM31

0x401785 VMULPD	%ZMM31,%ZMM5,%ZMM5

0x40178b VFMADD132PS	%ZMM29,%ZMM19,%ZMM0

0x401791 VDIVPD	%ZMM6,%ZMM15,%ZMM6

0x401797 VFMADD132PS	%ZMM29,%ZMM18,%ZMM0

0x40179d VFMADD132PS	%ZMM29,%ZMM17,%ZMM0

0x4017a3 VDIVPD	%ZMM5,%ZMM15,%ZMM5

0x4017a9 VCVTPS2PD	%YMM0,%ZMM29

0x4017af VEXTRACTF32X8	$0x1,%ZMM0,%YMM0

0x4017b6 VCVTPS2PD	%YMM0,%ZMM0

0x4017bc VADDPD	%ZMM29,%ZMM6,%ZMM6

0x4017c2 VCVTPD2PS	%ZMM6,%YMM6

0x4017c8 VADDPD	%ZMM0,%ZMM5,%ZMM5

0x4017ce VCVTPD2PS	%ZMM5,%YMM0

0x4017d4 VINSERTF64X4	$0x1,%YMM0,%ZMM6,%ZMM5

0x4017db VMULPS	%ZMM28,%ZMM5,%ZMM6

0x4017e1 VMULPS	%ZMM6,%ZMM9,%ZMM0{%K2}{z}

0x4017e7 VMULPS	%ZMM6,%ZMM8,%ZMM9{%K2}{z}

0x4017ed VMULPS	%ZMM6,%ZMM7,%ZMM8{%K2}{z}

0x4017f3 VADDPS	%ZMM0,%ZMM10,%ZMM10

0x4017f9 VADDPS	%ZMM9,%ZMM11,%ZMM11

0x4017ff VADDPS	%ZMM8,%ZMM12,%ZMM12

0x401805 CMP	%R11,%RBX

0x401808 JNE	4016f0

/beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 31

--------------------------------------------------------------------------------

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.38
Bottlenecks	P8, P9,
Function	Step10_orig
Source	Step10_orig.c:19-31
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	8.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	2.67
P7 cycles	21.00
P8 cycles	19.00
P9 cycles	15.50
P10 cycles	15.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	50.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	52.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.60
Nb FLOP add-sub	128.00
Nb FLOP mul	96.00
Nb FLOP fma	112.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	92.05
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.08

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.38
Bottlenecks	P8, P9,
Function	Step10_orig
Source	Step10_orig.c:19-31
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	8.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	2.67
P7 cycles	21.00
P8 cycles	19.00
P9 cycles	15.50
P10 cycles	15.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	50.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	52.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.60
Nb FLOP add-sub	128.00
Nb FLOP mul	96.00
Nb FLOP fma	112.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	92.05
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.08

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-31
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-31.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 92% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 50.00 to 21.00 cycles (2.38x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
If you accept to loose numerical precision up to 2 ulp, you can speedup your code by passing the following options to your compiler: (ffast-math or Ofast) and mrecip

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 20.50 cycles (2.44x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPD2PS: 2 occurrences
VCVTPS2PD: 4 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

21 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 480 FP arithmetical operations:

240: addition or subtraction (112 inside FMA instructions)
208: multiply (112 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 256 bytes (64 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.87 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	52
loop length	286
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	27
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.00	11.00	11.00	11.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	21.00	19.00	15.50	15.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	8.67
Dispatch	21.00
DIV/SQRT	50.00
Data deps.	3.00
Overall L1	50.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	92%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	73%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4016f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
VMOVUPS (%RDX,%R11,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPS (%RSI,%R11,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPS (%RCX,%R11,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPS %ZMM26,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VSUBPS %ZMM27,%ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VSUBPS %ZMM25,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VMULPS %ZMM8,%ZMM8,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PS %ZMM9,%ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD231PS %ZMM7,%ZMM7,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VADDPS %ZMM23,%ZMM29,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VCMPPS $0xe,%ZMM16,%ZMM29,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1
VCMPPS $0x1,%ZMM24,%ZMM29,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1
VMOVUPS (%R8,%R11,1),%ZMM13{%K1}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
ADD $0x40,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VCVTPS2PD %YMM0,%ZMM6	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VEXTRACTF32X8 $0x1,%ZMM0,%YMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50
VMOVAPS %ZMM29,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PS %ZMM22,%ZMM21,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VCVTPS2PD %YMM5,%ZMM5	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VMOVAPS %ZMM13,%ZMM28{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PS %ZMM29,%ZMM20,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VSQRTPD %ZMM6,%ZMM30	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMULPD %ZMM30,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM5,%ZMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMULPD %ZMM31,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD132PS %ZMM29,%ZMM19,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VDIVPD %ZMM6,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9
VFMADD132PS %ZMM29,%ZMM18,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD132PS %ZMM29,%ZMM17,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VDIVPD %ZMM5,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9
VCVTPS2PD %YMM0,%ZMM29	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VEXTRACTF32X8 $0x1,%ZMM0,%YMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50
VCVTPS2PD %YMM0,%ZMM0	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VADDPD %ZMM29,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VCVTPD2PS %ZMM6,%YMM6	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33
VADDPD %ZMM0,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VCVTPD2PS %ZMM5,%YMM0	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33
VINSERTF64X4 $0x1,%YMM0,%ZMM6,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1
VMULPS %ZMM28,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPS %ZMM6,%ZMM9,%ZMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPS %ZMM6,%ZMM8,%ZMM9{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPS %ZMM6,%ZMM7,%ZMM8{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPS %ZMM0,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VADDPS %ZMM9,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VADDPS %ZMM8,%ZMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
CMP %R11,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 4016f0 <Step10_orig+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	Step10_orig
Source file and lines	Step10_orig.c:19-31
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 92% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
If you accept to loose numerical precision up to 2 ulp, you can speedup your code by passing the following options to your compiler: (ffast-math or Ofast) and mrecip

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 20.50 cycles (2.44x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPD2PS: 2 occurrences
VCVTPS2PD: 4 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 480 FP arithmetical operations:

240: addition or subtraction (112 inside FMA instructions)
208: multiply (112 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 256 bytes (64 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.87 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	52
loop length	286
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	27
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	11.00	11.00	11.00	11.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	21.00	19.00	15.50	15.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	8.67
Dispatch	21.00
DIV/SQRT	50.00
Data deps.	3.00
Overall L1	50.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	92%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	73%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4016f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
VMOVUPS (%RDX,%R11,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPS (%RSI,%R11,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPS (%RCX,%R11,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VSUBPS %ZMM26,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VSUBPS %ZMM27,%ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VSUBPS %ZMM25,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VMULPS %ZMM8,%ZMM8,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PS %ZMM9,%ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD231PS %ZMM7,%ZMM7,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VADDPS %ZMM23,%ZMM29,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VCMPPS $0xe,%ZMM16,%ZMM29,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1
VCMPPS $0x1,%ZMM24,%ZMM29,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1
VMOVUPS (%R8,%R11,1),%ZMM13{%K1}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
ADD $0x40,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VCVTPS2PD %YMM0,%ZMM6	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VEXTRACTF32X8 $0x1,%ZMM0,%YMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50
VMOVAPS %ZMM29,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PS %ZMM22,%ZMM21,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VCVTPS2PD %YMM5,%ZMM5	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VMOVAPS %ZMM13,%ZMM28{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PS %ZMM29,%ZMM20,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VSQRTPD %ZMM6,%ZMM30	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMULPD %ZMM30,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSQRTPD %ZMM5,%ZMM31	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	21	16
VMULPD %ZMM31,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD132PS %ZMM29,%ZMM19,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VDIVPD %ZMM6,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9
VFMADD132PS %ZMM29,%ZMM18,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD132PS %ZMM29,%ZMM17,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VDIVPD %ZMM5,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	13	9
VCVTPS2PD %YMM0,%ZMM29	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VEXTRACTF32X8 $0x1,%ZMM0,%YMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50
VCVTPS2PD %YMM0,%ZMM0	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	6	1.33
VADDPD %ZMM29,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VCVTPD2PS %ZMM6,%YMM6	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33
VADDPD %ZMM0,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VCVTPD2PS %ZMM5,%YMM0	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	7	1.33
VINSERTF64X4 $0x1,%YMM0,%ZMM6,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1
VMULPS %ZMM28,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPS %ZMM6,%ZMM9,%ZMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPS %ZMM6,%ZMM8,%ZMM9{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPS %ZMM6,%ZMM7,%ZMM8{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPS %ZMM0,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VADDPS %ZMM9,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
VADDPS %ZMM8,%ZMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1
CMP %R11,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 4016f0 <Step10_orig+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable> MPI Command: mpirun -np <number_processes> -ppn <number_processes_per_node>Dataset: Run Directory: /home/eoseret/tst_HACCmkI_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 1x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x128	OMP_NUM_THREADS: 128I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 1x192	OMP_NUM_THREADS: 192I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	1	0.15	1	0.13	1	0.35	0.99	1.29	0.97	2.5	0.91	5.77	0.86	7.47	0.76	10.2

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	661.1	99.87
1x2	2	1	2	2	331.1	98.63
1x4	4	1	3.99	4	165.68	97.2
1x8	8	1	7.97	8	83.25	94.61
1x16	16	0.99	15.77	16	42.28	89.83
1x32	32	0.97	30.99	32	22.12	79.44
1x64	64	0.91	58.56	64	11.96	67.81
1x128	128	0.86	109.45	128	6.67	51.57
1x192	192	0.76	146.59	192	5.16	43.11

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency