OV - exec - Loop 3

	Loop Id: 3	Module: exec	Source: Step10_orig.c:19-35 [...]	Coverage: 0.17%

0x2025a0 VMOVSHDUP	%XMM8,%XMM14

0x2025a5 VMOVSS	(%RCX),%XMM0

0x2025a9 LEA	0x1(%RAX),%R9

0x2025ad CMP	%RSI,%RAX

0x2025b0 VFMADD213SS	0x38c0e0(,%RAX,4),%XMM0,%XMM14

0x2025ba VFMADD213SS	0x3edb60(,%RAX,4),%XMM0,%XMM8

0x2025c4 VFMADD213SS	0x44f5e0(,%RAX,4),%XMM0,%XMM9

0x2025ce VMOVSS	%XMM14,0x38c0e0(,%RAX,4)

0x2025d7 VMOVSS	%XMM8,0x3edb60(,%RAX,4)

0x2025e0 VMOVSS	%XMM9,0x44f5e0(,%RAX,4)

0x2025e9 MOV	%R9,%RAX

0x2025ec JGE	202507

0x2025f2 VXORPS	%XMM14,%XMM14,%XMM14

0x2025f7 VXORPS	%XMM8,%XMM8,%XMM8

0x2025fc VXORPS	%XMM9,%XMM9,%XMM9

0x202601 TEST	%EDX,%EDX

0x202603 JLE	2025a5

0x202605 VMOVSS	0x2056e0(,%RAX,4),%XMM17

0x202610 VMOVSS	0x267160(,%RAX,4),%XMM30

0x20261b VMOVSS	0x2c8be0(,%RAX,4),%XMM11

0x202624 VMOVSS	(%R14),%XMM12

0x202629 VMOVSS	(%RBX),%XMM13

0x20262d CMP	$0x4,%EDX

0x202630 JAE	202640

0x202632 VXORPS	%XMM8,%XMM8,%XMM8

0x202637 XOR	%R9D,%R9D

0x20263a JMP	202b90

0x202640 CMP	$0x10,%EDX

0x202643 JAE	20264d

0x202645 XOR	%R9D,%R9D

0x202648 JMP	2029ec

0x20264d VBROADCASTSS	%XMM17,%YMM8

0x202653 VBROADCASTSS	%XMM30,%YMM19

0x202659 VBROADCASTSS	%XMM11,%YMM21

0x20265f VBROADCASTSS	%XMM12,%YMM14

0x202664 VBROADCASTSS	%XMM13,%YMM23

0x20266a MOV	%EDX,%R9D

0x20266d AND	$-0x10,%R9D

0x202671 VXORPS	%XMM16,%XMM16,%XMM16

0x202677 VXORPS	%XMM9,%XMM9,%XMM9

0x20267c VXORPS	%XMM18,%XMM18,%XMM18

0x202682 VXORPS	%XMM20,%XMM20,%XMM20

0x202688 VXORPS	%XMM24,%XMM24,%XMM24

0x20268e VXORPS	%XMM25,%XMM25,%XMM25

0x202694 XOR	%R10D,%R10D

0x202697 VMOVAPS	%XMM17,-0x60(%RBP)

0x20269e VMOVAPS	%XMM30,-0x50(%RBP)

0x2026a5 JMP	2027ec

  (6) 0x2026b0 VPCMPEQD	%YMM17,%YMM2,%K1

  (6) 0x2026b6 VBROADCASTSS	-0x1dd3(%RIP),%YMM7

  (6) 0x2026bf VADDPS	%YMM23,%YMM15,%YMM5

  (6) 0x2026c5 VADDPS	%YMM23,%YMM0,%YMM1

  (6) 0x2026cb VCMPPS	$0x1,%YMM0,%YMM10,%K2

  (6) 0x2026d2 ADD	$0x40,%R10

  (6) 0x2026d6 VMOVAPS	%YMM4,%YMM2{%K1}{z}

  (6) 0x2026dc VPCMPEQD	%YMM17,%YMM3,%K1

  (6) 0x2026e2 VBROADCASTSS	-0x1e0b(%RIP),%YMM4

  (6) 0x2026eb VBROADCASTSS	-0x1e0d(%RIP),%YMM17

  (6) 0x2026f5 VBROADCASTSD	-0x1d37(%RIP),%ZMM3

  (6) 0x2026ff VMOVAPS	%YMM22,%YMM22{%K1}{z}

  (6) 0x202705 VCMPPS	$0x1,%YMM15,%YMM10,%K1

  (6) 0x20270c VCVTPS2PD	%YMM5,%ZMM5

  (6) 0x202712 VCVTPS2PD	%YMM1,%ZMM1

  (6) 0x202718 VMOVAPS	%YMM4,%YMM6

  (6) 0x20271c VFMSUB213PS	%YMM17,%YMM15,%YMM6

  (6) 0x202722 VFMSUB213PS	%YMM17,%YMM0,%YMM4

  (6) 0x202728 VSQRTPD	%ZMM5,%ZMM17

  (6) 0x20272e VMULPD	%ZMM5,%ZMM5,%ZMM5

  (6) 0x202734 VDIVPD	%ZMM5,%ZMM3,%ZMM5

  (6) 0x20273a VFMSUB213PS	%YMM7,%YMM15,%YMM6

  (6) 0x20273f VFMSUB213PS	%YMM7,%YMM0,%YMM4

  (6) 0x202744 VBROADCASTSS	-0x1e75(%RIP),%YMM7

  (6) 0x20274d VFMSUB213PS	%YMM7,%YMM15,%YMM6

  (6) 0x202752 VFMSUB213PS	%YMM7,%YMM0,%YMM4

  (6) 0x202757 VBROADCASTSS	-0x1e98(%RIP),%YMM7

  (6) 0x202760 VFMSUB213PS	%YMM7,%YMM15,%YMM6

  (6) 0x202765 VFMSUB213PS	%YMM7,%YMM0,%YMM4

  (6) 0x20276a VBROADCASTSS	-0x1e97(%RIP),%YMM7

  (6) 0x202773 VFNMADD213PS	%YMM7,%YMM15,%YMM6

  (6) 0x202778 VFNMADD213PS	%YMM7,%YMM0,%YMM4

  (6) 0x20277d VSQRTPD	%ZMM1,%ZMM7

  (6) 0x202783 VMULPD	%ZMM1,%ZMM1,%ZMM1

  (6) 0x202789 VDIVPD	%ZMM1,%ZMM3,%ZMM1

  (6) 0x20278f VCVTPS2PD	%YMM6,%ZMM6

  (6) 0x202795 VCVTPS2PD	%YMM4,%ZMM4

  (6) 0x20279b VFMSUB231PD	%ZMM5,%ZMM17,%ZMM6

  (6) 0x2027a1 VCVTPD2PS	%ZMM6,%YMM5

  (6) 0x2027a7 VMULPS	%YMM5,%YMM2,%YMM0{%K1}{z}

  (6) 0x2027ad VFMSUB231PD	%ZMM1,%ZMM7,%ZMM4

  (6) 0x2027b3 VFMADD231PS	%YMM29,%YMM0,%YMM24

  (6) 0x2027b9 VFMADD231PS	%YMM30,%YMM0,%YMM18

  (6) 0x2027bf VFMADD231PS	%YMM31,%YMM0,%YMM16

  (6) 0x2027c5 VCVTPD2PS	%ZMM4,%YMM1

  (6) 0x2027cb VMULPS	%YMM1,%YMM22,%YMM1{%K2}{z}

  (6) 0x2027d1 VFMADD231PS	%YMM26,%YMM1,%YMM25

  (6) 0x2027d7 VFMADD231PS	%YMM27,%YMM1,%YMM20

  (6) 0x2027dd VFMADD231PS	%YMM28,%YMM1,%YMM9

  (6) 0x2027e3 CMP	%R10,%RDI

  (6) 0x2027e6 JE	2028cd

  (6) 0x2027ec VMOVUPS	0x2056e0(%R10),%YMM0

  (6) 0x2027f5 VMOVUPS	0x205700(%R10),%YMM2

  (6) 0x2027fe VBROADCASTSS	-0x1f44(%RIP),%YMM17

  (6) 0x202808 VSUBPS	%YMM8,%YMM0,%YMM29

  (6) 0x20280e VMOVUPS	0x267160(%R10),%YMM0

  (6) 0x202817 VSUBPS	%YMM8,%YMM2,%YMM26

  (6) 0x20281d VMOVUPS	0x267180(%R10),%YMM2

  (6) 0x202826 VMULPS	%YMM29,%YMM29,%YMM15

  (6) 0x20282c VSUBPS	%YMM19,%YMM0,%YMM30

  (6) 0x202832 VMOVUPS	0x2c8be0(%R10),%YMM0

  (6) 0x20283b VSUBPS	%YMM19,%YMM2,%YMM27

  (6) 0x202841 VMOVUPS	0x2c8c00(%R10),%YMM2

  (6) 0x20284a VFMADD231PS	%YMM30,%YMM30,%YMM15

  (6) 0x202850 VSUBPS	%YMM21,%YMM0,%YMM31

  (6) 0x202856 VMULPS	%YMM26,%YMM26,%YMM0

  (6) 0x20285c VSUBPS	%YMM21,%YMM2,%YMM28

  (6) 0x202862 VFMADD231PS	%YMM27,%YMM27,%YMM0

  (6) 0x202868 VFMADD231PS	%YMM31,%YMM31,%YMM15

  (6) 0x20286e VFMADD231PS	%YMM28,%YMM28,%YMM0

  (6) 0x202874 VCMPPS	$0x1,%YMM14,%YMM15,%K0

  (6) 0x20287b VCMPPS	$0x1,%YMM14,%YMM15,%YMM2

  (6) 0x202881 VANDPS	%YMM17,%YMM2,%YMM2

  (6) 0x202887 VCMPPS	$0x1,%YMM14,%YMM0,%K1

  (6) 0x20288e VCMPPS	$0x1,%YMM14,%YMM0,%YMM3

  (6) 0x202894 KUNPCKBW	%K0,%K1,%K0

  (6) 0x202898 VANDPS	%YMM17,%YMM3,%YMM3

  (6) 0x20289e KORTESTW	%K0,%K0

  (6) 0x2028a2 JE	2026b0

  (6) 0x2028a8 VPCMPEQD	%YMM17,%YMM2,%K1

  (6) 0x2028ae VMOVUPS	0x32a660(%R10),%YMM4{%K1}{z}

  (6) 0x2028b8 VPCMPEQD	%YMM17,%YMM3,%K1

  (6) 0x2028be VMOVUPS	0x32a680(%R10),%YMM22{%K1}{z}

  (6) 0x2028c8 JMP	2026b0

0x2028cd VADDPS	%YMM24,%YMM25,%YMM0

0x2028d3 VEXTRACTF128	$0x1,%YMM0,%XMM2

0x2028d9 VADDPS	%XMM2,%XMM0,%XMM0

0x2028dd VPERMILPD	$0x1,%XMM0,%XMM2

0x2028e3 VADDPS	%XMM2,%XMM0,%XMM0

0x2028e7 VMOVSHDUP	%XMM0,%XMM2

0x2028eb VADDSS	%XMM2,%XMM0,%XMM14

0x2028ef VADDPS	%YMM18,%YMM20,%YMM0

0x2028f5 VEXTRACTF128	$0x1,%YMM0,%XMM2

0x2028fb VADDPS	%XMM2,%XMM0,%XMM0

0x2028ff VPERMILPD	$0x1,%XMM0,%XMM2

0x202905 VADDPS	%XMM2,%XMM0,%XMM0

0x202909 VMOVSHDUP	%XMM0,%XMM2

0x20290d VADDSS	%XMM2,%XMM0,%XMM8

0x202911 VADDPS	%YMM16,%YMM9,%YMM0

0x202917 VEXTRACTF128	$0x1,%YMM0,%XMM2

0x20291d VADDPS	%XMM2,%XMM0,%XMM0

0x202921 VPERMILPD	$0x1,%XMM0,%XMM2

0x202927 VADDPS	%XMM2,%XMM0,%XMM0

0x20292b VMOVSHDUP	%XMM0,%XMM2

0x20292f VADDSS	%XMM2,%XMM0,%XMM9

0x202933 CMP	%RDX,%R9

0x202936 JNE	202989

0x202938 VMOVSD	-0x1f78(%RIP),%XMM5

0x202940 VMOVSS	-0x2068(%RIP),%XMM6

0x202948 VMOVSS	-0x2084(%RIP),%XMM7

0x202950 VMOVSS	-0x205a(%RIP),%XMM22

0x20295a VMOVSS	-0x2070(%RIP),%XMM25

0x202964 VMOVSS	-0x208a(%RIP),%XMM26

0x20296e VMOVSS	-0x2068(%RIP),%XMM27

0x202978 VXORPS	%XMM28,%XMM28,%XMM28

0x20297e VXORPS	%XMM29,%XMM29,%XMM29

0x202984 JMP	2025a5

0x202989 VMOVSD	-0x1fc9(%RIP),%XMM5

0x202991 VMOVSS	-0x20b9(%RIP),%XMM6

0x202999 VMOVSS	-0x20d5(%RIP),%XMM7

0x2029a1 VMOVSS	-0x20ab(%RIP),%XMM22

0x2029ab VMOVSS	-0x20c1(%RIP),%XMM25

0x2029b5 VMOVSS	-0x20db(%RIP),%XMM26

0x2029bf VMOVSS	-0x20b9(%RIP),%XMM27

0x2029c9 VXORPS	%XMM28,%XMM28,%XMM28

0x2029cf VXORPS	%XMM29,%XMM29,%XMM29

0x2029d5 TEST	$0xc,%DL

0x2029d8 JE	202b77

0x2029de VMOVAPS	-0x60(%RBP),%XMM17

0x2029e5 VMOVAPS	-0x50(%RBP),%XMM30

0x2029ec VXORPS	%XMM0,%XMM0,%XMM0

0x2029f0 VBLENDPS	$0x1,%XMM9,%XMM0,%XMM9

0x2029f6 VBLENDPS	$0x1,%XMM8,%XMM0,%XMM8

0x2029fc VBLENDPS	$0x1,%XMM14,%XMM0,%XMM0

0x202a02 VBROADCASTSS	%XMM17,%XMM14

0x202a08 VBROADCASTSS	%XMM30,%XMM15

0x202a0e VBROADCASTSS	%XMM11,%XMM16

0x202a14 VBROADCASTSS	%XMM12,%XMM18

0x202a1a VBROADCASTSS	%XMM13,%XMM19

0x202a20 MOV	%R9,%R10

0x202a23 MOV	%EDX,%R9D

0x202a26 AND	$-0x4,%R9D

0x202a2a JMP	202ac4

  (5) 0x202a30 VADDPS	%XMM19,%XMM24,%XMM1

  (5) 0x202a36 VBROADCASTSD	-0x2077(%RIP),%YMM3

  (5) 0x202a3f VMOVAPS	%XMM2,%XMM2{%K1}{z}

  (5) 0x202a45 VCMPPS	$0x1,%XMM24,%XMM29,%K1

  (5) 0x202a4c MOV	%R11,%R10

  (5) 0x202a4f VCVTPS2PD	%XMM1,%YMM1

  (5) 0x202a53 VMULPD	%YMM1,%YMM1,%YMM4

  (5) 0x202a57 VSQRTPD	%YMM1,%YMM1

  (5) 0x202a5b VDIVPD	%YMM4,%YMM3,%YMM3

  (5) 0x202a5f VBROADCASTSS	-0x2188(%RIP),%XMM4

  (5) 0x202a68 VFMADD213PS	-0x21a6(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a72 VFMADD213PS	-0x217c(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a7c VFMADD213PS	-0x2192(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a86 VFMADD213PS	-0x21ac(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a90 VFMADD213PS	-0x218a(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a9a VCVTPS2PD	%XMM4,%YMM4

  (5) 0x202a9e VFMADD231PD	%YMM3,%YMM1,%YMM4

  (5) 0x202aa3 VCVTPD2PS	%YMM4,%XMM1

  (5) 0x202aa7 VMULPS	%XMM1,%XMM2,%XMM1{%K1}{z}

  (5) 0x202aad VFMADD231PS	%XMM20,%XMM1,%XMM0

  (5) 0x202ab3 VFMADD231PS	%XMM21,%XMM1,%XMM8

  (5) 0x202ab9 VFMADD231PS	%XMM23,%XMM1,%XMM9

  (5) 0x202abf CMP	%R11,%R8

  (5) 0x202ac2 JE	202b30

  (5) 0x202ac4 VMOVAPS	0x2056e0(,%R10,4),%XMM2

  (5) 0x202ace LEA	0x4(%R10),%R11

  (5) 0x202ad2 VSUBPS	%XMM14,%XMM2,%XMM20

  (5) 0x202ad8 VMOVAPS	0x267160(,%R10,4),%XMM2

  (5) 0x202ae2 VMULPS	%XMM20,%XMM20,%XMM24

  (5) 0x202ae8 VSUBPS	%XMM15,%XMM2,%XMM21

  (5) 0x202aee VMOVAPS	0x2c8be0(,%R10,4),%XMM2

  (5) 0x202af8 VFMADD231PS	%XMM21,%XMM21,%XMM24

  (5) 0x202afe VSUBPS	%XMM16,%XMM2,%XMM23

  (5) 0x202b04 VFMADD231PS	%XMM23,%XMM23,%XMM24

  (5) 0x202b0a VCMPPS	$0x1,%XMM18,%XMM24,%K1

  (5) 0x202b11 KORTESTB	%K1,%K1

  (5) 0x202b15 JE	202a30

  (5) 0x202b1b VMOVUPS	0x32a660(,%R10,4),%XMM2{%K1}{z}

  (5) 0x202b26 JMP	202a30

0x202b30 VPERMILPD	$0x1,%XMM0,%XMM2

0x202b36 VADDPS	%XMM2,%XMM0,%XMM0

0x202b3a VMOVSHDUP	%XMM0,%XMM2

0x202b3e VADDPS	%XMM2,%XMM0,%XMM14

0x202b42 VPERMILPD	$0x1,%XMM8,%XMM0

0x202b48 VADDPS	%XMM0,%XMM8,%XMM0

0x202b4c VMOVSHDUP	%XMM0,%XMM2

0x202b50 VADDPS	%XMM2,%XMM0,%XMM8

0x202b54 VPERMILPD	$0x1,%XMM9,%XMM0

0x202b5a VADDPS	%XMM0,%XMM9,%XMM0

0x202b5e VMOVSHDUP	%XMM0,%XMM2

0x202b62 VADDSS	%XMM2,%XMM0,%XMM9

0x202b66 CMP	%RDX,%R9

0x202b69 JE	2025a5

0x202b6f VINSERTPS	$0x1c,%XMM14,%XMM8,%XMM8

0x202b75 JMP	202b90

0x202b77 VMOVAPS	-0x60(%RBP),%XMM17

0x202b7e VMOVAPS	-0x50(%RBP),%XMM30

0x202b85 VINSERTPS	$0x10,%XMM14,%XMM8,%XMM8

0x202b8b NOPL	(%RAX,%RAX,1)

0x202b90 VINSERTPS	$0x10,%XMM17,%XMM30,%XMM0

0x202b97 JMP	202c13

  (4) 0x202ba0 VADDSS	%XMM13,%XMM16,%XMM2

  (4) 0x202ba6 VMOVAPS	%XMM6,%XMM4

  (4) 0x202baa VFMADD213SS	%XMM7,%XMM16,%XMM4

  (4) 0x202bb0 VCMPSS	$0x1,%XMM16,%XMM28,%K1

  (4) 0x202bb7 INC	%R9

  (4) 0x202bba VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (4) 0x202bbe VFMADD213SS	%XMM22,%XMM16,%XMM4

  (4) 0x202bc4 VSQRTSD	%XMM2,%XMM2,%XMM3

  (4) 0x202bc8 VMULSD	%XMM2,%XMM2,%XMM2

  (4) 0x202bcc VFMADD213SS	%XMM25,%XMM16,%XMM4

  (4) 0x202bd2 VDIVSD	%XMM2,%XMM5,%XMM2

  (4) 0x202bd6 VFMADD213SS	%XMM26,%XMM16,%XMM4

  (4) 0x202bdc VFMADD213SS	%XMM27,%XMM16,%XMM4

  (4) 0x202be2 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (4) 0x202be6 VFMADD231SD	%XMM2,%XMM3,%XMM4

  (4) 0x202beb VCVTSD2SS	%XMM4,%XMM4,%XMM2

  (4) 0x202bef VMULSS	%XMM2,%XMM17,%XMM2

  (4) 0x202bf5 VMOVSS	%XMM2,%XMM2,%XMM2{%K1}{z}

  (4) 0x202bfb VBROADCASTSS	%XMM2,%XMM3

  (4) 0x202c00 VFMADD231SS	%XMM15,%XMM2,%XMM9

  (4) 0x202c05 VFMADD231PS	%XMM14,%XMM3,%XMM8

  (4) 0x202c0a CMP	%R9,%RDX

  (4) 0x202c0d JE	2025a0

  (4) 0x202c13 VMOVSS	0x267160(,%R9,4),%XMM2

  (4) 0x202c1d VXORPS	%XMM17,%XMM17,%XMM17

  (4) 0x202c23 VINSERTPS	$0x10,0x2056e0(,%R9,4),%XMM2,%XMM2

  (4) 0x202c2e VSUBPS	%XMM0,%XMM2,%XMM14

  (4) 0x202c32 VMOVSS	0x2c8be0(,%R9,4),%XMM2

  (4) 0x202c3c VSUBSS	%XMM11,%XMM2,%XMM15

  (4) 0x202c41 VMULPS	%XMM14,%XMM14,%XMM2

  (4) 0x202c46 VMOVSHDUP	%XMM2,%XMM3

  (4) 0x202c4a VADDSS	%XMM3,%XMM2,%XMM16

  (4) 0x202c50 VFMADD231SS	%XMM15,%XMM15,%XMM16

  (4) 0x202c56 VUCOMISS	%XMM12,%XMM16

  (4) 0x202c5c JAE	202ba0

  (4) 0x202c62 VMOVSS	0x32a660(,%R9,4),%XMM17

  (4) 0x202c6d JMP	202ba0

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 140 - 146

--------------------------------------------------------------------------------

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►99.82+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.21
CQA speedup if FP arith vectorized	1.86
CQA speedup if fully vectorized	4.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	.omp_outlined..6
Source	main.c:140-140,main.c:144-146,Step10_orig.c:19-21
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.33
CQA cycles if no scalar integer	17.67
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	4.79
Front-end cycles	21.33
P0 cycles	7.00
P1 cycles	3.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	7.00
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	10.67
P8 cycles	7.50
P9 cycles	15.17
P10 cycles	15.17
P11 cycles	15.17
P12 cycles	2.50
P13 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	128.00
Nb loads	27.00
Nb stores	5.00
Nb stack references	2.00
FLOP/cycle	3.66
Nb FLOP add-sub	72.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.75
Bytes prefetched	0.00
Bytes loaded	164.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	51.92
Vectorization ratio load	14.81
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	77.78
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	62.96
Vector-efficiency ratio all	16.17
Vector-efficiency ratio load	9.49
Vector-efficiency ratio store	13.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.78

Metric	Value
CQA speedup if no scalar integer	1.21
CQA speedup if FP arith vectorized	1.86
CQA speedup if fully vectorized	4.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	.omp_outlined..6
Source	main.c:140-140,main.c:144-146,Step10_orig.c:19-21
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.33
CQA cycles if no scalar integer	17.67
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	4.79
Front-end cycles	21.33
P0 cycles	7.00
P1 cycles	3.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	7.00
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	10.67
P8 cycles	7.50
P9 cycles	15.17
P10 cycles	15.17
P11 cycles	15.17
P12 cycles	2.50
P13 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	128.00
Nb loads	27.00
Nb stores	5.00
Nb stack references	2.00
FLOP/cycle	3.66
Nb FLOP add-sub	72.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.75
Bytes prefetched	0.00
Bytes loaded	164.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	51.92
Vectorization ratio load	14.81
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	77.78
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	62.96
Vector-efficiency ratio all	16.17
Vector-efficiency ratio load	9.49
Vector-efficiency ratio store	13.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.78

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..6
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:140-146
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=27
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 27 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.33 to 17.67 cycles (1.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
77% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
62% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 3 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 3 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 11 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 3 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 78 FP arithmetical operations:

75: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 164 bytes (41 single precision FP elements). The binary loop is storing 44 bytes (11 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	128
loop length	724
used x86 registers	9
used mmx registers	0
used xmm registers	25
used ymm registers	12
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.33 cycles
front end	21.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	3.50	3.25	3.25	7.00	10.67	10.67	10.67	7.50	15.17	15.17	15.17	2.50	2.50
cycles	7.00	3.50	3.25	3.25	7.00	10.67	10.67	10.67	7.50	15.17	15.17	15.17	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.33
Dispatch	15.17
Overall L1	21.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	55%
load	14%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	77%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	72%

INT+FP

all	51%
load	14%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	77%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	16%
load	9%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	16%
load	9%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.33 cycles. At this rate:

8% of peak load performance is reached (7.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.06 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.33 to 15.17 cycles (1.41x speedup).

ASM code

In the binary file, the address of the loop is: 2025f2

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVSHDUP %XMM8,%XMM14	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VMOVSS (%RCX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RAX),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
VFMADD213SS 0x38c0e0(,%RAX,4),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x3edb60(,%RAX,4),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x44f5e0(,%RAX,4),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM14,0x38c0e0(,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM8,0x3edb60(,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM9,0x44f5e0(,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JGE 202507 <.omp_outlined..6+0x87>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPS %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 2025a5 <.omp_outlined..6+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSS 0x2056e0(,%RAX,4),%XMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x267160(,%RAX,4),%XMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x2c8be0(,%RAX,4),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%R14),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%RBX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
CMP $0x4,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JAE 202640 <.omp_outlined..6+0x1c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPS %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 202b90 <.omp_outlined..6+0x710>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x10,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JAE 20264d <.omp_outlined..6+0x1cd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2029ec <.omp_outlined..6+0x56c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSS %XMM17,%YMM8	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM30,%YMM19	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM11,%YMM21	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM12,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM13,%YMM23	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPS %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVAPS %XMM17,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVAPS %XMM30,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
JMP 2027ec <.omp_outlined..6+0x36c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDPS %YMM24,%YMM25,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
VADDPS %YMM18,%YMM20,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
VADDPS %YMM16,%YMM9,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
CMP %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 202989 <.omp_outlined..6+0x509>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x1f78(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x2068(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x2084(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x205a(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x2070(%RIP),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x208a(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x2068(%RIP),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 2025a5 <.omp_outlined..6+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD -0x1fc9(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x20b9(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20d5(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20ab(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20c1(%RIP),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20db(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20b9(%RIP),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
TEST $0xc,%DL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 202b77 <.omp_outlined..6+0x6f7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPS -0x60(%RBP),%XMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS -0x50(%RBP),%XMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VBLENDPS $0x1,%XMM9,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM8,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM14,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBROADCASTSS %XMM17,%XMM14	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM30,%XMM15	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM11,%XMM16	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM12,%XMM18	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM13,%XMM19	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 202ac4 <.omp_outlined..6+0x644>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDPS %XMM2,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM0,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDPS %XMM2,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM0,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
CMP %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 2025a5 <.omp_outlined..6+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VINSERTPS $0x1c,%XMM14,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
JMP 202b90 <.omp_outlined..6+0x710>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS -0x60(%RBP),%XMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS -0x50(%RBP),%XMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM14,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VINSERTPS $0x10,%XMM17,%XMM30,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
JMP 202c13 <.omp_outlined..6+0x793>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	.omp_outlined..6
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:140-146
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=27
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
77% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
62% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 3 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 3 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 78 FP arithmetical operations:

75: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 164 bytes (41 single precision FP elements). The binary loop is storing 44 bytes (11 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	128
loop length	724
used x86 registers	9
used mmx registers	0
used xmm registers	25
used ymm registers	12
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.33 cycles
front end	21.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	3.50	3.25	3.25	7.00	10.67	10.67	10.67	7.50	15.17	15.17	15.17	2.50	2.50
cycles	7.00	3.50	3.25	3.25	7.00	10.67	10.67	10.67	7.50	15.17	15.17	15.17	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.33
Dispatch	15.17
Overall L1	21.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	55%
load	14%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	77%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	72%

INT+FP

all	51%
load	14%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	77%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	16%
load	9%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	16%
load	9%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.33 cycles. At this rate:

8% of peak load performance is reached (7.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.06 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 2025f2

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVSHDUP %XMM8,%XMM14	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VMOVSS (%RCX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RAX),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
VFMADD213SS 0x38c0e0(,%RAX,4),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x3edb60(,%RAX,4),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x44f5e0(,%RAX,4),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM14,0x38c0e0(,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM8,0x3edb60(,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM9,0x44f5e0(,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JGE 202507 <.omp_outlined..6+0x87>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPS %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 2025a5 <.omp_outlined..6+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSS 0x2056e0(,%RAX,4),%XMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x267160(,%RAX,4),%XMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x2c8be0(,%RAX,4),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%R14),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%RBX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
CMP $0x4,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JAE 202640 <.omp_outlined..6+0x1c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPS %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 202b90 <.omp_outlined..6+0x710>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x10,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JAE 20264d <.omp_outlined..6+0x1cd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2029ec <.omp_outlined..6+0x56c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSS %XMM17,%YMM8	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM30,%YMM19	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM11,%YMM21	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM12,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VBROADCASTSS %XMM13,%YMM23	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPS %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVAPS %XMM17,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVAPS %XMM30,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
JMP 2027ec <.omp_outlined..6+0x36c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDPS %YMM24,%YMM25,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
VADDPS %YMM18,%YMM20,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
VADDPS %YMM16,%YMM9,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
CMP %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 202989 <.omp_outlined..6+0x509>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x1f78(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x2068(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x2084(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x205a(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x2070(%RIP),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x208a(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x2068(%RIP),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 2025a5 <.omp_outlined..6+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD -0x1fc9(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x20b9(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20d5(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20ab(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20c1(%RIP),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20db(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x20b9(%RIP),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
TEST $0xc,%DL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 202b77 <.omp_outlined..6+0x6f7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPS -0x60(%RBP),%XMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS -0x50(%RBP),%XMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VBLENDPS $0x1,%XMM9,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM8,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM14,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBROADCASTSS %XMM17,%XMM14	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM30,%XMM15	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM11,%XMM16	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM12,%XMM18	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
VBROADCASTSS %XMM13,%XMM19	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 202ac4 <.omp_outlined..6+0x644>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VPERMILPD $0x1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDPS %XMM2,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM0,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDPS %XMM2,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VPERMILPD $0x1,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (25.0%)
VADDPS %XMM0,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	vect (12.5%)
VADDSS %XMM2,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (6.3%)
CMP %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 2025a5 <.omp_outlined..6+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VINSERTPS $0x1c,%XMM14,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
JMP 202b90 <.omp_outlined..6+0x710>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS -0x60(%RBP),%XMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS -0x50(%RBP),%XMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM14,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VINSERTPS $0x10,%XMM17,%XMM30,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33	scal (6.3%)
JMP 202c13 <.omp_outlined..6+0x793>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code