OV - exec - Loop 6

	Loop Id: 6	Module: exec	Source: Step10_orig.c:19-35	Coverage: 47.76%

0x2026b0 VPCMPEQD	%YMM17,%YMM2,%K1

0x2026b6 VBROADCASTSS	-0x1dd3(%RIP),%YMM7    [2]

0x2026bf VADDPS	%YMM23,%YMM15,%YMM5

0x2026c5 VADDPS	%YMM23,%YMM0,%YMM1

0x2026cb VCMPPS	$0x1,%YMM0,%YMM10,%K2

0x2026d2 ADD	$0x40,%R10

0x2026d6 VMOVAPS	%YMM4,%YMM2{%K1}{z}

0x2026dc VPCMPEQD	%YMM17,%YMM3,%K1

0x2026e2 VBROADCASTSS	-0x1e0b(%RIP),%YMM4    [2]

0x2026eb VBROADCASTSS	-0x1e0d(%RIP),%YMM17    [2]

0x2026f5 VBROADCASTSD	-0x1d37(%RIP),%ZMM3    [2]

0x2026ff VMOVAPS	%YMM22,%YMM22{%K1}{z}

0x202705 VCMPPS	$0x1,%YMM15,%YMM10,%K1

0x20270c VCVTPS2PD	%YMM5,%ZMM5

0x202712 VCVTPS2PD	%YMM1,%ZMM1

0x202718 VMOVAPS	%YMM4,%YMM6

0x20271c VFMSUB213PS	%YMM17,%YMM15,%YMM6

0x202722 VFMSUB213PS	%YMM17,%YMM0,%YMM4

0x202728 VSQRTPD	%ZMM5,%ZMM17

0x20272e VMULPD	%ZMM5,%ZMM5,%ZMM5

0x202734 VDIVPD	%ZMM5,%ZMM3,%ZMM5

0x20273a VFMSUB213PS	%YMM7,%YMM15,%YMM6

0x20273f VFMSUB213PS	%YMM7,%YMM0,%YMM4

0x202744 VBROADCASTSS	-0x1e75(%RIP),%YMM7    [2]

0x20274d VFMSUB213PS	%YMM7,%YMM15,%YMM6

0x202752 VFMSUB213PS	%YMM7,%YMM0,%YMM4

0x202757 VBROADCASTSS	-0x1e98(%RIP),%YMM7    [2]

0x202760 VFMSUB213PS	%YMM7,%YMM15,%YMM6

0x202765 VFMSUB213PS	%YMM7,%YMM0,%YMM4

0x20276a VBROADCASTSS	-0x1e97(%RIP),%YMM7    [2]

0x202773 VFNMADD213PS	%YMM7,%YMM15,%YMM6

0x202778 VFNMADD213PS	%YMM7,%YMM0,%YMM4

0x20277d VSQRTPD	%ZMM1,%ZMM7

0x202783 VMULPD	%ZMM1,%ZMM1,%ZMM1

0x202789 VDIVPD	%ZMM1,%ZMM3,%ZMM1

0x20278f VCVTPS2PD	%YMM6,%ZMM6

0x202795 VCVTPS2PD	%YMM4,%ZMM4

0x20279b VFMSUB231PD	%ZMM5,%ZMM17,%ZMM6

0x2027a1 VCVTPD2PS	%ZMM6,%YMM5

0x2027a7 VMULPS	%YMM5,%YMM2,%YMM0{%K1}{z}

0x2027ad VFMSUB231PD	%ZMM1,%ZMM7,%ZMM4

0x2027b3 VFMADD231PS	%YMM29,%YMM0,%YMM24

0x2027b9 VFMADD231PS	%YMM30,%YMM0,%YMM18

0x2027bf VFMADD231PS	%YMM31,%YMM0,%YMM16

0x2027c5 VCVTPD2PS	%ZMM4,%YMM1

0x2027cb VMULPS	%YMM1,%YMM22,%YMM1{%K2}{z}

0x2027d1 VFMADD231PS	%YMM26,%YMM1,%YMM25

0x2027d7 VFMADD231PS	%YMM27,%YMM1,%YMM20

0x2027dd VFMADD231PS	%YMM28,%YMM1,%YMM9

0x2027e3 CMP	%R10,%RDI

0x2027e6 JE	2028cd

0x2027ec VMOVUPS	0x2056e0(%R10),%YMM0    [1]

0x2027f5 VMOVUPS	0x205700(%R10),%YMM2    [1]

0x2027fe VBROADCASTSS	-0x1f44(%RIP),%YMM17    [2]

0x202808 VSUBPS	%YMM8,%YMM0,%YMM29

0x20280e VMOVUPS	0x267160(%R10),%YMM0    [1]

0x202817 VSUBPS	%YMM8,%YMM2,%YMM26

0x20281d VMOVUPS	0x267180(%R10),%YMM2    [1]

0x202826 VMULPS	%YMM29,%YMM29,%YMM15

0x20282c VSUBPS	%YMM19,%YMM0,%YMM30

0x202832 VMOVUPS	0x2c8be0(%R10),%YMM0    [1]

0x20283b VSUBPS	%YMM19,%YMM2,%YMM27

0x202841 VMOVUPS	0x2c8c00(%R10),%YMM2    [1]

0x20284a VFMADD231PS	%YMM30,%YMM30,%YMM15

0x202850 VSUBPS	%YMM21,%YMM0,%YMM31

0x202856 VMULPS	%YMM26,%YMM26,%YMM0

0x20285c VSUBPS	%YMM21,%YMM2,%YMM28

0x202862 VFMADD231PS	%YMM27,%YMM27,%YMM0

0x202868 VFMADD231PS	%YMM31,%YMM31,%YMM15

0x20286e VFMADD231PS	%YMM28,%YMM28,%YMM0

0x202874 VCMPPS	$0x1,%YMM14,%YMM15,%K0

0x20287b VCMPPS	$0x1,%YMM14,%YMM15,%YMM2

0x202881 VANDPS	%YMM17,%YMM2,%YMM2

0x202887 VCMPPS	$0x1,%YMM14,%YMM0,%K1

0x20288e VCMPPS	$0x1,%YMM14,%YMM0,%YMM3

0x202894 KUNPCKBW	%K0,%K1,%K0

0x202898 VANDPS	%YMM17,%YMM3,%YMM3

0x20289e KORTESTW	%K0,%K0

0x2028a2 JE	2026b0

0x2028a8 VPCMPEQD	%YMM17,%YMM2,%K1

0x2028ae VMOVUPS	0x32a660(%R10),%YMM4{%K1}{z}    [1]

0x2028b8 VPCMPEQD	%YMM17,%YMM3,%K1

0x2028be VMOVUPS	0x32a680(%R10),%YMM22{%K1}{z}    [1]

0x2028c8 JMP	2026b0

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►99.53+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.04
Bottlenecks
Function	.omp_outlined..6
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	14.75
P0 cycles	1.25
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	1.25
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	24.50
P9 cycles	24.00
P10 cycles	12.75
P11 cycles	12.75
P12 cycles	0.50
P13 cycles	0.50
DIV/SQRT cycles	50.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	81.50
Nb uops	88.50
Nb loads	15.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.92
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.20
Bytes prefetched	0.00
Bytes loaded	260.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.33
Vectorization ratio load	46.43
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	71.39
Vector-efficiency ratio all	52.08
Vector-efficiency ratio load	26.98
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	66.67
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	54.55
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	41.28

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P8, P9,
Function	.omp_outlined..6
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	15.17
P0 cycles	1.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	1.50
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	5.33
P8 cycles	25.00
P9 cycles	24.50
P10 cycles	12.75
P11 cycles	12.75
P12 cycles	0.50
P13 cycles	0.50
DIV/SQRT cycles	50.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	91.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.92
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.84
Bytes prefetched	0.00
Bytes loaded	292.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.61
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	72.41
Vector-efficiency ratio all	52.03
Vector-efficiency ratio load	28.52
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	66.67
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	54.55
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	41.59

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.08
Bottlenecks	P8, P9,
Function	.omp_outlined..6
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	50.00
CQA cycles if no scalar integer	50.00
CQA cycles if FP arith vectorized	50.00
CQA cycles if fully vectorized	50.00
Front-end cycles	14.33
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	1.00
P5 cycles	4.67
P6 cycles	4.67
P7 cycles	4.67
P8 cycles	24.00
P9 cycles	23.50
P10 cycles	12.75
P11 cycles	12.75
P12 cycles	0.50
P13 cycles	0.50
DIV/SQRT cycles	50.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	86.00
Nb loads	14.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.92
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.56
Bytes prefetched	0.00
Bytes loaded	228.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.04
Vectorization ratio load	42.86
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	70.37
Vector-efficiency ratio all	52.14
Vector-efficiency ratio load	25.45
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	66.67
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	54.55
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	40.97

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..6
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

It is main loop of related source loop which is unrolled by 16 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 52% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
71% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 20.50 cycles (2.44x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTW: 1 occurrences
VCVTPD2PS: 2 occurrences
VCVTPS2PD: 4 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

38 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 260 bytes (65 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.91 FP operations per loaded or stored byte.

General properties

nb instructions	81.50
nb uops	88.50
loop length	522.50
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	29
used zmm registers	7
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	14.75 cycles
front end	14.75 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	0.75	0.75	0.50	1.25	5.00	5.00	5.00	20.50	20.00	12.75	12.75	0.50	0.50
cycles	1.25	0.75	0.75	0.50	1.25	5.00	5.00	5.00	24.50	24.00	12.75	12.75	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	14.75
Dispatch	24.50
DIV/SQRT	50.00
Data deps.	4.00
Overall L1	50.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	88%
load	46%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	68%

INT+FP

all	89%
load	46%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	71%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	52%
load	26%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	40%

INT+FP

all	52%
load	26%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	41%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

5% of peak load performance is reached (5.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	.omp_outlined..6
Source file and lines	Step10_orig.c:19-35
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 52% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
72% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 50.00 to 25.00 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 21.00 cycles (2.38x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTW: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:27
VCVTPD2PS: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 8 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:22
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:22
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:23
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:23
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:27
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:27

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 292 bytes (73 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.70 FP operations per loaded or stored byte.

General properties

nb instructions	84
nb uops	91
loop length	541
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	29
used zmm registers	7
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	5.33	5.33	5.33	21.00	20.50	12.75	12.75	0.50	0.50
cycles	1.50	0.75	0.75	0.50	1.50	5.33	5.33	5.33	25.00	24.50	12.75	12.75	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	15.17
Dispatch	25.00
DIV/SQRT	50.00
Data deps.	4.00
Overall L1	50.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	89%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	68%

INT+FP

all	89%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	72%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	52%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	40%

INT+FP

all	52%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	41%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

6% of peak load performance is reached (5.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2027ec

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VPCMPEQD %YMM17,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1dd3(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VADDPS %YMM23,%YMM15,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VADDPS %YMM23,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VCMPPS $0x1,%YMM0,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x40,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVAPS %YMM4,%YMM2{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPCMPEQD %YMM17,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e0b(%RIP),%YMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSS -0x1e0d(%RIP),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSD -0x1d37(%RIP),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1	scal (12.5%)
VMOVAPS %YMM22,%YMM22{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPS $0x1,%YMM15,%YMM10,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCVTPS2PD %YMM5,%ZMM5	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VCVTPS2PD %YMM1,%ZMM1	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VMOVAPS %YMM4,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMSUB213PS %YMM17,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM17,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %ZMM5,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16	vect (100.0%)
VMULPD %ZMM5,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM5,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9	vect (100.0%)
VFMSUB213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e75(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMSUB213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e98(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMSUB213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e97(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFNMADD213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM1,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9	vect (100.0%)
VCVTPS2PD %YMM6,%ZMM6	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VCVTPS2PD %YMM4,%ZMM4	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VFMSUB231PD %ZMM5,%ZMM17,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VCVTPD2PS %ZMM6,%YMM5	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33	vect (100.0%)
VMULPS %YMM5,%YMM2,%YMM0{%K1}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMSUB231PD %ZMM1,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VFMADD231PS %YMM29,%YMM0,%YMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM30,%YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM31,%YMM0,%YMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCVTPD2PS %ZMM4,%YMM1	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33	vect (100.0%)
VMULPS %YMM1,%YMM22,%YMM1{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM26,%YMM1,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM27,%YMM1,%YMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM28,%YMM1,%YMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
CMP %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 2028cd <.omp_outlined..6+0x44d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPS 0x2056e0(%R10),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x205700(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSS -0x1f44(%RIP),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBPS %YMM8,%YMM0,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x267160(%R10),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM8,%YMM2,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x267180(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPS %YMM29,%YMM29,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM19,%YMM0,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x2c8be0(%R10),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM19,%YMM2,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x2c8c00(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM30,%YMM30,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM21,%YMM0,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMULPS %YMM26,%YMM26,%YMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM21,%YMM2,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM27,%YMM27,%YMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM31,%YMM31,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM28,%YMM28,%YMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM15,%K0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VANDPS %YMM17,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM0,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
KUNPCKBW %K0,%K1,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	N/A
VANDPS %YMM17,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
KORTESTW %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1	N/A
JE 2026b0 <.omp_outlined..6+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPCMPEQD %YMM17,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPS 0x32a660(%R10),%YMM4{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPCMPEQD %YMM17,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPS 0x32a680(%R10),%YMM22{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
JMP 2026b0 <.omp_outlined..6+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	.omp_outlined..6
Source file and lines	Step10_orig.c:19-35
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 52% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
70% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 20.00 cycles (2.50x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTW: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:27
VCVTPD2PS: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 6 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:21
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:22
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:22
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:23
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:23

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPD2PS (FP64 to FP32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 228 bytes (57 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.18 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	86
loop length	504
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	29
used zmm registers	7
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.33 cycles
front end	14.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.75	0.75	0.50	1.00	4.67	4.67	4.67	20.00	19.50	12.75	12.75	0.50	0.50
cycles	1.00	0.75	0.75	0.50	1.00	4.67	4.67	4.67	24.00	23.50	12.75	12.75	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	50.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	14.33
Dispatch	24.00
DIV/SQRT	50.00
Data deps.	4.00
Overall L1	50.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	88%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	68%

INT+FP

all	89%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	70%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	52%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	40%

INT+FP

all	52%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	50%
fma	54%
div/sqrt	100%
other	40%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles. At this rate:

4% of peak load performance is reached (4.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2027ec

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VPCMPEQD %YMM17,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1dd3(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VADDPS %YMM23,%YMM15,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VADDPS %YMM23,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VCMPPS $0x1,%YMM0,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x40,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVAPS %YMM4,%YMM2{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPCMPEQD %YMM17,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e0b(%RIP),%YMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSS -0x1e0d(%RIP),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSD -0x1d37(%RIP),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1	scal (12.5%)
VMOVAPS %YMM22,%YMM22{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPS $0x1,%YMM15,%YMM10,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCVTPS2PD %YMM5,%ZMM5	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VCVTPS2PD %YMM1,%ZMM1	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VMOVAPS %YMM4,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMSUB213PS %YMM17,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM17,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %ZMM5,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16	vect (100.0%)
VMULPD %ZMM5,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM5,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9	vect (100.0%)
VFMSUB213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e75(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMSUB213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e98(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFMSUB213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMSUB213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSS -0x1e97(%RIP),%YMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VFNMADD213PS %YMM7,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD213PS %YMM7,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %ZMM1,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM1,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9	vect (100.0%)
VCVTPS2PD %YMM6,%ZMM6	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VCVTPS2PD %YMM4,%ZMM4	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	1.33	vect (50.0%)
VFMSUB231PD %ZMM5,%ZMM17,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VCVTPD2PS %ZMM6,%YMM5	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33	vect (100.0%)
VMULPS %YMM5,%YMM2,%YMM0{%K1}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMSUB231PD %ZMM1,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VFMADD231PS %YMM29,%YMM0,%YMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM30,%YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM31,%YMM0,%YMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCVTPD2PS %ZMM4,%YMM1	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33	vect (100.0%)
VMULPS %YMM1,%YMM22,%YMM1{%K2}{z}	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM26,%YMM1,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM27,%YMM1,%YMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM28,%YMM1,%YMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
CMP %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 2028cd <.omp_outlined..6+0x44d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPS 0x2056e0(%R10),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x205700(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSS -0x1f44(%RIP),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VSUBPS %YMM8,%YMM0,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x267160(%R10),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM8,%YMM2,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x267180(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPS %YMM29,%YMM29,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM19,%YMM0,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x2c8be0(%R10),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM19,%YMM2,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMOVUPS 0x2c8c00(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM30,%YMM30,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM21,%YMM0,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMULPS %YMM26,%YMM26,%YMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VSUBPS %YMM21,%YMM2,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VFMADD231PS %YMM27,%YMM27,%YMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM31,%YMM31,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PS %YMM28,%YMM28,%YMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM15,%K0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VANDPS %YMM17,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM0,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VCMPPS $0x1,%YMM14,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
KUNPCKBW %K0,%K1,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	N/A
VANDPS %YMM17,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
KORTESTW %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1	N/A
JE 2026b0 <.omp_outlined..6+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop