OV - - Function main

	Function: main	Module: exec	Source: main.c:50-191 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191

--------------------------------------------------------------------------------

50: {

[...]

65:   rank = 0;

66:   nprocs = 1;

67:

68:   //count = 327;

69:   count = 3000;

70:

71:   if ( rank == 0 )

72:   {

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   printf( "N is set %ld\n", NN );

81:

82: #pragma omp parallel

[...]

97:   for ( n = 400; n < NN; n = n + 20 )

98:   {

99:       /* Initial data preparation */

100:       fcoeff = 0.23f;

101:       fsrrmax2 = 0.5f;

102:       mp_rsm2 = 0.03f;

103:       dx1 = 1.0f/(float)n;

104:       dy1 = 2.0f/(float)n;

105:       dz1 = 3.0f/(float)n;

106:       xx[0] = 0.f;

107:       yy[0] = 0.f;

108:       zz[0] = 0.f;

109:       mass[0] = 2.f;

110:

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

117:       }

118:

119:       for ( i = 0; i < n; i++ )

120:       {

121:           vx1[i] = 0.f;

122:           vy1[i] = 0.f;

123:           vz1[i] = 0.f;

[...]

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

166:       t3 = (t2 - t1) * 1e6;

167: #endif

168:

169:       elapsed = elapsed + t3;

[...]

183:   if ( rank == 0 )

184:   {

185:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

191:   return 0;

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/mysecond.c: 22 - 23

--------------------------------------------------------------------------------

22:         i = gettimeofday(&tp,&tzp);

23:         return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6 );

0x201da0 PUSH	%RBP

0x201da1 MOV	%RSP,%RBP

0x201da4 PUSH	%R15

0x201da6 PUSH	%R14

0x201da8 PUSH	%R13

0x201daa PUSH	%R12

0x201dac PUSH	%RBX

0x201dad SUB	$0x48,%RSP

0x201db1 MOV	%RSI,%R14

0x201db4 MOV	%EDI,%R15D

0x201db7 MOV	$0x2009c7,%EDI

0x201dbc MOV	$0xbb8,%ESI

0x201dc1 XOR	%EAX,%EAX

0x201dc3 MOVL	$0,-0x30(%RBP)

0x201dca MOVL	$0xbb8,-0x34(%RBP)

0x201dd1 CALL	202560 <@plt_start@+0x10>

0x201dd6 MOV	$0x200928,%EDI

0x201ddb MOV	$0x1,%ESI

0x201de0 XOR	%EAX,%EAX

0x201de2 CALL	202560 <@plt_start@+0x10>

0x201de7 MOV	$0x186a0,%EBX

0x201dec CMP	$0x2,%R15D

0x201df0 JNE	201e10

0x201df2 MOV	0x8(%R14),%RDI

0x201df6 MOV	$0x200a5b,%ESI

0x201dfb MOV	$0x2,%EDX

0x201e00 CALL	202570 <@plt_start@+0x20>

0x201e05 TEST	%EAX,%EAX

0x201e07 MOV	$0x3a98,%EAX

0x201e0c CMOVE	%RAX,%RBX

0x201e10 MOV	$0x2009b9,%EDI

0x201e15 MOV	%RBX,%RSI

0x201e18 XOR	%EAX,%EAX

0x201e1a CALL	202560 <@plt_start@+0x10>

0x201e1f LEA	-0x30(%RBP),%RCX

0x201e23 MOV	$0x200ac0,%EDI

0x201e28 MOV	$0x202040,%EDX

0x201e2d MOV	$0x1,%ESI

0x201e32 XOR	%EAX,%EAX

0x201e34 CALL	2025a0 <@plt_start@+0x50>

0x201e39 VMOVSS	-0x1551(%RIP),%XMM4

0x201e41 MOV	$0x190,%EAX

0x201e46 VXORPS	%XMM0,%XMM0,%XMM0

0x201e4a LEA	-0x50(%RBP),%R14

0x201e4e LEA	-0x68(%RBP),%R15

0x201e52 LEA	-0x40(%RBP),%R12

0x201e56 MOVL	$0x190,-0x2c(%RBP)

0x201e5d JMP	201f1c

0x201e62 NOPW	%CS:(%RAX,%RAX,1)

(0) 0x201e70 MOV	%R14,%RDI

(0) 0x201e73 MOV	%R15,%RSI

(0) 0x201e76 CALL	2025d0 <@plt_start@+0x80>

(0) 0x201e7b VCVTSI2SDQ	-0x50(%RBP),%XMM5,%XMM0

(0) 0x201e81 VMOVSD	-0x1571(%RIP),%XMM1

(0) 0x201e89 LEA	-0x38(%RBP),%R10

(0) 0x201e8d XOR	%EAX,%EAX

(0) 0x201e8f MOV	$0x200b08,%EDI

(0) 0x201e94 MOV	$0x202070,%EDX

(0) 0x201e99 MOV	$0x5,%ESI

(0) 0x201e9e LEA	-0x34(%RBP),%RCX

(0) 0x201ea2 LEA	-0x2c(%RBP),%R8

(0) 0x201ea6 MOV	%R12,%R9

(0) 0x201ea9 VCVTSI2SDQ	-0x48(%RBP),%XMM5,%XMM2

(0) 0x201eaf VFMADD213SD	%XMM0,%XMM1,%XMM2

(0) 0x201eb4 VMOVSD	%XMM2,-0x58(%RBP)

(0) 0x201eb9 PUSH	%R10

(0) 0x201ebb LEA	-0x3c(%RBP),%R10

(0) 0x201ebf PUSH	%R10

(0) 0x201ec1 CALL	2025a0 <@plt_start@+0x50>

(0) 0x201ec6 ADD	$0x10,%RSP

(0) 0x201eca MOV	%R14,%RDI

(0) 0x201ecd MOV	%R15,%RSI

(0) 0x201ed0 CALL	2025d0 <@plt_start@+0x80>

(0) 0x201ed5 VCVTSI2SDQ	-0x50(%RBP),%XMM5,%XMM0

(0) 0x201edb VMOVSS	-0x15f3(%RIP),%XMM4

(0) 0x201ee3 MOVSXD	-0x2c(%RBP),%RAX

(0) 0x201ee7 VCVTSI2SDQ	-0x48(%RBP),%XMM5,%XMM1

(0) 0x201eed ADD	$0x14,%RAX

(0) 0x201ef1 MOV	%EAX,-0x2c(%RBP)

(0) 0x201ef4 VFMADD132SD	-0x15e5(%RIP),%XMM0,%XMM1

(0) 0x201efd VSUBSD	-0x58(%RBP),%XMM1,%XMM0

(0) 0x201f02 VMOVSD	-0x60(%RBP),%XMM1

(0) 0x201f07 VMULSD	-0x15ff(%RIP),%XMM0,%XMM0

(0) 0x201f0f VADDSD	%XMM0,%XMM1,%XMM0

(0) 0x201f13 CMP	%RAX,%RBX

(0) 0x201f16 JLE	20200f

(0) 0x201f1c VMOVSD	%XMM0,-0x60(%RBP)

(0) 0x201f21 MOVL	$0x3e6b851f,-0x38(%RBP)

(0) 0x201f28 MOVL	$0x3f000000,-0x40(%RBP)

(0) 0x201f2f MOVL	$0x3cf5c28f,-0x3c(%RBP)

(0) 0x201f36 MOVL	$0,0x2930(%RIP)

(0) 0x201f40 MOVL	$0,0x643a6(%RIP)

(0) 0x201f4a MOVL	$0,0xc5e1c(%RIP)

(0) 0x201f54 MOVL	$0x40000000,0x127892(%RIP)

(0) 0x201f5e MOV	%EAX,%R13D

(0) 0x201f61 CMP	$0x2,%EAX

(0) 0x201f64 JL	201fd1

(0) 0x201f66 VMOVAPS	-0x166e(%RIP),%XMM1

(0) 0x201f6e VCVTSI2SS	%EAX,%XMM5,%XMM0

(0) 0x201f72 MOV	$0x1,%ECX

(0) 0x201f77 VBROADCASTSS	%XMM0,%XMM0

(0) 0x201f7c VDIVPS	%XMM0,%XMM1,%XMM0

(0) 0x201f80 VXORPS	%XMM1,%XMM1,%XMM1

(0) 0x201f84 NOPW	%CS:(%RAX,%RAX,1)

  (1) 0x201f90 VADDPS	%XMM1,%XMM0,%XMM1

  (1) 0x201f94 VCVTSI2SS	%ECX,%XMM5,%XMM3

  (1) 0x201f98 VPERMILPD	$0x1,%XMM1,%XMM2

  (1) 0x201f9e VEXTRACTPS	$0x1,%XMM1,0x2662f0(,%RCX,4)

  (1) 0x201fa9 VMOVSS	%XMM1,0x2c7d70(,%RCX,4)

  (1) 0x201fb2 VFMADD132SS	%XMM4,%XMM2,%XMM3

  (1) 0x201fb7 VMOVSS	%XMM2,0x204870(,%RCX,4)

  (1) 0x201fc0 VMOVSS	%XMM3,0x3297f0(,%RCX,4)

  (1) 0x201fc9 INC	%RCX

  (1) 0x201fcc CMP	%RCX,%R13

  (1) 0x201fcf JNE	201f90

(0) 0x201fd1 TEST	%EAX,%EAX

(0) 0x201fd3 JLE	201e70

(0) 0x201fd9 SAL	$0x2,%R13

(0) 0x201fdd MOV	$0x38b270,%EDI

(0) 0x201fe2 XOR	%ESI,%ESI

(0) 0x201fe4 MOV	%R13,%RDX

(0) 0x201fe7 CALL	2025f0 <@plt_start@+0xa0>

(0) 0x201fec MOV	$0x3eccf0,%EDI

(0) 0x201ff1 XOR	%ESI,%ESI

(0) 0x201ff3 MOV	%R13,%RDX

(0) 0x201ff6 CALL	2025f0 <@plt_start@+0xa0>

(0) 0x201ffb MOV	$0x44e770,%EDI

(0) 0x202000 XOR	%ESI,%ESI

(0) 0x202002 MOV	%R13,%RDX

(0) 0x202005 CALL	2025f0 <@plt_start@+0xa0>

(0) 0x20200a JMP	201e70

0x20200f CMPL	$0,-0x30(%RBP)

0x202013 JNE	202029

0x202015 VMULSD	-0x1705(%RIP),%XMM0,%XMM0

0x20201d MOV	$0x200a39,%EDI

0x202022 MOV	$0x1,%AL

0x202024 CALL	202560 <@plt_start@+0x10>

0x202029 XOR	%EAX,%EAX

0x20202b ADD	$0x48,%RSP

0x20202f POP	%RBX

0x202030 POP	%R12

0x202032 POP	%R13

0x202034 POP	%R14

0x202036 POP	%R15

0x202038 POP	%RBP

0x202039 RET

0x20203a INT	$0x3

0x20203b INT	$0x3

0x20203c INT	$0x3

0x20203d INT	$0x3

0x20203e INT	$0x3

0x20203f INT	$0x3

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_libalm

Source file and lines	main.c:50-191
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:50,65-82,97-123,139,166-169,183-185,191
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/mysecond.c:22-23

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 1.17 cycles (9.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 11.50 to 0.74 cycles (15.56x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

@plt_start@: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:185
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:77
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:82

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 24 bytes (3 double precision FP elements). The binary function is storing 12 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	69
loop length	257
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	7.50	7.50	7.50	5.00	4.33	4.33	4.33	0.50	0.50	0.00	0.00	0.00	0.00
cycles	7.50	7.50	7.50	7.50	5.00	4.33	4.33	4.33	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	7.50
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	7%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	9%
store	6%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.50 cycles. At this rate:

2% of peak load performance is reached (2.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 7.50 cycles (1.53x speedup).

ASM code

In the binary file, the address of the function is: 201da0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x2009c7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0xbb8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0xbb8,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x200928,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x186a0,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x2,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 201e10 <main+0x70>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV $0x200a5b,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x2,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 202570 <@plt_start@+0x20>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x3a98,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x2009b9,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
LEA -0x30(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200ac0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x202040,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 2025a0 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
VMOVSS -0x1551(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV $0x190,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA -0x50(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x68(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0x190,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
JMP 201f1c <main+0x17c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMPL $0,-0x30(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
JNE 202029 <main+0x289>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD -0x1705(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV $0x200a39,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_libalm

Source file and lines	main.c:50-191
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:50,65-82,97-123,139,166-169,183-185,191
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/mysecond.c:22-23

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 1.17 cycles (9.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

@plt_start@: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:185
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:77
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:82

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 24 bytes (3 double precision FP elements). The binary function is storing 12 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	69
loop length	257
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	7.50	7.50	7.50	5.00	4.33	4.33	4.33	0.50	0.50	0.00	0.00	0.00	0.00
cycles	7.50	7.50	7.50	7.50	5.00	4.33	4.33	4.33	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	7.50
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	7%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	9%
store	6%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.50 cycles. At this rate:

2% of peak load performance is reached (2.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 201da0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x2009c7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0xbb8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0xbb8,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x200928,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x186a0,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x2,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 201e10 <main+0x70>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV $0x200a5b,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x2,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 202570 <@plt_start@+0x20>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x3a98,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x2009b9,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
LEA -0x30(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200ac0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x202040,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 2025a0 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
VMOVSS -0x1551(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV $0x190,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA -0x50(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x68(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0x190,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
JMP 201f1c <main+0x17c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMPL $0,-0x30(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
JNE 202029 <main+0x289>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD -0x1705(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV $0x200a39,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 202560 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

Name	Coverage (%)	Time (s)
▼main–	0.03	0.03
▼Loop 0 - main.c:97-169 - exec–	0.00	0.00
○Loop 1 - main.c:111-116 - exec	0.03	4.90

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code