OV - - Function .omp

	Function: .omp_outlined..6	Module: exec	Source: main.c:139-146 [...]	Coverage (incl. loops): 28.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

0x202070 PUSH	%RBP

0x202071 MOV	%RSP,%RBP

0x202074 PUSH	%R15

0x202076 PUSH	%R14

0x202078 PUSH	%R13

0x20207a PUSH	%R12

0x20207c PUSH	%RBX

0x20207d SUB	$0x58,%RSP

0x202081 MOV	(%RDX),%R12D

0x202084 MOV	%R9,-0x78(%RBP)

0x202088 TEST	%R12D,%R12D

0x20208b JLE	202108

0x20208d MOV	(%RDI),%ESI

0x20208f DEC	%R12D

0x202092 MOV	%R8,%R14

0x202095 MOV	%RCX,%R15

0x202098 MOVL	$0,-0x30(%RBP)

0x20209f MOVL	$0x1,-0x70(%RBP)

0x2020a6 MOVL	$0,-0x6c(%RBP)

0x2020ad MOV	%R12D,-0x2c(%RBP)

0x2020b1 SUB	$0x8,%RSP

0x2020b5 LEA	-0x70(%RBP),%RAX

0x2020b9 LEA	-0x6c(%RBP),%RCX

0x2020bd LEA	-0x30(%RBP),%R8

0x2020c1 LEA	-0x2c(%RBP),%R9

0x2020c5 MOV	$0x200ad8,%EDI

0x2020ca MOV	%ESI,-0x34(%RBP)

0x2020cd MOV	$0x22,%EDX

0x2020d2 PUSH	$0x1

0x2020d4 PUSH	$0x1

0x2020d6 PUSH	%RAX

0x2020d7 CALL	2025b0 <@plt_start@+0x60>

0x2020dc ADD	$0x20,%RSP

0x2020e0 MOV	-0x2c(%RBP),%EAX

0x2020e3 MOVSXD	-0x30(%RBP),%R13

0x2020e7 CMP	%R12D,%EAX

0x2020ea CMOVL	%EAX,%R12D

0x2020ee MOV	%R12D,-0x2c(%RBP)

0x2020f2 CMP	%R12D,%R13D

0x2020f5 JLE	202177

0x2020fb MOV	-0x34(%RBP),%ESI

0x2020fe MOV	$0x200af0,%EDI

0x202103 CALL	2025c0 <@plt_start@+0x70>

0x202108 ADD	$0x58,%RSP

0x20210c POP	%RBX

0x20210d POP	%R12

0x20210f POP	%R13

0x202111 POP	%R14

0x202113 POP	%R15

0x202115 POP	%RBP

0x202116 RET

0x202117 NOPW	(%RAX,%RAX,1)

(2) 0x202120 MOV	-0x2c(%RBP),%R12D

(2) 0x202124 MOV	0x10(%RBP),%RAX

(2) 0x202128 MOVSXD	%R12D,%RCX

(2) 0x20212b CMP	%RCX,%R13

(2) 0x20212e VMOVSS	(%RAX),%XMM0

(2) 0x202132 LEA	0x1(%R13),%RAX

(2) 0x202136 VFMADD213SS	0x38b270(,%R13,4),%XMM0,%XMM3

(2) 0x202140 VFMADD213SS	0x3eccf0(,%R13,4),%XMM0,%XMM2

(2) 0x20214a VFMADD213SS	0x44e770(,%R13,4),%XMM0,%XMM1

(2) 0x202154 VMOVSS	%XMM3,0x38b270(,%R13,4)

(2) 0x20215e VMOVSS	%XMM2,0x3eccf0(,%R13,4)

(2) 0x202168 VMOVSS	%XMM1,0x44e770(,%R13,4)

(2) 0x202172 MOV	%RAX,%R13

(2) 0x202175 JGE	2020fb

(2) 0x202177 MOV	(%R15),%EBX

(2) 0x20217a VXORPS	%XMM3,%XMM3,%XMM3

(2) 0x20217e VXORPS	%XMM2,%XMM2,%XMM2

(2) 0x202182 VXORPS	%XMM1,%XMM1,%XMM1

(2) 0x202186 TEST	%EBX,%EBX

(2) 0x202188 JLE	202124

(2) 0x20218a VMOVSS	0x2662f0(,%R13,4),%XMM5

(2) 0x202194 VMOVSS	0x2c7d70(,%R13,4),%XMM4

(2) 0x20219e MOV	-0x78(%RBP),%RAX

(2) 0x2021a2 VMOVSS	0x204870(,%R13,4),%XMM0

(2) 0x2021ac SAL	$0x2,%RBX

(2) 0x2021b0 XOR	%R12D,%R12D

(2) 0x2021b3 VMOVSS	%XMM5,-0x44(%RBP)

(2) 0x2021b8 VMOVSS	%XMM4,-0x40(%RBP)

(2) 0x2021bd VMOVSS	(%R14),%XMM5

(2) 0x2021c2 VMOVSS	(%RAX),%XMM4

(2) 0x2021c6 VMOVSS	%XMM0,-0x48(%RBP)

(2) 0x2021cb VMOVSS	%XMM5,-0x3c(%RBP)

(2) 0x2021d0 VMOVSS	%XMM4,-0x38(%RBP)

(2) 0x2021d5 JMP	20228a

0x2021da NOPW	(%RAX,%RAX,1)

  (3) 0x2021e0 VMOVSS	%XMM0,-0x50(%RBP)

  (3) 0x2021e5 VADDSS	-0x38(%RBP),%XMM2,%XMM0

  (3) 0x2021ea VMOVSD	-0x18d2(%RIP),%XMM1

  (3) 0x2021f2 VMOVSS	%XMM2,-0x4c(%RBP)

  (3) 0x2021f7 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (3) 0x2021fb CALL	2025e0 <@plt_start@+0x90>

  (3) 0x202200 VMOVSS	-0x4c(%RBP),%XMM2

  (3) 0x202205 VMOVSS	-0x1935(%RIP),%XMM1

  (3) 0x20220d ADD	$0x4,%R12

  (3) 0x202211 VFMADD213SS	-0x1932(%RIP),%XMM2,%XMM1

  (3) 0x20221a VFMADD213SS	-0x1937(%RIP),%XMM2,%XMM1

  (3) 0x202223 VFMADD213SS	-0x194c(%RIP),%XMM2,%XMM1

  (3) 0x20222c VFMADD213SS	-0x1965(%RIP),%XMM2,%XMM1

  (3) 0x202235 VFMADD213SS	-0x195a(%RIP),%XMM2,%XMM1

  (3) 0x20223e VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (3) 0x202242 VSUBSD	%XMM1,%XMM0,%XMM0

  (3) 0x202246 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (3) 0x20224a VMULSS	-0x50(%RBP),%XMM0,%XMM0

  (3) 0x20224f VCMPSS	$0xe,-0x197e(%RIP),%XMM2,%K1

  (3) 0x20225a VMOVSS	-0x60(%RBP),%XMM3

  (3) 0x20225f VMOVSS	-0x64(%RBP),%XMM2

  (3) 0x202264 VMOVSS	-0x68(%RBP),%XMM1

  (3) 0x202269 VMOVSS	%XMM0,%XMM0,%XMM0{%K1}{z}

  (3) 0x20226f VFMADD231SS	-0x5c(%RBP),%XMM0,%XMM3

  (3) 0x202275 VFMADD231SS	-0x58(%RBP),%XMM0,%XMM2

  (3) 0x20227b VFMADD231SS	-0x54(%RBP),%XMM0,%XMM1

  (3) 0x202281 CMP	%R12,%RBX

  (3) 0x202284 JE	202120

  (3) 0x20228a VMOVSS	0x204870(%R12),%XMM0

  (3) 0x202294 VMOVSS	%XMM1,-0x68(%RBP)

  (3) 0x202299 VMOVSS	%XMM2,-0x64(%RBP)

  (3) 0x20229e VMOVSS	%XMM3,-0x60(%RBP)

  (3) 0x2022a3 VSUBSS	-0x48(%RBP),%XMM0,%XMM1

  (3) 0x2022a8 VMOVSS	0x2662f0(%R12),%XMM0

  (3) 0x2022b2 VSUBSS	-0x44(%RBP),%XMM0,%XMM2

  (3) 0x2022b7 VMOVSS	0x2c7d70(%R12),%XMM0

  (3) 0x2022c1 VSUBSS	-0x40(%RBP),%XMM0,%XMM0

  (3) 0x2022c6 VMOVSS	%XMM1,-0x5c(%RBP)

  (3) 0x2022cb VMOVSS	%XMM2,-0x58(%RBP)

  (3) 0x2022d0 VMULSS	%XMM2,%XMM2,%XMM2

  (3) 0x2022d4 VMOVSS	%XMM0,-0x54(%RBP)

  (3) 0x2022d9 VFMADD231SS	%XMM1,%XMM1,%XMM2

  (3) 0x2022de VFMADD231SS	%XMM0,%XMM0,%XMM2

  (3) 0x2022e3 VMOVSS	-0x3c(%RBP),%XMM0

  (3) 0x2022e8 VUCOMISS	%XMM2,%XMM0

  (3) 0x2022ec VXORPS	%XMM0,%XMM0,%XMM0

  (3) 0x2022f0 JBE	2021e0

  (3) 0x2022f6 VMOVSS	0x3297f0(%R12),%XMM0

  (3) 0x202300 JMP	2021e0

0x202305 INT	$0x3

0x202306 INT	$0x3

0x202307 INT	$0x3

0x202308 INT	$0x3

0x202309 INT	$0x3

0x20230a INT	$0x3

0x20230b INT	$0x3

0x20230c INT	$0x3

0x20230d INT	$0x3

0x20230e INT	$0x3

0x20230f INT	$0x3

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_libalm

Source file and lines	main.c:139-146
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.83 to 0.57 cycles (15.52x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	64
nb uops	53
loop length	193
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.00	5.00	4.75	4.75	2.50	4.67	4.67	4.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	4.75	4.75	2.50	4.67	4.67	4.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	5.00
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	7%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.83 cycles. At this rate:

2% of peak load performance is reached (2.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.83 to 5.00 cycles (1.77x speedup).

ASM code

In the binary file, the address of the function is: 202070

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202108 <.omp_outlined..6+0x98>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
DEC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x6c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x6c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200ad8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2025b0 <@plt_start@+0x60>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOVSXD -0x30(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVL %EAX,%R12D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202177 <.omp_outlined..6+0x107>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV $0x200af0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2025c0 <@plt_start@+0x70>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_libalm

Source file and lines	main.c:139-146
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	64
nb uops	53
loop length	193
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.00	5.00	4.75	4.75	2.50	4.67	4.67	4.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	4.75	4.75	2.50	4.67	4.67	4.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	5.00
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	7%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.83 cycles. At this rate:

2% of peak load performance is reached (2.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 202070

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202108 <.omp_outlined..6+0x98>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
DEC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x6c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x6c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200ad8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2025b0 <@plt_start@+0x60>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOVSXD -0x30(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVL %EAX,%R12D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R12D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202177 <.omp_outlined..6+0x107>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV $0x200af0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2025c0 <@plt_start@+0x70>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

Name	Coverage (%)	Time (s)
▼.omp_outlined..6–	28.33	23.72
▼Loop 2 - Step10_orig.c:19-35 - exec–	0.01	0.01
○Loop 3 - Step10_orig.c:19-35 - exec	28.32	23.54

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code