OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-191 [...]	Coverage (incl. loops): 0.28% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191

--------------------------------------------------------------------------------

50: {

[...]

65:   rank = 0;

66:   nprocs = 1;

67:

68:   //count = 327;

69:   count = 3000;

70:

71:   if ( rank == 0 )

72:   {

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   printf( "N is set %ld\n", NN );

81:

82: #pragma omp parallel

[...]

97:   for ( n = 400; n < NN; n = n + 20 )

98:   {

99:       /* Initial data preparation */

100:       fcoeff = 0.23f;

101:       fsrrmax2 = 0.5f;

102:       mp_rsm2 = 0.03f;

103:       dx1 = 1.0f/(float)n;

104:       dy1 = 2.0f/(float)n;

105:       dz1 = 3.0f/(float)n;

106:       xx[0] = 0.f;

107:       yy[0] = 0.f;

108:       zz[0] = 0.f;

109:       mass[0] = 2.f;

110:

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

117:       }

118:

119:       for ( i = 0; i < n; i++ )

120:       {

121:           vx1[i] = 0.f;

122:           vy1[i] = 0.f;

123:           vz1[i] = 0.f;

[...]

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

166:       t3 = (t2 - t1) * 1e6;

167: #endif

168:

169:       elapsed = elapsed + t3;

[...]

183:   if ( rank == 0 )

184:   {

185:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

191:   return 0;

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/mysecond.c: 22 - 23

--------------------------------------------------------------------------------

22:         i = gettimeofday(&tp,&tzp);

23:         return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6 );

0x201e90 PUSH	%RBP

0x201e91 MOV	%RSP,%RBP

0x201e94 PUSH	%R15

0x201e96 PUSH	%R14

0x201e98 PUSH	%R13

0x201e9a PUSH	%R12

0x201e9c PUSH	%RBX

0x201e9d AND	$-0x40,%RSP

0x201ea1 SUB	$0x200,%RSP

0x201ea8 MOV	%RSI,%R14

0x201eab MOV	%EDI,%R15D

0x201eae MOV	$0x200a77,%EDI

0x201eb3 MOV	$0xbb8,%ESI

0x201eb8 XOR	%EAX,%EAX

0x201eba MOVL	$0,0x2c(%RSP)

0x201ec2 MOVL	$0xbb8,0x30(%RSP)

0x201eca CALL	2033f0 <@plt_start@+0x10>

0x201ecf MOV	$0x2009d8,%EDI

0x201ed4 MOV	$0x1,%ESI

0x201ed9 XOR	%EAX,%EAX

0x201edb CALL	2033f0 <@plt_start@+0x10>

0x201ee0 MOV	$0x186a0,%EBX

0x201ee5 CMP	$0x2,%R15D

0x201ee9 JNE	201f09

0x201eeb MOV	0x8(%R14),%RDI

0x201eef MOV	$0x200b0b,%ESI

0x201ef4 MOV	$0x2,%EDX

0x201ef9 CALL	203400 <@plt_start@+0x20>

0x201efe TEST	%EAX,%EAX

0x201f00 MOV	$0x3a98,%EAX

0x201f05 CMOVE	%RAX,%RBX

0x201f09 MOV	$0x200a69,%EDI

0x201f0e MOV	%RBX,%RSI

0x201f11 XOR	%EAX,%EAX

0x201f13 CALL	2033f0 <@plt_start@+0x10>

0x201f18 LEA	0x2c(%RSP),%RCX

0x201f1d MOV	$0x200b70,%EDI

0x201f22 MOV	$0x202450,%EDX

0x201f27 MOV	$0x1,%ESI

0x201f2c XOR	%EAX,%EAX

0x201f2e CALL	203430 <@plt_start@+0x50>

0x201f33 VBROADCASTSS	-0x1639(%RIP),%ZMM28

0x201f3d VPBROADCASTD	-0x164f(%RIP),%ZMM27

0x201f47 VPBROADCASTD	-0x167d(%RIP),%ZMM29

0x201f51 VPBROADCASTD	-0x165f(%RIP),%ZMM30

0x201f5b VPBROADCASTD	-0x1675(%RIP),%ZMM31

0x201f65 VMOVDDUP	-0x159d(%RIP),%XMM1

0x201f6d VMOVSS	-0x1673(%RIP),%XMM26

0x201f77 MOV	$0x190,%EAX

0x201f7c VXORPS	%XMM0,%XMM0,%XMM0

0x201f80 LEA	0x40(%RSP),%R14

0x201f85 LEA	0x78(%RSP),%R15

0x201f8a MOVL	$0x190,0x28(%RSP)

0x201f92 VMOVAPS	%XMM1,0x60(%RSP)

0x201f98 VMOVDQA64	%ZMM27,0x180(%RSP)

0x201fa0 VMOVDQA64	%ZMM29,0x100(%RSP)

0x201fa8 VMOVDQA64	%ZMM30,0xc0(%RSP)

0x201fb0 VMOVDQA64	%ZMM31,0x80(%RSP)

0x201fb8 VMOVAPS	%ZMM28,0x140(%RSP)

0x201fc0 JMP	2020bb

0x201fc5 NOPW	%CS:(%RAX,%RAX,1)

(0) 0x201fd0 MOV	%R14,%RDI

(0) 0x201fd3 MOV	%R15,%RSI

(0) 0x201fd6 VZEROUPPER

(0) 0x201fd9 CALL	203460 <@plt_start@+0x80>

(0) 0x201fde MOV	0x40(%RSP),%R13

(0) 0x201fe3 MOV	0x48(%RSP),%R12

(0) 0x201fe8 LEA	0x34(%RSP),%R10

(0) 0x201fed XOR	%EAX,%EAX

(0) 0x201fef MOV	$0x200bb8,%EDI

(0) 0x201ff4 MOV	$0x202480,%EDX

(0) 0x201ff9 MOV	$0x5,%ESI

(0) 0x201ffe LEA	0x30(%RSP),%RCX

(0) 0x202003 LEA	0x28(%RSP),%R8

(0) 0x202008 LEA	0x3c(%RSP),%R9

(0) 0x20200d PUSH	%R10

(0) 0x20200f LEA	0x40(%RSP),%R10

(0) 0x202014 PUSH	%R10

(0) 0x202016 CALL	203430 <@plt_start@+0x50>

(0) 0x20201b ADD	$0x10,%RSP

(0) 0x20201f MOV	%R14,%RDI

(0) 0x202022 MOV	%R15,%RSI

(0) 0x202025 CALL	203460 <@plt_start@+0x80>

(0) 0x20202a VMOVDQA	0x40(%RSP),%XMM0

(0) 0x202030 VPBROADCASTQ	0x48(%RSP),%XMM1

(0) 0x202037 VMOVSS	-0x173d(%RIP),%XMM26

(0) 0x202041 VMOVDQA64	0x180(%RSP),%ZMM27

(0) 0x202049 VMOVAPS	0x140(%RSP),%ZMM28

(0) 0x202051 VMOVDQA64	0x100(%RSP),%ZMM29

(0) 0x202059 VMOVDQA64	0xc0(%RSP),%ZMM30

(0) 0x202061 VMOVDQA64	0x80(%RSP),%ZMM31

(0) 0x202069 MOVSXD	0x28(%RSP),%RAX

(0) 0x20206e ADD	$0x14,%RAX

(0) 0x202072 MOV	%EAX,0x28(%RSP)

(0) 0x202076 VPINSRQ	$0x1,%R13,%XMM0,%XMM0

(0) 0x20207c VPINSRQ	$0x1,%R12,%XMM1,%XMM1

(0) 0x202082 VCVTQQ2PD	%XMM0,%XMM0

(0) 0x202088 VCVTQQ2PD	%XMM1,%XMM1

(0) 0x20208e VFMADD132PD	0x60(%RSP),%XMM0,%XMM1

(0) 0x202095 VPERMILPD	$0x1,%XMM1,%XMM0

(0) 0x20209b VSUBSD	%XMM0,%XMM1,%XMM0

(0) 0x20209f VMOVSD	0x58(%RSP),%XMM1

(0) 0x2020a5 VFMADD231SD	-0x16ee(%RIP),%XMM0,%XMM1

(0) 0x2020ae VMOVAPD	%XMM1,%XMM0

(0) 0x2020b2 CMP	%RAX,%RBX

(0) 0x2020b5 JLE	202417

(0) 0x2020bb VMOVSD	%XMM0,0x58(%RSP)

(0) 0x2020c1 VXORPS	%XMM4,%XMM4,%XMM4

(0) 0x2020c5 VCVTSI2SS	%EAX,%XMM4,%XMM2

(0) 0x2020c9 VMOVSS	-0x1811(%RIP),%XMM0

(0) 0x2020d1 MOVL	$0x3e6b851f,0x34(%RSP)

(0) 0x2020d9 MOVL	$0x3f000000,0x3c(%RSP)

(0) 0x2020e1 MOVL	$0x3cf5c28f,0x38(%RSP)

(0) 0x2020e9 MOVL	$0,0x360d(%RIP)

(0) 0x2020f3 MOVL	$0,0x65083(%RIP)

(0) 0x2020fd MOVL	$0,0xc6af9(%RIP)

(0) 0x202107 MOVL	$0x40000000,0x12856f(%RIP)

(0) 0x202111 MOV	%EAX,%R13D

(0) 0x202114 VDIVSS	%XMM2,%XMM0,%XMM0

(0) 0x202118 VBROADCASTSS	%XMM0,%XMM0

(0) 0x20211d VMULPS	-0x1805(%RIP),%XMM0,%XMM0

(0) 0x202125 CMP	$0x2,%EAX

(0) 0x202128 JL	2023d6

(0) 0x20212e LEA	-0x1(%R13),%RDX

(0) 0x202132 CMP	$0x40,%RDX

(0) 0x202136 JAE	202150

(0) 0x202138 VXORPS	%XMM1,%XMM1,%XMM1

(0) 0x20213c MOV	$0x1,%ECX

(0) 0x202141 JMP	202390

0x202146 NOPW	%CS:(%RAX,%RAX,1)

(0) 0x202150 VMOVSS	-0x1850(%RIP),%XMM3

(0) 0x202158 VMOVAPS	-0x1822(%RIP),%ZMM7

(0) 0x202162 VMOVSS	-0x185e(%RIP),%XMM8

(0) 0x20216a VPERMILPS	$-0x56,%XMM0,%XMM6

(0) 0x202170 VMOVSHDUP	%XMM0,%XMM5

(0) 0x202174 MOV	%RDX,%RSI

(0) 0x202177 AND	$-0x40,%RSI

(0) 0x20217b XOR	%EDI,%EDI

(0) 0x20217d VBROADCASTSD	%XMM5,%ZMM4

(0) 0x202183 VBROADCASTSD	%XMM6,%ZMM6

(0) 0x202189 VPBROADCASTQ	%RSI,%YMM1

(0) 0x20218f LEA	0x1(%RSI),%RCX

(0) 0x202193 VCVTQQ2PS	%YMM1,%XMM1

(0) 0x202199 VMULPS	%XMM1,%XMM0,%XMM1

(0) 0x20219d VDIVPS	%XMM2,%XMM3,%XMM2

(0) 0x2021a1 VMULPS	%ZMM7,%ZMM4,%ZMM10

(0) 0x2021a7 VMULPS	%ZMM7,%ZMM6,%ZMM11

(0) 0x2021ad VMULSS	%XMM5,%XMM8,%XMM5

(0) 0x2021b1 VMULSS	%XMM0,%XMM8,%XMM3

(0) 0x2021b5 VBROADCASTSS	%XMM3,%ZMM3

(0) 0x2021bb VBROADCASTSS	%XMM5,%ZMM5

(0) 0x2021c1 VBROADCASTSS	%XMM2,%ZMM2

(0) 0x2021c7 VMULPS	%ZMM7,%ZMM2,%ZMM9

(0) 0x2021cd VPERMILPD	$0x1,%XMM0,%XMM7

(0) 0x2021d3 VMULSS	%XMM7,%XMM8,%XMM7

(0) 0x2021d7 VMOVDQA64	-0x1861(%RIP),%ZMM8

(0) 0x2021e1 VBROADCASTSS	%XMM7,%ZMM7

(0) 0x2021e7 NOPW	(%RAX,%RAX,1)

  (1) 0x2021f0 VADDPS	%ZMM3,%ZMM9,%ZMM12

  (1) 0x2021f6 VADDPS	%ZMM7,%ZMM11,%ZMM18

  (1) 0x2021fc VADDPS	%ZMM5,%ZMM10,%ZMM15

  (1) 0x202202 VADDPS	%ZMM4,%ZMM10,%ZMM10

  (1) 0x202208 VADDPS	%ZMM2,%ZMM9,%ZMM9

  (1) 0x20220e VPADDD	%ZMM27,%ZMM8,%ZMM21

  (1) 0x202214 VADDPS	%ZMM6,%ZMM11,%ZMM11

  (1) 0x20221a VPADDD	%ZMM29,%ZMM8,%ZMM22

  (1) 0x202220 VPADDD	%ZMM30,%ZMM8,%ZMM23

  (1) 0x202226 VADDPS	%ZMM7,%ZMM18,%ZMM19

  (1) 0x20222c VADDPS	%ZMM3,%ZMM12,%ZMM13

  (1) 0x202232 VMOVUPS	%ZMM10,0x267184(,%RDI,4)

  (1) 0x20223d VADDPS	%ZMM2,%ZMM12,%ZMM10

  (1) 0x202243 VADDPS	%ZMM5,%ZMM15,%ZMM16

  (1) 0x202249 VADDPS	%ZMM4,%ZMM15,%ZMM15

  (1) 0x20224f VMOVUPS	%ZMM9,0x2c8c04(,%RDI,4)

  (1) 0x20225a VCVTDQ2PS	%ZMM8,%ZMM9

  (1) 0x202260 VADDPS	%ZMM6,%ZMM18,%ZMM18

  (1) 0x202266 VMOVUPS	%ZMM11,0x205704(,%RDI,4)

  (1) 0x202271 VPADDD	%ZMM31,%ZMM8,%ZMM8

  (1) 0x202277 VADDPS	%ZMM7,%ZMM19,%ZMM20

  (1) 0x20227d VADDPS	%ZMM2,%ZMM13,%ZMM12

  (1) 0x202283 VMOVUPS	%ZMM10,0x2c8c44(,%RDI,4)

  (1) 0x20228e VCVTDQ2PS	%ZMM21,%ZMM10

  (1) 0x202294 VMOVUPS	%ZMM15,0x2671c4(,%RDI,4)

  (1) 0x20229f VADDPS	%ZMM6,%ZMM19,%ZMM19

  (1) 0x2022a5 VCVTDQ2PS	%ZMM23,%ZMM15

  (1) 0x2022ab VADDPS	%ZMM3,%ZMM13,%ZMM14

  (1) 0x2022b1 VADDPS	%ZMM5,%ZMM16,%ZMM17

  (1) 0x2022b7 VFMADD213PS	%ZMM11,%ZMM28,%ZMM9

  (1) 0x2022bd VADDPS	%ZMM4,%ZMM16,%ZMM16

  (1) 0x2022c3 VMOVUPS	%ZMM18,0x205744(,%RDI,4)

  (1) 0x2022ce VADDPS	%ZMM6,%ZMM20,%ZMM24

  (1) 0x2022d4 VMOVUPS	%ZMM12,0x2c8c84(,%RDI,4)

  (1) 0x2022df VCVTDQ2PS	%ZMM22,%ZMM12

  (1) 0x2022e5 VFMADD213PS	%ZMM18,%ZMM28,%ZMM10

  (1) 0x2022eb VADDPS	%ZMM2,%ZMM14,%ZMM13

  (1) 0x2022f1 VADDPS	%ZMM4,%ZMM17,%ZMM25

  (1) 0x2022f7 VADDPS	%ZMM7,%ZMM20,%ZMM11

  (1) 0x2022fd VMOVUPS	%ZMM19,0x205784(,%RDI,4)

  (1) 0x202308 VMOVUPS	%ZMM16,0x267204(,%RDI,4)

  (1) 0x202313 VMOVUPS	%ZMM9,0x32a684(,%RDI,4)

  (1) 0x20231e VADDPS	%ZMM3,%ZMM14,%ZMM9

  (1) 0x202324 VFMADD213PS	%ZMM19,%ZMM28,%ZMM12

  (1) 0x20232a VFMADD213PS	%ZMM24,%ZMM28,%ZMM15

  (1) 0x202330 VMOVUPS	%ZMM24,0x2057c4(,%RDI,4)

  (1) 0x20233b VMOVUPS	%ZMM25,0x267244(,%RDI,4)

  (1) 0x202346 VMOVUPS	%ZMM13,0x2c8cc4(,%RDI,4)

  (1) 0x202351 VMOVUPS	%ZMM10,0x32a6c4(,%RDI,4)

  (1) 0x20235c VADDPS	%ZMM5,%ZMM17,%ZMM10

  (1) 0x202362 VMOVUPS	%ZMM12,0x32a704(,%RDI,4)

  (1) 0x20236d VMOVUPS	%ZMM15,0x32a744(,%RDI,4)

  (1) 0x202378 ADD	$0x40,%RDI

  (1) 0x20237c CMP	%RDI,%RSI

  (1) 0x20237f JNE	2021f0

(0) 0x202385 CMP	%RSI,%RDX

(0) 0x202388 JE	2023d6

(0) 0x20238a NOPW	(%RAX,%RAX,1)

  (2) 0x202390 VADDPS	%XMM0,%XMM1,%XMM1

  (2) 0x202394 VXORPS	%XMM4,%XMM4,%XMM4

  (2) 0x202398 VCVTSI2SS	%ECX,%XMM4,%XMM3

  (2) 0x20239c VPERMILPD	$0x1,%XMM1,%XMM2

  (2) 0x2023a2 VEXTRACTPS	$0x1,%XMM1,0x267180(,%RCX,4)

  (2) 0x2023ad VMOVSS	%XMM1,0x2c8c00(,%RCX,4)

  (2) 0x2023b6 VFMADD132SS	%XMM26,%XMM2,%XMM3

  (2) 0x2023bc VMOVSS	%XMM2,0x205700(,%RCX,4)

  (2) 0x2023c5 VMOVSS	%XMM3,0x32a680(,%RCX,4)

  (2) 0x2023ce INC	%RCX

  (2) 0x2023d1 CMP	%RCX,%R13

  (2) 0x2023d4 JNE	202390

(0) 0x2023d6 TEST	%EAX,%EAX

(0) 0x2023d8 JLE	201fd0

(0) 0x2023de SAL	$0x2,%R13

(0) 0x2023e2 MOV	$0x38c100,%EDI

(0) 0x2023e7 XOR	%ESI,%ESI

(0) 0x2023e9 MOV	%R13,%RDX

(0) 0x2023ec VZEROUPPER

(0) 0x2023ef CALL	203470 <@plt_start@+0x90>

(0) 0x2023f4 MOV	$0x3edb80,%EDI

(0) 0x2023f9 XOR	%ESI,%ESI

(0) 0x2023fb MOV	%R13,%RDX

(0) 0x2023fe CALL	203470 <@plt_start@+0x90>

(0) 0x202403 MOV	$0x44f600,%EDI

(0) 0x202408 XOR	%ESI,%ESI

(0) 0x20240a MOV	%R13,%RDX

(0) 0x20240d CALL	203470 <@plt_start@+0x90>

(0) 0x202412 JMP	201fd0

0x202417 CMPL	$0,0x2c(%RSP)

0x20241c JNE	202432

0x20241e VMULSD	-0x1a56(%RIP),%XMM0,%XMM0

0x202426 MOV	$0x200ae9,%EDI

0x20242b MOV	$0x1,%AL

0x20242d CALL	2033f0 <@plt_start@+0x10>

0x202432 XOR	%EAX,%EAX

0x202434 LEA	-0x28(%RBP),%RSP

0x202438 POP	%RBX

0x202439 POP	%R12

0x20243b POP	%R13

0x20243d POP	%R14

0x20243f POP	%R15

0x202441 POP	%RBP

0x202442 RET

0x202443 INT	$0x3

0x202444 INT	$0x3

0x202445 INT	$0x3

0x202446 INT	$0x3

0x202447 INT	$0x3

0x202448 INT	$0x3

0x202449 INT	$0x3

0x20244a INT	$0x3

0x20244b INT	$0x3

0x20244c INT	$0x3

0x20244d INT	$0x3

0x20244e INT	$0x3

0x20244f INT	$0x3

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_libalm

Source file and lines	main.c:50-191
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:50,65-82,97-123,139,166-169,183-185,191
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/mysecond.c:22-23

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.33 to 5.50 cycles (2.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.33 to 12.15 cycles (1.18x speedup).

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
66% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
4% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

@plt_start@: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:185
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:77
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:82

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
VMOVDQA64: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 52 bytes (6 double precision FP elements). The binary function is storing 348 bytes (43 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	90
nb uops	86
loop length	387
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	5
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.33 cycles
front end	14.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	7.50	7.50	7.50	5.00	8.33	8.33	8.33	1.00	0.50	0.50	0.00	5.50	5.50
cycles	7.50	7.50	7.50	7.50	5.00	8.33	8.33	8.33	1.00	0.50	0.50	0.00	5.50	5.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.33
Dispatch	8.33
Overall L1	14.33

Vectorization ratios

INT

all	13%
load	0%
store	57%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	0%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	19%
load	0%
store	66%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	19%
load	7%
store	59%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	26%
load	9%
store	62%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	21%
load	8%
store	60%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.33 cycles. At this rate:

3% of peak load performance is reached (3.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (24.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.33 to 8.33 cycles (1.72x speedup).

ASM code

In the binary file, the address of the function is: 201e90

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x200,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x200a77,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0xbb8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0xbb8,0x30(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x2009d8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x186a0,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x2,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 201f09 <main+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV $0x200b0b,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x2,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 203400 <@plt_start@+0x20>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x3a98,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x200a69,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
LEA 0x2c(%RSP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200b70,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x202450,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 203430 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS -0x1639(%RIP),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1	scal (6.3%)
VPBROADCASTD -0x164f(%RIP),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VPBROADCASTD -0x167d(%RIP),%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VPBROADCASTD -0x165f(%RIP),%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VPBROADCASTD -0x1675(%RIP),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VMOVDDUP -0x159d(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x1673(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV $0x190,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA 0x40(%RSP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x78(%RSP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0x190,0x28(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVAPS %XMM1,0x60(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVDQA64 %ZMM27,0x180(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVDQA64 %ZMM29,0x100(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVDQA64 %ZMM30,0xc0(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVDQA64 %ZMM31,0x80(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVAPS %ZMM28,0x140(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
JMP 2020bb <main+0x22b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMPL $0,0x2c(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
JNE 202432 <main+0x5a2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD -0x1a56(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV $0x200ae9,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_libalm

Source file and lines	main.c:50-191
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:50,65-82,97-123,139,166-169,183-185,191
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/mysecond.c:22-23

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.33 to 5.50 cycles (2.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
66% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
4% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

@plt_start@: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:185
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:77
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:82

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
VMOVDQA64: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:97

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 52 bytes (6 double precision FP elements). The binary function is storing 348 bytes (43 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	90
nb uops	86
loop length	387
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	5
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.33 cycles
front end	14.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	7.50	7.50	7.50	5.00	8.33	8.33	8.33	1.00	0.50	0.50	0.00	5.50	5.50
cycles	7.50	7.50	7.50	7.50	5.00	8.33	8.33	8.33	1.00	0.50	0.50	0.00	5.50	5.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.33
Dispatch	8.33
Overall L1	14.33

Vectorization ratios

INT

all	13%
load	0%
store	57%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	0%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	19%
load	0%
store	66%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	19%
load	7%
store	59%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	26%
load	9%
store	62%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	21%
load	8%
store	60%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.33 cycles. At this rate:

3% of peak load performance is reached (3.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (24.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 201e90

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x200,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x200a77,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0xbb8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0xbb8,0x30(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x2009d8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV $0x186a0,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x2,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 201f09 <main+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV $0x200b0b,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x2,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 203400 <@plt_start@+0x20>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x3a98,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMOVE %RAX,%RBX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x200a69,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
LEA 0x2c(%RSP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200b70,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x202450,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 203430 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS -0x1639(%RIP),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1	scal (6.3%)
VPBROADCASTD -0x164f(%RIP),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VPBROADCASTD -0x167d(%RIP),%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VPBROADCASTD -0x165f(%RIP),%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VPBROADCASTD -0x1675(%RIP),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50	scal (6.3%)
VMOVDDUP -0x159d(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x1673(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV $0x190,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA 0x40(%RSP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x78(%RSP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0x190,0x28(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVAPS %XMM1,0x60(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVDQA64 %ZMM27,0x180(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVDQA64 %ZMM29,0x100(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVDQA64 %ZMM30,0xc0(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVDQA64 %ZMM31,0x80(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	4	2	vect (100.0%)
VMOVAPS %ZMM28,0x140(%RSP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
JMP 2020bb <main+0x22b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMPL $0,0x2c(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
JNE 202432 <main+0x5a2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD -0x1a56(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV $0x200ae9,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2033f0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

Name	Coverage (%)	Time (s)
▼main–	0.28	0.03
▼Loop 0 - main.c:97-169 - exec–	0.00	0.00
○Loop 1 - main.c:113-116 - exec	0.28	4.71
○Loop 2 - main.c:111-116 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code