OV - exec - Function .omp

	Function: .omp_outlined..6	Module: exec	Source: main.c:139-146 [...]	Coverage (incl. loops): 45.49% \| (excl. loops): 0.03%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

0x202480 PUSH	%RBP

0x202481 MOV	%RSP,%RBP

0x202484 PUSH	%R15

0x202486 PUSH	%R14

0x202488 PUSH	%R13

0x20248a PUSH	%R12

0x20248c PUSH	%RBX

0x20248d SUB	$0x38,%RSP

0x202491 MOV	(%RDX),%R13D

0x202494 TEST	%R13D,%R13D

0x202497 JLE	202517

0x202499 MOV	(%RDI),%R15D

0x20249c DEC	%R13D

0x20249f MOV	%R9,%RBX

0x2024a2 MOV	%R8,%R14

0x2024a5 MOV	%RCX,%R12

0x2024a8 MOVL	$0,-0x30(%RBP)

0x2024af MOVL	$0x1,-0x38(%RBP)

0x2024b6 MOVL	$0,-0x34(%RBP)

0x2024bd MOV	%R13D,-0x2c(%RBP)

0x2024c1 SUB	$0x8,%RSP

0x2024c5 LEA	-0x38(%RBP),%RAX

0x2024c9 LEA	-0x34(%RBP),%RCX

0x2024cd LEA	-0x30(%RBP),%R8

0x2024d1 LEA	-0x2c(%RBP),%R9

0x2024d5 MOV	$0x200b88,%EDI

0x2024da MOV	%R15D,%ESI

0x2024dd MOV	$0x22,%EDX

0x2024e2 PUSH	$0x1

0x2024e4 PUSH	$0x1

0x2024e6 PUSH	%RAX

0x2024e7 CALL	203440 <@plt_start@+0x60>

0x2024ec ADD	$0x20,%RSP

0x2024f0 MOV	-0x2c(%RBP),%EAX

0x2024f3 CMP	%R13D,%EAX

0x2024f6 CMOVL	%EAX,%R13D

0x2024fa MOVSXD	-0x30(%RBP),%RAX

0x2024fe MOV	%R13D,-0x2c(%RBP)

0x202502 CMP	%R13D,%EAX

0x202505 JLE	202526

0x202507 MOV	$0x200ba0,%EDI

0x20250c MOV	%R15D,%ESI

0x20250f VZEROUPPER

0x202512 CALL	203450 <@plt_start@+0x70>

0x202517 ADD	$0x38,%RSP

0x20251b POP	%RBX

0x20251c POP	%R12

0x20251e POP	%R13

0x202520 POP	%R14

0x202522 POP	%R15

0x202524 POP	%RBP

0x202525 RET

0x202526 VMOVSD	-0x1b66(%RIP),%XMM5

0x20252e VMOVSS	-0x1c56(%RIP),%XMM6

0x202536 VMOVSS	-0x1c72(%RIP),%XMM7

0x20253e VMOVSS	-0x1c48(%RIP),%XMM22

0x202548 VMOVSS	-0x1c5e(%RIP),%XMM25

0x202552 VMOVSS	-0x1c78(%RIP),%XMM26

0x20255c VMOVSS	-0x1c56(%RIP),%XMM27

0x202566 MOV	(%R12),%EDX

0x20256a MOV	0x10(%RBP),%RCX

0x20256e MOVSXD	%R13D,%RSI

0x202571 VXORPS	%XMM28,%XMM28,%XMM28

0x202577 VXORPS	%XMM29,%XMM29,%XMM29

0x20257d VXORPS	%XMM10,%XMM10,%XMM10

0x202582 MOV	%RDX,%RDI

0x202585 SHR	$0x4,%RDI

0x202589 MOV	%EDX,%R8D

0x20258c AND	$-0x4,%R8D

0x202590 SAL	$0x6,%RDI

0x202594 JMP	2025f2

0x202596 NOPW	%CS:(%RAX,%RAX,1)

(3) 0x2025a0 VMOVSHDUP	%XMM8,%XMM14

(3) 0x2025a5 VMOVSS	(%RCX),%XMM0

(3) 0x2025a9 LEA	0x1(%RAX),%R9

(3) 0x2025ad CMP	%RSI,%RAX

(3) 0x2025b0 VFMADD213SS	0x38c100(,%RAX,4),%XMM0,%XMM14

(3) 0x2025ba VFMADD213SS	0x3edb80(,%RAX,4),%XMM0,%XMM8

(3) 0x2025c4 VFMADD213SS	0x44f600(,%RAX,4),%XMM0,%XMM9

(3) 0x2025ce VMOVSS	%XMM14,0x38c100(,%RAX,4)

(3) 0x2025d7 VMOVSS	%XMM8,0x3edb80(,%RAX,4)

(3) 0x2025e0 VMOVSS	%XMM9,0x44f600(,%RAX,4)

(3) 0x2025e9 MOV	%R9,%RAX

(3) 0x2025ec JGE	202507

(3) 0x2025f2 VXORPS	%XMM14,%XMM14,%XMM14

(3) 0x2025f7 VXORPS	%XMM8,%XMM8,%XMM8

(3) 0x2025fc VXORPS	%XMM9,%XMM9,%XMM9

(3) 0x202601 TEST	%EDX,%EDX

(3) 0x202603 JLE	2025a5

(3) 0x202605 VMOVSS	0x205700(,%RAX,4),%XMM17

(3) 0x202610 VMOVSS	0x267180(,%RAX,4),%XMM30

(3) 0x20261b VMOVSS	0x2c8c00(,%RAX,4),%XMM11

(3) 0x202624 VMOVSS	(%R14),%XMM12

(3) 0x202629 VMOVSS	(%RBX),%XMM13

(3) 0x20262d CMP	$0x4,%EDX

(3) 0x202630 JAE	202640

(3) 0x202632 VXORPS	%XMM8,%XMM8,%XMM8

(3) 0x202637 XOR	%R9D,%R9D

(3) 0x20263a JMP	202b90

0x20263f NOP

(3) 0x202640 CMP	$0x10,%EDX

(3) 0x202643 JAE	20264d

(3) 0x202645 XOR	%R9D,%R9D

(3) 0x202648 JMP	2029ec

(3) 0x20264d VBROADCASTSS	%XMM17,%YMM8

(3) 0x202653 VBROADCASTSS	%XMM30,%YMM19

(3) 0x202659 VBROADCASTSS	%XMM11,%YMM21

(3) 0x20265f VBROADCASTSS	%XMM12,%YMM14

(3) 0x202664 VBROADCASTSS	%XMM13,%YMM23

(3) 0x20266a MOV	%EDX,%R9D

(3) 0x20266d AND	$-0x10,%R9D

(3) 0x202671 VXORPS	%XMM16,%XMM16,%XMM16

(3) 0x202677 VXORPS	%XMM9,%XMM9,%XMM9

(3) 0x20267c VXORPS	%XMM18,%XMM18,%XMM18

(3) 0x202682 VXORPS	%XMM20,%XMM20,%XMM20

(3) 0x202688 VXORPS	%XMM24,%XMM24,%XMM24

(3) 0x20268e VXORPS	%XMM25,%XMM25,%XMM25

(3) 0x202694 XOR	%R10D,%R10D

(3) 0x202697 VMOVAPS	%XMM17,-0x60(%RBP)

(3) 0x20269e VMOVAPS	%XMM30,-0x50(%RBP)

(3) 0x2026a5 JMP	2027ec

0x2026aa NOPW	(%RAX,%RAX,1)

  (6) 0x2026b0 VPCMPEQD	%YMM17,%YMM2,%K1

  (6) 0x2026b6 VBROADCASTSS	-0x1dd3(%RIP),%YMM7

  (6) 0x2026bf VADDPS	%YMM23,%YMM15,%YMM5

  (6) 0x2026c5 VADDPS	%YMM23,%YMM0,%YMM1

  (6) 0x2026cb VCMPPS	$0x1,%YMM0,%YMM10,%K2

  (6) 0x2026d2 ADD	$0x40,%R10

  (6) 0x2026d6 VMOVAPS	%YMM4,%YMM2{%K1}{z}

  (6) 0x2026dc VPCMPEQD	%YMM17,%YMM3,%K1

  (6) 0x2026e2 VBROADCASTSS	-0x1e0b(%RIP),%YMM4

  (6) 0x2026eb VBROADCASTSS	-0x1e0d(%RIP),%YMM17

  (6) 0x2026f5 VBROADCASTSD	-0x1d37(%RIP),%ZMM3

  (6) 0x2026ff VMOVAPS	%YMM22,%YMM22{%K1}{z}

  (6) 0x202705 VCMPPS	$0x1,%YMM15,%YMM10,%K1

  (6) 0x20270c VCVTPS2PD	%YMM5,%ZMM5

  (6) 0x202712 VCVTPS2PD	%YMM1,%ZMM1

  (6) 0x202718 VMOVAPS	%YMM4,%YMM6

  (6) 0x20271c VFMSUB213PS	%YMM17,%YMM15,%YMM6

  (6) 0x202722 VFMSUB213PS	%YMM17,%YMM0,%YMM4

  (6) 0x202728 VSQRTPD	%ZMM5,%ZMM17

  (6) 0x20272e VMULPD	%ZMM5,%ZMM5,%ZMM5

  (6) 0x202734 VDIVPD	%ZMM5,%ZMM3,%ZMM5

  (6) 0x20273a VFMSUB213PS	%YMM7,%YMM15,%YMM6

  (6) 0x20273f VFMSUB213PS	%YMM7,%YMM0,%YMM4

  (6) 0x202744 VBROADCASTSS	-0x1e75(%RIP),%YMM7

  (6) 0x20274d VFMSUB213PS	%YMM7,%YMM15,%YMM6

  (6) 0x202752 VFMSUB213PS	%YMM7,%YMM0,%YMM4

  (6) 0x202757 VBROADCASTSS	-0x1e98(%RIP),%YMM7

  (6) 0x202760 VFMSUB213PS	%YMM7,%YMM15,%YMM6

  (6) 0x202765 VFMSUB213PS	%YMM7,%YMM0,%YMM4

  (6) 0x20276a VBROADCASTSS	-0x1e97(%RIP),%YMM7

  (6) 0x202773 VFNMADD213PS	%YMM7,%YMM15,%YMM6

  (6) 0x202778 VFNMADD213PS	%YMM7,%YMM0,%YMM4

  (6) 0x20277d VSQRTPD	%ZMM1,%ZMM7

  (6) 0x202783 VMULPD	%ZMM1,%ZMM1,%ZMM1

  (6) 0x202789 VDIVPD	%ZMM1,%ZMM3,%ZMM1

  (6) 0x20278f VCVTPS2PD	%YMM6,%ZMM6

  (6) 0x202795 VCVTPS2PD	%YMM4,%ZMM4

  (6) 0x20279b VFMSUB231PD	%ZMM5,%ZMM17,%ZMM6

  (6) 0x2027a1 VCVTPD2PS	%ZMM6,%YMM5

  (6) 0x2027a7 VMULPS	%YMM5,%YMM2,%YMM0{%K1}{z}

  (6) 0x2027ad VFMSUB231PD	%ZMM1,%ZMM7,%ZMM4

  (6) 0x2027b3 VFMADD231PS	%YMM29,%YMM0,%YMM24

  (6) 0x2027b9 VFMADD231PS	%YMM30,%YMM0,%YMM18

  (6) 0x2027bf VFMADD231PS	%YMM31,%YMM0,%YMM16

  (6) 0x2027c5 VCVTPD2PS	%ZMM4,%YMM1

  (6) 0x2027cb VMULPS	%YMM1,%YMM22,%YMM1{%K2}{z}

  (6) 0x2027d1 VFMADD231PS	%YMM26,%YMM1,%YMM25

  (6) 0x2027d7 VFMADD231PS	%YMM27,%YMM1,%YMM20

  (6) 0x2027dd VFMADD231PS	%YMM28,%YMM1,%YMM9

  (6) 0x2027e3 CMP	%R10,%RDI

  (6) 0x2027e6 JE	2028cd

  (6) 0x2027ec VMOVUPS	0x205700(%R10),%YMM0

  (6) 0x2027f5 VMOVUPS	0x205720(%R10),%YMM2

  (6) 0x2027fe VBROADCASTSS	-0x1f44(%RIP),%YMM17

  (6) 0x202808 VSUBPS	%YMM8,%YMM0,%YMM29

  (6) 0x20280e VMOVUPS	0x267180(%R10),%YMM0

  (6) 0x202817 VSUBPS	%YMM8,%YMM2,%YMM26

  (6) 0x20281d VMOVUPS	0x2671a0(%R10),%YMM2

  (6) 0x202826 VMULPS	%YMM29,%YMM29,%YMM15

  (6) 0x20282c VSUBPS	%YMM19,%YMM0,%YMM30

  (6) 0x202832 VMOVUPS	0x2c8c00(%R10),%YMM0

  (6) 0x20283b VSUBPS	%YMM19,%YMM2,%YMM27

  (6) 0x202841 VMOVUPS	0x2c8c20(%R10),%YMM2

  (6) 0x20284a VFMADD231PS	%YMM30,%YMM30,%YMM15

  (6) 0x202850 VSUBPS	%YMM21,%YMM0,%YMM31

  (6) 0x202856 VMULPS	%YMM26,%YMM26,%YMM0

  (6) 0x20285c VSUBPS	%YMM21,%YMM2,%YMM28

  (6) 0x202862 VFMADD231PS	%YMM27,%YMM27,%YMM0

  (6) 0x202868 VFMADD231PS	%YMM31,%YMM31,%YMM15

  (6) 0x20286e VFMADD231PS	%YMM28,%YMM28,%YMM0

  (6) 0x202874 VCMPPS	$0x1,%YMM14,%YMM15,%K0

  (6) 0x20287b VCMPPS	$0x1,%YMM14,%YMM15,%YMM2

  (6) 0x202881 VANDPS	%YMM17,%YMM2,%YMM2

  (6) 0x202887 VCMPPS	$0x1,%YMM14,%YMM0,%K1

  (6) 0x20288e VCMPPS	$0x1,%YMM14,%YMM0,%YMM3

  (6) 0x202894 KUNPCKBW	%K0,%K1,%K0

  (6) 0x202898 VANDPS	%YMM17,%YMM3,%YMM3

  (6) 0x20289e KORTESTW	%K0,%K0

  (6) 0x2028a2 JE	2026b0

  (6) 0x2028a8 VPCMPEQD	%YMM17,%YMM2,%K1

  (6) 0x2028ae VMOVUPS	0x32a680(%R10),%YMM4{%K1}{z}

  (6) 0x2028b8 VPCMPEQD	%YMM17,%YMM3,%K1

  (6) 0x2028be VMOVUPS	0x32a6a0(%R10),%YMM22{%K1}{z}

  (6) 0x2028c8 JMP	2026b0

(3) 0x2028cd VADDPS	%YMM24,%YMM25,%YMM0

(3) 0x2028d3 VEXTRACTF128	$0x1,%YMM0,%XMM2

(3) 0x2028d9 VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x2028dd VPERMILPD	$0x1,%XMM0,%XMM2

(3) 0x2028e3 VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x2028e7 VMOVSHDUP	%XMM0,%XMM2

(3) 0x2028eb VADDSS	%XMM2,%XMM0,%XMM14

(3) 0x2028ef VADDPS	%YMM18,%YMM20,%YMM0

(3) 0x2028f5 VEXTRACTF128	$0x1,%YMM0,%XMM2

(3) 0x2028fb VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x2028ff VPERMILPD	$0x1,%XMM0,%XMM2

(3) 0x202905 VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x202909 VMOVSHDUP	%XMM0,%XMM2

(3) 0x20290d VADDSS	%XMM2,%XMM0,%XMM8

(3) 0x202911 VADDPS	%YMM16,%YMM9,%YMM0

(3) 0x202917 VEXTRACTF128	$0x1,%YMM0,%XMM2

(3) 0x20291d VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x202921 VPERMILPD	$0x1,%XMM0,%XMM2

(3) 0x202927 VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x20292b VMOVSHDUP	%XMM0,%XMM2

(3) 0x20292f VADDSS	%XMM2,%XMM0,%XMM9

(3) 0x202933 CMP	%RDX,%R9

(3) 0x202936 JNE	202989

(3) 0x202938 VMOVSD	-0x1f78(%RIP),%XMM5

(3) 0x202940 VMOVSS	-0x2068(%RIP),%XMM6

(3) 0x202948 VMOVSS	-0x2084(%RIP),%XMM7

(3) 0x202950 VMOVSS	-0x205a(%RIP),%XMM22

(3) 0x20295a VMOVSS	-0x2070(%RIP),%XMM25

(3) 0x202964 VMOVSS	-0x208a(%RIP),%XMM26

(3) 0x20296e VMOVSS	-0x2068(%RIP),%XMM27

(3) 0x202978 VXORPS	%XMM28,%XMM28,%XMM28

(3) 0x20297e VXORPS	%XMM29,%XMM29,%XMM29

(3) 0x202984 JMP	2025a5

(3) 0x202989 VMOVSD	-0x1fc9(%RIP),%XMM5

(3) 0x202991 VMOVSS	-0x20b9(%RIP),%XMM6

(3) 0x202999 VMOVSS	-0x20d5(%RIP),%XMM7

(3) 0x2029a1 VMOVSS	-0x20ab(%RIP),%XMM22

(3) 0x2029ab VMOVSS	-0x20c1(%RIP),%XMM25

(3) 0x2029b5 VMOVSS	-0x20db(%RIP),%XMM26

(3) 0x2029bf VMOVSS	-0x20b9(%RIP),%XMM27

(3) 0x2029c9 VXORPS	%XMM28,%XMM28,%XMM28

(3) 0x2029cf VXORPS	%XMM29,%XMM29,%XMM29

(3) 0x2029d5 TEST	$0xc,%DL

(3) 0x2029d8 JE	202b77

(3) 0x2029de VMOVAPS	-0x60(%RBP),%XMM17

(3) 0x2029e5 VMOVAPS	-0x50(%RBP),%XMM30

(3) 0x2029ec VXORPS	%XMM0,%XMM0,%XMM0

(3) 0x2029f0 VBLENDPS	$0x1,%XMM9,%XMM0,%XMM9

(3) 0x2029f6 VBLENDPS	$0x1,%XMM8,%XMM0,%XMM8

(3) 0x2029fc VBLENDPS	$0x1,%XMM14,%XMM0,%XMM0

(3) 0x202a02 VBROADCASTSS	%XMM17,%XMM14

(3) 0x202a08 VBROADCASTSS	%XMM30,%XMM15

(3) 0x202a0e VBROADCASTSS	%XMM11,%XMM16

(3) 0x202a14 VBROADCASTSS	%XMM12,%XMM18

(3) 0x202a1a VBROADCASTSS	%XMM13,%XMM19

(3) 0x202a20 MOV	%R9,%R10

(3) 0x202a23 MOV	%EDX,%R9D

(3) 0x202a26 AND	$-0x4,%R9D

(3) 0x202a2a JMP	202ac4

0x202a2f NOP

  (5) 0x202a30 VADDPS	%XMM19,%XMM24,%XMM1

  (5) 0x202a36 VBROADCASTSD	-0x2077(%RIP),%YMM3

  (5) 0x202a3f VMOVAPS	%XMM2,%XMM2{%K1}{z}

  (5) 0x202a45 VCMPPS	$0x1,%XMM24,%XMM29,%K1

  (5) 0x202a4c MOV	%R11,%R10

  (5) 0x202a4f VCVTPS2PD	%XMM1,%YMM1

  (5) 0x202a53 VMULPD	%YMM1,%YMM1,%YMM4

  (5) 0x202a57 VSQRTPD	%YMM1,%YMM1

  (5) 0x202a5b VDIVPD	%YMM4,%YMM3,%YMM3

  (5) 0x202a5f VBROADCASTSS	-0x2188(%RIP),%XMM4

  (5) 0x202a68 VFMADD213PS	-0x21a6(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a72 VFMADD213PS	-0x217c(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a7c VFMADD213PS	-0x2192(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a86 VFMADD213PS	-0x21ac(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a90 VFMADD213PS	-0x218a(%RIP){1to4},%XMM24,%XMM4

  (5) 0x202a9a VCVTPS2PD	%XMM4,%YMM4

  (5) 0x202a9e VFMADD231PD	%YMM3,%YMM1,%YMM4

  (5) 0x202aa3 VCVTPD2PS	%YMM4,%XMM1

  (5) 0x202aa7 VMULPS	%XMM1,%XMM2,%XMM1{%K1}{z}

  (5) 0x202aad VFMADD231PS	%XMM20,%XMM1,%XMM0

  (5) 0x202ab3 VFMADD231PS	%XMM21,%XMM1,%XMM8

  (5) 0x202ab9 VFMADD231PS	%XMM23,%XMM1,%XMM9

  (5) 0x202abf CMP	%R11,%R8

  (5) 0x202ac2 JE	202b30

  (5) 0x202ac4 VMOVAPS	0x205700(,%R10,4),%XMM2

  (5) 0x202ace LEA	0x4(%R10),%R11

  (5) 0x202ad2 VSUBPS	%XMM14,%XMM2,%XMM20

  (5) 0x202ad8 VMOVAPS	0x267180(,%R10,4),%XMM2

  (5) 0x202ae2 VMULPS	%XMM20,%XMM20,%XMM24

  (5) 0x202ae8 VSUBPS	%XMM15,%XMM2,%XMM21

  (5) 0x202aee VMOVAPS	0x2c8c00(,%R10,4),%XMM2

  (5) 0x202af8 VFMADD231PS	%XMM21,%XMM21,%XMM24

  (5) 0x202afe VSUBPS	%XMM16,%XMM2,%XMM23

  (5) 0x202b04 VFMADD231PS	%XMM23,%XMM23,%XMM24

  (5) 0x202b0a VCMPPS	$0x1,%XMM18,%XMM24,%K1

  (5) 0x202b11 KORTESTB	%K1,%K1

  (5) 0x202b15 JE	202a30

  (5) 0x202b1b VMOVUPS	0x32a680(,%R10,4),%XMM2{%K1}{z}

  (5) 0x202b26 JMP	202a30

0x202b2b NOPL	(%RAX,%RAX,1)

(3) 0x202b30 VPERMILPD	$0x1,%XMM0,%XMM2

(3) 0x202b36 VADDPS	%XMM2,%XMM0,%XMM0

(3) 0x202b3a VMOVSHDUP	%XMM0,%XMM2

(3) 0x202b3e VADDPS	%XMM2,%XMM0,%XMM14

(3) 0x202b42 VPERMILPD	$0x1,%XMM8,%XMM0

(3) 0x202b48 VADDPS	%XMM0,%XMM8,%XMM0

(3) 0x202b4c VMOVSHDUP	%XMM0,%XMM2

(3) 0x202b50 VADDPS	%XMM2,%XMM0,%XMM8

(3) 0x202b54 VPERMILPD	$0x1,%XMM9,%XMM0

(3) 0x202b5a VADDPS	%XMM0,%XMM9,%XMM0

(3) 0x202b5e VMOVSHDUP	%XMM0,%XMM2

(3) 0x202b62 VADDSS	%XMM2,%XMM0,%XMM9

(3) 0x202b66 CMP	%RDX,%R9

(3) 0x202b69 JE	2025a5

(3) 0x202b6f VINSERTPS	$0x1c,%XMM14,%XMM8,%XMM8

(3) 0x202b75 JMP	202b90

(3) 0x202b77 VMOVAPS	-0x60(%RBP),%XMM17

(3) 0x202b7e VMOVAPS	-0x50(%RBP),%XMM30

(3) 0x202b85 VINSERTPS	$0x10,%XMM14,%XMM8,%XMM8

(3) 0x202b8b NOPL	(%RAX,%RAX,1)

(3) 0x202b90 VINSERTPS	$0x10,%XMM17,%XMM30,%XMM0

(3) 0x202b97 JMP	202c13

0x202b99 NOPL	(%RAX)

  (4) 0x202ba0 VADDSS	%XMM13,%XMM16,%XMM2

  (4) 0x202ba6 VMOVAPS	%XMM6,%XMM4

  (4) 0x202baa VFMADD213SS	%XMM7,%XMM16,%XMM4

  (4) 0x202bb0 VCMPSS	$0x1,%XMM16,%XMM28,%K1

  (4) 0x202bb7 INC	%R9

  (4) 0x202bba VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (4) 0x202bbe VFMADD213SS	%XMM22,%XMM16,%XMM4

  (4) 0x202bc4 VSQRTSD	%XMM2,%XMM2,%XMM3

  (4) 0x202bc8 VMULSD	%XMM2,%XMM2,%XMM2

  (4) 0x202bcc VFMADD213SS	%XMM25,%XMM16,%XMM4

  (4) 0x202bd2 VDIVSD	%XMM2,%XMM5,%XMM2

  (4) 0x202bd6 VFMADD213SS	%XMM26,%XMM16,%XMM4

  (4) 0x202bdc VFMADD213SS	%XMM27,%XMM16,%XMM4

  (4) 0x202be2 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (4) 0x202be6 VFMADD231SD	%XMM2,%XMM3,%XMM4

  (4) 0x202beb VCVTSD2SS	%XMM4,%XMM4,%XMM2

  (4) 0x202bef VMULSS	%XMM2,%XMM17,%XMM2

  (4) 0x202bf5 VMOVSS	%XMM2,%XMM2,%XMM2{%K1}{z}

  (4) 0x202bfb VBROADCASTSS	%XMM2,%XMM3

  (4) 0x202c00 VFMADD231SS	%XMM15,%XMM2,%XMM9

  (4) 0x202c05 VFMADD231PS	%XMM14,%XMM3,%XMM8

  (4) 0x202c0a CMP	%R9,%RDX

  (4) 0x202c0d JE	2025a0

  (4) 0x202c13 VMOVSS	0x267180(,%R9,4),%XMM2

  (4) 0x202c1d VXORPS	%XMM17,%XMM17,%XMM17

  (4) 0x202c23 VINSERTPS	$0x10,0x205700(,%R9,4),%XMM2,%XMM2

  (4) 0x202c2e VSUBPS	%XMM0,%XMM2,%XMM14

  (4) 0x202c32 VMOVSS	0x2c8c00(,%R9,4),%XMM2

  (4) 0x202c3c VSUBSS	%XMM11,%XMM2,%XMM15

  (4) 0x202c41 VMULPS	%XMM14,%XMM14,%XMM2

  (4) 0x202c46 VMOVSHDUP	%XMM2,%XMM3

  (4) 0x202c4a VADDSS	%XMM3,%XMM2,%XMM16

  (4) 0x202c50 VFMADD231SS	%XMM15,%XMM15,%XMM16

  (4) 0x202c56 VUCOMISS	%XMM12,%XMM16

  (4) 0x202c5c JAE	202ba0

  (4) 0x202c62 VMOVSS	0x32a680(,%R9,4),%XMM17

  (4) 0x202c6d JMP	202ba0

0x202c72 INT	$0x3

0x202c73 INT	$0x3

0x202c74 INT	$0x3

0x202c75 INT	$0x3

0x202c76 INT	$0x3

0x202c77 INT	$0x3

0x202c78 INT	$0x3

0x202c79 INT	$0x3

0x202c7a INT	$0x3

0x202c7b INT	$0x3

0x202c7c INT	$0x3

0x202c7d INT	$0x3

0x202c7e INT	$0x3

0x202c7f INT	$0x3

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run aocc_libalm

Source file and lines	main.c:139-146
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.17 to 3.17 cycles (3.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.17 to 0.81 cycles (14.97x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	91
nb uops	73
loop length	322
used x86 registers	14
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	3.00	6.67	6.67	6.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	3.00	6.67	6.67	6.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	6.67
Overall L1	12.17

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	30%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Vector efficiency ratios

INT

all	8%
load	8%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	7%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

5% of peak load performance is reached (4.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.17 to 6.67 cycles (1.83x speedup).

ASM code

In the binary file, the address of the function is: 202480

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDX),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
TEST %R13D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202517 <.omp_outlined..6+0x97>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
DEC %R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200b88,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 203440 <@plt_start@+0x60>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CMP %R13D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVL %EAX,%R13D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R13D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202526 <.omp_outlined..6+0xa6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x200ba0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 203450 <@plt_start@+0x70>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVSD -0x1b66(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x1c56(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c72(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c48(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c5e(%RIP),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c78(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c56(%RIP),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV (%R12),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOVSXD %R13D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x4,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %EDX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x4,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
SAL $0x6,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
JMP 2025f2 <.omp_outlined..6+0x172>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run aocc_libalm

Source file and lines	main.c:139-146
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.17 to 3.17 cycles (3.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	91
nb uops	73
loop length	322
used x86 registers	14
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	3.00	6.67	6.67	6.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	3.00	6.67	6.67	6.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	6.67
Overall L1	12.17

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	30%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Vector efficiency ratios

INT

all	8%
load	8%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	7%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

5% of peak load performance is reached (4.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 202480

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDX),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
TEST %R13D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202517 <.omp_outlined..6+0x97>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
DEC %R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x200b88,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 203440 <@plt_start@+0x60>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CMP %R13D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVL %EAX,%R13D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R13D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 202526 <.omp_outlined..6+0xa6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x200ba0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 203450 <@plt_start@+0x70>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVSD -0x1b66(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSS -0x1c56(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c72(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c48(%RIP),%XMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c5e(%RIP),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c78(%RIP),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x1c56(%RIP),%XMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV (%R12),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOVSXD %R13D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x4,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %EDX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x4,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
SAL $0x6,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
JMP 2025f2 <.omp_outlined..6+0x172>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A
INT $0x3																		N/A

Name	Coverage (%)	Time (s)
▼.omp_outlined..6–	45.49	4.12
▼Loop 3 - Step10_orig.c:19-35 - exec–	0.07	0.01
○Loop 6 - Step10_orig.c:19-35 - exec	45.39	3.95
○Loop 5 - Step10_orig.c:19-35 - exec	0.01	0.00
○Loop 4 - Step10_orig.c:19-35 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code